Semiconductor equipment

Abstract

To provide a semiconductor device which can reduce the cost and can increase the heat releasing property.SOLUTION: A semiconductor device 101 includes at least two semiconductor chips 11, 12 with different potentials having drain electrodes 11a and 12a in a first surface and source electrodes 11b and 12b in a second surface opposite to the first surface. The semiconductor device 101 includes: a first substrate 20 and a second substrate 30 to which the semiconductor chips are separately equipped; a third substrate 50 electrically connected to the semiconductor chips; and a sealing resin unit 90 for integrally sealing the semiconductor chips and the substrates. The first and second substrates have equipped coppers 21, 31 equipped with the semiconductor chips, heat releasing coppers 22 and 32 for releasing heat from the semiconductor chips; and insulating layers 23, 33 for insulating the equipped coppers and the heat releasing coppers. The heat releasing coppers are exposed from the sealing resin unit at the surface opposed to the surface facing the insulating layer. The equipped coppers are thicker than the heat releasing coppers.SELECTED DRAWING: Figure 1

Description

Technical Field

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[0003] , , , , , , ​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​ Two or more wiring boards (20, 30) on which each semiconductor element is individually mounted, A wiring member (50) that electrically connects each semiconductor element, It comprises a sealing resin part (90) that integrally seals the semiconductor element, the wiring board, and the wiring member, Each wiring board has mounting metal plates (21, 31) which are mounting areas for each semiconductor element and are connected to the first electrode, heat dissipation metal plates (22, 32) which dissipate heat emitted from the semiconductor element, and insulating layers (23, 33) which are placed between the mounting metal plates and the heat dissipation metal plates and electrically insulate the mounting metal plates from each other. The heat dissipation metal plate has an outer surface opposite to the insulating layer that is exposed from the sealing resin portion. The mounting metal plate is thicker than the heat dissipation metal plate. Ku, The wiring members are arranged opposite the second electrodes of each semiconductor element, and a first wiring board (51a) connected to the second electrode of one semiconductor element and a second wiring board (51b) connected to the second electrode of another semiconductor element are provided as a single substrate. Furthermore, it includes a first main terminal (41) connected to a mounting metal plate on which semiconductor elements connected to the first wiring board are mounted, and a second main terminal (42) connected to the second wiring board. The first main terminal and the second main terminal protrude in the same direction relative to the sealing resin portion. It is characterized by the following:

[0007] Thus, since semiconductor devices have a wiring board on which each semiconductor element is individually mounted, there is no need to process the wiring board by cutting or other means to mount semiconductor elements with different potentials. Therefore, semiconductor devices can be made more cost-effective.

[0008] Furthermore, in the wiring board, the thickness of the mounting metal plate located on the semiconductor element side of the insulating layer is greater than the thickness of the heat dissipation metal plate. Therefore, the semiconductor device can improve the heat dissipation performance of the heat emitted from the semiconductor element compared to a configuration where the heat dissipation metal plate is thicker than the mounting metal plate.

[0009] The various embodiments disclosed in this specification employ different technical means to achieve their respective objectives. The claims and the reference numerals in parentheses in this section are illustrative in their correspondence with the embodiments described later and are not intended to limit the technical scope. The objectives, features, and effects disclosed in this specification will become clearer by referring to the subsequent detailed description and the accompanying drawings. [Brief explanation of the drawing]

[0010] [Figure 1] This is a cross-sectional view showing the schematic configuration of a semiconductor device in an embodiment. [Figure 2] This is a plan view showing the schematic configuration of the lead frame in the embodiment. [Figure 3] This is a cross-sectional view along line III-III in Figure 2. [Figure 4] This is a cross-sectional view along the line IV-IV in Figure 2. [Figure 5] This is a perspective view showing the schematic configuration of a semiconductor device in an embodiment. [Figure 6] This is a cross-sectional view showing the schematic configuration of the semiconductor device in Modification Example 1. [Figure 7] This is a cross-sectional view showing the schematic configuration of the semiconductor device in modified example 2. [Modes for carrying out the invention]

[0011] In the following, several embodiments for implementing this disclosure will be described with reference to the drawings. In each embodiment, parts corresponding to matters described in a prior embodiment may be denoted by the same reference numerals, and redundant descriptions may be omitted. If only a part of the configuration is described in each embodiment, other parts of the configuration can be referred to and applied to other embodiments described in advance.

[0012] In the following, the three mutually orthogonal directions will be referred to as the X, Y, and Z directions. The plane defined by the X and Y directions will be called the XY plane. Viewing from the Z direction will also be called a plan view. Therefore, a plan view can be considered a plan diagram as seen from the Z direction.

[0013] (Embodiment) The semiconductor device 101 of the first embodiment will be described with reference to FIGS. 1 to 5. As shown in FIGS. 1, 2, etc., the semiconductor device 101 includes semiconductor chips 11, 12, a first substrate 20, a second substrate 30, terminals 41 to 45, a third substrate 50, terminals 61 to 63, solder 71 to 78, bonding wires 80, and a sealing resin portion 90. The semiconductor device 101 can be applied to, for example, an inverter in a power conversion device. The inverter is configured to include upper and lower arm circuits for three phases. Note that, for example, the circuit configuration of the inverter can be applied with Japanese Patent Application Laid-Open No. 2022-126905. Further, FIG. 1 corresponds to a cross-sectional view taken along line I-I of FIG. 5.

[0014] The semiconductor device 101 constitutes, for example, an upper and lower arm circuit for one phase. In the present embodiment, an example in which one high-side switch 11 and one low-side switch 12 are directly connected is adopted. However, the present disclosure can also be adopted for a configuration in which a plurality of high-side switches 11 are connected in parallel and a plurality of low-side switches 12 are connected in parallel.

[0015] Note that FIG. 2 shows a state before the positive terminal 41, negative terminal 42, output terminal 43, signal terminal 44, and gate terminal 45, which are part of the lead frame 1, are divided. Further, FIG. 5 shows a state before the sealing resin portion 90 is provided and the lead frame 1 is divided.

[0016] <semiconductor chips 11, 12> As shown in FIG. 1, the semiconductor device 101 includes a high-side switch 11 and a low-side switch 12 as semiconductor chips 11, 12. That is, it can be said that the semiconductor device 101 includes two or more semiconductor chips 11, 12 having different potentials. The high-side switch 11 and the low-side switch 12 have the same configuration. Therefore, when there is no need to distinguish between the high-side switch 11 and the low-side switch 12, the high-side switch 11 will be used for explanation. The high-side switch 11 and the low-side switch 12 correspond to semiconductor elements.

[0017] The high-side switch 11 is formed on a semiconductor substrate made of materials such as silicon (Si) or a wide-bandgap semiconductor with a wider bandgap than silicon. Examples of wide-bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. The high-side switch 11 is sometimes referred to as a semiconductor device.

[0018] The high-side switch 11 has a plate thickness direction that coincides with the Z direction. The elements formed on the high-side switch 11 have a vertical structure so that the main current flows in the Z direction. IGBTs, MOSFETs, diodes, etc. can be used as vertical elements. In this embodiment, a MOSFET forming one arm is formed as a vertical element. The high-side switch 11 has a gate electrode (not shown).

[0019] The high-side switch 11 has main electrodes on both sides in the thickness direction of its plate, i.e., the Z direction. Specifically, it has a drain electrode 11a on one side and a source electrode 11b on the opposite side as its main electrodes. On the other hand, the low-side switch 12 has a drain electrode 12a on one side and a source electrode 12b on the opposite side as its main electrodes. The drain electrodes 11a and 12a correspond to the first electrodes. The source electrodes 11b and 12b correspond to the second electrodes.

[0020] The high-side switch 11 has a substantially rectangular shape in plan. The high-side switch 11 has a plurality of pads formed on the opposite side at positions different from the source electrode 11b. The source electrode 11b and the pads are exposed from a protective film (not shown) on the opposite side of the semiconductor substrate, respectively. The source electrode 11b is formed on a portion of the opposite side of the high-side switch 11. The drain electrode 11a is formed over almost the entire surface of one side.

[0021] The pads are electrodes for signals. The pads are electrically isolated from the source electrode 11b. The pads are formed, for example, at the end opposite to the formation region of the source electrode 11b in the Y direction. The pads include at least a gate pad for the gate electrode. They may also include signal pads for current sensing, a temperature-sensitive diode for detecting the temperature of either the semiconductor chip 11 or 12 (here, the low-side switch 12), and so on. As shown in Figure 1, the low-side switch 12 has its signal pad and signal terminal 44 connected via a bonding wire 80. The high-side switch 11 and the low-side switch 12 have their gate pads and gate terminal 45 connected via a bonding wire 80.

[0022] <Terminals 61-63> The first terminal 61, the second terminal 62, and the joint terminal 63 are conductive blocks mainly composed of metal. These terminals 61-63 are part of the wiring of the semiconductor device 101.

[0023] The first terminal 61 is located on the source electrode 11b of the high-side switch 11. One end of the first terminal 61 is connected to the source electrode 11b by solder 72. The other end of the first terminal 61 is connected to the first mounted copper 51a by solder 73.

[0024] The second terminal 62 is located on the source electrode 12b of the low-side switch 12. One end of the second terminal 62 is connected to the source electrode 12b by solder 75. The other end of the second terminal 62 is connected to the second mounted copper 51b by solder 76.

[0025] One end of the connector terminal 63 is connected to the mounted copper 31 by solder 77. The other end of the connector terminal 63 is connected to the first mounted copper 51a by solder 78. The mounted copper 31, the first mounted copper 51a, and the second mounted copper 51b will be explained later.

[0026] <First substrate 20, second substrate 30> As shown in Figure 1, the first substrate 20 is a wiring board on which the high-side switch 11 is mounted. The first substrate 20 comprises mounted copper 21, heat-dissipating copper 22, and an insulating layer 23. The mounted copper 21, insulating layer 23, and heat-dissipating copper 22 are laminated in this order on the first substrate 20. The mounted copper 21 is in contact with the insulating layer 23 on the surface facing the insulating layer 23. The heat-dissipating copper 22 is in contact with the insulating layer 23 on the surface facing the insulating layer 23.

[0027] The mounted copper 21 is part of the wiring, primarily composed of copper. The mounted copper 21 may have a plating film on its surface. Unlike a thin film, the mounted copper 21 is a plate-like component. Therefore, the mounted copper 21 can also be called a metal plate or copper plate. The mounted copper 21 is the mounting area for the high-side switch 11 and is connected to the drain electrode 11a. The mounted copper 21 is connected to the drain electrode 11a by solder 71. The mounted copper 21 is connected to the positive terminal 41, which is one of the main terminals. The mounted copper 21 corresponds to a mounted metal plate. The mounted copper 21 is thicker than the heat-dissipating copper 22. For example, the mounted copper 21 has a thickness of 0.8 mm or more. The plate thickness can also be said to be the length along the Z direction. The positive terminal 41 corresponds to the first main terminal. The positive terminal 41 is connected to the mounted copper 21 on which the high-side switch 11, which is connected to the first mounted copper 51a (explained later), is mounted.

[0028] The heat-dissipating copper 22 is made of the same material as the mounted copper 21. The heat-dissipating copper 22 has an outer surface opposite to the insulating layer 23 that is exposed from the sealing resin part 90. The heat-dissipating copper 22 is a component that dissipates heat emitted from the high-side switch 11. In other words, the heat-dissipating copper 22 receives heat from the high-side switch 11 via the insulating layer 23 and dissipates that heat to the outside of the sealing resin part 90. The heat-dissipating copper 22 corresponds to a heat-dissipating metal plate. Note that the mounted copper 21 and the heat-dissipating copper 22 can be made of materials whose main component is a metal other than copper.

[0029] The insulating layer 23 is placed between the mounted copper 21 and the heat-dissipating copper 22, and is a component that electrically insulates the mounted copper 21 and the heat-dissipating copper 22.

[0030] The second substrate 30 is a wiring board on which the low-side switch 12 is mounted. The second substrate 30 has mounting copper 31, heat-dissipating copper 32, and an insulating layer 33, and is configured in the same way as the first substrate 20. The mounting copper 31 has the same configuration as the mounting copper 21. The heat-dissipating copper 32 has the same configuration as the heat-dissipating copper 22. The insulating layer 33 has the same configuration as the insulating layer 23.

[0031] The mounted copper 31 is connected to the drain electrode 12a by solder 74. The mounted copper 31 is connected to the coupling terminal 63 by solder 77. Furthermore, the mounted copper 31 is connected to the output terminal 43, which is one of the main terminals.

[0032] As shown in Figure 1, the sides of the mounted copper 21 and 31 are provided with convex V-cut portions 24 and 34. In other words, the sides of the mounted copper 21 and 31 are V-shaped. Furthermore, the sides of the mounted copper 21 and 31 are V-cut. In addition, in the Z direction, the apex of the convex shape of the mounted copper 21 and 31 is located on the mounting surface side of the semiconductor chips 11 and 12 rather than on the contact surface side with the insulating layers 23 and 33. The V-cut portions 24 and 34 are provided around the entire circumference of the sides of the mounted copper 21 and 31.

[0033] This allows the semiconductor device 101 to reduce peeling of the sealing resin portion 90 around the semiconductor chips 11 and 12, and to reduce stress on the solder 71 and 74. The mounted copper 21 and 31 may also have a shape in which the cross-sectional area along the XY plane increases from the insulating layer 23 and 33 side towards the semiconductor chips 11 and 12 side. Even with this, the semiconductor device 101 can achieve similar effects.

[0034] As shown in Figure 1, the heat-dissipating copper 22 and 32 are provided in areas excluding the edges of the insulating layers 23 and 33. In other words, the heat-dissipating copper 22 is provided in a part of the insulating layer 23 when viewed from the Z direction in a plan view. Furthermore, the heat-dissipating copper 22 is provided in a position excluding the annular outer circumference of the insulating layer 23. The insulating layer 23 can be said to have a creepage portion 25 that surrounds the heat-dissipating copper 22. The creepage portion 25 is a portion that ensures insulation between the mounted copper 21 and the heat-dissipating copper 22. In other words, the creepage portion 25 is a portion that ensures a creepage distance between the mounted copper 21 and the heat-dissipating copper 22.

[0035] Similarly, the heat-dissipating copper 32 is provided in positions other than the annular outer periphery of the insulating layer 33. Therefore, it can be said that the insulating layer 33 has a creepage portion 35 that surrounds the heat-dissipating copper 32. The creepage portion 35 is a portion that ensures insulation between the mounted copper 31 and the heat-dissipating copper 32.

[0036] <Third substrate> As shown in Figure 1, the third substrate 50 is placed on the semiconductor chips 11 and 12. The third substrate 50 is positioned opposite the source electrodes 11b and 12b. The third substrate 50 is a wiring member that electrically connects the high-side switch 11 and the low-side switch 12.

[0037] The third substrate 50 comprises a first mounted copper 51a, a second mounted copper 51b, a heat-dissipating copper 52, and an insulating layer 53. The first mounted copper 51a and the second mounted copper 51b are in contact with the insulating layer 53 on the surfaces facing the insulating layer 53. The heat-dissipating copper 52 is in contact with the insulating layer 53 on the surface facing the insulating layer 53. Therefore, the third substrate 50 is constructed by stacking the first mounted copper 51a (second mounted copper 51b), the insulating layer 53, and the heat-dissipating copper 52 in this order.

[0038] As shown in Figure 1, the first mounted copper 51a and the second mounted copper 51b are provided on the same surface of the insulating layer 53. However, as shown in Figure 5, the first mounted copper 51a and the second mounted copper 51b are not in contact but are arranged at a distance from each other. Thus, the third substrate 50 is provided with the first mounted copper 51a and the second mounted copper 51b as a single substrate. The first mounted copper 51a and the second mounted copper 51b are made of the same material as the mounted copper 21.

[0039] The first mounted copper 51a has a rectangular shape in plan view. The first mounted copper 51a is provided extending from the region opposite the source electrode 11b to the region opposite the mounted copper 31.

[0040] The first mounted copper 51a is connected to the source electrode 11b of the high-side switch 11. More specifically, the first mounted copper 51a is connected to the first terminal 61 by solder 73. The first terminal 61 is then connected to the source electrode 11b. Therefore, the first mounted copper 51a is connected to the source electrode 11b via the first terminal 61.

[0041] Furthermore, the first mounted copper 51a is connected to the mounted copper 31. More specifically, the first mounted copper 51a is connected to the joint terminal 63 by solder 78. The joint terminal 63 is then connected to the mounted copper 31. Therefore, the first mounted copper 51a is connected to the mounted copper 31 via the joint terminal 63. Note that the high-side switch 11 corresponds to a single semiconductor element. The first mounted copper 51a corresponds to the first wiring board.

[0042] The second mounted copper 51b has a shape that partially surrounds the first mounted copper 51a in a plan view. The second mounted copper 51b is integrally provided with a portion adjacent to the first mounted copper 51a in the X direction and two portions adjacent to the first mounted copper 51a in the Y direction. Therefore, the second mounted copper 51b has a shape in which a part of the annular structure is divided as an electrical path.

[0043] The second mounted copper 51b is connected to the source electrode 12b of the low-side switch 12. More specifically, the second mounted copper 51b is connected to the second terminal 62 by solder 76. The second terminal 62 is connected to the source electrode 12b. Therefore, the second mounted copper 51b is connected to the source electrode 12b via the second terminal 62. The second terminal 62 is connected to the portion of the second mounted copper 51b adjacent to the first mounted copper 51a in the X direction. In addition, the negative electrode terminals 42 are connected to two portions of the second mounted copper 51b adjacent to the first mounted copper 51a in the Y direction.

[0044] Note that the low-side switch 12 corresponds to other semiconductor elements. The second mounted copper 51b corresponds to the second wiring board. The negative terminal 42 corresponds to the second main terminal.

[0045] The heat-dissipating copper 52 is made of the same material as the mounted copper 21. The heat-dissipating copper 52 has an outer surface opposite to the surface facing the insulating layer 53 that is exposed from the sealing resin part 90. The heat-dissipating copper 52 is a component that dissipates heat emitted from the semiconductor chips 11 and 12. In other words, the heat-dissipating copper 52 receives heat from the semiconductor chips 11 and 12 via the insulating layer 53 and dissipates that heat to the outside of the sealing resin part 90. Like the mounted copper 21 and 31, the heat-dissipating copper 52 has a V-cut portion 54 on its side.

[0046] Furthermore, the mounted copper 51a, 51b and the heat-dissipating copper 52 can be made primarily of metals other than copper. In the third substrate 50, the heat-dissipating copper 52 is thicker than the mounted copper 51a, 51b. However, the heat-dissipating copper 52 and the mounted copper 51a, 51b may have the same thickness. Moreover, the mounted copper 51a, 51b may be thicker than the heat-dissipating copper 52.

[0047] The insulating layer 53 is placed between the mounted copper 51a, 51b and the heat dissipation copper 52, and is a component that electrically insulates the mounted copper 51a, 51b from the heat dissipation copper 52.

[0048] <Sealing resin part 90> The sealing resin portion 90 integrally covers the semiconductor chips 11, 12, the first substrate 20, the second substrate 30, terminals 41-45, the third substrate 50, terminals 61-63, solder 71-78, and bonding wires 80. As a result, the semiconductor device 101 can protect the semiconductor chips 11, 12 and other components from the external environment.

[0049] Furthermore, the opposite side of each heat-dissipating copper 22, 32, and 52 from the surface facing the insulating layers 23, 33, and 53 is exposed from the sealing resin portion 90. This improves the heat dissipation performance of the semiconductor device 101.

[0050] As shown in Figure 5, terminals 41 to 45 are partially exposed from the sealing resin portion 90, while the remaining portion is covered by the sealing resin portion 90. The positive terminal 41, the negative terminal 42, and the gate terminal 45 on the high-side switch 11 side protrude from the sealing resin portion 90 in the same direction. The output terminal 43, the gate terminal 45 on the low-side switch 12 side, and the signal terminal 44 protrude from the sealing resin portion 90 in the same direction. The positive terminal 41 and the output terminal 43 protrude in the opposite direction relative to the sealing resin portion 90.

[0051] As described above, the semiconductor device 101 has a configuration in which semiconductor chips 11 and 12 are sandwiched between the first substrate 20, the second substrate 30, and the third substrate 50. Therefore, the semiconductor device 101 has a double-sided heat dissipation structure.

[0052] <Manufacturing method> The manufacturing method of the semiconductor device 101 will be explained using Figures 2, 3, 4, and 5. First, as shown in Figure 2, a lead frame 1 on which terminals 41 to 45 are integrally provided, a first substrate 20, and a second substrate 30 are prepared. The lead frame 1 is placed on a base together with the first substrate 20 and the second substrate 30. At this time, the lead frame 1 is positioned by positioning pins 200. The lead frame 1 is also provided with through holes 411 as reference holes. The positioning pins 200 are also passed through these through holes 411. In this way, the lead frame 1 is positioned relative to the first substrate 20 and the second substrate 30.

[0053] In this configuration, as shown in Figure 3, one end of the positive terminal 41 of the lead frame 1 is positioned on the mounted copper 21. Also, one end of the output terminal 43 of the lead frame 1 is positioned on the mounted copper 31. The negative terminal 42 is connected to the first mounted copper 51a. Therefore, as shown in Figure 4, the negative terminal 42 is separated from the mounted copper 21.

[0054] With the lead frame 1 positioned as described above, one end of the positive terminal 41 and the mounted copper 21 are connected by ultrasonic bonding. Similarly, one end of the output terminal 43 and the mounted copper 31 are connected by ultrasonic bonding.

[0055] Subsequently, the negative terminal 42 is connected to the first mounted copper 51a. The signal terminal 44 and gate terminal 45 are connected to the pads of the semiconductor chips 11 and 12 via bonding wires 80. As shown in Figure 5, a sealing resin portion 90 is formed to integrally cover the semiconductor chips 11 and 12, the first substrate 20, the second substrate 30, terminals 41 to 45, the third substrate 50, terminals 61 to 63, solder 71 to 78, and bonding wires 80. Each terminal 41 to 45 is separated from the frame portion of the lead frame on which the sealing resin portion 90 is formed.

[0056] <Effects> The semiconductor device 101 includes a first substrate 20 and a second substrate 30, on which each semiconductor chip 11 and 12 is individually mounted, as a wiring board. Therefore, the semiconductor device 101 does not require processing of the wiring board by cutting or other means to mount the semiconductor chips 11 and 12 which have different potentials. Thus, the semiconductor device 101 can be manufactured at a lower cost.

[0057] Furthermore, in the first substrate 20 and the second substrate 30, the thickness of the mounted copper 21 and 31 is greater than the thickness of the heat dissipation copper 22 and 32. As a result, the semiconductor device 101 can improve the heat dissipation performance of the heat emitted from the semiconductor chips 11 and 12 compared to a configuration in which the heat dissipation copper 22 and 32 is thicker than the mounted copper 21 and 31.

[0058] In the semiconductor device 101, the third substrate 50 on the source electrode 11b, 12b side is constructed as a single integrated unit as described above. Therefore, the semiconductor device 101 can have the wiring from the positive terminal 41 to the output terminal 43 and the wiring from the output terminal 43 to the negative terminal 42 facing each other. In addition, the semiconductor device 101 can reduce the size of the loop from the positive terminal 41 to the negative terminal 42. Therefore, the semiconductor device 101 can achieve low inductance.

[0059] Preferred embodiments of the present disclosure have been described above. However, the present disclosure is not limited to the above embodiments, and various modifications are possible without departing from the spirit of the present disclosure. Below, modifications 1 and 2 are described as other forms of the present disclosure. The above embodiments and modifications 1 and 2 can be implemented individually, but they can also be implemented in various combinations as appropriate. The present disclosure can be implemented in various combinations, not limited to the combinations shown in the embodiments.

[0060] (Variation 1) Figure 6 will be used to describe the semiconductor device 102 of the modified example 1. Here, we will mainly describe the differences between the semiconductor device 102 and the semiconductor device 101. The configuration of the first mounted copper 51a and the second mounted copper 51b in the semiconductor device 102 differs from that of the semiconductor device 101.

[0061] The first mounted copper 51a is provided with solder absorption grooves 55 capable of accommodating solder 73 and 78 that overflow from the areas opposite the first terminal 61 and the joint terminal 63. The second mounted copper 51b is provided with solder absorption grooves 55 capable of accommodating solder 76 that overflows from the area opposite the second terminal 62. The solder absorption grooves 55 are recessed areas compared to the surrounding area. The solder absorption grooves 55 correspond to recesses.

[0062] (Modification 2) Figure 7 will be used to describe the semiconductor device 103 of the modified example 2. Here, we will mainly describe the differences between the semiconductor device 103 and the semiconductor device 101. The configuration of the first substrate 20 of the semiconductor device 103 differs from that of the semiconductor device 101.

[0063] The heat-dissipating copper 22 is provided around the area opposite the connection between the mounted copper 21 and the positive terminal 41. In other words, the insulating layer 23 has a non-formed portion 26 in the opposing region where the heat-dissipating copper 22 is formed.

[0064] When ultrasonic bonding is performed between the positive electrode terminal 41 and the mounted copper 21, there is a possibility that the insulating layer 23 of the first substrate 20 may crack. Even if the insulating layer 23 of the first substrate 20 cracks, the insulating properties between the mounted copper 21 and the heat dissipation copper 22 can be ensured.

[0065] This disclosure is described in accordance with embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, while various combinations and forms are shown in this disclosure, other combinations and forms that include one, more, or fewer of those elements also fall within the scope and idea of ​​this disclosure. [Explanation of symbols]

[0066] 11...High-side switch, 11a...Drain electrode, 11b...Source electrode, 12...Low-side switch, 12a...Drain electrode, 12b...Source electrode, 20...First substrate, 21...Mounted copper, 22...Heat dissipation copper, 23...Insulating layer, 24...V-cut section, 25...Creepage area, 26...Unformed area, 30...Second substrate, 31...Mounted copper, 32...Heat dissipation copper, 33...Insulating layer, 34...V-cut section, 35...Creepage area, 41...Positive terminal, 42...Negative terminal Child, 43…Output terminal, 44…Signal terminal, 45…Gate terminal, 411…Through hole, 50…Third substrate, 51a…First mounted copper, 51b…Second mounted copper, 52…Heat dissipation copper, 53…Insulating layer, 54…V-cut section, 55…Solder absorption groove, 61…First terminal, 62…Second terminal, 63…Joint, 71~78…Solder, 80…Bonding wire, 90…Sealing resin section, 101~103…Semiconductor equipment, 200…Positioning pin

Claims

1. A semiconductor element (11, 12) having first electrodes (11a, 12a) on one side and second electrodes (11b, 12b) on the opposite side of the same side, with two or more different potentials, Two or more wiring boards (20, 30) on which each semiconductor element is individually mounted, A wiring member (50) that electrically connects each semiconductor element, The device comprises a sealing resin portion (90) that integrally seals the semiconductor element, the wiring substrate, and the wiring member, Each wiring board has mounting metal plates (21, 31) which are mounting areas for each semiconductor element and are connected to the first electrode, heat dissipation metal plates (22, 32) which dissipate heat emitted from the semiconductor element, and insulating layers (23, 33) which are disposed between the mounting metal plates and the heat dissipation metal plates and electrically insulate the mounting metal plates and the heat dissipation metal plates. The heat dissipation metal plate has a side opposite to the side facing the insulating layer that is exposed from the sealing resin portion. The aforementioned mounting metal plate has a thicker plate thickness than the aforementioned heat dissipation metal plate. The wiring member is arranged facing the second electrode of each semiconductor element, and a first wiring board (51a) connected to the second electrode of one semiconductor element and a second wiring board (51b) connected to the second electrode of another semiconductor element are provided as a single substrate. Furthermore, it includes a first main terminal (41) connected to the mounting metal plate on which the semiconductor element connected to the first wiring board is mounted, and a second main terminal (42) connected to the second wiring board, A semiconductor device in which the first main terminal and the second main terminal protrude in the same direction relative to the sealing resin portion.

2. The semiconductor device according to claim 1, wherein the first wiring board and the second wiring board are connected to conductive terminals (61, 62) arranged opposite the second electrode via solder (73, 76), and recesses (55) capable of accommodating the solder that overflows from the opposing region are provided around the opposing region of the terminal.

3. The semiconductor device according to claim 1 or 2, wherein the mounting metal plate has a convex shape on its side surface, and the apex of the convex shape is located on the mounting surface side of the semiconductor element rather than on the contact surface side with the insulating layer.

4. The semiconductor device according to claim 1, wherein the mounting metal plate and the first main terminal are connected by ultrasonic bonding.

5. The semiconductor device according to claim 4, wherein the heat dissipation metal plate is provided around the area opposite the connection portion between the mounting metal plate and the first main terminal.

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