Electronic device and method for manufacturing an electronic device

Abstract

To provide electronic devices that can ensure electrical connection reliability.SOLUTION: An electronic device 100 has a mounted component 20 on which a plurality of component side lands 22 is formed, and a wiring board 10 on which the mounted component 20 is mounted and on which a plurality of substrate side lands 12 is formed. The electronic device 100 is also provided with a plurality of solder balls 24 electrically connecting the component side lands 22 and the substrate side lands 12. The land areas of the component side lands 22 and the substrate side lands 12 are smaller at a farther distance than at a closer distance between the mounted component 20 and the wiring board 10.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to an electronic device and a method for manufacturing the electronic device.

Background Art

[0002] Patent Document 1 discloses an example of an electronic device. The electronic device includes a mother board and a multi-chip module mounted on the mother board. The multi-chip module includes an MCM on which a plurality of semiconductor chips are mounted on the surface of an MCM substrate and the back side is connected to the mother board by a land grid array. The MCM substrate has a region having a curved shape so that the distance from the mother board increases, and chip components of peripheral circuit elements are mounted on the back surface of the region.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, there are portions where the distances are different between two circuit components such as a mother board and a multi-chip module in an electronic device. Due to the distance, there is a risk that connection reliability such as solder non-wetting and adjacent short circuit decreases.

[0005] One of the disclosed objects is to provide an electronic device capable of ensuring electrical connection reliability. Another disclosed object is to provide a method for manufacturing an electronic device capable of ensuring electrical connection reliability.

Means for Solving the Problems

[0006] The electronic device disclosed herein is A first circuit component (20) having multiple first lands (22) formed thereon, The first circuit component is mounted on a second circuit component (10) on which multiple second lands (12) are formed, The device comprises a plurality of solders (24) that electrically connect the first land and the second land, The land area of ​​at least one of the first land and the second land is smaller where the distance between the first circuit component and the second circuit component is greater than where the distance is greater. Ku, The second circuit component comprises an electrically insulating insulating substrate (11) mainly composed of resin, a conductive wiring layer (14) laminated via the insulating substrate, and a conductive interlayer connection part (15) that electrically connects the wiring layers of different layers. The location where the interlayer connection of the second circuit component is provided is a location where the coefficient of linear expansion in the thickness direction of the second circuit component is smaller than that of the surrounding area, and the distance between these areas is greater than that of the surrounding area. The second land, located in the opposing region of the interlayer connection, has a smaller land area than the surrounding second land. It is characterized by the following:

[0007] Therefore, the electronic device can actively wet and spread the solder laterally in areas where the distances are close, thereby suppressing uneven deformation of the solder. Thus, the electronic device can suppress stress concentration on the solder and short circuits between adjacent solder joints caused by uneven deformation. Furthermore, the electronic device can suppress the lateral wetting and spreading of solder in areas where the distances are far apart, and can actively extend the solder in the vertical direction. Thus, the electronic device can connect the solder to both the first and second lands. In other words, the electronic device can suppress solder non-wetting. Consequently, the electronic device can ensure the electrical connection reliability between the first and second circuit components. Furthermore, the electronic devices disclosed herein are A first circuit component (20) having multiple first lands (22) formed thereon, The first circuit component is mounted on a second circuit component (10) on which multiple second lands (12) are formed, The device comprises a plurality of solders (24) that electrically connect the first land and the second land, The land area of ​​at least one of the first land and the second land is smaller where the distance between the first circuit component and the second circuit component is greater than where the distance is greater. The second circuit component comprises an electrically insulating insulating substrate (11) mainly composed of resin, a conductive wiring layer (14) laminated via the insulating substrate, and a conductive interlayer connection part (15) that electrically connects the wiring layers of different layers. The location where the interlayer connection of the second circuit component is provided is a location where the coefficient of linear expansion in the thickness direction of the second circuit component is smaller than that of the surrounding area, and the distance between these areas is greater than that of the surrounding area. The first land provided in the opposing region of the interlayer connection is characterized by having a smaller land area than the surrounding first land.

[0008] The method for manufacturing an electronic device disclosed herein is: A method for manufacturing an electronic device, comprising: a first circuit component (20) having a plurality of first lands (22); a second circuit component (10) having a plurality of second lands (12); and a plurality of solder joints (24) for electrically connecting the first lands and the second lands. A land forming step of forming at least one of the first lands and the second lands. A step performed after the land forming step, in which the first circuit component is placed on the second circuit component with solder disposed between the first land and the second land. A step performed after the placement step, in which the solder is melted to connect the first land and the second land, comprising a reflow step. In the land forming step, based on interval information correlated with the interval between the first circuit component and the second circuit component due to deformation of at least one of the first circuit component and the second circuit component during the reflow step, the area of at least one of the first land and the second land is made smaller at locations farther away than at locations where the interval is small. death, The second circuit component comprises an electrically insulating insulating substrate (11) mainly composed of resin, a conductive wiring layer (14) laminated via the insulating substrate, and a conductive interlayer connection part (15) that electrically connects the wiring layers of different layers. In the land formation process, based on information regarding the interlayer connection portion in the second circuit component as spacing information, the land area of ​​the second land provided in the region opposite the interlayer connection portion is made smaller than that of the surrounding second lands. Characterized in that.

[0009] Therefore, with this manufacturing method, an electronic device as described above can be manufactured. Thus, this manufacturing method can manufacture an electronic device capable of ensuring electrical connection reliability between the first circuit component and the second circuit component. Furthermore, the method for manufacturing the electronic device disclosed herein is A method for manufacturing an electronic device comprising a first circuit component (20) having a plurality of first lands (22) formed thereon, a second circuit component (10) having a plurality of second lands (12) formed thereon, and a plurality of solders (24) electrically connecting the first lands and the second lands, A land formation step that forms at least one of the first land and the second land, This process is performed after the land formation process, and involves a placement process in which the first circuit component is placed on the second circuit component with solder already placed between the first land and the second land. This process is performed after the placement process and includes a reflow process in which solder is melted to connect the first land and the second land. In the land formation process, based on spacing information correlated with the distance between the first and second circuit components due to the deformation of at least one of the first and second circuit components during the reflow process, the area of ​​at least one of the first and second lands is reduced in areas further apart than in areas closer together. The second circuit component comprises an electrically insulating insulating substrate (11) mainly composed of resin, a conductive wiring layer (14) laminated via the insulating substrate, and a conductive interlayer connection part (15) that electrically connects the wiring layers of different layers. The land formation process is characterized by making the land area of ​​the first land provided in the region opposite the interlayer connection portion of the second circuit component smaller than that of the surrounding first lands, based on information regarding the interlayer connection portion as spacing information.

[0010] The various embodiments disclosed in this specification employ different technical means to achieve their respective objectives. The claims and the reference numerals in parentheses in this section are illustrative in their correspondence with the embodiments described later and are not intended to limit the technical scope. The objectives, features, and effects disclosed in this specification will become clearer by referring to the subsequent detailed description and the accompanying drawings. [Brief explanation of the drawing]

[0011] [Figure 1] This is a plan view showing the schematic configuration of an electronic device. [Figure 2] This is a cross-sectional view along the line II-II in Figure 1. [Figure 3] This is a magnified cross-sectional view of the solder ball portion. [Figure 4] This is a plan view showing the schematic configuration of a wiring board. [Figure 5] This is a plan view showing the schematic configuration of the mounted components. [Figure 6] This is a cross-sectional view showing the schematic configuration of the wiring board and mounted components before the reflow process. [Figure 7] This is a cross-sectional view showing the schematic configuration of the electronic device according to the second embodiment. [Figure 8] This is a plan view showing the schematic configuration of the wiring board of the second embodiment. [Figure 9] This is a plan view showing the schematic configuration of the mounted components in the second embodiment. [Figure 10] This is a cross-sectional view showing the schematic configuration of the wiring board and mounted components before the reflow process in the second embodiment. [Figure 11] This is a plan view showing the schematic configuration of the electronic device of the third embodiment. [Figure 12] This is a cross-sectional view along the line XII-XII in Figure 11. [Figure 13] This is a cross-sectional view showing the schematic configuration of the electronic device according to the fourth embodiment. [Figure 14] This is a plan view showing the schematic configuration of the wiring board of the fourth embodiment. [Figure 15]This is a plan view showing the schematic configuration of the mounted components in the fourth embodiment. [Figure 16] This is a cross-sectional view showing the schematic configuration of the wiring board and mounted components before the reflow process in the fourth embodiment. [Figure 17] This is a cross-sectional view showing the schematic configuration of the electronic device according to the fifth embodiment. [Modes for carrying out the invention]

[0012] In the following, several embodiments for implementing this disclosure will be described with reference to the drawings. In each embodiment, parts corresponding to matters described in a prior embodiment may be denoted by the same reference numerals, and redundant descriptions may be omitted. If only a part of the configuration is described in each embodiment, other parts of the configuration can be referred to and applied to other embodiments described in advance.

[0013] In the following, the three mutually orthogonal directions will be referred to as the X direction, Y direction, and Z direction. Furthermore, the plane defined by the X direction and the Y direction will be referred to as the XY plane, the plane defined by the X direction and the Z direction will be referred to as the XZ plane, and the plane defined by the Y direction and the Z direction will be referred to as the YZ plane.

[0014] (First Embodiment) The electronic device 100 of the first embodiment will be described with reference to Figures 1 to 6. As shown in Figures 1 and 2, the electronic device 100 comprises a wiring board 10 and mounted components 20 mounted on the wiring board 10. The electronic device 100 also comprises a plurality of solder balls 24.

[0015] The electronic device 100 is arranged such that the opposing surface S11 of the mounted component 20 faces one surface S1 of the wiring board 10. Furthermore, the wiring board 10 and the mounted component 20 are stacked in the Z direction of the electronic device 100. The wiring board 10 and the mounted component 20 are electrically connected via solder balls 24.

[0016] More specifically, the solder ball 24 electrically connects the circuit board-side land 12 and the component-side land 22, which will be explained later. Furthermore, the mounted component 20 is electrically connected to the wiring sections 14 and 15 of the wiring board 10 via the solder ball 24. The electronic device 100 forms a circuit through the electrical connection between the wiring board 10 and the mounted component 20. The electronic device 100 can be applied to control devices and the like.

[0017] Thus, the electronic device 100 can be said to include a wiring board 10 and mounted components 20 as circuit components that constitute a circuit. Furthermore, the electronic device 100 can be said to include a pair of circuit components, namely the wiring board 10 and the mounted components 20. In this embodiment, the wiring board 10 corresponds to the second circuit component, and the mounted components 20 correspond to the first circuit component.

[0018] In this embodiment, an electronic device 100 equipped with one mounted component 20 is used as an example. However, this disclosure is not limited thereto. The electronic device 100 may have multiple mounted components 20 mounted on the wiring board 10. Furthermore, mounted components 20 may also be mounted on the back side S2, which is the opposite side of the front side S1 of the wiring board 10.

[0019] <Wiring board> As shown in Figure 2, the wiring board 10 comprises an electrically insulating base material 11 and conductive wiring portions 14 and 15 provided on the base material 11. The wiring board 10 also includes a substrate-side protective film 13 that covers the base material 11 and a portion of the wiring portions 14 and 15. The base material 11 is, for example, a substrate mainly composed of resin. The base material 11 corresponds to an insulating substrate.

[0020] The substrate-side protective film 13 covers a portion of the base material 11 and a portion of the wiring portions 14 and 15 for the purpose of protecting against the adhesion of dust and other debris, as well as damage. The portion of the base material 11 is the surface on one side S1, which is the area where the wiring portions 14 and 15 are not provided. The portion of the wiring portions 14 and 15 is a portion of the wiring layer 14 in the wiring portions 14 and 15. Furthermore, the portion of the wiring layer 14 is the portion of the wiring layer 14 provided on one side S1, excluding the substrate-side lands 12. In other words, the substrate-side protective film 13 covers the wiring layer 14 provided on one side S1 of the base material 11 so that the substrate-side lands 12 are exposed. It can also be said that the wiring board 10 has multiple substrate-side lands 12 exposed on one side S1.

[0021] The substrate-side land 12, exposed from the substrate-side protective film 13, functions as an electrode for external connection. Solder balls 24 are connected to the substrate-side land 12. External connection refers to its use in connecting to mounted components 20 and other components located outside the wiring board 10.

[0022] The wiring sections 14 and 15 include wiring layers 14 laminated via a substrate 11 and interlayer connection sections 15 that electrically connect wiring layers 14 of different layers. The wiring layers 14 are provided inside the substrate 11 and on the surface of the substrate 11. The wiring layers 14 also include substrate-side lands 12. The substrate-side lands 12 are portions of the wiring layers 14 that are exposed from the substrate 11 and the substrate-side protective film 13. The wiring substrate 10 has a plurality of substrate-side lands 12. The substrate-side lands 12 correspond to second lands. Thus, in this embodiment, a multilayer substrate in which wiring layers 14 are laminated is used as the wiring substrate 10. However, this disclosure is not limited thereto.

[0023] The substrate 11 and the wiring sections 14 and 15 have different coefficients of thermal expansion. Therefore, the wiring board 10 may warp during the reflow process, which will be explained later. In this embodiment, as an example, a case where the board warps upward in the XZ and YZ planes is adopted. Therefore, at least when the mounted components 20 are attached, one surface S1 of the wiring board 10 is not parallel to the XY plane. However, the warp shape of the wiring board 10 is not limited to this.

[0024] <Mounted Components> As shown in Figure 2, the mounted component 20 includes a semiconductor chip, an electrically insulating component-side resin part 21, and conductive component-side lands 22. The component-side resin part 21 is a component that covers the semiconductor chip. The component-side lands 22 are electrically connected to the semiconductor chip via conductive wiring. The mounted component 20 has multiple component-side lands 22.

[0025] Furthermore, the mounted component 20 is provided with a component-side protective film 23 so that the component-side land 22 is exposed. The component-side protective film 23 covers a portion of the component-side resin portion 21 for the purpose of protecting against the adhesion of dust and other debris, as well as damage. The portion of the component-side resin portion 21 is the part excluding the component-side land 22 on the opposing surface S11 side. The mounted component 20 has an opposing surface S11 with respect to the wiring board 10, and a non-opposing surface S12 which is the opposite surface of the opposing surface S11.

[0026] The component-side land 22, exposed from the component-side protective film 23, functions as an electrode for external connection. The mounted component 20 can also be described as having multiple component-side lands 22 exposed on its opposing surface S11. Solder balls 24 are connected to the component-side land 22. The mounted component 20 is mounted on the wiring board 10 via the solder balls 24 connected to the component-side land 22. For this reason, the mounted component 20 can be described as a surface-mount type circuit component. Note that "for external connection" refers to its use in connecting to the wiring board 10 or other externally located components. The component-side land 22 corresponds to the first land.

[0027] Furthermore, discrete components and module components can be used as the mounted components 20. Discrete components are electronic components with a single function, such as MOSFETs, IGBTs, diodes, and resistors. Module components are electronic components that provide a system using multiple semiconductor chips. Module components can also be called system-on-a-chip (SoC) or multi-chip modules. Module components tend to be larger in size than discrete components. Therefore, module components can be considered large components, and discrete components can be considered small components.

[0028] The resin portion 21 on the component side and the semiconductor chip and the land 22 on the component side have different coefficients of thermal expansion. Therefore, the mounted component 20 may warp when subjected to the reflow process, which will be explained later. In this embodiment, as an example, a case in which the component warps downward in the XZ plane and the YZ plane is adopted. Therefore, at least when mounted on the wiring board 10, the opposing surface S11 of the mounted component 20 is not parallel to the XY plane.

[0029] However, the curvature of the mounted component 20 is not limited to this. Furthermore, mounted components 20 can be those that do not have a curvature. In addition, the electronic device 100 may include mounted components 20 with a curvature and mounted components 20 without a curvature. Note that mounted components 20 without a curvature have opposing surfaces S11, etc., that are parallel to the XY plane.

[0030] <Land, solder> Here, we will explain the substrate-side land 12, the component-side land 22, and the solder ball 24 using Figures 3, 4, and 5.

[0031] The symbols in Figure 3 are as follows: The symbol GP indicates the gap (distance) between the wiring board 10 and the mounted component 20. A gap GP=L indicates a large gap. A gap GP=S indicates a small gap. The magnitude of the gap GP is, for example, its relationship to a reference value of the gap GP. Here, the gap GP uses the distance between the end of the board-side land 12 and the end of the component-side land 22. However, the gap GP may also be the distance between the mounted component 20 and the center 122 of the land formation region 121 in Figure 4.

[0032] The symbol LD indicates the land diameter of each land 12 and 22. A land diameter LD=L indicates a large land diameter. A land diameter LD=S indicates a small land diameter. The relative size of the land diameter LD is, for example, its relationship to a reference value.

[0033] In this embodiment, nearly circular lands 12 and 22 are used. Therefore, the land diameter LD is used here as a value correlated with the land area of ​​each land 12 and 22. In other words, each land 12 and 22 can be considered to have a large land area when the land diameter is large, and a small land area when the land diameter is small. Thus, the land diameter LD corresponds to the land area.

[0034] However, this disclosure is not limited thereto. Each land 12, 22 may have a shape other than an ellipse or a circle. In this case, the land area of ​​each land 12, 22 is used instead of the land diameter LD. The land area of ​​the substrate-side land 12 is the area of ​​the surface exposed to the side S1. On the other hand, the land area of ​​the component-side land 22 is the area of ​​the surface exposed to the opposite side S11.

[0035] Furthermore, the symbol BH indicates the ball height of the solder ball 24. A ball height BH=H indicates a high ball height. A ball height BH=L indicates a low ball height. Note that the high or low ball height BH is related to, for example, a reference value for ball height BH. The ball height BH is the height in the Z direction passing through the center of the solder ball 24.

[0036] As shown in Figures 3, 4, and 5, the land diameter LD, i.e., land area, of the substrate-side land 12 and the component-side land 22 differs depending on the location. More specifically, the wiring board 10 and the mounted component 20 have warping as described above. Therefore, the gap GP differs depending on the location of the wiring board 10 and the mounted component 20.

[0037] As shown in Figure 3, the land diameter LD is smaller where the gap GP is larger than where the gap GP is smaller. In other words, the land diameter LD is smaller on the GP=L side than on the GP=S side. Therefore, the land diameter LD is LD=L on the GP=S side and LD=S on the GP=L side. To put it another way, the land area is smaller where the gap GP is larger than where the gap GP is smaller.

[0038] Note that areas with a small gap GP correspond to areas where the distance between the wiring board 10 and the mounted components 20 is close. Areas with a large gap GP correspond to areas where the distance between the wiring board 10 and the mounted components 20 is far.

[0039] Incidentally, as shown in Figure 4, the wiring board 10 has multiple board-side lands 12 in the region opposite the mounted component 20. Furthermore, in that opposing region, for example, three board-side lands 12 with land diameters LD are provided. In the region where the gap GP = L, a board-side land 12 with land diameter LD = S is provided. Also, in the region where the gap GP = S, a board-side land 12 with land diameter LD = L is provided. And in the region where the gap GP is the gap reference value, a board-side land 12 with land diameter LD that is larger than land diameter LD = S and smaller than land diameter LD = L is provided. In other words, in the region where the gap GP is the gap reference value, a board-side land 12 with land diameter LD that is the reference value is provided.

[0040] On the other hand, as shown in Figure 5, the mounted component 20 is provided with a component-side land 22 that is the same size as the land diameter LD of the opposing substrate-side land 12. Thus, in this embodiment, it can be said that a constant land diameter LD = L and a constant land diameter LD = S are adopted.

[0041] However, this disclosure is not limited thereto. This disclosure can also be applied to lands 12,22 having only two land diameters LD, LD=L and LD=S, depending on the size of the gap GP. Furthermore, this disclosure can also be applied to lands 12,22 having four or more land diameters LD depending on the size of the gap GP. In other words, this disclosure can also be applied to lands 12,22 where the land diameter LD gradually decreases as the gap GP increases.

[0042] Furthermore, this disclosure allows at least one of the substrate-side land 12 and the component-side land 22 to have different land diameters LD depending on the location, as described above. For example, the land diameter LD of the substrate-side land 12 may be smaller in areas with a larger gap GP than in areas with a smaller gap GP. This allows the electronic device 100 to be used even if the mounted component 20 has multiple component-side lands 22 with all the same land diameter LD. In other words, the electronic device 100 can be used even if the mounted component 20 has multiple component-side lands 22 with predetermined land diameters LD. This point can also be applied to other embodiments.

[0043] Multiple solder balls 24 are provided between the wiring board 10 and the mounted components 20. All of the solder balls 24 have the same volume. However, as shown in Figure 3, the shape of the solder balls 24 differs depending on the size of the land diameter LD. The larger the land diameter LD, the more the solder ball 24 spreads out in the lateral direction, and the smaller the land diameter LD, the more it extends in the height direction. The height direction is the Z direction. The lateral direction is the direction along the XY plane.

[0044] <Manufacturing method> The manufacturing method of the electronic device 100 will be explained using Figures 4, 5, and 6.

[0045] This manufacturing method comprises an information acquisition step, a land formation step, a placement step, and a reflow step. The manufacturing method is performed in the following order: information acquisition step, land formation step, placement step, and reflow step. This manufacturing method is a process executed by the manufacturing equipment.

[0046] First, in the information acquisition process, spacing information is acquired based on the warping behavior of the wiring board 10 and mounted components 20 at the ambient temperature during the reflow process. The spacing information is information correlated with the gap GP due to the deformation of the wiring board 10 and mounted components 20 during the reflow process. For example, the spacing information is associated with the positional information of each land 12, 22 and the gap GP between each land 12, 22.

[0047] In the information acquisition process, the reflow process is actually performed in a reflow oven on the wiring board 10 and mounted components 20. For example, when mass-producing electronic devices 100, the reflow process is performed on one of the wiring boards 10 and one of the mounted components 20 that will actually be used in the electronic devices 100 for measurement purposes. In addition, the reflow process is performed on boards and components similar to the wiring board 10 and mounted components 20 that will actually be used in the electronic devices 100 for measurement purposes. Note that multiple wiring boards 10 and multiple mounted components 20 may be used for measurement purposes.

[0048] In the information acquisition process, the warping behavior of the wiring board 10 and mounted components 20 after the reflow process is determined. For example, a measuring device equipped with a computer is used to measure the gap GP between each land 12, 22 on the wiring board 10 and mounted components 20. The positional information of each land 12, 22 and the gap GP between each land 12, 22 are then associated and stored in the computer's memory. Note that the gap GP may be the average value of values ​​measured for multiple wiring boards 10 and multiple mounted components 20.

[0049] The information acquisition process is not limited to the above. The information acquisition process only needs to be able to acquire interval information. Furthermore, this manufacturing method does not even need to include an information acquisition process. The interval information can be pre-set estimated values ​​or the like.

[0050] In the land formation process, substrate-side lands 12 and component-side lands 22 are formed. In the land formation process, substrate-side lands 12 and component-side lands 22 are formed by well-known plating or etching processes. As shown in Figures 4 and 5, in the land formation process, based on spacing information, substrate-side lands 12 and component-side lands 22 are formed such that the land diameter is smaller in areas with a larger gap GP than in areas with a smaller gap GP.

[0051] As described above, the electronic device 100 only needs to have at least one of the substrate-side lands 12 and the component-side lands 22 have different land diameters LD depending on their location. Therefore, the land formation process may only form at least one of the substrate-side lands 12 and the component-side lands 22. In other words, the land formation process may only form the one of the substrate-side lands 12 and the component-side lands 22 whose land diameters LD differ depending on their location. In particular, the land formation process may only form the substrate-side lands 12. This point can also be applied to other embodiments.

[0052] Next, the placement process is performed after the land formation process. As shown in Figure 6, in the placement process, solder balls 24 are placed between the substrate-side land 12 and the component-side land 22, and the mounted components 20 are placed on the wiring board 10. The placement process is performed using a transport robot or the like.

[0053] The reflow process is performed after the placement process. The reflow process is carried out using a reflow oven and a transport device. The reflow oven is at a temperature above the melting point of the solder balls 24. In the reflow process, the wiring board 10 and mounted components 20, which are stacked via the solder balls 24, are placed (transported) into the reflow oven. Then, in the reflow process, the solder balls 24 are melted to connect the board-side lands 12 and the component-side lands 22. As a result, an electronic device 100 can be manufactured using this manufacturing method.

[0054] <Effects> As described above, the electronic device 100 is configured such that the land diameter LD of lands 12 and 22 is smaller in areas where the gap GP is larger than in areas where the gap GP is smaller. Therefore, the electronic device 100 can actively wet and spread the solder balls 24 laterally in areas where the land diameter LD is large, i.e., in areas where the gap GP is small. As a result, the electronic device 100 can suppress distorted deformation of the solder balls 24. Furthermore, the electronic device 100 can suppress stress concentration on the solder balls 24 and short circuits between adjacent solder balls 24 caused by distorted deformation of the solder balls 24.

[0055] Furthermore, the electronic device 100 can suppress the lateral wetting and spreading of the solder balls 24 in areas where the land diameter LD is small, i.e., where the gap GP is large. Therefore, the electronic device 100 can actively extend the solder balls 24 in the height direction. Thus, the electronic device 100 can connect the solder balls 24 to both the substrate-side land 12 and the component-side land 22. In other words, the electronic device 100 can suppress non-wetting of the solder balls 24.

[0056] Therefore, the electronic device 100 can suppress both short circuits and non-wetting of solder balls 24, even if there is warping in the wiring board 10 and the mounted components 20. In other words, the electronic device 100 can ensure the electrical connection reliability between the wiring board 10 and the mounted components 20.

[0057] Incidentally, it is conceivable that warping will be more pronounced in larger module components than in smaller discrete components. However, as described above, the electronic device 100 can suppress both short circuits and non-wetting of solder balls 24. Therefore, even large components can be mounted on the wiring board 10 as part of the electronic device 100.

[0058] Furthermore, warping of the wiring board 10 and mounted components 20 can be suppressed by the arrangement of conductive materials, etc. For example, warping of the wiring board 10 can be suppressed by the layout of the wiring sections 14 and 15. However, as described above, the electronic device 100 can suppress both short circuits and non-wetting of the solder balls 24 even if it is warped. Therefore, the electronic device 100 can eliminate constraints on arrangement and other matters related to warping suppression. As a result, the electronic device 100 can improve the design freedom regarding the wiring sections 14 and 15, etc. Furthermore, the electronic device 100 can improve the yield of the wiring board 10 and mounted components 20.

[0059] Furthermore, the electronic device 100 may change the size of the solder balls 24 depending on the size of the gap GP. In other words, it may change the amount of solder balls 24. For example, the electronic device 100 may make the solder balls 24 larger in areas with a smaller gap GP than in areas with a larger gap GP. This makes it easier for the electronic device 100 to actively extend the solder balls 24 in the height direction.

[0060] This manufacturing method can produce an electronic device 100. Therefore, this manufacturing method can produce an electronic device 100 that can ensure the electrical connection reliability between the wiring board 10 and the mounted components 20.

[0061] Preferred embodiments of the present disclosure have been described above. However, the present disclosure is not limited in any way to the above embodiments, and various modifications are possible without departing from the spirit of the present disclosure. Below, second to fifth embodiments of the present disclosure are described as other forms of the present disclosure. The above embodiments and second to fifth embodiments can be implemented individually, but they can also be implemented in various combinations as appropriate. The present disclosure can be implemented in various combinations, not limited to the combinations shown in the embodiments.

[0062] (Second Embodiment) The electronic device 101 of the second embodiment will be described using Figures 7 to 10. Here, we will mainly describe the differences from the electronic device 100. The electronic device 101 differs from the electronic device 100 in the shape of the wiring board 10 and the mounted components 20. Other parts are the same as the electronic device 100.

[0063] As shown in Figure 10, the wiring board 10 and the mounted components 20 have a shape that is almost completely free of warping before the reflow process. However, as shown in Figure 7, the wiring board 10 becomes warped downwards in the XZ and YZ planes after the reflow process. On the other hand, the mounted components 20 become warped upwards in the XZ and YZ planes.

[0064] Therefore, the gap GP is larger near the center in the YX plane and smaller near the outer edge. Thus, as shown in Figures 8 and 9, the land diameter LD is smaller near the center and larger near the outer edge. The electronic device 101 can be manufactured using the same manufacturing method as in the first embodiment. The electronic device 101 can achieve the same effects as in the first embodiment.

[0065] (Third embodiment) The electronic device 102 of the third embodiment will be described using Figures 11 and 12. Here, we will mainly describe the differences from the electronic device 100. The electronic device 102 differs from the electronic device 100 mainly in the shape of the wiring board 10 and the mounted components 20. Other parts are the same as the electronic device 100.

[0066] In this embodiment, as shown in Figure 11, an electronic device 102 is employed that includes other components 30 in addition to the mounted components 20. The other components 30 are elements that constitute a circuit together with the mounted components 20. However, the other components 30 do not have the same significant warping as the mounted components 20. Also, the other components 30 are smaller elements compared to the mounted components 20. The mounted components 20 are larger than the other components 30 and therefore heavier.

[0067] As shown in Figure 12, the wiring board 10 has a shape that follows an upward convex curve, similar to the first embodiment. However, the wiring board 10 may warp due to the weight of the large mounted components 20 in addition to the temperature of the reflow process. The mounted components 20 are mounted on the wiring board 10 at a position offset from the center. Therefore, the wiring board 10 warps more in the area where the mounted components 20 are mounted than in the surrounding area. On the other hand, the mounted components 20 have a shape that follows a downward convex curve, similar to the first embodiment.

[0068] Therefore, as shown in Figure 12, the gap GP is smaller near the center in the YX plane and larger near the outer edge. Consequently, the land diameter LD is larger near the center and smaller near the outer edge. The electronic device 102 can be manufactured using the same manufacturing method as in the first embodiment. The electronic device 102 can achieve the same effects as in the first embodiment.

[0069] (Fourth Embodiment) The electronic device 103 of the fourth embodiment will be described using Figures 13 to 16. Here, we will mainly describe the differences from the electronic device 100. The electronic device 103 differs from the electronic device 100 mainly in the shape of the wiring board 10 and the mounted components 20. Other parts are the same as the electronic device 100.

[0070] As shown in Figure 16, the wiring board 10 includes a substrate-side land 12 located directly above the interlayer connection portion 15, and another substrate-side land 12 located around the area directly above the interlayer connection portion 15. The area where the interlayer connection portion 15 is located on the wiring board 10 has a lower coefficient of thermal expansion in the thickness direction of the wiring board 10 than the area around that portion. Note that "directly above" can also be described as the region opposite the interlayer connection portion 15 in the Z direction.

[0071] The wiring board 10 and mounted components 20 have a shape with almost no warping before the reflow process. Furthermore, as shown in Figure 13, even after the reflow process, the wiring board 10 and mounted components 20 do not warp as much as in the first embodiment.

[0072] However, the wiring board 10 undergoes partial warping due to the reflow process. In other words, the wiring board 10 undergoes partial deformation. In particular, the coefficient of thermal expansion differs between the area where the interlayer connection portion 15 is provided and the surrounding area of ​​the wiring board 10. Therefore, as shown in Figure 13, the area where the interlayer connection portion 15 is provided on the wiring board 10 becomes more recessed than the surrounding area. Consequently, the gap GP in the electronic device 103 is larger at the area where the interlayer connection portion 15 is provided than at the surrounding area.

[0073] Therefore, as shown in Figure 14, the substrate-side land 12 provided in the opposing region of the interlayer connection portion 15 has a smaller area than the surrounding substrate-side land 12. Also, as shown in Figure 15, the component-side land 22 provided in the opposing region of the interlayer connection portion 15 has a smaller area than the surrounding component-side land 22. The electronic device 103 can be manufactured using the same manufacturing method as in the first embodiment. The electronic device 103 can achieve the same effects as in the first embodiment.

[0074] Furthermore, in the electronic device 103, only the substrate-side land 12 provided in the region opposite the interlayer connection portion 15 may have a smaller area than the surrounding substrate-side land 12. In this case, during the land formation process, the area of ​​the substrate-side land 12 provided in the region opposite the interlayer connection portion 15 is made smaller than the surrounding substrate-side land 12 based on information regarding the interlayer connection portion 15 in the wiring board 10 as spacing information. The information regarding the interlayer connection portion 15 in the wiring board 10 is, for example, associated with the position information of the substrate-side land 12 provided in the region opposite the interlayer connection portion 15 and the gap GP between that substrate-side land 12 and the component-side land 22.

[0075] Furthermore, in the electronic device 103, only the component-side land 22 provided in the region opposite the interlayer connection portion 15 may have a smaller area than the surrounding component-side land 22. In this case, during the land formation process, the area of ​​the component-side land 22 provided in the region opposite the interlayer connection portion 15 is made smaller than the surrounding component-side land 22 based on information about the interlayer connection portion 15 in the wiring board 10 as spacing information. The information about the interlayer connection portion 15 in the wiring board 10 is, for example, associated with the position information of the component-side land 22 provided in the region opposite the interlayer connection portion 15 and the gap GP between the component-side land 22 and the substrate-side land 12.

[0076] (Fifth embodiment) The electronic device 104 of the fourth embodiment will be described using Figure 17. Here, we will mainly describe the differences from the electronic device 100. The main difference between the electronic device 104 and the electronic device 100 is that the circuit components are stacked in three layers. Other parts are the same as the electronic device 100. Note that the wiring sections 14 and 15 are omitted in Figure 17.

[0077] The electronic device 100 includes a wiring board 10, mounted components 20, and a semiconductor chip 40 as circuit components. The wiring board 10 is the same as in the first embodiment. The mounted components 20 are module components. The semiconductor chip 40 is a discrete component.

[0078] The electronic device 104 can be said to have two pairs of circuit components: a pair of a wiring board 10 and a mounted component 20, and a pair of a mounted component 20 and a semiconductor chip 40. In the pair of the wiring board 10 and the mounted component 20, the wiring board 10 corresponds to the second circuit component, and the mounted component 20 corresponds to the first circuit component. In the pair of the mounted component 20 and the semiconductor chip 40, the mounted component 20 corresponds to the second circuit component, and the semiconductor chip 40 corresponds to the first circuit component. Furthermore, the pair of the wiring board 10 and the mounted component 20 can also be called the first component pair, and the pair of the mounted component 20 and the semiconductor chip 40 can be called the second component pair.

[0079] The mounted component 20 has a semiconductor chip 40 mounted on it. Therefore, the mounted component 20 also has component-side lands 22 on the non-opposing surface S12. The mounted component 20 has different land diameters LD for the component-side lands 22 on the opposing surface S11 and the component-side lands 22 on the non-opposing surface S22. The land diameter LD of the component-side lands 22 on the opposing surface S11 is defined according to the gap GP between the wiring board 10 and the mounted component 20, as in the first embodiment. On the other hand, the land diameter LD of the component-side lands 22 on the non-opposing surface S22 is defined according to the gap GP between the mounted component 20 and the semiconductor chip 40.

[0080] The semiconductor chip 40 comprises a bare semiconductor chip, a chip-side resin portion 41 covering the bare semiconductor chip, a chip-side land 42 electrically connected to the bare semiconductor chip, and a chip-side protective film 43 provided around the chip-side land 42. Solder balls 44 are connected to the chip-side land 42 of the semiconductor chip 40. The solder balls 44 are also connected to the component-side land 22 on the non-opposing surface S22. The semiconductor chip 40 is mounted on the mounted component 20 via the solder balls 44. Furthermore, the semiconductor chip 40 is electrically connected to the mounted component 20 via the solder balls 44.

[0081] The semiconductor chip 40, like the mounted component 20, may warp due to the reflow process. In this embodiment, the semiconductor chip 40 is used that has a downward convex shape, similar to the mounted component 20, at least after the reflow process.

[0082] However, the semiconductor chip 40 has a different coefficient of thermal expansion than the mounted component 20. Therefore, even though the semiconductor chip 40 has a downward convex shape, its degree of warping differs from that of the mounted component 20. Furthermore, the semiconductor chip 40 is mounted at a position offset from the center of the mounted component 20 in the XY plane. As a result, the gap GP between the semiconductor chip 40 and the non-opposing surface S12 is not uniform across the entire XY plane but varies from place to place. Consequently, the land diameter LD of the chip-side land 42 is smaller where the gap GP is larger than where it is smaller. The same applies to the component-side land 22 on the non-opposing surface S12.

[0083] As shown in Figure 17, the wiring board 10 and the mounted components 20 have the same warped shape as in the first embodiment, at least after the reflow process. Therefore, the gap GP between the wiring board 10 and the mounted components 20 is the same as in the first embodiment. Also, the land diameter LD of the board-side land 12 and the component-side land 22 is the same as in the first embodiment.

[0084] The electronic device 104 can be manufactured using the same manufacturing method as in the first embodiment. The electronic device 104 can achieve the same effects as in the first embodiment. Only the land diameter LD of the land 12 may be sized to match the gap GP between the wiring board 10 and the mounted component 20. The electronic device 104 may have only the component-side land 22 on the opposing surface S11 sized to match the gap GP between the wiring board 10 and the mounted component 20. The electronic device 104 may have only the component-side land 22 on the non-opposing surface S12 sized to match the gap GP between the mounted component 20 and the semiconductor chip 40. The electronic device 104 may have only the chip-side land 42 sized to match the gap GP between the mounted component 20 and the semiconductor chip 40. Any of these configurations can achieve the same effects as in the first embodiment. Furthermore, since electronic devices with these configurations can be manufactured using the same manufacturing method as in the first embodiment, they can achieve the same effects as in the first embodiment.

[0085] The electronic device 104 can also be configured to consist only of a first circuit component and a second circuit component that have a curved shape relationship, such as a second component pair. Even with such a configuration, the same effects as the first embodiment can be achieved by making the land area of ​​at least one of the first land and the second land smaller at locations further away from the gap GP between the first circuit component and the second circuit component than at locations closer to it. Furthermore, since an electronic device with such a configuration can be manufactured using the same manufacturing method as the first embodiment, it can achieve the same effects as the first embodiment.

[0086] This disclosure is described in accordance with embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, while various combinations and forms are shown in this disclosure, other combinations and forms that include one, more, or fewer of those elements also fall within the scope and idea of ​​this disclosure. [Explanation of Symbols]

[0087] 10...Wiring board, 11...Substrate, 12...Substrate-side land, 121:Land formation area, 122...Center, 13...Substrate-side protective film, 14...Wiring layer, 15...Interlayer connection part, 20,40...Mounted components, 21...Component-side resin part, 22...Component-side land, 23...Component-side protective film, 24...Solder, 30...Other components, 40...Semiconductor chip, 100~104...Electronic device

Claims

1. A first circuit component (20) having multiple first lands (22) formed thereon, The first circuit component is mounted on a second circuit component (10) on which a plurality of second lands (12) are formed, The device comprises a plurality of solders (24) that electrically connect the first land and the second land, The land area of ​​at least one of the first land and the second land is smaller at locations farther apart than at locations closer apart than the first circuit component. The second circuit component comprises an electrically insulating insulating substrate (11) mainly composed of resin, a conductive wiring layer (14) laminated via the insulating substrate, and a conductive interlayer connection portion (15) that electrically connects the wiring layers of different layers. The location where the interlayer connection portion of the second circuit component is provided is a location where the coefficient of linear expansion in the thickness direction of the second circuit component is smaller than that of the surrounding area, and where the distance is greater than that of the surrounding area. An electronic device wherein the second land provided in the opposing region of the interlayer connection portion has a smaller land area than the surrounding second land.

2. The electronic device according to claim 1, wherein the land area of ​​the second land is smaller at locations farther apart than at locations closer apart.

3. A first circuit component (20) having multiple first lands (22) formed thereon, The first circuit component is mounted on a second circuit component (10) on which a plurality of second lands (12) are formed, The device comprises a plurality of solders (24) that electrically connect the first land and the second land, The land area of ​​at least one of the first land and the second land is smaller at locations farther apart than at locations closer apart than the first circuit component. The second circuit component comprises an electrically insulating insulating substrate (11) mainly composed of resin, a conductive wiring layer (14) laminated via the insulating substrate, and a conductive interlayer connection portion (15) that electrically connects the wiring layers of different layers. The location where the interlayer connection portion of the second circuit component is provided is a location where the coefficient of linear expansion in the thickness direction of the second circuit component is smaller than that of the surrounding area, and where the distance is greater than that of the surrounding area. An electronic device wherein the first land provided in the opposing region of the interlayer connection portion has a smaller land area than the surrounding first land.

4. A method for manufacturing an electronic device comprising a first circuit component (20) having a plurality of first lands (22) formed thereon, a second circuit component (10) having a plurality of second lands (12) formed thereon, and a plurality of solders (24) electrically connecting the first lands and the second lands, A land forming step of forming at least one of the first land and the second land, A step performed after the land formation step, comprising a placement step in which the first circuit component is placed on the second circuit component with the solder placed between the first land and the second land, The process is performed after the placement process and includes a reflow process in which the solder is melted to connect the first land and the second land, In the land formation process, based on spacing information correlated with the spacing between the first and second circuit components due to the deformation of at least one of the first and second circuit components during the reflow process, the area of ​​at least one of the first and second lands is reduced in areas where the spacing is greater than in areas where it is closer. The second circuit component comprises an electrically insulating insulating substrate (11) mainly composed of resin, a conductive wiring layer (14) laminated via the insulating substrate, and a conductive interlayer connection portion (15) that electrically connects the wiring layers of different layers. A method for manufacturing an electronic device, wherein in the land formation step, based on information relating to the interlayer connection portion in the second circuit component as spacing information, the land area of ​​the second land provided in the region opposite the interlayer connection portion is made smaller than that of the surrounding second land.

5. The method for manufacturing an electronic device according to claim 4, wherein in the land formation step, only the second land is formed.

6. A method for manufacturing an electronic device comprising a first circuit component (20) having a plurality of first lands (22) formed thereon, a second circuit component (10) having a plurality of second lands (12) formed thereon, and a plurality of solders (24) electrically connecting the first lands and the second lands, A land forming step of forming at least one of the first land and the second land, A step performed after the land formation step, comprising a placement step in which the first circuit component is placed on the second circuit component with the solder placed between the first land and the second land, The process is performed after the placement process and includes a reflow process in which the solder is melted to connect the first land and the second land, In the land formation process, based on spacing information correlated with the spacing between the first and second circuit components due to the deformation of at least one of the first and second circuit components during the reflow process, the area of ​​at least one of the first and second lands is reduced in areas where the spacing is greater than in areas where it is closer. The second circuit component comprises an electrically insulating insulating substrate (11) mainly composed of resin, a conductive wiring layer (14) laminated via the insulating substrate, and a conductive interlayer connection portion (15) that electrically connects the wiring layers of different layers. A method for manufacturing an electronic device, wherein in the land formation step, based on information relating to the interlayer connection portion in the second circuit component as spacing information, the land area of ​​the first land provided in the region opposite the interlayer connection portion is made smaller than that of the surrounding first land.

7. A method for manufacturing an electronic device according to any one of claims 4 to 6, further comprising an information acquisition step, which is performed before the land formation step, and which acquires the spacing information based on the warping behavior of the first circuit component and the second circuit component at the ambient temperature during the reflow step.

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