Manufacturing method for semiconductor devices

Abstract

A semiconductor device manufacturing method according to the present disclosure comprises: (A) a step for arranging a first chip on a substrate; (B) a step for arranging a plurality of elevating sections on the substrate around the first chip or around a region in which the first chip is to be arranged; (C) a step for preparing an adhesive section-attached chip including a second chip and an adhesive section provided on one surface of the second chip; (D) and a step for applying a pressing force to the adhesive section-attached chip toward the substrate so that the first chip and at least a part of the elevating sections are embedded in the adhesive section.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] With the increasing multifunctionality of electronic devices, stacked MCP (Multi Chip Package) with increased capacity by stacking semiconductor elements in multiple layers has become widespread. Examples of stacked MCP include wire-embedded and chip-embedded semiconductor packages. The adhesive film used in the manufacture of wire-embedded semiconductor packages is called FOW (Film Over Wire). The adhesive film used in the manufacture of chip-embedded semiconductor packages is called FOD (Film Over Die). As an example of a chip-embedded semiconductor package, a mode in which a controller chip is disposed at the lowermost layer and embedded with a film-like adhesive is known (see Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, with the further miniaturization, thinning, multifunctionality, and high speed of chip-embedded semiconductor devices, the area of the controller chip tends to increase while the area of the chips stacked thereon tends to decrease. That is, the occupied area of the controller chip with respect to the stacked chips tends to increase. In addition, further thinning of the stacked chips is required. Along with these trends, the following problems have become more prominent. · Voids remaining around the controller chip after pressure bonding (generation of voids). • Adhesive used to embed the controller chip may seep out onto the circuit board (resulting in bleeding). - Insufficient removal of resin from the controller chip causes the chip placed on top of it to warp in the cry direction (resulting in a Boeing effect). Note that warping in the cry direction means that the chip warps so that it is convex upwards (see Figure 12(d)).

[0005] While some voids can be eliminated by the pressure curing process after crimping, larger voids may not be able to be eliminated. Voids can cause delamination between the chip and the substrate or cracking of the package during reflow. Bleeding can contaminate surrounding wire bonding pads or chips, leading to reduced wire bonding performance. Boeing can make multi-layer stacking of chips difficult or cause semiconductor elements to delaminate due to residual stress.

[0006] To address these challenges, various compositional improvements have been made to control the fluidity of film-like adhesives. However, increasing the fluidity of the film to reduce voids and bowing after crimping tends to increase bleeding. Conversely, decreasing the fluidity of the film to reduce bleeding increases voids and bowing. Thus, there is a trade-off relationship between voids / bowing and bleeding, making it difficult to improve these issues solely through material improvements. Furthermore, even with changes in process conditions such as crimping temperature or crimping load, for example, high-temperature, high-load crimping tends to reduce voids while increasing bleeding, making it difficult to simultaneously improve the above issues.

[0007] This disclosure has been made in view of the above circumstances and provides a method for manufacturing a semiconductor device using an adhesive film (FOD) for chip embedding, which can sufficiently suppress the occurrence of voids, bleeding, and bowing. Furthermore, this disclosure provides a highly reliable semiconductor device in which the occurrence of voids, bleeding, and bowing during the manufacturing process is sufficiently suppressed. [Means for solving the problem]

[0008] A method for manufacturing a semiconductor device relating to one aspect of this disclosure includes the following steps. (A) A step of placing the first chip on the substrate. (B) A step of placing a plurality of raising pieces on a substrate around the first chip or around the area where the first chip is to be placed. (C) A step of preparing an adhesive chip comprising a second chip and an adhesive chip provided on one surface of the second chip. (D) A step of applying pressure to the chip with the adhesive piece attached toward the substrate so that the first chip and at least a portion of the raising piece are embedded in the adhesive piece. Furthermore, steps (A), (B), and (C) may be performed in any combination of order.

[0009] The inventors of this invention investigated methods to suppress the occurrence of voids, bleeding, and bowing in the manufacturing process of semiconductor devices, and found that voids and bleeding occur due to bowing in the process of pressing a second chip onto a first chip. Figures 12(a) to 12(f) are schematic cross-sectional views showing a conventional process of pressing a chip onto a controller chip. Figure 12(a) shows a substrate 10 placed on a hot plate H, with the controller chip Tc (first chip) fixed to the substrate 10 by an adhesive piece Ac. An adhesive piece-attached chip 31 (a laminate of adhesive piece A1 and chip T1 (second chip)) is placed above the controller chip Tc, and is ready for pressing. Figure 12(b) shows the lower surface of adhesive piece A1 in contact with the upper surface of controller chip Tc. Figure 12(c) shows the state in which adhesive piece A1 has begun to melt on the upper surface of controller chip Tc. Figure 12(d) shows the state in which bowing has occurred on chip T1. Figure 12(e) shows the state in which the edge portion of adhesive piece A1 is in contact with the surface of substrate 10. Figure 12(f) shows the state after the thermocompression bonding of chip T1 is completed. As shown in Figure 12(f), bowing (warping in the cry direction) has occurred in chip T1, and voids V and bleed B have occurred in adhesive piece A1. In contrast, the inventors have obtained a new finding that if bowing does not occur in chip T1, voids and bleed can also be suppressed, as shown in Figures 13(a) to 13(c).

[0010] (B) The riser pieces placed on the substrate in step (B) are intended to suppress bowing of the second chip. In step (D), bowing of the second chip can be suppressed by applying pressure to the adhesive-attached chip in the direction of the substrate so that the first chip and at least a portion of the riser piece are embedded in the adhesive piece (see Figure 9). This also suppresses the generation of voids and bleed.

[0011] (B) From the viewpoint of efficiently carrying out step (B), a transfer film comprising a base film and a plurality of raising pieces provided on the surface of the base film may be used. In other words, step (B) may include transferring the plurality of raising pieces provided on the surface of the base film onto the surface of the substrate.

[0012] As described above, a certain amount of voids can be eliminated by the pressure curing process after bonding. That is, if the adhesive piece is made of a thermosetting resin composition, a step of curing the adhesive piece by heating under a pressurized atmosphere may be performed after step (D). Performing this step can further reduce voids.

[0013] According to the inventors' studies, when the shape of the second chip in plan view is rectangular and the ratio of the length of the long side B to the length of the short side A of this rectangle, B / A, is 2 or more, conventional crimping methods tend to cause open voids and bleeding due to bowing of the second chip. Open voids do not disappear even after the pressure curing process described above and should therefore be avoided. In contrast, according to the manufacturing method of the present disclosure, even when the shape of the second chip in plan view is rectangular and the ratio of the length of the long side B to the length of the short side A of this rectangle, B / A, is 2 or more, the raising piece suppresses downward bending of the short side of the second chip in step (D), thereby suppressing bowing of the second chip, and consequently suppressing open voids and bleeding.

[0014] A semiconductor device relating to one aspect of the present disclosure comprises a substrate, a first chip disposed on the substrate, a plurality of raising pieces disposed on the substrate and around the first chip, an adhesive piece embedding the first chip and at least a portion of the raising pieces, and a second chip disposed to cover the first chip while being bonded to the adhesive piece.

[0015] The above-mentioned semiconductor device is manufactured, for example, by the above-mentioned manufacturing method. This semiconductor device has excellent reliability because the occurrence of voids, bleeds, and bowing during the manufacturing process is sufficiently suppressed.

[0016] In the semiconductor device described above, the second chip is separated from the plurality of spacer pieces, and an adhesive (the adhesive piece) may be filled between the second chip and the plurality of spacer pieces. Further, the second chip is separated from the first chip, and an adhesive (the adhesive piece) may be filled between the second chip and the first chip.

[0017] The spacer piece has, for example, a multilayer structure including a dummy chip and an adhesive piece. The spacer piece may have a multilayer structure including a pair of surface layers made of a cured product of a thermosetting resin composition and an intermediate layer disposed between the pair of surface layers. The spacer piece may have a two-layer structure of a first layer and a second layer. The second layer is, for example, an adhesive piece and may be composed of a cured product of a thermosetting resin composition. The first layer may correspond to the intermediate layer described above.

[0018] The first chip may be wire-connected or flip-chip-connected to the substrate.

Advantages of the Invention

[0019] According to the present disclosure, there is provided a method for manufacturing a semiconductor device using an adhesive film for chip embedding (FOD), which can sufficiently suppress the generation of voids, bleed, and voiding. Further, according to the present disclosure, there is provided a semiconductor device excellent in reliability in which the generation of voids, bleed, and voiding in the manufacturing process is sufficiently suppressed.

Brief Description of the Drawings

[0020] [Figure 1] FIG. 1 is a cross-sectional view schematically showing an embodiment of a semiconductor device according to the present disclosure. [Figure 2] FIGS. 2(a) and 2(b) are plan views schematically showing an example of the positional relationship between a chip and a plurality of spacer pieces. [Figure 3]FIG. 3(a) is a plan view schematically showing an example of a laminated film for producing a raised piece, and FIG. 3(b) is a cross-sectional view taken along line b-b of FIG. 3(a). [Figure 4] FIG. 4 is a cross-sectional view schematically showing the process of bonding an adhesive layer and the laminated film shown in FIG. 3(b). [Figure 5] FIGS. 5(a) to 5(d) are cross-sectional views schematically showing the manufacturing process of the raised piece. [Figure 6] FIGS. 6(a) and 6(b) are cross-sectional views schematically showing examples of a chip with an adhesive piece, respectively. [Figure 7] FIG. 7 is a cross-sectional view schematically showing the process of manufacturing the semiconductor device shown in FIG. 1. [Figure 8] FIG. 8 is a cross-sectional view schematically showing the process of manufacturing the semiconductor device shown in FIG. 1. [Figure 9] FIG. 9 is a cross-sectional view schematically showing the process of manufacturing the semiconductor device shown in FIG. 1. [Figure 10] FIG. 10 is a cross-sectional view schematically showing the process of manufacturing the semiconductor device shown in FIG. 1. [Figure 11] FIG. 11 is a cross-sectional view schematically showing an example of a transfer film used for arranging the raised piece on the surface of a substrate. [Figure 12] FIGS. 12(a) to 12(f) are cross-sectional views schematically showing a conventional thermocompression bonding process. [Figure 13] FIGS. 13(a) to 13(c) are cross-sectional views schematically showing that voids and bleed are also suppressed assuming that no boiling occurs in the chip to be pressure-bonded.

MODE FOR CARRYING OUT THE INVENTION

[0021] Embodiments of the present disclosure will be described in detail below with reference to the drawings. However, the present disclosure is not limited to the following embodiments. In the following embodiments, components (including steps, etc.) are not essential unless otherwise specified. In the following description, the same or corresponding parts are denoted by the same reference numerals, and redundant descriptions are omitted. Also, unless otherwise specified, positional relationships such as up, down, left, and right are based on the positional relationships shown in the drawings. The sizes of components in each figure are conceptual, and the dimensional ratios in the drawings are not limited to the ratios shown.

[0022] The numerical values ​​and their ranges described herein do not limit this disclosure. Numerical ranges indicated using "~" in this specification include the numerical values ​​before and after "~" as the minimum and maximum values, respectively. In numerical ranges described in stages within this specification, the upper or lower limit of one numerical range may be replaced by the upper or lower limit of another numerical range described in stages.

[0023] <First Embodiment> [Semiconductor device] Figure 1 is a schematic cross-sectional view showing a semiconductor device according to this embodiment. The semiconductor device 100 shown in this figure is, for example, a three-dimensional NAND memory. The semiconductor device 100 includes a substrate 10, a controller chip Tc (first chip) disposed on the surface of the substrate 10, a plurality of risers R disposed on the substrate 10 around the controller chip Tc, an adhesive piece A1 embedding the entire controller chip Tc and at least a portion of the risers R, a chip T1 (second chip) disposed to cover the controller chip Tc while being bonded to the adhesive piece A1, five chips T2, T3, T4, T5, T6 laminated on the surface of chip T1, wires Wa, Wb electrically connecting electrodes 10a, 10b on the surface of the substrate 10 to the chips, and a sealing layer 50 that seals them. The adhesive piece A2 is disposed between chip T1 and chip T2. The adhesive piece A3 is disposed between chip T2 and chip T3. The adhesive piece A4 is disposed between chip T3 and chip T4. Adhesive piece A5 is placed between tip T4 and tip T5. Adhesive piece A6 is placed between tip T5 and tip T6.

[0024] The substrate 10 may be an organic substrate or a metal substrate such as a lead frame. From the viewpoint of suppressing warping of the semiconductor device 100, the thickness of the substrate 10 may be, for example, 90 to 300 μm, or 90 to 210 μm.

[0025] The controller chip Tc is bonded to the substrate 10 by an adhesive piece Ac and electrically connected to the electrode 10a by a wire Wa. The shape of the controller chip Tc in plan view is, for example, rectangular (square or rectangle). The length of one side of the controller chip Tc is, for example, 5 mm or less, and may be 2 to 5 mm or 1 to 5 mm. The thickness of the controller chip Tc is, for example, 20 to 150 μm, and may be 30 to 100 μm. The thickness of the adhesive piece Ac is, for example, 5 to 40 μm, and may be 10 to 25 μm. The sum of the thickness of the controller chip Tc and the thickness of the adhesive piece Ac (distance from the top surface of the substrate 10 to the top surface of the controller chip Tc) is, for example, 25 to 190 μm, and may be 40 to 125 μm.

[0026] The riser piece R is located on the substrate 10 and positioned around the controller chip Tc. The riser piece R plays a role in suppressing the bowing of the chip T1 during the bonding process (see Figure 9). In this embodiment, the riser piece R has a three-layer structure including a pair of surface layers R1, R1 and an intermediate layer R2 positioned between them. The length of one side of the riser piece R in plan view is, for example, 12 mm or less, and may be 2 to 10 mm or 3 to 8 mm.

[0027] The overall thickness of the riser piece R should be equal to the sum of the thickness of the controller tip Tc and the thickness of the adhesive piece Ac, for example, 25 to 190 μm, and may be 40 to 125 μm or 40 to 115 μm. The ratio of the overall thickness of the riser piece R to the sum of the thickness of the controller tip Tc and the thickness of the adhesive piece Ac is for example 0.8 to 1.2, may be 0.9 to 1.1, or for example 0.5 to 1.2 or 0.8 to 1.1. This ratio being within these ranges allows for a sufficiently uniform pressing force to be applied to the tip T1 during the tip T1 crimping process (see Figure 9). This suppresses bowing of the tip T1, and as a result, the occurrence of voids and bleeding can also be suppressed. This ratio may be less than 1.0, and may be 0.95 or less or 0.90 or less. The relatively thinness of the riser piece R suppresses the bleeding of the adhesive piece A1 onto the surface of the riser piece R. Adhesive fragments A1 that protrude onto the surface of the riser piece R may contaminate the wire bonding pad (not shown) of the tip T1 in subsequent processes, potentially reducing the reliability of the wire bonding.

[0028] The thickness of the surface layer R1 is, for example, 5 to 40 μm or 5 to 50 μm, and may also be 5 to 25 μm or 5 to 20 μm. The thicknesses of the two surface layers R1, R1 may be the same or different. The surface layer R1 consists of a thermosetting resin composition. The thermosetting resin composition can become a fully cured product (C stage) after going through a semi-cured (B stage) state and then undergoing a curing treatment. The thermosetting resin composition includes an epoxy resin, a curing agent, and an elastomer (e.g., an acrylic resin), and optionally further includes an inorganic filler and a curing accelerator. The compositions of the two surface layers R1, R1 may be the same or different.

[0029] The thickness of the intermediate layer R2 is, for example, 5 to 75 μm or 5 to 90 μm, and may also be 10 to 75 μm or 10 to 50 μm. It is preferable that the intermediate layer R2 is made of a material with sufficiently high mechanical strength. Specific examples of materials include resins such as polyimide and polyethylene terephthalate (PET), and metals such as copper and aluminum. The tensile modulus of the material constituting the intermediate layer R2 is, for example, 8.0 MPa or higher, and may also be 9.0 MPa or higher or 10.0 MPa or higher. Note that if the intermediate layer R2 is made of a resin material, the intermediate layer R2 is made of a different material than the resin material constituting the surface layer R1. By having multiple layers made of different materials in the raising piece, each layer can be assigned a specific function, and the functionality of the raising piece can be improved compared to a piece made of multiple layers of the same material.

[0030] As shown in Figure 2(a), two risers R (rectangular shape) may be placed at positions corresponding to the short side of the tip T1 in a plan view, or as shown in Figure 2(b), one riser R (square shape, a total of 4) may be placed at positions corresponding to the corners of the tip T1 in a plan view. From the viewpoint of suppressing bleed, it is preferable that the entirety of the multiple risers R is not covered by the tip T1, that is, it is preferable that a part of each riser R is positioned to protrude outward from the tip T1 in a plan view. It is preferable that the four corners of the tip T1 are balanced and cover at least a part of each riser R. With this configuration, both bowing and bleed can be suppressed even more effectively.

[0031] (Method for making height-raising pieces) An example of a method for producing the height-enhancing piece R will be described. Note that the surface layer R1 shown in Figure 1 is the state after the thermosetting resin composition constituting it has hardened. On the other hand, the surface layer S1 and the surface layer P1 obtained by fragmenting it are in the state before the thermosetting resin composition contained therein has completely hardened (see Figures 3(b) and 5(b)).

[0032] First, prepare the laminated film 20 shown in Figures 3(a) and 3(b). The laminated film 20 comprises a base film 1, an adhesive layer 2, and a three-layer film 15F. The base film 1 is, for example, a polyethylene terephthalate film (PET film). The adhesive layer 2 is formed in a circular shape by punching or the like (see Figure 3(a)). The adhesive layer 2 is made of, for example, an ultraviolet-curing adhesive. This adhesive layer 2 has the property of losing its tackiness when irradiated with ultraviolet light. The three-layer film 15F is formed in a circular shape by punching or the like and has a smaller diameter than the adhesive layer 2 (see Figure 3(a)).

[0033] The three-layer film 15F is composed of a pair of surface layers S1, S1 made of thermosetting resin layers and an intermediate layer M sandwiched between them. The thickness of the surface layer S1 is substantially the same as the surface layer R1 described above, for example, 5 to 40 μm, but may be 5 to 25 μm or 5 to 20 μm. The thickness of the intermediate layer M is the same as the intermediate layer R2 described above, for example, 5 to 75 μm, but may be 10 to 75 μm or 10 to 50 μm. The tensile modulus of the intermediate layer M is, for example, 8.0 MPa or more, but may be 9.0 MPa or more or 10.0 MPa or more. By having a tensile modulus of 8.0 MPa or more of the intermediate layer M, in the process of picking up the raising piece R (see Figure 5(d)), the intermediate layer R2 acts like a spring plate, achieving excellent pick-up performance. The upper limit of the tensile modulus of the intermediate layer M is approximately 15 MPa from the standpoint of material availability. Examples of materials constituting the intermediate layer M include polyimide and polyethylene terephthalate (PET). The intermediate layer M may also be a layer made of a thermosetting resin composition or a photocurable resin composition that has been cured so that its tensile modulus is within the above range.

[0034] The laminated film 20 can be manufactured, for example, by laminating a first laminated film having a base film 1 and an adhesive layer 2 on its surface, and a second laminated film having a cover film 3 and a three-layer film 15F on its surface (see Figure 4). The first laminated film is obtained by the steps of forming an adhesive layer on the surface of the base film 1 by coating, and processing the adhesive layer into a predetermined shape (e.g., circular) by punching or the like. The second laminated film is obtained by the steps of forming a surface layer S1 on the surface of the cover film 3 (e.g., PET film or polyethylene film) by coating, forming an intermediate layer M on the surface of the surface layer S1, forming a surface layer S1 on the surface of the intermediate layer M by coating, and processing the adhesive film formed through these steps into a predetermined shape (e.g., circular) by punching or the like. When using the laminated film 20, the cover film 3 is peeled off at an appropriate time.

[0035] As shown in Figure 5(a), a dicing ring DR is attached to the laminated film 20. That is, the dicing ring DR is attached to the adhesive layer 2 of the laminated film 20, and the three-layer film 15F is positioned inside the dicing ring DR. The three-layer film 15F is divided into individual pieces by dicing (see Figure 5(b)). This yields a number of raising pieces R from the three-layer film 15F. Subsequently, for example, the adhesive layer 2 is irradiated with ultraviolet light to reduce the adhesive force between the adhesive layer 2 and the raising pieces R. After ultraviolet irradiation, as shown in Figure 5(c), tension is applied to the base film 1 by pushing up the inner region of the dicing ring DR on the base film 1 with the ring Ra, causing the raising pieces R to separate from each other.

[0036] Next, as shown in Figure 5(d), the raising piece R is peeled from the adhesive layer 2 by pushing it up with the pushing jig 42, and the raising piece R is picked up by suction with the suction collet 44. The curing reaction of the thermosetting resin may be advanced by heating the three-layer film 15F before dicing or the raising piece R before picking. Excellent pickability can be achieved if the raising piece R is moderately cured at the time of picking. It is preferable that the cuts for individualization are formed up to the outer edge of the raising piece R. The diameter of the three-layer film 15F may be, for example, 300-310 mm or 300-305 mm. The shape of the three-layer film 15F in plan view is not limited to the circle shown in Figure 3(a), but may be rectangular (square or rectangle).

[0037] Here, a three-layered riser piece R is given as an example, but the riser piece may also have a two-layer structure, with one of the two surface layers R1, R1 being omitted. For example, the riser piece may have a two-layer structure consisting of a first layer in contact with the surface of the substrate 10 and a second layer provided on the surface of the first layer. The first layer corresponds to the surface layer R1 described above, and its material and physical properties may be the same as those of the surface layer R1. The second layer corresponds to the intermediate layer R2 described above, and its material and physical properties may be the same as those of the intermediate layer R2. The thickness of the two-layered riser piece may be, for example, 25 to 190 μm, and may also be 40 to 125 μm or 40 to 115 μm. Furthermore, the riser piece R may be a laminate of a dummy chip (first layer) and an adhesive piece (second layer) provided on one side of the dummy chip. Rising pieces with these configurations can be manufactured through a dicing process and a pickup process.

[0038] Chip T1 is, for example, a memory chip. In plan view, chip T1 has a larger area than controller chip Tc. Chip T1 is placed on the substrate 10 via adhesive piece A1 so as to cover the entire controller chip Tc. In plan view, the shape of chip T1 is, for example, rectangular (square or rectangle). The length of one side of chip T1 is, for example, 12 mm or less, and may be 6-10 mm or 2-4 mm. If the shape of these chips is rectangular, the ratio B / A of the length of the long side to the length of the short side A is, for example, 1.5-4, and may be 1.8-3.5 or 2.1-3.2. The thickness of chip T1 is, for example, 10-170 μm, and may be 10-30 μm. These chips have a complex circuit layer (top side in Figure 1) and a relatively thin semiconductor layer (bottom side in Figure 1). As the ratio of the thickness of the semiconductor layer to the total thickness of the chip decreases, the chip becomes more prone to warping in the smile direction. For example, if this ratio is 80% or less, a curve in the smile direction is likely to occur. A curve in the smile direction means that the tip curves downwards.

[0039] The size of the chip T1 and the adhesive piece A1 in plan view are substantially the same (see Figure 6(a)). The adhesive piece-attached chip 31 shown in Figure 6(a) is a laminate of adhesive piece A1 (before curing) and chip T1. The adhesive piece-attached chip 31 can be obtained by separating a laminate of an adhesive film (FOD) for chip embedding and a semiconductor wafer.

[0040] As shown in Figure 1, the chip T1 is spaced apart in the thickness direction of the semiconductor device 100 from multiple riser pieces R. The chip T1 is also spaced apart from the controller chip Tc in the thickness direction of the semiconductor device 100. This configuration suppresses the occurrence of bowing of the chip T1 and ensures sufficient distance from the top surface of the controller chip Tc to the bottom surface of the chip T1. Adhesive pieces A1 are filled between the chip T1 and the multiple riser pieces R. Adhesive pieces A1 are also filled between the chip T1 and the controller chip Tc.

[0041] Chips T2, T3, T4, T5, and T6 are, like chip T1, memory chips, for example. The shape, size, and thickness of chips T2, T3, T4, T5, and T6 in plan view may be the same as those of chip T1. The size of chip T2 and adhesive piece A2 in plan view are substantially the same (see Figure 6(b)). The adhesive piece-attached chip 32 shown in Figure 6(b) is a laminate of adhesive piece A2 (before curing) and chip T2. The adhesive piece-attached chip 32 can be obtained by dicing a laminate of die bonding film and semiconductor wafer. This die bonding film may be thinner than the adhesive film (FOD) for chip embedding described above. By dicing, in addition to the adhesive piece-attached chip 32, adhesive piece-attached chips 33, 34, 35, and 36, each containing chips T3, T4, T5, and T6, can also be obtained.

[0042] [Manufacturing method for semiconductor devices] The semiconductor device 100 is manufactured through the following process. (A) A step of placing the controller chip Tc on the substrate 10 (see Figure 7). (B) A step of arranging a plurality of risers R on the substrate 10 around the controller chip Tc (see Figure 8). Furthermore, process (A) may be performed first, followed by process (B), or process (B) may be performed first, followed by process (A). If process (B) is performed first, then process (A) may be performed. In process (B), multiple raising pieces R may be placed around the area on the substrate 10 where the controller chip Tc is to be placed. (C) A step to prepare the adhesive-backed tip 31 (see Figure 6(a)). Step (C) may be performed at any time before step (D). (D) A step in which the adhesive chip 31 is pressed toward the substrate 10 so that the entire controller chip Tc and a portion of each riser piece R are embedded in the adhesive piece A1 (see Figure 9). Step (D) can be carried out, for example, on a hot plate. The temperature conditions for heat sealing can be, for example, 80 to 150°C, or 90 to 130°C. The pressing force for heat sealing can be, for example, 0.05 to 0.5 MPa, or 0.1 to 0.3 MPa. (E) A step of sequentially stacking multiple adhesive chips 32-36 on the surface of chip T1 (see Figure 10). (F) A step of sealing chips and wires on the surface of the substrate 10 with a sealing material.

[0043] In step (D), when applying pressure to the adhesive chip 31 in the direction of the substrate 10, the presence of multiple risers R around the controller chip maintains the flat shape of the chip T1 and suppresses bowing. That is, by pressing the chip T1 so that the entire controller chip Tc and a portion of each riser R positioned at a location corresponding to the periphery of the chip T1 are embedded in the adhesive chip A1, a sufficiently uniform pressure is applied to the chip T1 (see Figure 9). As a result, bowing of the chip T1 can be suppressed, and consequently, the occurrence of voids and bleeding can also be suppressed.

[0044] Although embodiments of the present disclosure have been described in detail above, the present invention is not limited to the above embodiments. For example, in the above embodiments, a configuration in which the controller chip Tc is connected to the substrate 10 by wire Wa was illustrated, but the controller chip Tc may be flip-chip connected to the substrate 10. Also, in the above embodiments, a three-dimensional NAND memory in which the controller chip is embedded was illustrated, but the riser piece may be applied to semiconductor devices in other configurations in which other chips are embedded.

[0045] In the above embodiment, the case in which the raising pieces R are manufactured through a dicing process and a pick-up process was illustrated, but the raising pieces may also be placed on the substrate 10 using a transfer film. Figure 11 is a schematic cross-sectional view showing an example of a transfer film. The transfer film 60 shown in Figure 11 consists of a base film 61 and a plurality of raising pieces R provided on the surface of the base film 61.T It is equipped with a height-raising piece R. T For example, it is made of a thermosetting resin composition. By preparing such a transfer film 60 in advance, for example, multiple raising pieces R can be placed on the surface of the substrate 10 all at once by heat pressing. T It is possible to place them. [Industrial applicability]

[0046] This disclosure provides a method for manufacturing a semiconductor device using an adhesive film (FOD) for chip embedding, which can sufficiently suppress the occurrence of voids, bleeding, and bowing. Furthermore, this disclosure provides a highly reliable semiconductor device in which the occurrence of voids, bleeding, and bowing during the manufacturing process is sufficiently suppressed. [Explanation of symbols]

[0047] 1...Base film, 2...Adhesive layer, 3...Cover film, 10...Substrate, 10a...Electrode, 10b...Electrode, 15F...Three-layer film, 20...Laminated film, 31,32,33,34,35,36...Adhesive chip, 50...Sealing layer, 60...Transfer film, 61...Base film, 100...Semiconductor device, A1,A2,A3,A4,A5,A6,Ac...Adhesive chip, DR...Dicing ring, P1,R1,S1...Surface layer, R,R T ...raising piece, M, R2...intermediate layer, T1...chip (second chip), T2, T3, T4, T5, T6...chip, Tc...controller chip (first chip), Wa, Wb...wire.

Claims

1. (A) A step of placing the first chip on the substrate, (B) A step of arranging a plurality of raising pieces on the substrate around the first chip or around the area where the first chip is to be placed, (C) A step of preparing an adhesive chip comprising a second chip and an adhesive chip provided on one surface of the second chip, (D) A step of applying pressure to the adhesive piece-attached chip in the direction of the substrate so that the first chip and at least a portion of the raising piece are embedded in the adhesive piece, A method for manufacturing a semiconductor device, including the method described above.

2. (B) The method for manufacturing a semiconductor device according to claim 1, further comprising transferring the plurality of raising pieces provided on the surface of the base film onto the surface of the substrate.

3. The adhesive piece is made of a thermosetting resin composition, The method for manufacturing a semiconductor device according to claim 1 or 2, further comprising the step of curing the adhesive piece by heating in a pressurized atmosphere after step (D).

4. In a plan view, the shape of the second tip is rectangular. A method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the ratio B / A of the length of the long side to the length of the short side A is 2 or more.

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