Manufacturing method for semiconductor devices

Abstract

To provide a manufacturing method of semiconductor devices capable of improving the yield by suppressing overdetection while reducing the rejection of defective products to be commercialized by executing more appropriate quality judgment.SOLUTION: After preparing a semiconductor wafer, a device formation process is carried out to form semiconductor elements (S100). Subsequently, the electrical characteristics of each semiconductor device that is to be chipped from the semiconductor wafer are measured (S110). Subsequently, at least one of the areas of any region on the graph of the electrical characteristic waveform obtained by measuring the electrical characteristics and the slope of a line connecting any two points on the graph of the electrical characteristic waveform is defined as a feature, and the feature is calculated (S120). Based on the features and the discriminant, a pass / fail determination is made for each semiconductor device (S130).SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] This disclosure relates to a method for manufacturing a semiconductor device, and is particularly suitable for a method for manufacturing a compound semiconductor device using silicon carbide (hereinafter referred to as SiC) or gallium nitride (hereinafter referred to as GaN) as a semiconductor material. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a semiconductor device in which a crystal defect inspection is performed before the electrical characteristic inspection, which is carried out after the formation of a semiconductor device by a semiconductor process. Specifically, an appearance inspection using a laser, i.e., a crystal defect inspection by image detection, is performed in advance when an epitaxial film has been grown on a SiC substrate, and a crystal defect inspection device is used to detect crystal defects present in the epitaxial film. After the crystal defect inspection, when the device structure is formed on a semiconductor wafer and then diced into semiconductor chips, semiconductor chips in which no crystal defects were detected in the crystal defect inspection are selected as good product candidates. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-176696 [Overview of the project] [Problems that the invention aims to solve]

[0004] Semiconductors, especially compound semiconductors like SiC and GaN, have a high density of crystal defects, and may contain crystal defects known as "killer defects" that negatively impact subsequent processes and quality. It is necessary to properly detect such crystal defects and reject them before shipment to prevent them from being commercialized.

[0005] However, even if crystal defects are present, some defects do not cause problems in practical use, while small crystal defects can expand during product use and become killer defects. Therefore, crystal defect inspection using image detection is not accurate enough. As a result, problems can arise such as products that should have been rejected being commercialized, or over-detection of products that do not need to be rejected.

[0006] This disclosure aims to provide a method for manufacturing a semiconductor device that enables more appropriate good / bad judgment, suppresses the rejection of defective products and their subsequent commercialization, and improves yield by suppressing over-detection. [Means for solving the problem]

[0007] In one aspect of this disclosure, a method for manufacturing a semiconductor device is: After preparing a semiconductor wafer, a device formation process is carried out to form a semiconductor element (S100), (S110) The electrical characteristics of each semiconductor device that will be made into a chip from the aforementioned semiconductor wafer are measured, Area of ​​any region in the graph of the electrical characteristic waveform obtained by measuring the aforementioned electrical characteristics. , or the area and the slope of the straight line connecting any two points on the graph. Ki As a feature, the calculation of the feature (S120) The method includes (S130) determining whether each semiconductor device is good or bad based on the feature quantities and discriminant formula obtained by calculating the feature quantities.

[0008] Thus, the area of ​​any region in the graph of the electrical characteristic waveform obtained by measuring the electrical characteristics. , or the area and the slope of the electrical characteristic waveform graph KiAs a feature amount, based on the feature amount and discriminant, a pass / fail determination is made. Therefore, while increasing the detection rate of NG products, the over-detection rate can be reduced. Accordingly, it is possible to provide a method for manufacturing a semiconductor device that can more appropriately detect crystal defects that can become killer defects, suppress rejection and productization, suppress over-detection, and improve the yield.

[0009] Note that the reference numerals with parentheses attached to each component etc. show an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.

Brief Description of Drawings

[0010] [Figure 1] It is a perspective cross-sectional view of a SiC semiconductor device according to a first embodiment of the present disclosure. [Figure 2] It is an explanatory diagram of a current path in a SiC semiconductor device. [Figure 3A] It is an explanatory diagram showing the state of holes and electrons near the built-in diode. [Figure 3B] It is an explanatory diagram of defect growth caused by BPD near the built-in diode. [Figure 4] It is a graph showing the results of examining the electrical characteristics of the drain current Id with respect to the source-drain voltage Vds by experiment. [Figure 5] It is a graph showing the Gini coefficient. [Figure 6A] It is a diagram showing a case where three nodes are extracted from a graph of electrical characteristic waveforms. [Figure 6B] It is a diagram showing a graph of the normalized Gini coefficient of the three nodes extracted as shown in FIG. 6A. [Figure 7] It is a diagram showing an example of plotting the measured feature amounts of each SiC semiconductor device in a two-axis coordinate system with two feature amounts as the x-axis and y-axis, and setting a discriminant for good products and NG products. [Figure 8] It is a flowchart of the manufacturing process of a SiC semiconductor device. [Figure 9]It is a graph showing each region defined by the equal straight line and the Lorenz curve described in other embodiments.

Mode for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present disclosure will be described based on the drawings. In addition, including other embodiments described below, in each embodiment, parts that are identical or equivalent to each other will be described with the same reference numerals.

[0012] (First Embodiment) The first embodiment of the present disclosure will be described. In this embodiment, as a semiconductor device, a SiC semiconductor device using SiC as a semiconductor material will be described as an example.

[0013] [Configuration of SiC Semiconductor Device] The SiC semiconductor device according to this embodiment is formed with an inversion-type vertical MOSFET having a trench gate structure shown in FIG. 1 as a semiconductor element. These vertical MOSFETs shown in the figures are formed in the cell region of the SiC semiconductor device, and the SiC semiconductor device is configured by forming an outer peripheral breakdown voltage structure so as to surround the cell region. Here, only the vertical MOSFET is shown. Hereinafter, as shown in FIG. 1, one direction orthogonal to each other will be described as the X direction, the Y direction, and the Z direction, respectively. Specifically, the width direction of the vertical MOSFET is the X direction, the depth direction of the vertical MOSFET intersecting the X direction is the Y direction, and the thickness direction or the depth direction of the vertical MOSFET, that is, the normal direction with respect to the XY plane is the Z direction.

[0014] As shown in FIG. 1, an n-type SiC substrate 11 doped with n-type impurities is used in the SiC semiconductor device. The SiC substrate 11 is a part that constitutes the drain region in the vertical MOSFET. The SiC substrate 11 has an off-angle of 0 to 8° with respect to the (0001) Si plane, for example, and is configured by being doped with n-type impurities such as N (nitrogen) and P (phosphorus) at a high concentration. + 型のSiC基板11が用いられている。SiC基板11は、縦型MOSFETにおけるドレイン領域を構成する部分である。SiC基板11は、例えば、(0001)Si面に対して0~8°のオフ角を有し、N(窒素)やP(リン)等のn型不純物が高濃度にドープされて構成されている。

[0015] On the main surface of the SiC substrate 11, n is made of SiC which constitutes part of the drift layer. - A buffer layer 12 of type n is formed. The buffer layer 12 is formed by epitaxial growth on the surface of the SiC substrate 11, and the n-type impurity concentration is set to the impurity concentration between the SiC substrate 11 and the low-concentration layer 13 described later. In addition, on top of the buffer layer 12, there is an n-type layer made of SiC that constitutes part of the drift layer, which has a lower concentration than the SiC substrate 11. - A low-concentration layer 13 of the type is formed.

[0016] In the cell region, an n-type JFET portion 14, which constitutes part of the drift layer made of SiC, is formed on the low-concentration layer 13. The low-concentration layer 13 is connected to the JFET portion 14 on the side opposite to the SiC substrate 11. Furthermore, a p-type deep layer 15 is formed on the low-concentration layer 13, which is doped with p-type impurities such as Al (aluminum) in addition to the JFET portion 14.

[0017] The JFET section 14 and the deep layer 15 constitute a saturation current suppression layer, and both extend in the X direction as their longitudinal direction, and are arranged in alternating repeating patterns in the Y direction. In other words, when viewed from the direction normal to the main surface of the SiC substrate 11, at least a portion of the JFET section 14 and the deep layer 15 are each arranged in multiple lines, or in other words, stripes, and are arranged in an alternating pattern.

[0018] Each line-shaped portion of the deep layer 15, which is arranged in a striped pattern, has a constant width and is arranged at equal intervals, and the p-type impurity concentration is constant in the depth direction.

[0019] Furthermore, an n-type current dispersion layer 16, which constitutes part of the drift layer made of SiC, is formed on the JFET section 14 and the deep layer 15. The current dispersion layer 16 is a layer that allows the current flowing through the channel of the vertical MOSFET to diffuse in the Y direction, and is formed in contact with the leading edge in the depth direction of the gate trench 21, which will be described later. For example, the n-type impurity concentration is higher than that of the low-concentration layer 13.

[0020] In this embodiment, the drift layer is composed of a buffer layer 12, a low-concentration layer 13, a JFET section 14, and a current-dispersing layer 16. However, the configuration of the drift layer is arbitrary, and for example, a structure without a buffer layer is also possible.

[0021] A p-type base region 17 made of SiC is formed on the current dispersion layer 16. Furthermore, an n-type base region made of SiC is formed on the base region 17. + A source region 18 of type p is formed. The base region 17 has a lower p-type impurity concentration than the deep layer 15. In addition, the source region 18 has a higher n-type impurity concentration than the current dispersion layer 16.

[0022] Furthermore, the p-type impurity concentration is higher than that of the base region 17 so that it reaches from the surface of the source region 18 to the base region 17. + A p-shaped contact region 19 is formed. In this embodiment, the contact region 19 is configured in a linear shape with the Y direction as its longitudinal direction. Furthermore, below the contact region 19, a p-shaped connecting layer 20 is formed that connects the base region 17 and the deep layer 15. The connecting layer 20 is formed in a linear shape with the Y direction as its longitudinal direction together with the contact region 19, and is arranged on both sides of the current distribution layer 16.

[0023] The contact region 19 and the connecting layer 20 play a role in connecting the deep layer 15 and the base region 17 to the source electrode 25, which will be described later, in order to fix the deep layer 15 and the base region 17 to the source potential.

[0024] The spacing between the contact regions 19 and the connecting layers 20 is arbitrary, but in this embodiment, they are formed on both sides of the trench gate structure, which will be described later. The width of the contact regions 19 and the connecting layers 20 is also arbitrary, but here it is set to be less than or equal to the spacing between adjacent trench gate structures.

[0025] Furthermore, a gate trench 21 is formed with a predetermined width and depth so as to penetrate the source region 18 and the base region 17 and reach the current distribution layer 16. The base region 17 and source region 18 are formed so as to be in contact with the side surface of this gate trench 21, and the contact region 19 is positioned away from the gate trench 21. The gate trench 21 is formed in a linear layout with the X direction as the width direction, and the Y direction as the longitudinal direction and the Z direction as the depth direction, intersecting the longitudinal direction of the JFET section 14 and the deep layer 15. As shown in Figure 1, the gate trench 21 is arranged in a stripe shape with multiple trenches arranged at equal intervals in the X direction, and the base region 17, source region 18, contact region 19 and connecting layer 20 are positioned between each of them.

[0026] The portion of the base region 17 located on the side of the gate trench 21 is designated as a channel region connecting the source region 18 and the current dispersion layer 16 during operation of the vertical MOSFET, and the inner wall surface of the gate trench 21, including the channel region, is covered with a gate insulating film 22. A gate electrode 23 made of doped poly-Si is formed on the surface of the gate insulating film 22, and the trench gate structure is formed by arranging these gate insulating film 22 and gate electrode 23 within the gate trench 21. Furthermore, an interlayer insulating film 24 is formed to cover the gate electrode 23.

[0027] As shown in Figure 1, the source electrode 25 and other components are formed on the surface of the source region 18 and the gate electrode 23 via an interlayer insulating film 24. The source electrode 25 is composed of multiple metals, such as Ni / Al. Of these multiple metals, at least n-type SiC, specifically the portion in contact with the source region 18 and the gate electrode 23 in the case of n-type doping, is composed of a metal capable of ohmic contact with n-type SiC. Furthermore, of these multiple metals, at least p-type SiC, specifically the portion in contact with the contact region 19, is composed of a metal capable of ohmic contact with p-type SiC. The source electrode 25 is electrically insulated from the SiC portion by being formed on the interlayer insulating film 24, but it is electrically in contact with the source region 18 and the contact region 19 through contact holes 24a formed in the interlayer insulating film 24.

[0028] On the other hand, a drain electrode 26 electrically connected to the SiC substrate 11 is formed on the back side of the SiC substrate 11. This structure constitutes a vertical MOSFET with an n-channel inverted trench gate structure. Multiple such vertical MOSFETs are arranged to form a cell region. Although not shown in the figures, an outer peripheral breakdown voltage structure such as a guard ring is formed to surround the cell region, thereby forming a SiC semiconductor device.

[0029] In a SiC semiconductor device with this configuration, an internal diode is formed within the vertical MOSFET by a pn junction between a low-concentration layer 13, a JFET section 14, etc., and a deep layer 15, a connecting layer 20, etc.

[0030] The above is a basic configuration example of the SiC semiconductor device according to this embodiment. This SiC semiconductor device can be used, for example, in an inverter circuit for driving a three-phase motor that uses vertical MOSFETs as switching elements.

[0031] Here, as described above, the SiC semiconductor device has a structure in which a vertical MOSFET with a trench gate structure and a built-in diode composed of a pn junction are provided in the cell region. And in the drift layer including the SiC substrate 11 and the buffer layer 12, etc., there are wavy dislocations having dislocation lines on the (0001) plane called basal plane dislocations (hereinafter referred to as BPDs). Defects can occur in the SiC semiconductor device due to these BPDs.

[0032] As shown in FIG. 2, the equivalent circuit of the SiC semiconductor device is shown as a circuit configuration having a vertical MOSFET 30 and a built-in diode 40. When the vertical MOSFET 30 is on, an on-current I flows from the drain electrode 26 to the source electrode 25. ON In FIG. 2, "S", "D", and "G" correspond to the source electrode 25, the drain electrode 26, and the gate electrode 23, respectively. Specifically, when a predetermined voltage such as 20 V is applied to the gate electrode 23, a channel region is formed on the surface of the base region 17 in contact with the gate trench 21, and as a drain current Id flowing between the source electrode 25 and the drain electrode 26, an on-current I flows. ON flows.

[0033] After that, when the SiC semiconductor device is turned off, a reverse bias is applied and it enters a reverse conduction state. Therefore, the built-in diode 40 functions as a freewheeling diode, and a freewheeling current I flows as a drain current Id through the built-in diode 40. OFF flows. At this time, as shown in FIG. 3A, holes diffused from the p-type layer side to the n-type layer side of the pn junction constituting the built-in diode 40 recombine with electrons in the n-type layer. Since the recombination energy of these holes and electrons is large, as shown in FIG. 3B, the BPD 50 expands and the SSF 60 occurs. And this SSF 60 expands as the conduction stress applied to the built-in diode 40 accumulates. Since the SSF is larger in occupied area than the BPD 50, the on-current I ON and the freewheeling current I OFFThis hinders the process. Furthermore, because the SSF60 expands in response to the current stress on the built-in diode 40, the electrical characteristics after operation deteriorate compared to the electrical characteristics immediately after manufacturing, i.e., before the SSF60 is formed.

[0034] Therefore, it is desirable to be able to reject SiC semiconductor devices containing BPD50 that can be extended to SSF60, which would result in the inability to obtain the desired electrical characteristics as a product, in the good / bad judgment process.

[0035] However, as mentioned above, image detection for crystal defect inspection is insufficient in accuracy, which can lead to problems such as products that should be rejected being commercialized, or over-detection of defects that do not need to be rejected.

[0036] Therefore, we investigated crystal defect detection using electrical characteristic testing. However, the standard judgment method, which involves comparing values ​​such as leakage current, which are commonly measured in electrical characteristic testing, with a threshold value and determining whether the product is good or bad if the value does not exceed the threshold, proved insufficient. In other words, while values ​​such as leakage current obtained through electrical characteristic testing are obtained as absolute values, the magnitude of these absolute values ​​does not necessarily correspond to the presence of killer defects that adversely affect subsequent processes and quality when the SiC semiconductor device is actually used. For example, even if the leakage current exceeds the threshold during electrical characteristic testing, the leakage current may hardly increase when the SiC semiconductor device is actually used, making it suitable for practical use. Also, even if BPD50 is present, it may not expand to SSF60, which would have a adverse effect. In such cases, simply comparing the absolute value of the leakage current during electrical characteristic testing with a threshold value makes it difficult to accurately detect SiC semiconductor devices with killer defects, and accurate good / bad judgments could not be made.

[0037] Therefore, further intensive investigation revealed that the electrical characteristics of SiC semiconductor devices with killer defects sometimes exhibit a specific waveform shape, and that accurately detecting this specific waveform allows for the accurate detection of SiC semiconductor devices with killer defects. While various specific waveform shapes were confirmed, here we will describe, as an example, the electrical characteristics of the drain current Id flowing as leakage current with respect to the source-drain voltage Vds under reverse bias.

[0038] Experiments were conducted to investigate the electrical characteristics of drain current Id with respect to source-drain voltage Vds, and the electrical characteristics of SiC semiconductor devices that had killer defects after actual use. To obtain a large amount of real-world data, numerous SiC semiconductor devices manufactured using multiple SiC wafers were prepared. The gate voltage Vg=0V and source voltage Vs=0V were set, and the desired source-drain voltage Vds was applied, and the drain current Id was measured. The source-drain voltage Vds was applied instantaneously to create a reverse bias state instantaneously, and the drain current Id that flowed at that time was measured with a tester. The source-drain voltage Vds can be set arbitrarily, but here six levels were used: 100V, 400V, 600V, 900V, 1100V, and 1200V. Figure 4 shows the results. In the following explanation, each point that divides the graph of the electrical characteristic waveform shown in Figure 4 into multiple regions, in this case the relationship between the value of drain current Id and each source-drain voltage Vds, is called a node. Furthermore, the nodes are referred to as Node 1 to Node 6, in order from the lowest to the highest applied source-drain voltage Vds.

[0039] Furthermore, after this experiment, the SiC semiconductor device used in the experiment underwent an endurance test by applying a source-drain voltage Vds of 1000V for an extended period, for example, a test under conditions that could extend BPD50 to SSF60. After the endurance test, electrical characteristics were again inspected to determine whether the electrical characteristics of the SiC semiconductor device had deteriorated compared to immediately after manufacturing, thereby determining whether a killer defect was present. For example, the on-current I flowing as the drain current Id when the vertical MOSFET 30 is turned on... ONIf the value falls below the threshold, it is thought that BPD50 has expanded to SSF60, resulting in a decrease in electrical properties. Therefore, if the electrical properties of a SiC semiconductor device have deteriorated compared to immediately after manufacturing, it is determined that a killer defect was present.

[0040] As shown in Figure 4, we obtained a large amount of real-world data, and the basic electrical characteristic is that the drain current Id gradually increases as the source-drain voltage Vds increases. However, the change in drain current Id between each node was not constant, and its slope varied.

[0041] On the other hand, when we examined the electrical characteristics of the SiC semiconductor device that had a killer defect before the durability test, we found that line L in Figure 4 showed the same result. kill The characteristics were as shown. In the following explanation, the electrical characteristic waveform of a SiC semiconductor device in which a killer defect was identified will be referred to as the NG waveform. In Figure 4, line L kill This is the NG waveform. Furthermore, the electrical characteristic waveform of a SiC semiconductor device in which no killer defects were identified is called the good waveform. In Figure 4, line L kill The waveforms other than those listed are good waveforms.

[0042] When comparing the NG waveform and the good waveform, there was no clear relationship in the magnitude of the drain current Id at each node, and it was not possible to distinguish between the NG waveform and the good waveform based solely on the magnitude of the drain current Id. This means that simply comparing the absolute value of the leakage current during electrical characteristic testing with a threshold makes it difficult to accurately detect SiC semiconductor devices with killer defects, and therefore it is not possible to make accurate good / bad judgments.

[0043] For example, looking only at the magnitude of the drain current Id for node 2, the drain current Id of a SiC semiconductor device that was not identified as having a killer defect may be larger than that of a SiC semiconductor device that was identified as having a killer defect. Therefore, simply comparing the absolute value of the leakage current with a threshold can lead to over-detection, where a killer defect is identified as present when it does not exist. Conversely, it is also possible that a killer defect is present but not identified as absent.

[0044] Therefore, in this embodiment, a discriminant formula is calculated from the NG waveform based on actual device data, and when the manufactured SiC semiconductor device is subjected to electrical characteristic testing, a good or bad determination is made based on this discriminant formula. The method for calculating this discriminant formula will be explained below.

[0045] As described above, the electrical characteristic waveform is obtained as the relationship between the source-drain voltage Vds and the drain current Id. By viewing this electrical characteristic waveform as an area and a slope of a straight line, and quantifying the area, the electrical characteristic waveform can be selected. Here, we apply a geometric interpretation of the Gini coefficient, which has been widely used in statistics, to quantify the waveform shape. In the following explanation, the Gini coefficient is not a statistical measure, but a unique measure derived from the geometric interpretation described above for the purpose of quantifying the waveform shape. Furthermore, by dividing the graph of the electrical characteristic waveform into regions, calculating the "Gini coefficient" for each region, and calculating the "slope" of a straight line connecting any two points on the graph, we can accurately select a specific electrical characteristic waveform by applying a linear discrimination on two axes.

[0046] The "Gini coefficient" is generally a feature that numerically represents "bias" or "inequality", but here the Gini coefficient is used to quantify the shape information of the electrical characteristic waveform. As shown in Fig. 5, the Gini coefficient is defined as the ratio S1 / (S1 + S2) of the area S1 of the region enclosed by the Lorenz curve, which is drawn using two cumulative relative frequencies, and the equal line, to the total area S1 + S2 of the area S2 below the equal line. The smaller the difference between the Lorenz curve and the equal line and the closer the Gini coefficient is to 0, the smaller the "bias" or "inequality" is represented. Also, the larger the difference between the Lorenz curve and the equal line and the closer the Gini coefficient is to 1, the larger the "bias" or "inequality" is represented.

[0047] In the case of this embodiment, the electrical characteristic waveform showing the relationship between the source-drain voltage Vds and the drain current Id becomes the Lorenz curve. Also, for the source-drain voltage Vds on the x-axis as the horizontal axis and the drain current Id on the y-axis as the vertical axis, when each maximum value is normalized to 1 and each minimum value is normalized to 0, the line y = x becomes the equal line. When the Lorenz curve is the electrical characteristic waveform showing the relationship between the source-drain voltage Vds and the drain current Id, the Lorenz curve is always a curve whose y-coordinate value is lower than that of the equal line, that is, a curve satisfying the relationship y < x. Then, in order to quantify the waveform information of the electrical characteristic waveform, the area S1 of the crescent-shaped portion between the Lorenz curve and the equal line is calculated. When normalized, since the area of the right triangle formed by the equal line and the y-axis is 1 / 2, the area S1 becomes the value of 1 / 2 of the ratio S1 / (S1 + S2). 2×S1 obtained by doubling the area S1 represents the Gini coefficient.

[0048] The Gini coefficients are calculated by selecting at least three consecutive nodes from among several nodes. Specifically, the node with the smallest absolute value of its electrical characteristics among the three consecutive nodes—in this case, the node with the smallest source-drain voltage Vds and drain current Id—is designated as the MIN node, and the node with the largest value is designated as the MAX node. Then, the source-drain voltage Vds and drain current Id of the MIN node are normalized to 0, and the source-drain voltage Vds and drain current Id of the MAX node are normalized to 1. This yields a graph of the Gini coefficients, which plots the Lorentz curve represented by the selected three or more consecutive nodes and a uniform straight line where y=x.

[0049] For example, let's consider the case where the Gini coefficient is calculated using all six nodes. In this case, as shown in Figure 4, the source-drain voltage Vds of the MAX node is 1200V, and the drain current Id at that time is 5 × 10⁻⁶. -4 The result was A. Also, the source-drain voltage Vds at the MIN node was 100V, and the drain current Id at that time was 1.5 × 10⁻⁶. -9 The result was A. In this case, subtract 100 from the source-drain voltage Vds of each node, and then multiply by 1 / (1200-100) to obtain the normalized source-drain voltage Vds. Similarly, subtract 1.5 × 10 from the drain current Id of each node. -9 Subtracting that, then 1 / (5 × 10 -4 -1.5 × 10 -9 The value obtained by multiplying by ) becomes the normalized drain current Id. Note that the above conversion is performed when evaluating the waveform shape on a linear axis; when evaluating the waveform shape on a logarithmic axis, a logarithmic function is applied before performing the normalization calculation. For example, when evaluating the drain current Id axis as a logarithmic axis, the drain current at the MAX node is set to -3.3 and the drain current at the MIN node is set to -8.8 before performing normalization.

[0050] The same applies when calculating the Gini coefficient by selecting fewer nodes than the six nodes. For example, Figure 6A shows the selection of three consecutive nodes, Nodes 2 through 4. In this case, Node 2 is the MIN node and Node 4 is the MAX node. Then, normalization is performed by setting the source-drain voltage Vds and drain current Id of Node 2, the MIN node, to 0, and the source-drain voltage Vds and drain current Id of Node 4, the MAX node, to 1. As a result, a graph of the Gini coefficient is obtained, as shown in Figure 6B, which plots the Lorentz curve represented by Nodes 2 through 4 and a uniform straight line where y=x.

[0051] When selecting three or more nodes from the six nodes from Node 1 to Node 6, there are a total of 10 possible combinations: 4 sets when there are three nodes, 3 sets when there are four nodes, 2 sets when there are five nodes, and 1 set when there are six nodes. In addition, while Figure 4 above shows the electrical characteristic waveform with the drain current Id on the vertical axis represented on a logarithmic scale, it is also possible to represent the electrical characteristic waveform with the drain current Id on the vertical axis represented on a linear scale. Since the Gini coefficient can be calculated for both the logarithmic scale and the linear scale, the Gini coefficient can be calculated for 10 combinations in each pattern, for a total of 20 combinations.

[0052] The "slope" is also used to quantify the shape information of the electrical characteristic waveform. Here, "slope" refers to the gradient of the straight line connecting any two points on the electrical characteristic waveform graph, in this case, two nodes, and is expressed as the change in drain current Id on the vertical axis (x-axis) with respect to the change in source-drain voltage Vds on the horizontal axis (y-axis).

[0053] When selecting any two nodes from the six nodes from Node 1 to Node 6, the number of combinations is 6C2 = 15. Furthermore, while Figure 4 above shows the electrical characteristic waveform with the drain current Id on the vertical axis represented on a logarithmic scale, it is also possible to represent the electrical characteristic waveform with the drain current Id on the vertical axis represented on a linear scale. Since the slope can be calculated for both the logarithmic and linear scales, a total of 30 combinations can be calculated for the slope, 15 for each pattern.

[0054] In this way, by calculating the "Gini coefficient" and "slope," it is possible to create a total of 50 feature quantities: 30 for the Gini coefficient and 20 for the slope. From these 50 feature quantities, two feature quantities capable of accurately determining whether a product is good or bad are selected, and these two are set as the vertical and horizontal axes for linear discrimination. The criteria for being able to accurately determine whether a product is good or bad are a high detection rate of defective products and a low false positive rate where good products are mistakenly identified as defective products. The discriminant formula used for linear discrimination is calculated to satisfy these criteria. More specifically, it is preferable to consider the expenses such as repair costs that would be expected if defective products were mistakenly shipped, and the losses that would occur if products were not shipped due to false positives, and then set the discriminant formula to make a profit by looking at the difference between expenses and losses.

[0055] Specifically, for all SiC semiconductor devices used in the experiment, 50 feature quantities—in this case, the Gini coefficient and slope—along with data indicating whether the device was good or bad, are stored in a computer as training data. A microcomputer equipped with a CPU, ROM, RAM, I / O, etc., can be used as the computer. Next, two arbitrary feature quantities are selected from the 50, and a two-axis coordinate system is set with one as the x-axis and the other as the y-axis. Then, from all the stored feature quantities for each SiC semiconductor device, the same feature quantities as the two previously selected are extracted, and the values ​​of each feature quantity and their corresponding points are plotted on the two-axis coordinate system. If two arbitrary feature quantities are selected from the 50, 50Two-axis coordinates for 1225 possible combinations of C2 are set, and the features corresponding to the two axes are extracted from all the stored features of each SiC semiconductor device and plotted. At this time, it is possible to determine whether each plot was a good product or a defective product.

[0056] Figure 7 shows one example. Here, the Gini coefficient calculated by selecting five consecutive nodes from node 2 to node 6 on a logarithmic scale, and the slope of the line connecting two selected nodes, node 3 and node 5, on a linear scale, are selected as two features. The former is used as the horizontal axis and the latter as the vertical axis, forming a two-axis coordinate system. On this two-axis coordinate system, points corresponding to the Gini coefficient calculated by selecting five consecutive nodes from node 2 to node 6 for each SiC semiconductor device, and the slope of the line connecting the two selected nodes, node 3 and node 5, on a linear scale, are plotted. Based on this, a line L1 is drawn on the two-axis coordinate system that has a high detection rate for defective products and a low over-detection rate for good products, and the following discriminant formula is calculated based on the equation y = -ax + b that represents this line L1.

[0057] (Math 1) y≧-ax+b However, in equation 1, "-a" represents the slope of line L1, and "b" represents the intercept of line L1.

[0058] Specifically, the horizontal axis represents the Gini coefficient calculated by selecting five consecutive nodes from node 2 to node 6 on a logarithmic scale, and the vertical axis represents the slope of the line connecting two selected nodes, node 3 and node 5, on a linear scale, which is defined as y. When these features are substituted into the discriminant equation, if y ≥ -ax + b, the product is classified as good; if y < -ax + b, the product is classified as NG (Not Good).

[0059] The discriminant formula set in this way can be calculated using only arithmetic and logarithmic operations based on actual device data. Therefore, compared to performing good / bad judgment using machine learning, it is possible to calculate the discriminant formula with simple calculations and implement it easily. Of course, the discriminant formula used for linear discrimination can be a formula that represents a nonlinear curve or the like, rather than a formula that represents a straight line L1. However, using a formula that represents a straight line L1 makes it simpler. Furthermore, good / bad judgment based on the discriminant formula can increase the detection rate of defective products while keeping the over-detection rate low. Therefore, it is possible to more appropriately detect crystal defects caused by killer defects, suppress their rejection and commercialization, and manufacture highly reliable SiC semiconductor devices. In addition, it is possible to improve yield by suppressing over-detection.

[0060] As explained above, a discriminant formula can be obtained, and this formula can be used to determine whether a SiC semiconductor device is good or bad. Next, a method for manufacturing a SiC semiconductor device, including such good / bad determination, will be described.

[0061] The SiC semiconductor device shown in Figure 1 is manufactured according to the manufacturing process flowchart shown in Figure 8.

[0062] First, in step S100, a device formation process is carried out to form a semiconductor element. Specifically, after preparing a SiC wafer to constitute the SiC substrate 11, a buffer layer 12 and a low-concentration layer 13 are formed sequentially by epitaxial growth. Then, a mask (not shown) is formed on the surface of the low-concentration layer 13, with an opening in the area where the JFET portion 14 is to be formed, and the JFET portion 14 is formed by ion implantation of n-type impurities. Furthermore, a mask is formed again on the surfaces of the JFET portion 14 and the low-concentration layer 13, with an opening in the area where the deep layer 15 is to be formed, and the deep layer 15 is formed by ion implantation of p-type impurities.

[0063] Next, a current-dispersing layer 16 made of SiC is epitaxially grown on the low-concentration layer 13, the JFET section 14, and the deep layer 15. This forms a drift layer consisting of the buffer layer 12, the low-concentration layer 13, the JFET section 14, and the current-dispersing layer 16. After placing a mask in which the area to be formed of the connecting layer 20 is opened, the connecting layer 20 is formed by ion implantation of p-type impurities.

[0064] Furthermore, a base region 17 is formed by epitaxially growing a p-type impurity layer on the current dispersion layer 16 and the connecting layer 20, and then a source region 18 is formed by epitaxially growing an n-type impurity layer on the base region 17. Subsequently, a mask is placed in which the area to be formed in the contact region 19 is opened, and then the contact region 19 is formed by ion implantation of p-type impurities. In this way, each impurity layer is constructed.

[0065] Next, the trench gate structure is formed by anisotropic etching to create a gate trench 21, a gate insulating film 22, and a gate electrode 23. After that, the interlayer insulating film 24 is deposited, contact holes 24a are formed, source electrodes 25 and gate wiring are formed, and drain electrodes 26 are formed on the back side of the SiC substrate 11. Finally, the substrate is divided into chip units by dicing. This completes the production of the SiC semiconductor chip of this embodiment.

[0066] Next, in step S110, the electrical characteristics of each chip in the SiC semiconductor device are measured. The electrical characteristics are measured using a tester or the like. In this embodiment, the electrical characteristics of the drain current Id with respect to the source-drain voltage Vds are measured by changing the source-drain voltage Vds in multiple steps. For example, as described above, the drain current Id is measured by changing the source-drain voltage Vds in six steps: 100V, 400V, 600V, 900V, 1100V, and 1200V.

[0067] Furthermore, in step S120, the measurement data of the electrical characteristics is input into an inspection device (not shown). Then, the inspection device calculates the electrical characteristic features based on the measurement results. At this time, only the features used for good / bad judgment, that is, the features used for linear discrimination, need to be calculated.

[0068] As described above, a discriminant formula is calculated based on various feature quantities obtained in advance from a large amount of actual equipment data, which results in a high detection rate for defective products and a low rate of false positives for good products. This discriminant formula is also stored in the inspection device. For this reason, the inspection device also knows the feature quantities used for linear discriminant analysis, and these feature quantities are calculated from the measurement results of the electrical characteristics.

[0069] For example, if the Gini coefficient calculated by selecting five consecutive nodes from node 2 to node 6 on the logarithmic scale shown in Figure 7, and the slope of the line connecting two selected nodes, node 3 and node 5, on the linear scale, are features used in the discriminant formula, then these will be calculated. Of course, it is also possible to calculate all 50 of the above-mentioned features and extract the features used in the discriminant formula from among them, but since the inspection device already knows the features to be used in the discriminant formula, the computational load can be reduced by calculating only the necessary features.

[0070] In the following step S130, a good / bad product determination is performed. Specifically, for each SiC semiconductor device, the two calculated feature quantities are substituted as x and y values ​​in the discriminant formula y≧-ax+b, representing the x and y axes in a two-axis coordinate system. If the discriminant formula is satisfied, the device is determined to be a good product; if y<-ax+b and the discriminant formula is not satisfied, the device is determined to be a defective product. SiC semiconductor devices determined to be defective are rejected and disposed of, while those determined to be good products proceed to the shipping process.

[0071] This discriminant-based good / bad judgment method allows for a high detection rate of defective products while keeping the false positive rate low. Therefore, more accurate good / bad judgments can be made, allowing for the rejection of defective products, thus preventing products that should be rejected from being commercialized and enabling the manufacture of highly reliable SiC semiconductor devices. Furthermore, suppressing false positives improves yield.

[0072] (Other embodiments) This disclosure is written in accordance with the embodiments described above, but is not limited to those embodiments and includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and concept of this disclosure.

[0073] For example, in the above embodiment, an electrical characteristic waveform showing the relationship between the source-drain voltage Vds and drain current Id when a reverse bias is applied while the vertical MOSFET is off was used to extract the feature quantities, but other electrical characteristic waveforms may be used. For example, an electrical characteristic waveform showing the relationship between the gate voltage Vg and drain current Id when the vertical MOSFET 30 is turned on by applying a gate voltage Vg can be used. Alternatively, an electrical characteristic waveform showing the relationship between the source-drain voltage Vds and drain current Id when the vertical MOSFET 30 is turned on may be used.

[0074] Furthermore, although six measurement points for electrical characteristics were used in the above embodiment, three or more points are sufficient. Also, while the Gini coefficient and slope were used as features, only one of them may be used, or other parameters may be used. For example, the Gini coefficient is shown as an example of a case where the graph of the electrical characteristic waveform is divided into regions separated by nodes, and the area of ​​each divided region is used as a feature; however, it is also possible to use other areas that are divided in the same way as features.

[0075] Specifically, the Gini coefficient is the area S1 of the crescent-shaped region between the uniform straight line and the Lorentz curve, i.e., the graph of the electrical characteristic waveform, between the nodes. This corresponds to the sum of the areas of each region into which the crescent-shaped region is divided for each node. In other words, area S1 is calculated as the sum of the differences between the areas Sa1 to Sa5 shown by solid hatching in Figure 9 and the areas Sb1 to Sb5 shown by dashed hatching. That is, area S1 is the sum of the difference between the area Sa1 of the right-angled isosceles triangle between node 1 and node 2 and the area Sb1 of the right-angled triangle, and the difference between the areas Sa2 to Sa5 of the trapezoids between adjacent nodes from node 2 to node 6 and the areas Sb2 to Sb5 of the trapezoids.

[0076] In contrast, instead of using the sum of the divided areas, the area of ​​the divided region itself can be used as a feature. For example, the area obtained by dividing the crescent-shaped portion into nodes, such as the difference between area Sa1 and area Sb1, can be used as a feature. Alternatively, the areas Sb1 to Sb5 of the parts other than the crescent-shaped portion for each node can also be used as features.

[0077] Furthermore, in the above embodiment, two features are selected from among multiple features, and a two-axis coordinate system is set with one as the x-axis and the other as the y-axis. A discriminant expression is set to perform linear discrimination on the selected two axes to determine whether the product is good or bad. Alternatively, instead of a two-axis coordinate system, three features may be selected from among multiple features, and a three-axis coordinate system may be set with one as the x-axis, another as the y-axis, and the remaining one as the z-axis. A discriminant expression is then set for the selected three axes to determine whether the product is good or bad. In that case, the three features and their corresponding points are plotted on the three-axis coordinate system, and the discriminant expression for the three-axis coordinate system is calculated.

[0078] Furthermore, although the above embodiment described a SiC semiconductor device in which a semiconductor element is formed using SiC as the semiconductor material, this disclosure can be applied not only to SiC but also to semiconductor devices composed of other semiconductor materials such as GaN and Si. However, compound semiconductors such as SiC and GaN have particularly high crystal defect densities, and these crystal defects can become killer defects, so it is particularly suitable for application to semiconductor devices that use compound semiconductors as semiconductor materials.

[0079] Furthermore, although the above embodiment described a vertical MOSFET 30 as an example of a semiconductor element formed on a semiconductor device, this disclosure can also be applied to semiconductor devices on which other semiconductor elements, such as IGBTs, are formed. [Explanation of symbols]

[0080] 11…SiC substrate, 12…Buffer layer, 13…Low-concentration layer, 14…JFET section, 15…Deep layer, 16…Current dispersion layer, 17…Base region, 18…Source region, 19…Contact region, 20…Connecting layer, 21…Gate trench, 22…Gate insulating film, 23…Gate electrode, 24…Interlayer insulating film, 24a…Contact hole, 25…Source electrode, 26…Drain electrode, 30…Vertical MOSFET, 40…Built-in diode

Claims

1. After preparing a semiconductor wafer, a device formation process is carried out to form a semiconductor element (S100), (S110) Measuring the electrical characteristics of each semiconductor device that will be made into a chip from the aforementioned semiconductor wafer, (S120) The area of ​​an arbitrary region on the graph of the electrical characteristic waveform obtained by measuring the aforementioned electrical characteristics, or the slope of the line connecting the area and any two points on the graph, is used as a feature quantity to calculate the feature quantity. A method for manufacturing a semiconductor device, comprising: (S130) determining whether each of the semiconductor devices is good or bad based on the feature quantities and discriminant formula obtained by calculating the feature quantities.

2. In calculating the aforementioned feature quantities, the graph is divided into multiple regions, and the area of ​​each divided region, or the area and the slope of the line connecting any two points on the graph, are calculated as the feature quantities. The method for manufacturing a semiconductor device according to claim 1, wherein in the good / bad judgment, two are selected from the feature quantities calculated in each region, a mathematical formula is set as the discriminant formula to perform linear discrimination of the two selected features along two axes, and the good / bad judgment is performed based on the two selected feature quantities and the discriminant formula.

3. The method for manufacturing a semiconductor device according to claim 2, wherein the calculation of the aforementioned feature quantities involves calculating the area of ​​each region obtained by dividing the graph into multiple regions, and calculating the area as the Gini coefficient.

4. A method for manufacturing a semiconductor device according to claim 3, wherein each point dividing the graph into multiple regions is designated as a node, three or more nodes are selected from among the multiple nodes, the node with the smallest absolute value of the electrical characteristics among the three or more selected nodes is designated as the MIN node, the node with the largest absolute value of the electrical characteristics is designated as the MAX node, the electrical characteristics at the MIN node are normalized to 0 and the electrical characteristics at the MAX node are normalized to 1, and the value of twice the area enclosed by the uniform straight line where y=x on the two axes and the Lorentz curve connecting the three or more selected nodes is calculated as the characteristic quantity of the area of ​​each region.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the discriminant formula is calculated as a mathematical formula for distinguishing between good products and NG products based on actual device data obtained by calculating the feature quantities for a plurality of semiconductor devices manufactured in advance and inspecting whether the semiconductor device was a good product or an NG product.

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