On-chip integration of high-efficiency and high-retention inversion wide-base dual magnetic tunnel junction devices

Abstract

A method of fabrication and resulting devices are directed to an inverted wide base double magnetic tunnel junction device having both a high efficiency array and a high retention array. The method includes a method of fabricating a high efficiency array and a high retention array on a common stack for an inverted wide base double magnetic tunnel junction device. The method includes forming a first magnetic tunnel junction stack (MTJ2), forming a spin conducting layer on the MTJ2, and forming a second magnetic tunnel junction stack (MTJ1) on the spin conducting layer for the high efficiency array and the high retention array. A high retention critical dimension (CD) (HRCD) of the first magnetic tunnel junction stack for the high retention array is greater than a high efficiency critical dimension (HECD) of the first magnetic tunnel junction stack for the high efficiency array. The second magnetic tunnel junction stack (MTJ1) is shorted in the high retention array and is not shorted in the high efficiency array.

Description

[Technical Field]

[0001] The present invention relates to magnetic tunnel junction ("MTJ") devices and methods for manufacturing MTJ devices. More specifically, the present invention relates to an inverted wide-base dual MTJ device that includes both high-efficiency and high-retention components. [Overview of the project]

[0002] Embodiments of the present invention relate to a method for manufacturing an inverted wide-base dual magnetic tunnel junction device having both a high-efficiency array and a high-retention array. The method includes manufacturing a high-efficiency array and a high-retention array for an inverted wide-base dual magnetic tunnel junction device on a common stack. The method includes, for the high-efficiency array and the high-retention array, forming a first magnetic tunnel junction stack (MTJ2), forming a spin conduction layer on the MTJ2, and forming a second magnetic tunnel junction stack (MTJ1) on the spin conduction layer. The high retention limit dimension (CD) (HRCD) of the first magnetic tunnel junction stack for the high-retention array is greater than the high efficiency limit dimension (HECD) of the first magnetic tunnel junction stack for the high-efficiency array. The second magnetic tunnel junction stack (MTJ1) is short-circuited for the high-retention array and not short-circuited for the high-efficiency array.

[0003] Other embodiments relate to inverted wide-base dual magnetic tunnel junction devices having both high-efficiency arrays and high-retention arrays. These devices include a magnetic tunnel junction device comprising a high-efficiency array including a first magnetic tunnel junction stack (MTJ2), a spin conduction layer on the MTJ2, and a second magnetic tunnel junction stack (MTJ1) on the spin conduction layer, and a high-retention array including the first magnetic tunnel junction stack MTJ2, all on a common base. The device further includes a spin conduction layer on the MTJ2 and a second magnetic tunnel junction stack MTJ1 on the spin conduction layer. The high retention limit dimension (CD) (HRCD) of the first magnetic tunnel junction stack for the high-retention array is greater than the high efficiency limit dimension (HECD) of the first magnetic tunnel junction stack for the high-efficiency array. The second magnetic tunnel junction stack (MTJ1) is short-circuited in the high-retention array and not short-circuited in the high-efficiency array.

[0004] The above summary is not intended to describe each or all of the exemplified embodiments of the present invention.

[0005] The drawings included in this application are incorporated herein and form part thereof. They illustrate embodiments of the present invention and, together with the description, illustrate the principles of the present invention. The drawings are merely illustrative of specific embodiments and do not limit the present invention. [Brief explanation of the drawing]

[0006] [Figure 1] (A) and (B) are cross-sectional views of a specific base layer formed beneath a high-efficiency and high-retention inversion wide-base double magnetic tunnel junction device according to some embodiments. [Figure 2] (A) and (B) are cross-sectional views showing the high-efficiency and high-retention inverting wide-base dual magnetic tunnel junction devices of Figures 1(A) and 1(B) after additional manufacturing operations have been performed, according to some embodiments. [Figure 3](A) and (B) are cross-sectional views showing the high-efficiency and high-retention inverting wide-base dual magnetic tunnel junction devices of Figures 2(A) and 2(B) after additional fabrication operations have been performed, according to some embodiments. [Figure 4] (A) and (B) are cross-sectional views showing the high-efficiency and high-retention inverting wide-base dual magnetic tunnel junction devices of Figures 3(A) and 3(B) after additional fabrication operations have been performed, according to some embodiments. [Figure 5] (A) and (B) are cross-sectional views showing the high-efficiency and high-retention inverting wide-base dual magnetic tunnel junction devices of Figures 4(A) and 4(B) after additional fabrication operations have been performed, according to some embodiments. [Figure 6] (A) and (B) are cross-sectional views showing the high-efficiency and high-retention inverting wide-base dual magnetic tunnel junction devices of Figures 5(A) and 5(B) after additional fabrication operations have been performed, according to some embodiments. [Figure 7] (A) and (B) are cross-sectional views showing the high-efficiency and high-retention inverting wide-base dual magnetic tunnel junction devices of Figures 6(A) and 6(B) after additional manufacturing operations have been performed, according to some embodiments. [Figure 8] (A) and (B) are cross-sectional views showing the high-efficiency and high-retention inverting wide-base dual magnetic tunnel junction devices of Figures 7(A) and 7(B) after additional fabrication operations have been performed, according to some embodiments. [Figure 9] (A) and (B) are cross-sectional views showing the high-efficiency and high-retention inverting wide-base dual magnetic tunnel junction devices of Figures 8(A) and 8(B) after additional fabrication operations have been performed, according to some embodiments. [Figure 10] (A) and (B) are cross-sectional views showing the high-efficiency and high-retention inverting wide-base dual magnetic tunnel junction devices of Figures 9(A) and 9(B) after additional fabrication operations have been performed, according to some embodiments. [Figure 11](A) and (B) are cross-sectional views showing the high-efficiency and high-retention inverting wide-base dual magnetic tunnel junction devices of Figures 10(A) and 10(B) after additional manufacturing operations have been performed, according to some embodiments. [Figure 12] This is a flowchart illustrating the operations involved in the manufacturing of a high-efficiency, high-retention, inverting wide-base dual magnetic tunnel junction device according to some embodiments. [Modes for carrying out the invention]

[0007] This disclosure describes a dual magnetic tunnel junction ("DMTJ") device and a method for manufacturing a DMTJ device. In particular, this disclosure describes an inverted wide-base dual MTJ device that includes both high-speed and high-retention components.

[0008] Various embodiments of the present invention are described herein with reference to the relevant drawings. Alternative embodiments can be devised without departing from the scope of the present invention. Various connections and positional relationships (e.g., above, below, adjacent, etc.) are described between elements in the following description and drawings. These connections or positional relationships, or both, may be direct or indirect unless otherwise specified, and the disclosure is not intended to limit in this respect. Thus, the joining of entities may refer to either a direct or indirect joining, and the positional relationship between entities may be a direct or indirect positional relationship. As an example of an indirect positional relationship, the reference herein to forming layer "A" on layer "B" includes a situation in which one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B", provided that the relevant properties and functionality of layers "A" and "B" are not substantially altered by the intermediate layers.

[0009] The following definitions and abbreviations are used for the interpretation of the claims and specification. As used herein, the terms “comprise,” “comprising,” “includes,” “including,” “has,” “having,” “contains,” or “containing,” or any other variation thereof, are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus containing a list of elements is not necessarily limited to those elements alone and may include other elements not expressly enumerated or that are specific to such composition, mixture, process, method, article, or apparatus.

[0010] Unless otherwise specified, the ranges shown herein (e.g., time, concentration, temperature, etc.) include all numerical values ​​at both endpoints and between the endpoints. Unless otherwise specified, the use of “approximately,” “about,” or the tilde (~) in relation to a range applies to both ends of the range (e.g., “approximately 1g to 5g” should be interpreted as “approximately 1g to approximately 5g”), and in relation to a list of ranges, it applies to each range within the list (e.g., “approximately 1g to 5g, 5g to 10g, etc.” should be interpreted as “approximately 1g to approximately 5g, approximately 5g to approximately 10g, etc.”). Unless otherwise indicated, modifying terms such as “approximately,” “about,” and “~” indicate ±10% of the endpoints of the value, range of value, or range of one or more values ​​mentioned.

[0011] For the purposes of the following explanation, the terms “top,” “bottom,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall be as they appear in the described structures and methods, as oriented in the drawings. The terms “overlying,” “atop,” “on top,” “positioned on,” or “positioned atop” mean that a first element, such as a first structure, is located on a second element, such as a second structure, and that an intervening element, such as an interface structure, may be located between the first and second elements. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface of the two elements without an intermediate conductive, insulating, or semiconductor layer. For example, the term “selective to” means that the first element can be etched and the second element can act as an etch stop.

[0012] For the sake of brevity, prior art related to the manufacture of semiconductor devices and integrated circuits ("ICs") may or may not be described in detail herein. Furthermore, various tasks and process steps described herein can be incorporated into more comprehensive procedures or processes that have additional steps or functions not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps are only briefly mentioned herein or are completely omitted without providing details of well known processes.

[0013] Generally, the various processes used to form microchips that are packaged into ICs are classified into four common categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography.

[0014] Deposition is any process of growing, coating, or otherwise transferring material onto a wafer. Available techniques include, among others, physical vapor deposition ("PVD"), chemical vapor deposition ("CVD"), electrochemical deposition ("ECD"), molecular beam epitaxy ("MBE"), and more recently atomic layer deposition ("ALD"). Another deposition technique is plasma enhanced chemical vapor deposition ("PECVD"), which is a process that uses energy within a plasma to induce reactions on the wafer surface that would otherwise require higher temperatures typically associated with conventional CVD. Energy-ion bombardment during PECVD deposition can also improve the electrical and mechanical properties of the film.

[0015] Removal / etching is any process of removing material from a wafer. Examples include etching processes (either wet or dry), chemical mechanical planarization ("CMP"), etc. An example of a removal process is ion beam etching ("IBE"). Generally, IBE (or milling) refers to a dry plasma etching method that utilizes a remote broad beam ion / plasma source to remove substrate material by means of a physical inert gas, a chemically reactive gas, or both. Similar to other dry plasma etching techniques, IBE has advantages such as etching rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry removal process is reactive ion etching ("RIE"). Generally, RIE uses a chemically reactive plasma to remove material deposited on a wafer. In RIE, the plasma is generated under low pressure (vacuum) by an electromagnetic field. High energy ions from the RIE plasma attack the wafer surface and react with the wafer to remove the material.

[0016] Semiconductor doping generally involves changing electrical properties by diffusion or ion implantation or both, for example, by doping the source and drain of a transistor. Following these doping processes, furnace annealing or rapid thermal annealing ("RTA") is performed. Annealing serves to activate the implanted dopants. Films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. By selectively doping various regions of a semiconductor substrate, the conductivity of the substrate can be changed by applying a voltage. By creating the structures of these various components, millions of transistors can be constructed and wired together to form the complex circuits of modern microelectronic devices.

[0017] Semiconductor lithography is the formation of a three-dimensional relief image or pattern on a semiconductor substrate, followed by the transfer of that pattern to the substrate. In semiconductor lithography, the pattern is formed by a photosensitive polymer called a photoresist. To build the complex structures that make up a transistor and the numerous wires that connect the millions of transistors in a circuit, lithography and etching pattern transfer steps are repeated multiple times. Each pattern printed on the wafer is aligned to previously formed patterns, and conductors, insulators, and selectively doped regions are gradually built up to form the final device.

[0018] Turning to an overview of the technology more specifically relevant to aspects of the present invention, embedded DRAM ("eDRAM") is dynamic random-access memory ("DRAM") integrated on the same die or multi-chip module ("MCM") of an application-specific integrated circuit ("ASIC") or microprocessor. eDRAM technology has been implemented using silicon-on-insulator ("SOI") technology, which refers to the use of a layered silicon-insulator-silicon substrate instead of a conventional silicon substrate in semiconductor manufacturing. eDRAM technology has achieved various successes, and the demand for SOI technology as a server memory option has decreased in recent years.

[0019] Magnetic tunnel junction ("MTJ") magnetoresistive random-access memory ("MRAM") devices are one alternative to existing eDRAM technology. MRAM is a non-volatile memory, and this advantage is a driving force accelerating the development of this memory technology. Current MRAM MTJ structures are relatively slow, and the only way to achieve MTJ write target speeds comparable to eDRAM (approximately 5 ns) is to use a dual magnetic tunnel junction ("DMTJ"). DMTJ devices reduce the write current by half.

[0020] Certain DMTJ devices utilize wide, non-magnetic-based improved DMTJ devices to enhance the switching efficiency of the MTJ by eliminating both the resistance area ("RA") penalty and the magnetoresistance ("MR") penalty associated with standard DMTJs having similar top and bottom MTJs with similar limit dimensions ("CD"). These types of wide-based devices offer the advantages of dual-spin current sourcing ("DSTT"). Additionally, in these types of devices, the bottom barrier layer can have a relatively high RA. These devices can leverage spin diffusion transport within the non-magnetic ("NM") metal layer to achieve a reduction in charge current density through the bottom MgO layer. The bottom NM layer can also act as an additional boron drain conduit during the annealing process. In some of these devices, a non-magnetic spin conductor is used between two MTJ stacks (e.g., Cu, CuN, Cu3N, CuN / Cu / CuN, CuN / Cu(100)Ag, AgSn, etc.). During the fabrication of these devices, an in-situ stack deposition process is desirable to ensure stack integrity and avoid unexpected losses of spin conductance that can occur in ex-situ processes such as oxidation or CMP. However, these wide-based DMTJ devices require, for example, stop etching (harness) on Ag-type NM layers. Furthermore, it is necessary to control the nucleation front of a body-centered cubic (e.g., CoFe) layer.

[0021] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limitful to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the embodiments described. The terminology used herein has been selected to best describe the principles of the embodiments, their practical applications or technical improvements to marketable technologies, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0022] The following acronyms may be used below.

[0023] [Table 1]

[0024] The general concept of wide non-magneticbase modified double MTJs (mDMTJs) is known to improve the switching efficiency of MTJs by eliminating both the resistancearea (RA) and magnetoresistance (MR) penalties of standard double MTJs with similar critical dimensions (CD) for the top and bottom MTJs. Similarly, inverted MDMTJ designs are known to have better manufacturability and yield than conventional structures.

[0025] While MDMTJ designs offer the potential for high speed and efficiency, achieving both high density and high retention using this structure is challenging. To illustrate, when using an inverted structure in a high-efficiency array with a 35nm CD for the bottom MTJ and a 100nm CD for the top MTJ, achieving a high-retention array requires the following: a CD of approximately 80nm for the bottom MTJ and approximately 250nm for the top MTJ. This significantly reduces magnetoresistive random-access memory (MRAM) density (in this example, an MTJ pitch of approximately 500nm is required). However, reducing the CD of the top MTJ for an on-chip high-retention array dilutes (reduces) the tunnel magnetoresistance (TMR), which is undesirable (to minimize TMR dilution, it is typically necessary to increase the area tenfold or increase the CD by 3.1 times).

[0026] To address this and achieve high density, various embodiments described herein provide methods for achieving high-efficiency and high-retention arrays within the same stack without adversely impacting TMR. Various embodiments may have some or all of the following features: a) a structure and integration method for achieving high-density, high-efficiency, and high-retention on-chip arrays of STT-MRAM; b) all arrays share the same stack; c) high-retention arrays have a larger bottom MTJ CD while the top barrier is shorted; d) the structure maintains the high density of the high-retention arrays without adversely impacting its TMR; and e) a novel process flow is provided for the structure without adding process complexity and providing similar stacks for both arrays.

[0027] This embodiment includes a method for manufacturing DMJT and DMTJ structures in which a common stack shares both a high-efficiency array and a high-retention array. Cross-sectional views (Figures 1(A) to 11(B)) showing the structure at various stages of the manufacturing method 1200, provided by the flowchart in Figure 12, are provided. The flowchart of the method steps is described in relation to the cross-sectional views. In some alternative embodiments, the manufacturing steps in the flowchart may be performed in a different order than that shown in the figure. Furthermore, any of the layers shown in the figure may include multiple sublayers.

[0028] Here, similar numbers refer to drawings that represent the same or similar elements, but first referring to Figures 1(A) and 1(B), an exemplary method for manufacturing a DMTJ stack to which this embodiment may be applied is shown. In Figures 1(A) to 11(B), which are cross-sectional views shown in different manufacturing steps, figure numbers ending in "A" indicate embodiments of the high-efficiency array 100, and figure numbers ending in "B" indicate embodiments of the high-retention array 100'. Also, in the structural reference numbers of Figures "B", a prime (or, for simplicity as used herein) '' is added after a reference structure that is different from a similar structure shown in Figure "A", and a prime (or, for simplicity as used herein) '' is not added after a reference structure that is the same as the corresponding data structure shown in Figure "A".

[0029] In Figure 1(A), a cross-sectional view of the stack, the creation of the high-efficiency array 100 begins in operation 1205 (Figure 12) with the formation of the x-th level wiring process ("BEOL") layers 102, 104. Generally, BEOL is the second part of IC manufacturing where individual devices (transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer. As shown in Figure 1(A), the first BEOL layer includes a BEOL Mx dielectric layer 102 and a BEOL Mx metal layer 104. The Mx dielectric layer 102 is made of, for example, SiO x SiN x It may consist of SiBCN, low-κ NBLoK (nitrogen-doped silicon carbide), or any other suitable dielectric material. The Mx metal layer 104 may include, for example, Cu, TaN, Ta, Ti, TiN, or a combination thereof.

[0030] In operation 1210, a via layer may be formed above the Mx layer, and the via layer may include a via dielectric 110 portion and a via filling 112 portion. The via dielectric 110 portion can be deposited, for example, using lithography and RIE. The via filling 112 portion can be filled with a metal including, for example, W, Cu, TaN, Ta, Ti, TiN, TiOCN, TaOCN, or any combination, using CVD, PVD, ALD, or any combination, and the surface can be planarized using CMP. A similar process can be used for the high-retention array 100' as shown in Figure 1(B).

[0031] Figure 2(A) is a cross-sectional view of the stack # showing the result of operation 1215 for depositing MTJ2 120, as well as the seed / metal spacer layer and spin conduction layer 122. (The MTJ1 stack placed on top of this will be described later.)

[0032] MTJ2 120 has a reference (pinning) layer, a tunnel barrier, and a free layer above the tunnel barrier (not shown). MTJ1 has a reference layer and a tunnel barrier. The tunnel barrier may include materials with higher electrical tunnel conductance while maintaining spin polarization, such as MgO, AlO, and TiO, or semiconductors or low-bandgap insulators.

[0033] The magnetization reference layer may consist of a metal or metal alloy (or a stack thereof) containing one or more metals that have a fixed magnetization and exhibit high spin polarization at the tunnel barrier interface. The magnetization reference layer may contain Fe, Ni, Co, Cr, B, and Mn. The magnetization reference layer may also have a multilayer configuration comprising: 1) a high-spin-polarized region formed by the aforementioned metals or metal alloys, or both; and 2) a region composed of a material exhibiting strong perpendicular magnetic anisotropy (strong PMA). Exemplary materials with strong PMA that can be used include metals such as Co, Ni, Pt, Pd, Ir, or Ru, which may be stacked alternately. The strong PMA region may also contain alloys that exhibit strong intrinsic or bulk PMA (as opposed to the interface), and exemplary alloys include Co-Fe-Tb, Co-Fe-Gd, Co-Cr-Pt, Co-Pt, Co-Pd, Fe-Pt, or Fe-Pd, or combinations thereof. The alloy layers may be stacked alternately.

[0034] The free layer can consist of a magnetic material (or a stack of magnetic materials) having a magnetization whose orientation is variable relative to the magnetization direction of the magnetization reference layer. Examples of magnetic materials for the magnetization free layer include Co, Fe, and alloys or multilayers of Co-Fe, Ni, or combinations thereof, Ni-Fe alloys, Co-Fe-B alloys, and Mn x Ge y and Al x Mn y Examples include Heusler compounds such as Ge.

[0035] The MTJ2 stack 120 is formed, followed by the spin conduction layer 122, and then the MTJ1 stack 124. For simplification and ease of understanding, not all layers of the MTJ stack are shown in the figure. In some embodiments, the MTJ stacks 120 and 124 each include a reference layer, a first tunnel barrier layer, a first free layer, a metal spacer layer, a second free layer, and a second tunnel barrier layer. It should be understood that the MTJ stack may include additional layers, certain layers may be omitted, and each layer may include sublayers.

[0036] Generally, in an MTJ stack, information is stored in the form of the magnetization direction of the free layer film (described in further detail herein) relative to the magnetization direction of the reference layer. The reference layer may be a single layer or multiple layers. In one embodiment, the reference layer of the MTJ stack is a synthetic antiferromagnetic ("SAF") layer. In some embodiments, the reference layer of the MTJ stack includes multiple sublayers (e.g., 20 or more sublayers).

[0037] In the formation of any MTJ stack, a first tunnel barrier layer is formed on top of a reference layer. In one embodiment, the first tunnel barrier layer is a thin insulating layer or a barrier such as a potential between two conductive materials. Electrons (or quasiparticles) pass through the tunnel barrier by the process of quantum tunneling. In certain embodiments, the first tunnel barrier layer includes at least one sublayer made of MgO. The first tunnel barrier layer can also be formed using a material other than MgO. The free layer is a magnetized free layer adjacent to the first tunnel barrier layer and opposite the reference layer. The magnetized free layer has a reversible magnetic moment or magnetization. A second tunnel barrier layer is formed on top of the free layer. In certain embodiments, the second tunnel barrier includes an outermost sublayer (or some other sublayer) made of the same material as the first tunnel barrier layer (e.g., MgO). Either MTJ stacks 120 and 124 include additional layers, certain layers may be omitted, and each layer may include any number of sublayers. Furthermore, the composition of the layers, sublayers, or both may differ between the MTJ2 stack 120 and the MTJ1 stack 124. In some embodiments, the MTJ2 stack 120 and the MTJ1 stack 124 are formed by a self-aligning patterning process. However, in certain examples, the MTJ2 stack 120 is not self-aligned with the MTJ1 stack 124. A similar process can also be used for the high-retention array 100', as shown in Figure 2(B).

[0038] Figure 3(A) shows, for example, OPL, SiN x SiO xThis is a cross-sectional view of a stack # showing the result of operation 1220, in which a sacrificial dielectric / organic hard mask (HM), also referred to herein as a sacrificial HM (SHM) stack 130, is deposited for the next layer using a photoresist or photoresist. The SHM 130 may be patterned using, for example, lithography and RIE. Herein begins to differ between the high-efficiency array 100 and the high-retention array 100' in Figure 3(B). For the CD (HECD) of the high-efficiency array 100, a size of 35 nm may be typical (or, for example, in the range between 20 and 35 nm). For the CD (HRCD) of the high-retention array 100', a size of 80 nm may be typical (or, for example, in the range between 70 and 100 nm). This can reflect a CD ratio (HECD vs. HRCD) in the range of, for example, 1:2 to 1:5. The pitch size of a typical MTJ can be in the range of 150 to 200 nm. The pitch size of the MTJ may be scaled according to these dimensions to match other HECD and HRCD sizes.

[0039] Figure 4(A) is a cross-sectional view of the stacks showing the results of operation 1225 for the high-efficiency array 100, where MTJ2 120, 122 are patterned using, for example, IBE, RIE, or any combination thereof. Material removal can be stopped inside (near the top) of the via dielectric layer 110, and in operation 1225, partial short circuits due to metal redeposition can be removed by applying an optional air-break or controlled in-situ oxidation. Figure 4(B) shows the results of operation 1225 for the high-retention array 100', with similar results except that the CD of the MTJ2 stack 120', spin conduction layer stack 122', and sacrificial HM stack 130' is wider.

[0040] Figure 5(A) is a cross-sectional view of the stack showing the result of operation 1230, in which an MTJ2 dielectric (such as SiN or SiBCN) layer 132 is deposited and CMP is performed, stopping at the same height as the spin conduction layer 122. Figure 5(B) shows the same process, but with a smaller MTJ2 dielectric layer 132'.

[0041] FIG. 6(A) is a cross-sectional view of stack # showing the result of operation 1235 of depositing the second MTJ stack (MTJ1) 124 and related layers. In operation 1235, the surface is pre-sputter cleaned to remove native oxide, and then an additional spin conduction layer 122 (continuing the existing spin conduction layer) is deposited. Next, MTJ1 124 is deposited, followed by depositing an etch stop metal layer 134, which may be composed of, for example, Ru.

[0042] Next, a top electrode metal HM layer 136 is deposited. This metal HM layer 136 can include, for example, one of W, TaN, TiN, or any combination thereof. A dielectric / organic HM layer 138 may be added thereon, for example, OPL, SiN x , SiO x , or photoresist, or a combination thereof. The metal HM layer 136 and the dielectric HM layer 138 may be patterned, for example, by lithography and RIE. Here, the CD of MTJ1 124 is larger than that of the lower MTJ2 stack 120. For the high-efficiency array 100, the value of the top CD can typically be about 100 nm, which is, for example, 3.0 to 3.5 times the CD of the bottom MTJ2 stack 120. For the high-retention array 100' as shown in FIG. 6(B), the top CD can typically be 80 to 100 nm. Further, the pitch size of MTJ1 can be about 150 to 200 nm.

[0043] FIG. 7(A) is a cross-sectional view of a stack showing the result of operation 1240 in which MTJ1 124 of the high-efficiency array 100 is patterned using at least one of IBE and RIE. The material removal stops inside (near the top) of the via dielectric layer 110. An optional air break or controlled in-situ oxidation can be performed to avoid partial short circuits due to metal redeposition. A similar process is also applied to the high-retention array 100' in FIG. 7(B).

[0044] Figure 8(A) is a cross-sectional view of the stack showing the result of operation 1245 in which an encapsulation dielectric layer 140 is deposited on the high-efficiency array 100. Any optional pretreatment can be applied, for example, using techniques involving plasma O2, H2, N2, NH3, or a combination thereof. The encapsulation dielectric is AlO x , TiO x SiO x It can contain one of BN, SiN, SiBCN, or any combination thereof, and can be attached using at least one of PVD, ALD, or PECVD. A similar process is applied to the high-retention array 100' in Figure 8(B).

[0045] Figure 9(A) is a cross-sectional view of a stack showing the result of operation 1250 in which a mask 142 is applied to the high-efficiency array 100 using, for example, a resist or spin-on dielectric. Figure 9(B) shows the result of operation 1255 in which the encapsulant 140 is removed from the high-retention array 100'. This removal can be achieved, for example, using a RIE, wet, or IBE process.

[0046] Figure 10(A) is a cross-sectional view of the stack showing the result of operation 1260 on the high-efficiency array 100. The mask 142 has been peeled off from the high-efficiency array 100. Metal spacers 144A are formed on both the high-efficiency array 100 and the high-retention array 110' in Figure 10(B). The metal spacers 144A can be fabricated, for example, as TaN deposition by ALD and RIE. The purpose of the metal spacers 144A is to short-circuit the top MTJ1 124' of the high-retention array 100'. The sealing dielectric 140 prevents this short-circuit in the high-efficiency array 100.

[0047] Figure 11(A) is a cross-sectional view of a stack showing the results of operation 1265 on a high-efficiency array 100. A first interlayer dielectric (ILD1) 150A is deposited as a encapsulating dielectric and spacer dielectric, and CMP is applied. Next, a second interlayer dielectric (ILD2) 150B is deposited. Then, ILD2 150B can be patterned using at least one of lithography or RIE to create bit lines 146 and a filler liner 144B. The metal for the bit lines can include one of TA, TaN, and Cu or a combination thereof. A similar process yields the same results for the high-retention array 100' shown in Figure 11(B).

[0048] The descriptions of various embodiments are presented for illustrative purposes only and are not intended to be exhaustive or to limit the disclosed embodiments. Many variations and modifications will be apparent to those skilled in the art without departing from the scope of the embodiments described. The terminology used herein has been selected to best describe the principles of the embodiments, their practical application to market-available technologies or technical improvements, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0049] In a preferred embodiment of the present invention, a high-efficiency array formed on the common base includes a wiring step (BEOL) layer comprising an Mx dielectric and an Mx metal, a via layer on the BEOL layer comprising a via dielectric and via filling, wherein the BEOL layer and the via layer form a common base, and a high-efficiency array formed on the common base comprising a first magnetic tunnel junction stack MTJ2 formed on the via layer, a spin conduction layer on MTJ2, a second magnetic tunnel junction stack MTJ1 on the spin conduction layer, an etch-stop metal layer on MTJ1, a top electrode hard metal layer on the etch-stop metal layer, a spin conduction layer, MTJ1, an etch-stop metal layer, and a sealing dielectric layer on the side of the top electrode hard metal layer, a metal spacer A adjacent to the sealing dielectric layer, an additional metal spacer B on the top electrode hard metal layer, and bit lines on the additional metal spacer B, and a high-retention array formed on the common base. A magnetic tunnel junction device is provided, comprising a high-retention array including a first magnetic tunnel junction stack MTJ2 formed on a via layer, a spin conduction layer on MTJ2, a second magnetic tunnel junction stack MTJ1 on the spin conduction layer, an etch-stop metal layer on MTJ1, a top electrode hard metal layer on the etch-stop metal layer, a metal spacer A adjacent to the side of the top electrode hard metal layer, an additional metal spacer B on the top electrode hard metal layer, and a bit wire on the additional metal spacer B, wherein the high retention limit dimension (CD) (HRCD) of the first magnetic tunnel junction stack for the high-retention array is greater than the high efficiency limit dimension (HECD) of the first magnetic tunnel junction stack for the high-efficiency array, and the second magnetic tunnel junction stack (MTJ1) is short-circuited in the high-retention array but not in the high-efficiency array.

Claims

1. A method for manufacturing high-efficiency arrays and high-retention arrays for inverted wide-base dual magnetic tunnel junction devices on a common stack, Regarding the high-efficiency array and the high-retention array, To form a first magnetic tunnel junction stack (MTJ2), Forming a spin conduction layer on the MTJ2, Forming a second magnetic tunnel junction stack (MTJ1) on the spin conduction layer, Includes, The high retention limit dimension (CD) (HRCD) of the first magnetic tunnel junction stack for the high retention array is greater than the high efficiency limit dimension (HECD) of the first magnetic tunnel junction stack for the high efficiency array, and The second magnetic tunnel junction stack (MTJ1) is short-circuited in the high-retention array but not in the high-efficiency array. The above method further, A sacrificial hard mask (SHM) is provided on the spin conduction layer, The MTJ2 is formed on the HECD on the high-efficiency array, and the MTJ2 is formed on the HRCD on the high-retention array, The MTJ2 dielectric is provided adjacent to the MTJ2 and the spin conduction layer, To remove the aforementioned SHM, Methods that include...

2. M ｘ Dielectrics and M ｘ A metal-containing wiring layer (BEOL) is provided, The method involves providing a via layer on the BEOL layer, wherein the via layer includes a via dielectric and via filling. It further includes, The MTJ2 is formed on the via layer. The method according to claim 1.

3. Said M ｘ The dielectric is SiO ｘ SiN ｘ The material comprises a material selected from the group consisting of SiBCN and low-κ NBLoK. Said M ｘ The metal includes a material selected from the group consisting of Cu, TaN, Ta, Ti, and TiN. The via filling comprises a material selected from the group consisting of W, Cu, TaN, Ta, Ti, TiN, TiOCN, and TaOCN. The method according to claim 2.

4. The MTJ2 includes a reference layer, a tunnel barrier layer formed on the reference layer, and a free layer on the tunnel barrier layer. The MTJ1 includes a reference layer and a tunnel barrier layer. The method according to claim 1.

5. The method according to claim 1, wherein the ratio of HECD to HRCD of the MTJ2 is 1:2 to 1:

5.

6. The HECD of the MTJ2 is 20 to 35 nm. The HRCD of the MTJ2 is 70 to 100 nm. The method according to claim 5.

7. The method according to claim 6, wherein the pitch size of MTJ1 and the pitch size of MTJ2 are 150 to 200 nm.

8. Providing the aforementioned SHM is OPL, SiN ｘ SiO ｘ The process is carried out by patterning using lithography and RIE, using a material selected from the group consisting of , and photoresist. The spin conduction layer and the MTJ2 are patterned using a technique selected from the group consisting of IBE and RIE. The MTJ2 dielectric comprises a material selected from the group consisting of SiN and SiBCN, and stops at the same height as the spin conduction layer. The method according to claim 1.

9. The method according to claim 1, wherein the spin conduction layer is partially located on the MTJ2 and the MTJ2 dielectric.

10. A method for manufacturing high-efficiency arrays and high-retention arrays for inverted wide-base dual magnetic tunnel junction devices on a common stack, Regarding the high-efficiency array and the high-retention array, To form a first magnetic tunnel junction stack (MTJ2), Forming a spin conduction layer on the MTJ2, Forming a second magnetic tunnel junction stack (MTJ1) on the spin conduction layer, Includes, The high retention limit dimension (CD) (HRCD) of the first magnetic tunnel junction stack for the high retention array is greater than the high efficiency limit dimension (HECD) of the first magnetic tunnel junction stack for the high efficiency array, and The second magnetic tunnel junction stack (MTJ1) is short-circuited in the high-retention array but not in the high-efficiency array. The above method further, Forming an etch-stop metal layer on the MTJ1, Forming a top electrode hard mask layer on the aforementioned etch-stop metal layer, Forming a dielectric hard mask layer on the aforementioned top electrode hard mask layer, Methods that further include the above.

11. The etch-stop metal layer contains Ru, The top electrode hard mask layer comprises a material selected from the group consisting of W, TaN, and TiN. The dielectric hard mask layer includes a material selected from the group consisting of OPL, SiN ｘ , SiO ｘ , and photoresist. The method according to claim 10.

12. The method according to claim 10, wherein the top electrode hard mask layer and the dielectric hard mask layer are patterned by lithography and RIE.

13. A sacrificial hard mask (SHM) is provided on the spin conduction layer, The MTJ2 is formed on the HECD on the high-efficiency array, and the MTJ2 is formed on the HRCD on the high-retention array, The MTJ2 dielectric is provided adjacent to the MTJ2 and the spin conduction layer, To remove the aforementioned SHM, It further includes, The method according to claim 12, further comprising adding sealing dielectric layers to the high-efficiency array and the high-retention array, on the top electrode hard mask layer and the MTJ2 dielectric, and on the sides of the spin conduction layer, the MTJ1, and the etch-stop metal layer.

14. For the high-efficiency array, a mask is added on top of the sealing dielectric layer, but for the high-retention array, it is not added. The sealing dielectric layer is removed for the high-retention array, but not for the high-efficiency array. The method according to claim 13, further comprising:

15. To short-circuit the MTJ1, a metal spacer A is added to the side surface of the sealing dielectric layer, the side surface of the MTJ2 dielectric, the side surface of the spin conduction layer, and the side surface of the MTJ1 of the high-efficiency array. Adding an additional metal spacer B on top of the aforementioned top electrode hard mask layer, The bit wire is added on top of the additional metal spacer B, and the additional metal spacer B is provided on the side of the bit wire. Adding interlayer dielectrics A and B to the sides of the metal spacer A and the additional metal spacer B, The method according to claim 14, further comprising:

16. The method according to claim 1 or 10, wherein the HECD of MTJ1 is 3.0 to 3.5 times that of the HECD of MTJ2.

17. The method according to claim 16, wherein the HRCD range of the MTJ1 is 80 to 100 nm.

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