Photoelectric conversion device and imaging system

Abstract

To provide a photoelectric conversion device that can prevent a reduction in image quality when reading a plurality of pieces of pixel data from a plurality of signal lines in the same pixel column.SOLUTION: A photoelectric conversion device has: a pixel unit that has a plurality of pixels; a plurality of signal lines at least two of which are arranged in each column of the pixels and each of which is connected with the pixel in the corresponding column; a pixel control unit that controls reading of signals from the plurality of pixels row by row; a column circuit unit that performs AD conversion on the signals read into the plurality of signal lines to generate pixel data; and a signal processing unit that performs signal processing on the pixel data output from the column circuit unit. The plurality of signal lines include first and second signal lines arranged in the same column, and a period in which reading of signals into the first signal line is performed and a period in which reading of signals into the second signal line is performed overlap each other. The signal processing unit has a difference acquisition unit that acquires a differential value between the pieces of pixel data read into the first and second signal lines, and a correction unit that corrects the pixel data based on the differential value.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device and an imaging system.

Background Art

[0002] In a CMOS image sensor which is an XY address type imaging element, an imaging device is known which is configured such that a plurality of vertical signal lines are arranged in the same pixel column, and pixel data is read from a plurality of pixels in the same pixel column at the same time via these plurality of vertical signal lines. In an imaging device having a plurality of vertical signal lines in the same pixel column, by performing two or more different vertical scans at the same time, images with different purposes can be captured in parallel. Patent Document 1 discloses a technique for reading pixel signals for a live view image with a vertical signal line different from the vertical signal line for reading pixel signals for a still image during still image shooting.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, when reading a plurality of pixel data from a plurality of signal lines in the same pixel column as described in Patent Document 1, the image quality may deteriorate. An object of the present invention is to provide a photoelectric conversion device and an imaging system capable of suppressing deterioration of image quality when reading a plurality of pixel data from a plurality of signal lines in the same pixel column.

Means for Solving the Problems

[0005] According to one disclosure of this specification, the device comprises: a pixel unit having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each including a photoelectric conversion unit; a plurality of signal lines, at least two of which are arranged in each of the plurality of columns, each connected to the pixels of the corresponding column; a pixel control unit that controls the reading of signals from the plurality of pixels to the plurality of signal lines on a row-by-row basis; a column circuit unit that performs AD conversion on analog signals read from the pixel unit to each of the plurality of signal lines to generate pixel data which is a digital signal; and a signal processing unit that performs digital signal processing on the pixel data output from the column circuit unit, wherein the plurality of signal lines include a first signal line and a second signal line arranged in the same column, and the period during which reading is performed from the pixels of one row to the first signal line overlaps with the period during which reading is performed from the pixels of another row to the second signal line, and the signal processing unit comprises: a difference acquisition unit that acquires the difference value between the pixel data read to the first signal line and the pixel data read to the second signal line; and a correction unit that performs correction processing on the pixel data based on the difference value. Furthermore, the pixel data read out on the first signal line and the pixel data read out on the second signal line are pixel data based on incident light. A photoelectric converter is provided.

[0006] Furthermore, according to another disclosure of this specification, a signal processing device for processing signals output from a photoelectric converter, comprising: a pixel unit having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each including a photoelectric converter; a plurality of signal lines, at least two of which are arranged in each of the plurality of columns, each connected to the pixels of the corresponding column; a pixel control unit that controls the reading of signals from the plurality of pixels to the plurality of signal lines on a row-by-row basis; and a column circuit unit that performs AD conversion on analog signals read from the pixel unit to each of the plurality of signal lines to generate pixel data which is a digital signal, wherein the plurality of signal lines include a first signal line and a second signal line arranged in the same column, and the period during which reading is performed from the pixels of one row to the first signal line overlaps with the period during which reading is performed from the pixels of another row to the second signal line, comprising: a difference acquisition unit that acquires a difference value between the pixel data read to the first signal line and the pixel data read to the second signal line; and a correction unit that performs correction processing of the pixel data based on the difference value. 、 of The pixel data read out on the first signal line and the pixel data read out on the second signal line are pixel data based on incident light.A signal processing device is provided. [Effects of the Invention]

[0007] According to the present invention, it is possible to suppress the degradation of image quality when reading multiple pixel data from multiple signal lines of the same pixel sequence. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram showing an example configuration of a photoelectric conversion device according to the first embodiment of the present invention. [Figure 2] This is a perspective view showing an example configuration of a photoelectric conversion device according to the first embodiment of the present invention. [Figure 3] This is an equivalent circuit diagram showing an example of pixel configuration in a photoelectric conversion device according to the first embodiment of the present invention. [Figure 4] This is a schematic diagram showing the connection relationship between the vertical scanning unit and the pixel unit in a photoelectric conversion device according to the first embodiment of the present invention. [Figure 5] This is a schematic diagram showing the connection relationship between the pixel section and the column circuit section in a photoelectric conversion device according to the first embodiment of the present invention. [Figure 6A] This is a timing diagram (part 1) showing an example of operation of a photoelectric conversion device according to the first embodiment of the present invention. [Figure 6B] This is a timing diagram (part 2) showing an example of operation of a photoelectric conversion device according to the first embodiment of the present invention. [Figure 7] This is a block diagram showing an example of the configuration of the vertical signal line coupling correction unit in a photoelectric conversion device according to the first embodiment of the present invention. [Figure 8] This is a flowchart showing an example of the operation of the vertical signal line coupling correction unit in a photoelectric conversion device according to the first embodiment of the present invention. [Figure 9] This is a diagram (part 1) illustrating a method for correcting pixel data in a photoelectric conversion device according to the first embodiment of the present invention. [Figure 10] This is a diagram (part 2) illustrating a method for correcting pixel data in a photoelectric conversion device according to the first embodiment of the present invention. [Figure 11] This is a block diagram showing an example of the configuration of the vertical signal line coupling correction unit in a photoelectric conversion device according to a second embodiment of the present invention. [Figure 12] This flowchart shows an example of the operation of the vertical signal line coupling correction unit in a photoelectric conversion device according to a second embodiment of the present invention. [Figure 13] This block diagram shows a schematic configuration of an imaging system according to a third embodiment of the present invention. [Figure 14] This figure shows an example configuration of an imaging system and a mobile body according to a fourth embodiment of the present invention. [Figure 15] This is a block diagram showing the schematic configuration of a device according to the fifth embodiment of the present invention. [Modes for carrying out the invention]

[0009] [First Embodiment] A photoelectric conversion device according to a first embodiment of the present invention will be described with reference to Figures 1 to 10. Figure 1 is a block diagram showing an example configuration of the photoelectric conversion according to this embodiment. Figure 2 is a perspective view showing an example configuration of the photoelectric conversion device according to this embodiment. Figure 3 is an equivalent circuit diagram showing an example of the pixel configuration in the photoelectric conversion device according to this embodiment. Figure 4 is a schematic diagram showing the connection relationship between the vertical scanning unit and the pixel unit in the photoelectric conversion device according to this embodiment. Figure 5 is a schematic diagram showing the connection relationship between the pixel unit and the column circuit unit in the photoelectric conversion device according to this embodiment. Figures 6A and 6B are timing diagrams showing an example of the operation of the photoelectric conversion device according to this embodiment. Figure 7 is a block diagram showing an example configuration of the vertical signal line coupling correction unit in the photoelectric conversion device according to this embodiment. Figure 8 is a flowchart showing an example of the operation of the vertical signal line coupling correction unit in the photoelectric conversion device according to this embodiment. Figures 9 and 10 are diagrams illustrating a method for correcting pixel data in the photoelectric conversion device according to this embodiment.

[0010] As shown in FIG. 1, the photoelectric conversion device 100 according to the present embodiment can be composed of a pixel unit 10, a vertical scanning unit 20, a column circuit unit 30, a horizontal transfer unit 40, a signal processing unit 50, and a control unit 80. The vertical scanning unit 20 and the column circuit unit 30 are connected to the pixel unit 10. The horizontal transfer unit 40 is connected to the column circuit unit 30. The signal processing unit 50 is connected to the horizontal transfer unit 40. The control unit 80 is connected to the vertical scanning unit 20, the column circuit unit 30, the horizontal transfer unit 40, and the signal processing unit 50. A processing device 90 is connected to the control unit 80.

[0011] In the pixel unit 10, a plurality of pixels P each including a photoelectric conversion unit are two-dimensionally arranged so as to form a plurality of rows and a plurality of columns. Each of the plurality of pixels P is configured to output a pixel signal according to the amount of light incident on the photoelectric conversion unit. In FIG. 1, the pixels P arranged in an m-column × n-row matrix are represented by rectangular blocks. Some of the pixels P in FIG. 1 are marked with symbols with coordinates represented by (column number, row number) added to the pixel symbol P. In this specification, the direction in which each row extends (row direction) is defined as the horizontal direction, and the direction in which each column extends (column direction) is defined as the vertical direction. Also, the row number of the first row is the first row, and the column number of the first column is the first column.

[0012] The vertical scanning unit 20 is a control circuit (pixel control unit) that operates in response to a control signal from the control unit 80 and drives the pixels P constituting the pixel unit 10 in units of rows. The operations performed by the vertical scanning unit 20 on the plurality of pixels P constituting the pixel unit 10 include an electronic shutter scan and a read scan. The electronic shutter scan refers to an operation of starting exposure by sequentially releasing the reset state of the photoelectric conversion unit for the pixels P in some or all of the rows of the pixel unit 10 in units of rows to make the state capable of accumulating charges. The read scan refers to an operation of causing the pixels P in some or all of the rows of the pixel unit 10 to sequentially output signals according to the amount of charge accumulated in the photoelectric conversion unit in units of rows. The vertical scanning unit 20 supplies a control signal to the pixels P in units of rows via the control lines 12 arranged in each row of the pixel array. The vertical scanning unit 20 can be configured using a shift register and an address decoder.

[0013] The column circuit unit 30 is a signal processing circuit that performs predetermined processing on the signals output from the pixel unit 10. The column circuit unit 30 may include an amplification circuit, an analog-to-digital conversion (AD conversion) circuit, and a memory (not shown). The column circuit unit 30 performs amplification processing and AD conversion processing on each of the pixel signals, which are analog signals output from the pixels P in each column of the pixel unit 10 via the vertical output lines 14, and stores the pixel signals as digital data (pixel data) in the memory.

[0014] The horizontal transfer unit 40 operates in response to a control signal from the control unit 80, and is a circuit that sequentially transfers the pixel signals held in the memories of each column of the column circuit unit 30 to the signal processing unit 50 column by column. The horizontal transfer unit 40 may be configured using a shift register and an address decoder.

[0015] The signal processing unit 50 may include a digital signal processing unit (not shown), a parallel-to-serial conversion unit, and an output unit. The digital signal processing unit includes a vertical signal line coupling correction unit, which will be described later. The digital signal processing unit has a function of performing predetermined digital signal processing on the pixel signals transferred from the horizontal transfer unit 40. The specific configuration and operation of the digital signal processing unit will be described later. The parallel-to-serial conversion unit has a function of converting parallel data into serial data. The output unit is composed of an output circuit such as LVDS (Low Voltage Differential Signaling). The signal processing unit 50 digitally processes the signals output from the horizontal transfer unit 40 and outputs them as serial data to the outside of the photoelectric conversion device 100. In this embodiment, an example is shown in which the digital signal processing unit of the signal processing unit 50 is mounted on the photoelectric conversion device 100, but the digital signal processing unit of the signal processing unit 50 may be a component separate from the photoelectric conversion device 100. In this case, the signal processing unit 50 will only include the output unit.

[0016] The control unit 80 is a control circuit that receives control signals such as synchronization signals and setting signals such as operating modes from the processing unit 90, and outputs control signals to the vertical scanning unit 20, the column circuit unit 30, the horizontal transfer unit 40, and the signal processing unit 50 to control their operations and timing.

[0017] The processing unit 90 is, for example, a CPU (Central Processing Unit) and controls the overall operation of the photoelectric converter 100. The processing unit 90 outputs control signals such as synchronization signals and setting signals such as operating modes to the control unit 80. The processing unit 90 may be part of the photoelectric converter 100, or it may be located within the imaging system on which the photoelectric converter 100 is mounted, i.e., outside the photoelectric converter 100 (see Figure 1).

[0018] The photoelectric converter 100 according to this embodiment may be formed on a single substrate, or it may be configured as a stacked type photoelectric converter by stacking multiple substrates. In the latter case, for example, as shown in Figure 2, it can be configured as a stacked type photoelectric converter in which a pixel substrate 110 and a circuit board 120 are stacked and electrically connected. The pixel substrate 110 can be used to arrange the pixel section 10, which is one of the components of the photoelectric converter 100. The circuit board 120 can be used to arrange the vertical scanning section 20, the column circuit section 30, the horizontal transfer section 40, the signal processing section 50, and the control section 80, which are all components of the photoelectric converter 100.

[0019] By configuring the photoelectric converter 100 in this way, when manufacturing the photoelectric converter 100, it becomes possible to select an appropriate manufacturing process for each part, including the analog section 10 and the logic section 50. This makes it possible to independently improve the characteristics of each part of the photoelectric converter 100, and ultimately realize a photoelectric converter with improved image quality.

[0020] Figure 3 is an equivalent circuit diagram showing an example of the configuration of pixel P. Figure 3 illustrates pixel P(M,N) located in the Mth column and Nth row of pixel unit 10, but the same applies to other pixels P. Note that M is an integer from 1 to m, and N is an integer from 1 to n.

[0021] Each pixel P may be composed of, for example, a photoelectric conversion unit PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and selection transistors M4 and M5, as shown in Figure 3.

[0022] The photoelectric conversion unit PD can be composed of photoelectric conversion elements such as photodiodes and photogates. Here, we assume that the photoelectric conversion unit PD is composed of photodiodes. The photodiode constituting the photoelectric conversion unit PD has its anode connected to the ground node and its cathode connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. The connection node between the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 is a so-called floating diffusion unit FD. The drains of the reset transistor M2 and the amplifier transistor M3 are connected to the power supply voltage node (voltage VCC). The source of the amplification transistor M3 is connected to the drains of the selection transistor M4 and the selection transistor M5. The source of the selection transistor M4 is connected to the signal line Vline1(M) via the signal line sel1(N)_cM. The source of the selection transistor M5 is connected to the signal line Vline2(M) via the signal line sel2(N)_cM. Signal lines Vline1(M) and Vline2(M) are part of a group of signal lines that make up the vertical output line 14. Note that signal lines Vline1(M) and Vline2(M) may be the same signal line.

[0023] In the pixel configuration shown in Figure 3, each control line arranged in each row of the pixel unit 10 includes a transfer gate signal line, a reset signal line, and two selection signal lines. For example, the transfer gate signal line of the Nth row is connected to the gate of the transfer transistor M1 of the Nth row of pixels P, supplying the control signal PTX(N) output from the vertical scanning unit 20 to the gate of the transfer transistor M1 of these pixels P. The reset signal line of the Nth row is connected to the gate of the reset transistor M2 of the Nth row of pixels P, supplying the control signal PRES(N) output from the vertical scanning unit 20 to the gate of the reset transistor M2 of these pixels P. The first selection signal line of the Nth row is connected to the gate of the selection transistor M4 of the Nth row of pixels P, supplying the control signal PSEL1(N) output from the vertical scanning unit 20 to the gate of the selection transistor M4 of these pixels P. The second selection signal line for the Nth row is connected to the gate of the selection transistor M5 of the Nth row's pixel P, supplying the control signal PSEL2(N) output from the vertical scanning unit 20 to the gate of the selection transistor M5 of these pixels P. A common control signal is supplied from the vertical scanning unit 20 to pixels P in the same row.

[0024] When each transistor is composed of an N-channel transistor, a high-level control signal supplied from the vertical scanning unit 20 causes the corresponding transistor to conduct, and a low-level control signal supplied from the vertical scanning unit 20 causes the corresponding transistor to deconduct. Here, a high level corresponds to a logical value of "1," and a low level corresponds to a logical value of "0." Note that each transistor constituting the pixel P may be composed of an N-channel transistor, but may also be composed of a P-channel transistor.

[0025] The photoelectric conversion unit PD converts incident light into an amount of charge corresponding to the amount of light (photoelectric conversion) and stores the generated charge. When the transfer transistor M1 turns on (conducts), it transfers the charge held by the photoelectric conversion unit PD to the floating diffusion unit FD. The floating diffusion unit FD contains a capacitive component and holds the charge transferred from the photoelectric conversion unit PD in its capacitance, and the charge voltage conversion by its capacitance results in a potential corresponding to the amount of charge.

[0026] The amplification transistor M3 is configured to receive a bias current from a current source (not shown) via signal line Vline1(M) and selection transistor M4, or via signal line Vline2(M) and selection transistor M5. Furthermore, the power supply voltage (voltage VCC) is supplied to the drain of the amplification transistor M3. In other words, the amplification transistor M3 constitutes a source follower circuit with its gate as the input node. As a result, the amplification transistor M3 outputs a signal based on the potential of the floating diffusion section FD to signal line Vline1(M) via selection transistor M4, or to signal line Vline2(M) via selection transistor M5.

[0027] The reset transistor M2 resets the floating diffusion section FD to a potential corresponding to the power supply voltage (voltage VCC) when it is turned on (conducting). By turning on the transfer transistor M1 (conducting) at the same time as the reset transistor M2, the photoelectric conversion section PD can also be reset to a potential corresponding to voltage VCC. The selection transistor M4 switches the connection between the amplification transistor M3 and the signal line Vline1. The selection transistor M5 switches the connection between the amplification transistor M3 and the signal line Vline2.

[0028] Electronic shutter scanning is an operation that sequentially performs shutter operation on pixels P row by row. The shutter operation of pixels P releases the reset state of the photoelectric converter PD. The photoelectric converter PD is reset to a potential corresponding to the power supply voltage (voltage VCC) by turning on the transfer transistor M1 and the reset transistor M2. By turning off the transfer transistor M1 from this reset state, the reset state of the photoelectric converter PD is released, and exposure (charge accumulation) in the photoelectric converter PD begins.

[0029] Readout scanning is an operation that sequentially reads out pixels P row by row. In the pixel P readout operation, both N data (noise data) and S data (signal data) are read out.

[0030] N data is read out by first releasing the reset state of the floating diffusion unit FD, and then using the amplification transistor M3 to output a signal corresponding to the potential of the reset floating diffusion unit FD to the signal line Vline1(M) or signal line Vline2(M). The reset state of the floating diffusion unit FD is released by turning off the reset transistor M2. At that time, if N data is read out to the signal line Vline1(M), the selection transistor M4 is turned on, and if N data is read out to the signal line Vline2(M), the selection transistor M5 is turned on.

[0031] S data is read out by transferring the charge held by the photoelectric conversion unit PD to the floating diffusion unit FD after reading out the N data, and outputting a signal corresponding to the amount of charge transferred to the floating diffusion unit FD to signal line Vline1(M) or signal line Vline2(M). At that time, if S data is read out to signal line Vline1(M), the selection transistor M4 is turned on, and if S data is read out to signal line Vline2(M), the selection transistor M5 is turned on.

[0032] By applying correlated double sampling (SN) to the S data and N data read in this way, it is possible to obtain a pixel signal from which the reset noise of the floating diffusion unit FD has been removed.

[0033] Next, the connection relationship between the vertical scanning unit 20 and the pixel unit 10 will be explained using Figure 4. The vertical scanning unit 20 receives control signals from the control unit 80 and generates control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N). The vertical scanning unit 20 then outputs the generated control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) to the pixels P(1,N) to P(m,N) of the Nth row via the control line 12. For example, the control signals PTX(1), PRES(1), PSEL1(1), and PSEL2(1) are output to the pixels P(1,1) to P(m,1) of the first row. The control signals PTX(2), PRES(2), PSEL1(2), and PSEL2(2) are output to the pixels P(1,2) to P(m,2) of the second row. The pixels P(1,n) to P(m,n) in the nth row output the arrival signals PTX(n), PRES(n), PSEL1(n), and PSEL2(n).

[0034] The vertical scanning unit 20 controls the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) as appropriate, enabling shutter and readout operations for pixels P(1,N) to P(m,N) in the Nth row. Then, by sequentially controlling the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) for each row, shutter scanning and readout scanning can be performed.

[0035] Next, the connection relationship between the pixel section 10 and the column circuit section 30 will be explained using Figure 5. Each column of the pixel section 10 has a vertical output line 14. Each vertical output line 14 in each column contains a predetermined number (k) of signal lines cM_vlK (where K is an integer from 1 to k). Figure 5 assumes that each column's vertical output line 14 contains 6 signal lines. In this case, the vertical output line 14 of the first column contains signal lines c1_vl1, c1_vl2, c1_vl3, c1_vl4, c1_vl5, c1_vl6. The vertical output line 14 of the second column contains signal lines c2_vl1, c2_vl2, c2_vl3, c2_vl4, c2_vl5, c2_vl6. The vertical output line 14 of the mth column includes signal lines cm_vl1, cm_vl2, cm_vl3, cm_vl4, cm_vl5, and cm_vl6. Note that the aforementioned signal lines Vline1(M) and Vline2(M) are one of the signal lines cM_vl1 to cM_vlk. The signal line sel1(N)_cM connected to the selection transistor M4 of pixel P(M,N) and the signal line sel2(N)_cM connected to the selection transistor M5 are connected to one of the signal lines cM_vl1 to cM_vlk. The connection example in Figure 5 will be explained in detail below.

[0036] First, let's explain the signal line sel1(N)_cM connected to the selection transistor M4 of pixel P(M,N).

[0037] Each signal line sel1(N)_cM is connected to a predetermined signal line among signal lines cM_vl1 to cM_vl6 in a 6-row cycle. For example, signal line sel1(1)_cM is connected to signal line cM_vl1. Signal line sel1(2)_cM is connected to signal line cM_vl2. Signal line sel1(3)_cM is connected to signal line cM_vl3. Signal line sel1(4)_cM is connected to signal line cM_vl4. Signal line sel1(5)_cM is connected to signal line cM_vl5. Signal line sel1(6)_cM is connected to signal line cM_vl6. Similarly, subsequent signal lines sel1(7)_cM to sel1(n)_cM are connected to a predetermined signal line among signal lines cM_vl1 to cM_vl6 in a 6-row cycle. For example, signal line sel1(7)_cM is connected to signal line cM_vl1. Signal line sel1(12)_cM is connected to signal line cM_vl6. Signal line sel1(n)_cM is connected to signal line cM_vl6.

[0038] Note that here, the signal lines sel1(N)_cM are connected in the order of the rows: cM_vl1, cM_Vl2, cM_vl3, cM_vl4, cM_vl5, cM_vl6, cM_vl1, ... However, the order of connection is not necessarily required. It is sufficient that six consecutive rows of signal lines sel1(N)_cM are connected to different signal lines among cM_vl1 to cM_vl6.

[0039] Next, we will explain the signal line sel2(N)_cM connected to the selection transistor M5 of pixel P(M,N). The signal line sel2(N)_cM will be explained separately as the signal line connected to signal lines cM_vl1 to cM_vl4 and the signal line connected to signal lines cM_vl5 and cM_vl6.

[0040] First, let's explain the signal lines connected to signal lines cM_vl1 to cM_vl4 among the signal lines sel2(N)_cM. Of the signal lines sel2(N)_cM, signal line sel2(12i+1)_cM is connected to signal line cM_vl1. Signal line sel2(12i+4)_cM is connected to signal line cM_vl2. Signal line sel2(12i+7)_cM is connected to signal line cM_vl3. Signal line sel2(12i+10)_cM is connected to signal line cM_vl4. Here, i is an integer from 0 to (n / 12-1). For example, signal line sel2(1)_cM is connected to signal line cM_vl1. Signal line sel2(4)_cM is connected to signal line cM_vl2. The signal line sel2(7)_cM is connected to the signal line cM_vl3. The signal line sel2(10)_cM is connected to the signal line cM_vl4. Similarly, subsequent signal lines sel1(13)_cM to sel1(n-2)_cM are connected to a predetermined signal line among the signal lines cM_vl1 to cM_vl4 in a 12-row cycle.

[0041] Here, the signal lines sel2(N)_cM are connected to predetermined signal lines among signal lines cM_vl1~cM_vl4 at intervals of two rows. However, the signal lines sel2(N)_cM connected to signal lines cM_vl1~cM_vl4 do not necessarily have to be at intervals of two rows. The signal lines sel2(N)_cM may also be connected to predetermined signal lines among signal lines cM_vl1~cM_vl4 at intervals of S rows (S is an integer of 2 or more). Furthermore, the order in which the signal lines sel2(N)_cM are connected to signal lines cM_vl1, cM_vl2, cM_vl3, and cM_vl4 does not necessarily have to be in row order. It is sufficient to have one signal line sel2(N)_cM connected to each of signal lines cM_vl1~cM_vl4 within a continuous S×4 rows of signal lines sel2(N)_cM.

[0042] Next, we will explain the signal lines connected to signal lines cM_vl5 and cM_vl6 among the signal lines sel2(N)_cM. Among the signal lines sel2(N)_cM, signal line sel2(6j+2)_cM is connected to signal line cM_vl5. Signal line sel2(6j+5)_cM is connected to signal line cM_vl6. Here, j is an integer from 0 to (n / 6-1). For example, signal line sel2(2)_cM is connected to signal line cM_vl5. Signal line sel2(5)_cM is connected to signal line cM_vl6. Similarly, the subsequent signal lines sel1(8)_cM to sel1(n-1)_cM are connected to a predetermined signal line among signal lines cM_vl5 and cM_vl6 in a 6-row cycle.

[0043] Here, the signal lines sel2(N)_cM are connected to a predetermined signal line among signal lines cM_vl5 and cM_vl6 at intervals of two rows. However, the signal lines sel2(N)_cM connected to signal lines cM_vl5 and cM_vl6 do not necessarily have to be at intervals of two rows. The signal lines sel2(N)_cM may also be connected to a predetermined signal line among signal lines cM_vl5 and cM_vl6 at intervals of S rows (S is an integer of 2 or more). Furthermore, the order in which the signal lines sel2(N)_cM are connected to signal lines cM_vl5 and cM_vl6 does not necessarily have to be in row order. It is sufficient to have one signal line sel2(N)_cM connected to each of signal lines cM_vl5 and cM_vl6 within a continuous S × 2 rows of signal lines sel2(N)_cM.

[0044] For the signal lines sel2(N)_cM of pixels P in rows other than those mentioned above, they can be connected to any of the signal lines cM_vlK.

[0045] For example, connect signal line sel2(6j+3) to signal line cM_vl6 and signal line sel2(6n+6) to signal line cM_vl5. Here, j is an integer between 0 and (n / 6-1). With this connection, the pixel signal of pixel P in the (6j+2)th row and the pixel signal of pixel P in the (6n+6)th row can be added together using analog methods on signal line cM_vl5. Also, the pixel signal of pixel P in the (6n+3)th row and the pixel signal of pixel P in the (6n+5)th row can be added together using analog methods on signal line cM_vl6.

[0046] Alternatively, signal line sel2(12i+3) can be connected to signal line cM_vl1, and signal line sel2(12i+6) can be connected to signal line cM_vl2. Also, signal line sel2(12i+9) can be connected to signal line cM_vl3, and signal line sel2(12i+12) can be connected to signal line cM_vl4. Here, i is an integer from 0 to (n / 12-1). With this connection, analog summation of pixel signals can be performed on signal lines cM_vl1 to cM_vl4. Specifically, the pixel signal of pixel P in the (12i+1)th row and the pixel signal of pixel P in the (12i+3)th row can be added together on signal line cM_vl1. Also, the pixel signal of pixel P in the (12i+4)th row and the pixel signal of pixel P in the (12i+6)th row can be added together on signal line cM_vl2. Furthermore, the pixel signal of pixel P in the (12i+7)th row and the pixel signal of pixel P in the (12i+9)th row can be added together using analog methods on signal line cM_vl3. Also, the pixel signal of pixel P in the (12i+10)th row and the pixel signal of pixel P in the (12i+12th) row can be added together using analog methods on signal line cM_vl4.

[0047] Furthermore, by connecting them in this way, the number of selection transistors M4 and M5 connected to each of the six signal lines cM_vlK arranged in each column becomes the same, and the parasitic capacitance (transistor capacitance) connected to the signal lines cM_vlK can be made uniform.

[0048] Next, an example of the operation of the photoelectric converter according to this embodiment will be described using Figures 6A and 6B. Figures 6A and 6B are timing diagrams showing an example of the operation of the photoelectric converter according to this embodiment. Figures 6A and 6B are two diagrams obtained by dividing one timing diagram into two parts by a dashed line. Figure 6B shows the operation at a time later than the time shown in Figure 6A.

[0049] In this example, image data from the 1st row to the (3p+1)th row is acquired during the first vertical scan, while image data from the 2nd row to the (3q+2)th row is acquired during the second vertical scan. Here, p and q are integers greater than or equal to 1. The image obtained from the first vertical scan can be used, for example, as an image captured for live view. The image obtained from the second vertical scan can be used, for example, as an image for flicker detection.

[0050] When acquiring image data by readout scanning, only the selection transistor M5 for pixel P is used, and the pixel signal is read out from the six signal lines cM_vl1 to cM_vl6 arranged in each column. In the readout operation of the first vertical scan, four of the six signal lines cM_vl1 to cM_vl6 arranged in each column (signal lines cM_vl1 to cM_vl4) are used. In the readout operation of the second vertical scan, two of the six signal lines cM_vl1 to cM_vl6 arranged in each column (signal lines cM_vl5 and cM_vl6) are used.

[0051] Here, in the first frame, a first vertical scan including one shutter scan and one readout scan, and a second vertical scan including three shutter scans and two readout scans are performed. In the second frame, a first vertical scan including one shutter scan and one readout scan, and a second vertical scan including one shutter scan and two readout scans are performed. In the third frame, a first vertical scan including one shutter scan and one readout scan is performed. In Figures 6A and 6B, the period defined by the interval of the vertical synchronization signal VD is one frame period. The period from time T1 to time T2 is the first frame, the period from time T2 to time T3 is the second frame, and the period from time T3 to time T4 is the third frame.

[0052] First, the readout operation of the first vertical scan begins at time T1, which is the start time of the first frame. The period from time T1 to time T1m1, after one horizontal period defined by the interval of the horizontal synchronization signal HD has elapsed, is the period for reading out pixel signals from pixels P of the first, fourth, seventh, and tenth rows. The vertical scanning unit 20 controls the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) to read out pixel signals from pixels P of the first, fourth, seventh, and tenth rows, corresponding to the amount of charge accumulated in the photoelectric conversion unit PD during the period up to time T1. At this time, the pixel signals of pixels P of each row are output to the signal line cM_vlK via the selection transistor M5 and the signal line sel2(N)_cM. In other words, the pixel signal of pixel P in the first row is read from signal line cM_vl1, the pixel signal of pixel P in the fourth row is read from signal line cM_vl2, the pixel signal of pixel P in the seventh row is read from signal line cM_vl3, and the pixel signal of pixel P in the tenth row is read from signal line cM_vl4.

[0053] The period from time T1m1 to time T1m2, after one horizontal period has elapsed, is the period during which pixel signals are read from pixels P in the 13th, 16th, 19th, and 22nd rows. The vertical scanning unit 20 controls the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) to read out pixel signals from pixels P in the 13th, 16th, 19th, and 22nd rows, corresponding to the amount of charge accumulated in the photoelectric conversion unit PD during the period up to time T1m1. At this time, the pixel signals of pixels P in each row are output to the signal line cM_vlK via the selection transistor M5 and the signal line sel2(N)_cM. That is, the pixel signal of pixel P in the 13th row is read out from the signal line cM_vl1, and the pixel signal of pixel P in the 16th row is read out from the signal line cM_vl2. Additionally, the pixel signal of pixel P in row 19 is read from signal line cM_vl3, and the pixel signal of pixel P in row 22 is read from signal line cM_vl4.

[0054] From time T1m2 onward, similar to the period from time T1 to time T1m1 and the period from time T1m1 to time T1m2, sequential read operations are performed in synchronization with the horizontal synchronization signal HD, starting from row 25 to row (3p+1), with a period of one row every three rows (across two rows), for a total of four rows at a time. This series of read operations performed on pixels P from row 1 to row (3p+1) constitutes the read scan by the first vertical scan of the first frame.

[0055] From the following time T1ms1, the shutter operation corresponding to the readout operation of the first vertical scan of the second frame is started. The period from time T1ms1 to time T1ms2, after one horizontal period has elapsed, is the period for shutter operation of pixels P in the first, fourth, seventh, and tenth rows. The vertical scanning unit 20 controls the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) to release the reset of the photoelectric converter PD in pixels P in the first, fourth, seventh, and tenth rows.

[0056] From time T1ms2 onward, similar to the period from time T1ms1 to time T1ms2, the shutter operation is performed sequentially from the 13th row to the (3p+1)th row, in synchronization with the horizontal synchronization signal HD, with a period of one row every three rows (a two-row interval), for a total of four rows. This series of shutter operations performed on pixels P from the 1st row to the (3p+1)th row constitutes the shutter scan by the first vertical scan of the first frame.

[0057] At the following time T1bs1, the first shutter operation of the second vertical scan begins. The period from time T1bs1 to time T1bs2, after one horizontal period has elapsed, is the period during which the shutter operation of pixels P in the second and fifth rows is performed. The vertical scanning unit 20 controls the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) to release the reset of the photoelectric converter PD in pixels P in the second and fifth rows.

[0058] From time T1bs2 onward, similar to the period from time T1bs1 to time T1bs2, the shutter operation is performed sequentially from the 8th row to the (3q+2)th row, in synchronization with the horizontal synchronization signal HD, with a period of one row every three rows (a two-row interval), for a total of two rows at a time. This series of shutter operations performed on pixels P from the 2nd row to the (3q+2)th row constitutes the first shutter scan by the second vertical scan of the first frame.

[0059] At the following time T1b1, the first readout operation of the second vertical scan begins. The period from time T1b1 to time T1b2, after one horizontal period has elapsed, is the period for reading out pixel signals from the pixels P of the second and fifth rows. The vertical scanning unit 20 controls the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) to read out pixel signals from the pixels P of the second and fifth rows, corresponding to the amount of charge accumulated in the photoelectric conversion unit PD during the period up to time T1b1. At this time, the pixel signals of the pixels P of each row are output to the signal line cM_vlK via the selection transistor M5 and the signal line sel2(N)_cM. That is, the pixel signals of the pixels P of the second row are read out from the signal line cM_vl5, and the pixel signals of the pixels P of the fifth row are read out from the signal line cM_vl6.

[0060] The period from time T1b2 to time T1b3, after one horizontal period has elapsed, is the period during which pixel signals are read from the pixels P of the 8th and 11th rows. The vertical scanning unit 20 controls the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) to read out pixel signals from the pixels P of the 8th and 11th rows, corresponding to the amount of charge accumulated in the photoelectric conversion unit PD during the period up to time T1b2. At this time, the pixel signals of the pixels P of each row are output to the signal line cM_vlK via the selection transistor M5 and the signal line sel2(N)_cM. That is, the pixel signals of the pixels P of the 8th row are read out from the signal line cM_vl5, and the pixel signals of the pixels P of the 11th row are read out from the signal line cM_vl6.

[0061] From time T1b3 onward, similar to the period from time T1b1 to time T1b2 and the period from time T1b2 to time T1b3, sequential read operations are performed in synchronization with the horizontal synchronization signal HD, from the 14th row to the (3q+2)th row, with a period of one row every three rows (a two-row interval), for a total of two rows at a time. This series of read operations performed on pixels P from the 2nd row to the (3q+2)th row constitutes the first read scan by the second vertical scan of the first frame.

[0062] Furthermore, from time T1b3, the second shutter operation of the second vertical scan is started in parallel with the first readout operation of the second vertical scan. The period from time T1b3 until one horizontal period has elapsed is the period during which the shutter operation of pixels P in the second and fifth rows is performed. The vertical scanning unit 20 controls the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) to release the reset of the photoelectric converter PD in pixels P in the second and fifth rows.

[0063] From this point onward, similar to the period from time T1b3, the shutter operation is performed sequentially from the 8th row to the (3q+2)th row, in synchronization with the horizontal synchronization signal HD, with a period of one row every three rows (a two-row interval), for a total of two rows at a time. This series of shutter operations performed on pixels P from the 2nd row to the (3q+2)th row constitutes the second shutter scan of the second vertical scan of the first frame.

[0064] At the following time T1b4, the second readout operation of the second vertical scan begins. The period from time T1b4 until one horizontal period has elapsed is the period during which pixel signals are read out from the pixels P of the second and fifth rows. The vertical scanning unit 20 controls the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) to read out pixel signals from the pixels P of the second and fifth rows, corresponding to the amount of charge accumulated in the photoelectric conversion unit PD during the period up to time T1b4. At this time, the pixel signals of the pixels P of each row are output to the signal line cM_vlK via the selection transistor M5 and the signal line sel2(N)_cM. That is, the pixel signals of the pixels P of the second row are read out from the signal line cM_vl5, and the pixel signals of the pixels P of the fifth row are read out from the signal line cM_vl6.

[0065] From this point onward, similar to the period from time T1b4, the read operation is performed sequentially from the 8th row to the (3q+2)th row, in synchronization with the horizontal synchronization signal HD, with a period of one row every three rows (a two-row interval), for a total of two rows at a time. This series of read operations performed on pixels P from the 2nd row to the (3q+2)th row constitutes the second read scan by the second vertical scan of the first frame.

[0066] From the following time T1b5, the third shutter operation of the second vertical scan begins in parallel with the second readout operation of the second vertical scan. The period from time T1b5 until the end of one horizontal period is the period for shutter operation of pixels P in the second and fifth rows. The vertical scanning unit 20 controls the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) to release the reset of the photoelectric converter PD in pixels P in the second and fifth rows.

[0067] From this point onward, similar to the period from time T1b5, the shutter operation is performed sequentially from the 8th row to the (3q+2)th row, in synchronization with the horizontal synchronization signal HD, with a period of one row every three rows (a two-row interval), for a total of two rows at a time. This series of shutter operations performed on pixels P from the 2nd row to the (3q+2)th row constitutes the second shutter scan of the second vertical scan of the first frame.

[0068] Next, the readout operation of the first vertical scan begins at time T2, which is the start time of the second frame. The period from time T2 to time T2b1, after one horizontal period has elapsed, is the period for reading out pixel signals from pixels P of the first, fourth, seventh, and tenth rows. The vertical scanning unit 20 controls the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) to read out pixel signals from pixels P of the first, fourth, seventh, and tenth rows, corresponding to the amount of charge accumulated in the photoelectric conversion unit PD during the period up to time T2. At this time, the pixel signals of pixels P in each row are output to the signal line cM_vlK via the selection transistor M5 and the signal line sel2(N)_cM. In other words, the pixel signal of pixel P in the first row is read from signal line cM_vl1, the pixel signal of pixel P in the fourth row is read from signal line cM_vl2, the pixel signal of pixel P in the seventh row is read from signal line cM_vl3, and the pixel signal of pixel P in the tenth row is read from signal line cM_vl4.

[0069] The period from time T2b1 to time T2b2, after one horizontal period has elapsed, is the period during which pixel signals are read from pixels P in the 13th, 16th, 19th, and 22nd rows. The vertical scanning unit 20 controls the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) to read out pixel signals from pixels P in the 13th, 16th, 19th, and 22nd rows, corresponding to the amount of charge accumulated in the photoelectric conversion unit PD during the period up to time T2b1. At this time, the pixel signals of pixels P in each row are output to the signal line cM_vlK via the selection transistor M5 and the signal line sel2(N)_cM. That is, the pixel signal of pixel P in the 13th row is read out from the signal line cM_vl1, and the pixel signal of pixel P in the 16th row is read out from the signal line cM_vl2. Additionally, the pixel signal of pixel P in row 19 is read from signal line cM_vl3, and the pixel signal of pixel P in row 22 is read from signal line cM_vl4.

[0070] Similarly, the period from time T2b1 to time T2b2, after one horizontal period has elapsed, is also the period during which pixel signals are read from the pixels P of the second and fifth rows. The vertical scanning unit 20 controls the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) to read out pixel signals from the pixels P of the second and fifth rows, corresponding to the amount of charge accumulated in the photoelectric conversion unit PD during the period up to time T2b1. At this time, the pixel signals of the pixels P of each row are output to the signal line cM_vlK via the selection transistor M5 and the signal line sel2(N)_cM. That is, the pixel signals of the pixels P of the second row are read out from the signal line cM_vl5, and the pixel signals of the pixels P of the eighth row are read out from the signal line cM_vl6.

[0071] From time T2b2 onward, similar to the period from time T2 to time T2b1 and from time T2b1 to time T2b2, sequential read operations are performed in synchronization with the horizontal sync signal HD, from row 25 to row (3p+1), with a period of one row every three rows (a 2-row interval), for a total of four rows. This series of read operations performed on pixels P from row 1 to row (3p+1) constitutes the read scan by the first vertical scan of the second frame. Also, similar to the period from time T2b1 to time T2b2, sequential read operations are performed in synchronization with the horizontal sync signal HD, from row 8 to row (3q+2), with a period of one row every three rows (a 2-row interval), for a total of two rows. This series of read operations performed on pixels P from row 2 to row (3q+2) constitutes the first read scan by the second vertical scan of the second frame.

[0072] From the following time T2b3, the first shutter operation of the second vertical scan is started in parallel with the first readout operation of the second vertical scan. The period from time T2b3 until the end of one horizontal period is the period for shutter operation of the pixels P of the second and fifth rows. The vertical scanning unit 20 controls the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) to release the reset of the photoelectric converter PD in the pixels P of the second and fifth rows.

[0073] From this point onward, similar to the period from time T2b3, the shutter operation is performed sequentially from the 8th row to the (3q+2)th row, in synchronization with the horizontal synchronization signal HD, with a period of one row every three rows (a two-row interval), for a total of two rows at a time. This series of shutter operations performed on pixels P from the 2nd row to the (3q+2)th row constitutes the first shutter scan by the second vertical scan of the second frame.

[0074] At the following time T2b4, the second readout operation of the second vertical scan begins. The period from time T2b4 until the end of one horizontal period is the period for reading out pixel signals from the pixels P of the second and fifth rows. The vertical scanning unit 20 controls the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) to read out pixel signals from the pixels P of the second and fifth rows, corresponding to the amount of charge accumulated in the photoelectric conversion unit PD during the period up to time T2b4. At this time, the pixel signals of the pixels P of each row are output to the signal line cM_vlK via the selection transistor M5 and the signal line sel2(N)_cM. That is, the pixel signals of the pixels P of the second row are read out from the signal line cM_vl5, and the pixel signals of the pixels P of the fifth row are read out from the signal line cM_vl6.

[0075] From this point onward, similar to the period from time T2b4, the read operation is performed sequentially from the 8th row to the (3q+2)th row, in synchronization with the horizontal synchronization signal HD, with a period of one row every three rows (a two-row interval), for a total of two rows at a time. This series of read operations performed on pixels P from the 2nd row to the (3q+2)th row constitutes the second read scan by the second vertical scan of the second frame.

[0076] From the following time T2b5, the shutter operation of the first vertical scan begins. The period from time T2b5 until the end of one horizontal period is the period during which the shutter operation of pixels P in the first, fourth, seventh, and tenth rows is performed. The vertical scanning unit 20 controls the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) to release the reset of the photoelectric converter PD in pixels P in the first, fourth, seventh, and tenth rows.

[0077] From this point onward, similar to the period from time T2b5, the shutter operation is performed sequentially in synchronization with the horizontal synchronization signal HD, from the 13th row to the (3p+1)th row, with a period of one row every three rows (a two-row interval), for a total of four rows. This series of shutter operations performed on pixels P from the 1st row to the (3p+1)th row constitutes the shutter scan by the first vertical scan of the second frame.

[0078] Next, the readout operation of the first vertical scan begins at time T3, which is the start time of the third frame. The period from time T3 until one horizontal period has elapsed is the period for reading out pixel signals from pixels P of the first, fourth, seventh, and tenth rows. The vertical scanning unit 20 controls the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) to read out pixel signals from pixels P of the first, fourth, seventh, and tenth rows, corresponding to the amount of charge accumulated in the photoelectric conversion unit PD during the period up to time T3. At this time, the pixel signals of pixels P of each row are output to the signal line cM_vlK via the selection transistor M5 and the signal line sel2(N)_cM. In other words, the pixel signal of pixel P in the first row is read from signal line cM_vl1, the pixel signal of pixel P in the fourth row is read from signal line cM_vl2, the pixel signal of pixel P in the seventh row is read from signal line cM_vl3, and the pixel signal of pixel P in the tenth row is read from signal line cM_vl4.

[0079] From this point onward, similar to the period from time T3, the readout operation is performed sequentially from the 13th row to the (3p+1)th row, in synchronization with the horizontal synchronization signal HD, with a period of one row every three rows (a two-row interval), for a total of four rows at a time. This series of readout operations performed on pixels P from the 1st row to the (3p+1)th row constitutes the readout scan by the first vertical scan of the third frame.

[0080] From the following time T3b1, the shutter operation corresponding to the readout operation of the first vertical scan of the third frame is initiated. The period from time T3b1 until the end of one horizontal period is the period for shutter operation of pixels P in the first, fourth, seventh, and tenth rows. The vertical scanning unit 20 controls the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) to release the reset of the photoelectric converter PD in pixels P in the first, fourth, seventh, and tenth rows.

[0081] From this point onward, similar to the period from time T3b1, the shutter operation is performed sequentially in synchronization with the horizontal synchronization signal HD, from the 13th row to the (3p+1)th row, with a period of one row every three rows (an interval of two rows), for a total of four rows. This series of shutter operations performed on pixels P from the 1st row to the (3p+1)th row constitutes the shutter scan by the first vertical scan of the third frame.

[0082] Next, the readout operation of the first vertical scan begins at T4, which is the start time of the fourth frame. The period from time T4 until one horizontal period has elapsed is the period for reading out pixel signals from pixels P of the first, fourth, seventh, and tenth rows. The vertical scanning unit 20 controls the control signals PTX(N), PRES(N), PSEL1(N), and PSEL2(N) to read out pixel signals from pixels P of the first, fourth, seventh, and tenth rows, corresponding to the amount of charge accumulated in the photoelectric conversion unit PD during the period up to time T4. At this time, the pixel signals of pixels P of each row are output to the signal line cM_vlK via the selection transistor M5 and the signal line sel2(N)_cM. In other words, the pixel signal of pixel P in the first row is read from signal line cM_vl1, the pixel signal of pixel P in the fourth row is read from signal line cM_vl2, the pixel signal of pixel P in the seventh row is read from signal line cM_vl3, and the pixel signal of pixel P in the tenth row is read from signal line cM_vl4.

[0083] From this point onward, similar to the period from time T4, the read operation is performed sequentially from the 13th row to the (3p+1)th row, in synchronization with the horizontal synchronization signal HD, with a cycle of one row every three rows (a two-row interval), for a total of four rows at a time. This series of read operations performed on pixels P from the 1st row to the (3p+1)th row constitutes the read scan by the first vertical scan of the 4th frame.

[0084] When two different vertical scans are performed simultaneously, one vertical scan may read pixels located in a different signal line cM_vlK at the same time as the other vertical scan, which is scanning pixels located in a column-wise distant position from the pixels being read by the other vertical scan. For example, in the above example, the read operations of the first vertical scan and the second vertical scan overlap during the period from time T2 to time T3, so it is possible that the pixel signals of pixels P located in distant rows are read during the same period. In such a case, if a strong light source or the like is present in the pixel area being read by one vertical scan, causing the signal level of the signal line to become strong, capacitive coupling between signal lines may affect the read pixel data of the other vertical scan, potentially degrading image quality. In other words, a large difference in signal levels may occur between signal lines cM_vl1~cM_vl4 and signal lines cM_vl5,cM_vl6.

[0085] In a photoelectric converter that performs only a single vertical scan, pixels read out simultaneously are located close together and have similar brightness levels. However, when multiple vertical scans are performed simultaneously, the pixel positions to be read out become further apart, and a large difference in brightness between pixels can occur. Furthermore, if the number of signal lines arranged in the same pixel row is increased to speed up the readout of pixel data, the effect of capacitive coupling between signal lines becomes more pronounced due to the narrow pitch arrangement of the signal lines.

[0086] In this embodiment, the start times for the first vertical scan are T1, T2, and T3, and the start times for the second vertical scan are T1b1, T1b4, T2b1, and T2b4. However, each vertical scan can be started at any time. In this case, the row positions of the pixels P read by each vertical scan during the overlapping read operations may differ depending on the start time of each vertical scan.

[0087] Next, the vertical signal line coupling correction unit of the signal processing unit 50 will be explained with reference to Figure 7. As mentioned above, the signal processing unit 50 has a vertical signal line coupling correction unit 52 as at least part of the digital signal processing unit. As shown in Figure 7, the vertical signal line coupling correction unit 52 includes a pixel data acquisition unit 54, a difference acquisition unit 56, a comparison unit 58, a threshold setting unit 60, a correction unit 62, and a correction value setting unit 64.

[0088] The vertical signal line coupling correction unit 52 has k pixel data acquisition units 54, (k-1) difference acquisition units 56, (k-1) comparison units 58, and k correction units 62, corresponding to the number (k) signal lines cM_vlK included in the vertical output lines 14 of each row. The k pixel data acquisition units 54 and k correction units 62 are provided corresponding to each of the k signal lines cM_vlK. The (k-1) difference acquisition units 56 and (k-1) comparison units 58 are provided corresponding to each pair of adjacent signal lines cM_vlK.

[0089] Each of the pixel data acquisition units 54 is configured to receive pixel data output from the corresponding signal line cM_vlK. Each of the difference acquisition units 56 is connected to two pixel data acquisition units 54 that receive pixel data from two corresponding signal lines cM_vlK. Each of the comparison units 58 is connected to a difference acquisition unit 56 corresponding to the same two signal lines cM_vlK and to a threshold setting unit 60. Each of the correction units 62 is connected to a pixel data acquisition unit 54 that receives pixel data from the corresponding signal line cM_vlK, and to a difference acquisition unit 56 and a comparison unit 58 corresponding to the corresponding signal line cM_vlK. Each of the correction units 62 is also connected to a correction value setting unit 64.

[0090] The vertical signal line coupling correction unit 52 acquires and processes pixel data read from k (6 in this embodiment) signal lines cM_vlK arranged in the same pixel column in parallel from the memory of the column circuit unit 30 via the horizontal transfer unit 40.

[0091] The pixel data acquisition unit 54 acquires digitized pixel data from the memory of the column circuit unit 30 via the horizontal transfer unit 40.

[0092] The difference acquisition unit 56 calculates the difference value of the pixel data acquired by the two pixel data acquisition units 54 corresponding to adjacent signal lines cM_vlK and cM_vl(K+1), and outputs the calculated difference value.

[0093] The comparison unit 58 compares the difference value calculated by the difference acquisition unit 56 with a threshold value pre-set in the threshold setting unit 60, and outputs the comparison result to the correction unit 62.

[0094] The correction unit 62 determines whether or not to correct the pixel data based on the comparison result from the comparison unit 58. If the correction unit 62 determines that it should correct the pixel data, it outputs the difference value calculated by the difference acquisition unit 56 to the correction value setting unit 64. Furthermore, the correction unit 62 corrects the pixel data based on the correction value obtained from the correction value setting unit 64 and outputs the corrected image data from the vertical signal line coupling correction unit 52 to the subsequent circuit.

[0095] The correction value setting unit 64 calculates a correction value based on the pre-set information and the input difference value, and outputs the calculated correction value to the correction unit 62.

[0096] The threshold setting unit 60 and the correction value setting unit 64 may be configured using volatile storage media such as flip-flops or SRAM, and their values ​​may be updated after power-on. Alternatively, the threshold setting unit 60 and the correction value setting unit 64 may be configured using non-volatile storage media such as ROM, and fixed values ​​may be stored in advance.

[0097] Next, the specific processing procedure in the vertical signal line coupling correction unit 52 will be explained using Figure 8.

[0098] First, the pixel data acquisition unit 54 acquires k pixel data held in the memory of the Mth column of the column circuit unit 30 (step S101). Here, the pixel data output via the signal line cM_vlK is called pixel data K, and the pixel data output via the signal line cM_vl(K+1) is called pixel data K+1. Here, K is an integer from 1 to (k-1).

[0099] Next, the difference acquisition unit 56 acquires the difference value of pixel data K and K+1 output via adjacent signal lines cM_vlK and cM_vl(K+1) (step S102).

[0100] Next, the comparison unit 58 compares the difference value acquired by the difference acquisition unit 56 with the threshold value pre-set in the threshold setting unit 60 to determine whether the difference value exceeds the threshold (step S103). If the result of the determination is that the difference value does not exceed the threshold (No), the pixel data is not corrected and the process ends. If the result of the determination is that the difference value exceeds the threshold (Yes), the process proceeds to step S104.

[0101] Next, the comparison unit 58 compares the signal level of pixel data K with the signal level of pixel data K+1 to determine whether the signal level of pixel data K is lower than the signal level of pixel data K+1 (step S104). If the result of the determination is that the signal level of pixel data K is lower than the signal level of pixel data K+1 (Yes), the process proceeds to step S105; if the signal level of pixel data K is equal to or greater than the signal level of pixel data K+1 (No), the process proceeds to step S107.

[0102] In step S105, the correction value setting unit 64 calculates a correction value for the pixel data K. Then, in step S106, the correction of the pixel data K is performed according to the calculated correction value.

[0103] In step S107, the correction value setting unit 64 calculates a correction value for the pixel data K+1. Then, in step S108, the correction of the pixel data K+1 is performed according to the calculated correction value.

[0104] In the vertical signal line coupling correction unit 52, the processes of steps S102 to S108 in the above flow are executed in parallel for k pixel data read from k signal lines cM_vlK arranged in the same pixel row.

[0105] The calculation of the correction value in the correction value setting unit 64 is not particularly limited, but can be performed by, for example, the following method.

[0106] One method involves storing the coefficients of a linear function representing the relationship between the effect of coupling between signal lines cM_vlK and the difference value between pixel data in the correction value setting unit 64 as parameters for calculating the correction value. The correction value can be expressed as, for example, as shown in Figure 9, with the slope of the linear function being a and the intercept being b, as correction value = a × difference value + b. Therefore, by storing the coefficients a and b of the linear function representing the relationship between the effect of coupling between signal lines cM_vlK and the difference value between pixel data in the correction value setting unit 64, the correction value can be calculated based on the difference value calculated by the comparison unit 58. The correction unit 62 can correct the pixel data by subtracting the correction value obtained from the correction value setting unit 64 from the pixel data.

[0107] A second method involves storing a lookup table in the correction value setting unit 64 that represents the relationship between the effect of coupling between signal lines cM_vlK and the difference value between pixel data as parameters for calculating the correction value. The lookup table sets, for example, the effect of coupling between signal lines cM_vlK, i.e., the minimum and maximum values ​​of the difference value between pixel data with respect to the correction value, as shown in Figure 10. For example, the minimum value of the difference value for which the correction value is 1 LSB is set as min1 and the maximum value as max1, and similarly, the minimum value of the difference value for which the correction value is 2 LSB is set as min2 and the maximum value as max2. The minimum and maximum values ​​are set in the same manner up to the required correction value n. The correction value setting unit 64 refers to the difference value notified from the correction unit 62 and the lookup table, searches for a correction value that contains a difference value between the minimum and maximum values, and outputs the corresponding correction value to the correction unit 62. The correction unit 62 can correct the pixel data by subtracting the correction value obtained from the correction value setting unit 64 from the pixel data.

[0108] Thus, in this embodiment, a correction value is calculated according to the difference in signal levels between pixel data passing through vertical signal lines arranged in the same pixel column, and the pixel data is corrected. Therefore, according to this embodiment, the influence of coupling between vertical signal lines is reduced, and it becomes possible to acquire high-quality images.

[0109] [Second Embodiment] A photoelectric conversion device according to a second embodiment of the present invention will be described with reference to Figures 11 and 12. Figure 11 is a block diagram showing an example of the configuration of the vertical signal line coupling correction unit in the photoelectric conversion device according to this embodiment. Figure 12 is a flowchart showing an example of the operation of the vertical signal line coupling correction unit in the photoelectric conversion device according to this embodiment. Components similar to those in the photoelectric conversion device according to the first embodiment are denoted by the same reference numerals, and their descriptions are omitted or simplified.

[0110] The photoelectric converter according to this embodiment is the same as the photoelectric converter according to the first embodiment, except that the configuration of the vertical signal line coupling correction unit is different. As shown in Figure 11, the vertical signal line coupling correction unit 52 of this embodiment includes a pixel data acquisition unit 54, a difference acquisition unit 56, a comparison unit 58, a threshold setting unit 60, a correction unit 62, a correction value setting unit 64, a comparison value acquisition unit 66, and a comparison result storage unit 68.

[0111] The pixel data acquisition unit 54 and the comparison value acquisition unit 66 are connected to the horizontal transfer unit 40. The difference acquisition unit 56 is connected to the pixel data acquisition unit 54 and the comparison value acquisition unit 66. The comparison unit 58 is connected to the difference acquisition unit 56 and the threshold setting unit 60. The comparison result storage unit 68 is connected to the difference acquisition unit 56 and the comparison unit 58. The correction unit 62 is connected to the pixel data acquisition unit 54, the difference acquisition unit 56, the comparison unit 58, the comparison result storage unit 68, and the correction value setting unit 64.

[0112] The vertical signal line coupling correction unit 52 sequentially acquires pixel data one by one from the memory of the column circuit unit 30 via the horizontal transfer unit 40, based on the k (6 in this embodiment) signal lines cM_vlK arranged in the same pixel column, and processes them.

[0113] The pixel data acquisition unit 54 acquires digitized pixel data from the memory of the column circuit unit 30. The order in which the pixel data is acquired may be in ascending order from the pixel data of signal line cM_vl1 to the pixel data of signal line cM_vl6, or in descending order from the pixel data of signal line cM_vl6 to the pixel data of signal line cM_vl1.

[0114] The comparison value acquisition unit 66 acquires pixel data for signal lines cM_vl(K+1) or cM_vl(K-1) adjacent to signal line cM_vlK from which the pixel data acquired by the pixel data acquisition unit 54 has output. For example, if the pixel data acquisition unit 54 starts acquiring pixel data in ascending order from signal line cM_vl1, the comparison value acquisition unit 66 acquires pixel data for signal line cM_vl2. Next, when the pixel data acquisition unit 54 acquires pixel data for signal line cM_vl2, the comparison value acquisition unit 66 acquires pixel data for signal line cM_vl3. Similarly, the comparison value acquisition unit 66 sequentially acquires pixel data up to the pixel data for signal line cM_vl6.

[0115] The difference acquisition unit 56 calculates the difference between the pixel data acquired by the pixel data acquisition unit 54 and the pixel data acquired by the comparison value acquisition unit 66, and outputs the calculated difference to the comparison unit 58, the correction unit 62, and the comparison result storage unit 68.

[0116] The comparison unit 58 compares the difference value calculated by the difference acquisition unit 56 with a threshold value pre-set in the threshold setting unit 60, and outputs the comparison result to the correction unit 62. The comparison result storage unit 68 stores the difference value calculated by the difference acquisition unit 56 and the comparison result performed by the comparison unit 58.

[0117] The correction unit 62 determines whether or not to correct the pixel data based on the comparison result from the comparison unit 58 or the comparison result stored in the comparison result storage unit 68. If the correction unit 62 determines that the pixel data should be corrected, it outputs the difference value calculated by the difference acquisition unit 56 or the difference value stored in the comparison result storage unit 68 to the correction value setting unit 64. Furthermore, the correction unit 62 corrects the pixel data based on the correction value obtained from the correction value setting unit 64 and outputs the corrected image data from the vertical signal line coupling correction unit 52 to the subsequent circuit.

[0118] The correction value setting unit 64 calculates a correction value based on the pre-set information and the input difference value, and outputs the calculated correction value to the correction unit 62.

[0119] The threshold setting unit 60 and the correction value setting unit 64 may be configured using volatile storage media such as flip-flops or SRAM, and their values ​​may be updated after power-on. Alternatively, the threshold setting unit 60 and the correction value setting unit 64 may be configured using non-volatile storage media such as ROM, and fixed values ​​may be stored in advance.

[0120] Next, the specific processing procedure in the vertical signal line coupling correction unit 52 will be explained using Figure 12. Here, we assume that the pixel data acquisition unit 54 acquires pixel data in ascending order from signal line cM_vl1 to signal line cM_vl6.

[0121] First, the pixel data acquisition unit 54 acquires the pixel data corresponding to the signal line cM_vlK from among the k pixel data held in the memory of the Mth column of the column circuit unit 30. Then, the comparison value acquisition unit 66 acquires the pixel data corresponding to the signal line CM_vl(K+1) from among the k pixel data held in the memory of the Mth column of the column circuit unit 30 (step S201). Here, the pixel data output via the signal line cM_vlK is called pixel data K, and the pixel data output via the signal line cM_vl(K+1) is called pixel data K+1. Here, K is an integer from 1 to (k-1). For example, the pixel data acquired by the pixel data acquisition unit 54 is the pixel data of signal line cM_vl1, and the pixel data acquired by the comparison value acquisition unit 66 is the pixel data of signal line cM_vl2.

[0122] Next, the information stored in the comparison result storage unit 68 is referenced to determine whether or not the information corresponds to the correction conditions for the pixel data (step S202). The comparison result storage unit 68 stores the comparison result for the previous data, that is, the comparison result between the pixel data of signal line cM_vl(K-1) and the pixel data of signal line cM_vlK. Specifically, the comparison result storage unit 68 stores whether or not the difference value between pixel data K-1 and pixel data K exceeds a threshold, and whether or not pixel data K is greater than or equal to pixel data K-1. If the difference value between pixel data K-1 and pixel data K exceeds a threshold, AND pixel data K is greater than pixel data K-1, the correction condition is met. If pixel data K-1 and pixel data K do not satisfy this relationship, the correction condition is not met.

[0123] If the result of the determination in step S202 indicates that the information stored in the comparison result storage unit 68 does not meet the correction conditions (No), the process proceeds to step S205. If the information stored in the comparison result storage unit 68 does meet the correction conditions (Yes), the process proceeds to step S203. In step S203, the correction value setting unit 64 calculates a correction value for the pixel data K. Then, in step S204, the correction of the pixel data K is performed according to the calculated correction value. Note that information is written to the comparison result storage unit 68 in step S210, which will be described later, so when the initial pixel data is determined, information indicating that it does not meet the correction conditions is stored in the comparison result storage unit 68 as an initial value.

[0124] Next, the difference acquisition unit 56 acquires the difference value between the pixel data K acquired in step S201 and the pixel data K+1 (step S205).

[0125] Next, the comparison unit 58 compares the difference value acquired by the difference acquisition unit 56 with the threshold value pre-set in the threshold setting unit 60 to determine whether the difference value exceeds the threshold (step S206). If the result of the determination is that the difference value does not exceed the threshold (No), no correction is performed on the pixel data K, and the process proceeds to step S210. If the result of the determination is that the difference value exceeds the threshold (Yes), the process proceeds to step S207.

[0126] In step S207, the comparison unit 58 compares the signal level of pixel data K with the signal level of pixel data K+1 to determine whether the signal level of pixel data K is lower than the signal level of pixel data K+1. If the result of the determination is that the signal level of pixel data K is equal to or greater than the signal level of pixel data K+1 (No), the process proceeds to step S210. If the result of the determination is that the signal level of pixel data K is lower than the signal level of pixel data K+1 (Yes), the process proceeds to step S208.

[0127] In step S208, the correction value setting unit 64 calculates a correction value for the pixel data K. Then, in step S209, the correction unit 62 performs correction of the pixel data K according to the calculated correction value.

[0128] In step S210, the difference value obtained in step S205 and the comparison results obtained in steps S206 and S207 are stored in the comparison result storage unit 68.

[0129] Next, it is determined whether the processing of all pixel data output via the signal lines cM_vl1 to cM_vl6 included in the vertical output line 14 of one column has been completed (step S211). If the result of the determination is that the processing of all pixel data has been completed (Yes), the series of processes in the vertical signal line coupling correction unit 52 is terminated. If the result of the determination is that the processing of all pixel data has not been completed (No), the process returns to step S201 and proceeds to the processing of the next pixel data.

[0130] In the above driving example, the pixel data acquisition unit 54 was shown acquiring pixel data in ascending order from signal line cM_vl1 to signal line cM_vl6. However, the pixel data may also be acquired in descending order from signal line cM_vl6 to signal line cM_vl1. In this case, the processing of each step should be appropriately modified to match the processing order of the pixel data.

[0131] According to the above configuration of this embodiment, even when the signal processing unit 50 sequentially processes multiple pixel data output via multiple signal lines arranged in the same pixel row, it is possible to correct the pixel data by simultaneously acquiring comparison values ​​and calculating the difference value.

[0132] [Third Embodiment] A third embodiment of the imaging system according to the present invention will be described with reference to Figure 13. Figure 13 is a block diagram showing the schematic configuration of the imaging system according to this embodiment.

[0133] The photoelectric converter 100 described in the first and second embodiments above is applicable to various imaging systems. Examples of applicable imaging systems include digital still cameras, digital camcorders, surveillance cameras, photocopiers, fax machines, mobile phones, in-vehicle cameras, and observation satellites. Camera modules, which include optical systems such as lenses and imaging devices, are also included in imaging systems. Figure 13 shows a block diagram of a digital still camera as an example of these.

[0134] The imaging system 200 illustrated in Figure 13 includes an imaging device 201, a lens 202 for forming an optical image of a subject onto the imaging device 201, an aperture 204 for varying the amount of light passing through the lens 202, and a barrier 206 for protecting the lens 202. The lens 202 and aperture 204 are an optical system that focuses light onto the imaging device 201. The imaging device 201 is a photoelectric conversion device 100 described in the first or second embodiment, which converts the optical image formed by the lens 202 into image data.

[0135] The imaging system 200 also includes a signal processing unit 208 that processes the output signal from the imaging device 201. The signal processing unit 208 generates image data from the digital signal output by the imaging device 201. The signal processing unit 208 also performs various corrections and compressions as needed before outputting the image data. The imaging device 201 may include an AD conversion unit that generates the digital signal processed by the signal processing unit 208. The AD conversion unit may be formed on the semiconductor layer (semiconductor substrate) on which the photoelectric conversion unit of the imaging device 201 is formed, or on a semiconductor substrate separate from the semiconductor layer on which the photoelectric conversion unit of the imaging device 201 is formed. The signal processing unit 208 may also be formed on the same semiconductor substrate as the imaging device 201.

[0136] The imaging system 200 further includes a buffer memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. Furthermore, the imaging system 200 includes a recording medium 214 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading data from the recording medium 214. The recording medium 214 may be built into the imaging system 200 or it may be detachable.

[0137] Furthermore, the imaging system 200 includes an overall control and calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, the timing signals and the like may be input from an external source, and the imaging system 200 only needs to include at least an imaging device 201 and a signal processing unit 208 that processes the output signals output from the imaging device 201.

[0138] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0139] Thus, according to this embodiment, an imaging system can be realized that applies the photoelectric converter 100 according to the first or second embodiment.

[0140] [Fourth Embodiment] A fourth embodiment of the present invention, consisting of an imaging system and a mobile body, will be described with reference to Figure 14. Figure 14 is a diagram showing the configuration of the imaging system and mobile body according to this embodiment.

[0141] Figure 14(a) shows an example of an imaging system for an in-vehicle camera. The imaging system 300 includes an imaging device 310. The imaging device 310 is the photoelectric converter 100 described in the first or second embodiment above. The imaging system 300 includes an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the imaging system 300. The imaging system 300 also includes a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 318 may use any of this distance information to determine the possibility of collision. The means for acquiring distance information may be implemented by specially designed hardware, or by a software module. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0142] The imaging system 300 is connected to the vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 318. The imaging system 300 is also connected to a warning device 340 that issues a warning to the driver based on the judgment result of the collision judgment unit 318. For example, if the collision judgment result of the collision judgment unit 318 indicates a high probability of collision, the control ECU 330 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 340 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0143] In this embodiment, the imaging system 300 captures images of the area around the vehicle, for example, the front or rear. Figure 14(b) shows the imaging system when capturing images of the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the imaging system 300 or the imaging device 310. This configuration allows for further improvement of the accuracy of distance measurement.

[0144] The above example illustrates control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles or automatically prevent vehicles from straying from their lanes. Furthermore, the imaging system can be applied not only to vehicles such as the vehicle itself, but also to moving objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to moving objects but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0145] [Fifth Embodiment] A fifth embodiment of the present invention will be described with reference to Figure 15. Figure 15 is a block diagram showing the schematic configuration of the device according to this embodiment.

[0146] Figure 15 is a schematic diagram showing an instrument EQP including a photoelectric converter APR. The photoelectric converter APR has the functions of a photoelectric converter 100 of the first or second embodiment. All or part of the photoelectric converter APR is a semiconductor device IC. The photoelectric converter APR in this example can be used, for example, as an image sensor, an AF (Auto Focus) sensor, a photometering sensor, or a distance measuring sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including a photoelectric conversion unit are arranged in a matrix. The semiconductor device IC may have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0147] The photoelectric converter APR may have a stacked structure (chip stacking structure) comprising a first semiconductor chip equipped with multiple photoelectric conversion units and a second semiconductor chip equipped with peripheral circuits. The peripheral circuits on the second semiconductor chip can each be a column circuit corresponding to a pixel row of the first semiconductor chip. Alternatively, the peripheral circuits on the second semiconductor chip can each be a matrix circuit corresponding to a pixel or pixel block of the first semiconductor chip. Connections between the first and second semiconductor chips can be made using through-silicon vias (TSVs), direct bonding of conductors such as copper for inter-chip wiring, microbump connections between chips, or wire bonding.

[0148] The photoelectric converter APR may include a semiconductor device IC as well as a package PKG that houses the semiconductor device IC. The package PKG may include a substrate on which the semiconductor device IC is fixed, a cover made of glass or the like that faces the semiconductor device IC, and connecting members such as bonding wires or bumps that connect terminals provided on the substrate to terminals provided on the semiconductor device IC.

[0149] The EQP device may further comprise at least one of the following: an optical device OPT, a control unit CTRL, a processing unit PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric converter APR as a photoelectric converter, and is, for example, a lens, shutter, or mirror. The control unit CTRL controls the photoelectric converter APR and is, for example, a semiconductor device such as an ASIC. The processing unit PRCS processes the signals output from the photoelectric converter APR and constitutes an AFE (analog front end) or a DFE (digital front end). The processing unit PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application-specific integrated circuit). The display device DSPL is an EL display device or liquid crystal display device that displays information (images) obtained from the photoelectric converter APR. The memory device MMRY is a magnetic device or semiconductor device that stores information (images) obtained from the photoelectric converter APR. The memory device MMRY is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive. The mechanical device MCHN has movable parts or propulsion parts such as motors and engines. The device EQP displays signals output from the photoelectric converter APR on the display device DSPL, or transmits them to the outside using a communication device (not shown) provided by the device EQP. For this purpose, it is preferable that the device EQP further includes a memory device MMRY and a processing device PRCS, separate from the memory circuit and arithmetic circuit of the photoelectric converter APR.

[0150] The EQP (Equipment Equipped Device) shown in Figure 15 can be electronic devices such as information terminals with imaging capabilities (e.g., smartphones and wearable devices) or cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, surveillance cameras). In cameras, the mechanical device MCHN can drive components of the optical device OPT for zooming, focusing, and shutter operation. Furthermore, the EQP can be transportation equipment (mobile devices) such as vehicles, ships, and aircraft. Also, the EQP can be medical devices such as endoscopes and CT scanners.

[0151] The mechanical device MCHN in transport equipment can be used as a mobile device. The device EQP as transport equipment is suitable for transporting the photoelectric converter APR, or for assisting and / or automating driving (operation) through its imaging function. The processing device PRCS for assisting and / or automating driving (operation) can perform processing to operate the mechanical device MCHN as a mobile device based on information obtained from the photoelectric converter APR.

[0152] The photoelectric converter APR according to this embodiment can provide high value to its designers, manufacturers, distributors, buyers, and / or users. Therefore, by installing the photoelectric converter APR in the EQP (Equipment Equipment), the value of the EQP can also be increased. Thus, when manufacturing and selling the EQP, deciding to install the photoelectric converter APR of this embodiment in the EQP is advantageous in increasing the value of the EQP.

[0153] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways.

[0154] For example, an example in which a part of the configuration of one embodiment is added to another embodiment, or in which a part of the configuration of another embodiment is replaced, is also an embodiment of the present invention.

[0155] Furthermore, in the above embodiment, correction processing was performed between the pixel data output via signal line cM_vlK and the pixel data output via signal line cM_vl(K+1) adjacent to signal line cM_vlK, but the combination of pixel data is not limited to this. The comparison data for the pixel data to be corrected does not necessarily have to be the pixel data output via the adjacent signal line, but may be the pixel data output via two or more adjacent signal lines. Also, the comparison data for the pixel data to be corrected does not necessarily have to be a single pixel data, but may be two or more pixel data. In these cases, the vertical signal line coupling correction unit 52 should be appropriately modified so that it can also process the difference value with the pixel data output via two or more adjacent signal lines.

[0156] Furthermore, although the above embodiment shows a photoelectric converter 100 having a signal processing unit 50 including a vertical signal line coupling correction unit 52, the signal processing unit 50 does not necessarily have to be included in the photoelectric converter 100. For example, a device other than the photoelectric converter 100 may have a functional block equipped with the functions of the signal processing unit 50 (vertical signal line coupling correction unit 52). Alternatively, a signal processing device other than the photoelectric converter 100 may have the functions of the signal processing unit 50 (vertical signal line coupling correction unit 52). In this case, the signal processing device may be, for example, a computer such as a personal computer that includes a processor (e.g., CPU or MPU). Also, the signal processing unit 50 (vertical signal line coupling correction unit 52) ​​may be a circuit such as an ASIC.

[0157] Furthermore, in the third to fifth embodiments described above, an imaging device, which is a device for acquiring images, was given as an example of a photoelectric conversion device. However, the application examples of the present invention are not necessarily limited to imaging devices. For example, when applied to a device whose primary purpose is distance measurement, as described in the fourth embodiment above, it is not necessarily required to output an image. In such cases, the device can be described as a photoelectric conversion device that converts optical information into a predetermined electrical signal. An imaging device is one type of photoelectric conversion device.

[0158] Furthermore, the imaging systems shown in the third and fourth embodiments above are examples of imaging systems to which the photoelectric conversion device of the present invention can be applied, and the imaging systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 13 and 14.

[0159] The present invention can also be realized by supplying a program that implements one or more of the functions of the above-described embodiments to a system or device via a network or storage medium, and by having one or more processors in the computer of that system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that implements one or more functions.

[0160] It should be noted that the above embodiments are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted as being limited by them. In other words, the present invention can be implemented in various forms without departing from its technical concept or its main features. [Explanation of symbols]

[0161] 10...Pixel area 20…Vertical scanning unit 30...Column circuit section 40…Horizontal transfer unit 50... Signal Processing Unit 52... Vertical signal line coupling correction unit 54...Pixel data acquisition unit 56…Difference acquisition part 58...Comparison section 60...Threshold setting section 62... Correction section 64...Correction value setting section 66... ​​Comparison value acquisition unit 68…Comparison result storage unit 80... Control Unit 100... Photoelectric converter

Claims

1. A pixel section is arranged in multiple rows and multiple columns, each having multiple pixels including a photoelectric conversion unit, Each of the aforementioned multiple columns is provided with at least two, each connected to a pixel in the corresponding column, and the signal lines are connected to the pixels of that column. A pixel control unit that controls the reading of signals from the plurality of pixels to the plurality of signal lines in units of the row, A column circuit unit generates pixel data, which is a digital signal, by performing AD conversion on the analog signals read from each of the plurality of signal lines from the pixel unit. The system includes a signal processing unit that performs digital signal processing on the pixel data output from the column circuit unit, The plurality of signal lines include a first signal line and a second signal line arranged in the same column, and the period during which reading is performed from a pixel in one row to the first signal line overlaps with the period during which reading is performed from a pixel in another row to the second signal line. The signal processing unit, A difference acquisition unit that acquires the difference value between the pixel data read out on the first signal line and the pixel data read out on the second signal line, It includes a correction unit that performs correction processing on the pixel data based on the difference value, The pixel data read out on the first signal line and the pixel data read out on the second signal line are pixel data based on incident light. A photoelectric conversion device characterized by the following features.

2. The pixel control unit performs a first scan in which it sequentially reads signals from pixels in some of the rows of the plurality of rows, in units of the row, and a second scan in which it sequentially reads signals from pixels in other of the plurality of rows, in units of the row. The period during which a first signal line is read from a pixel in one row during the first scan overlaps with the period during which a second signal line is read from a pixel in another row during the second scan. The photoelectric conversion device according to claim 1, characterized by the features described above.

3. The signal processing unit further includes a comparison unit that compares the difference value with a predetermined threshold value, The correction unit corrects the pixel data when the difference value is greater than the threshold value. The photoelectric conversion device according to claim 1 or 2, characterized in that it is a photoelectric conversion device.

4. The correction unit performs a correction on the pixel data with the lower value among the pixel data read out on the first signal line and the pixel data read out on the second signal line. The photoelectric conversion device according to any one of claims 1 to 3.

5. The correction unit performs a correction by subtracting a correction value obtained from the difference value and a predetermined coefficient of a linear function from the pixel data. The photoelectric conversion device according to any one of claims 1 to 4.

6. The correction unit performs a correction by searching for the range to which the difference value corresponds in a table showing the relationship between a preset range of difference values ​​and the corresponding correction value, and subtracting the obtained correction value from the pixel data. The photoelectric conversion device according to any one of claims 1 to 4.

7. The difference acquisition unit acquires the difference value of the read pixel data for each pair of adjacent signal lines in a plurality of signal lines arranged in the same column. The photoelectric conversion device according to any one of claims 1 to 6.

8. The signal processing unit acquires the pixel data from each of the multiple signal lines arranged in the same column during overlapping periods, and acquires the difference values ​​for each of the adjacent pairs of signal lines in parallel. The photoelectric conversion device according to claim 7.

9. The signal processing unit sequentially acquires the pixel data for each of the adjacent signal line pairs and sequentially acquires the difference value for each of the adjacent signal line pairs. The photoelectric conversion device according to claim 7.

10. The first signal line and the second signal line are adjacent to each other. The photoelectric conversion device according to any one of claims 1 to 9.

11. The device comprises a first substrate on which at least the pixel portion is provided, and a second substrate laminated on the first substrate and on which at least the signal processing unit is provided. The photoelectric conversion device according to any one of claims 1 to 10.

12. A signal processing device for processing signals output from a photoelectric converter, comprising: a pixel section arranged in multiple rows and multiple columns, each having multiple pixels including a photoelectric conversion unit; a plurality of signal lines, at least two of which are arranged in each of the plurality of columns, each connected to the pixels of the corresponding column; a pixel control unit that controls the reading of signals from the plurality of pixels to the plurality of signal lines on a row-by-row basis; and a column circuit section that performs AD conversion on analog signals read from the pixel section to each of the plurality of signal lines to generate pixel data, which is a digital signal, wherein the plurality of signal lines include a first signal line and a second signal line arranged in the same column, and the period during which reading is performed from the pixels of one row to the first signal line overlaps with the period during which reading is performed from the pixels of another row to the second signal line, A difference acquisition unit that acquires the difference value between the pixel data read out on the first signal line and the pixel data read out on the second signal line, It includes a correction unit that performs correction processing on the pixel data based on the difference value, The pixel data read out on the first signal line and the pixel data read out on the second signal line are pixel data based on incident light. A signal processing device characterized by the following:

13. The system further includes a comparison unit that compares the difference value with a predetermined threshold, The correction unit corrects the pixel data when the difference value is greater than the threshold value. The signal processing apparatus according to claim 12, characterized in that it is a signal processing apparatus.

14. The correction unit performs a correction on the pixel data with the lower value among the pixel data read out on the first signal line and the pixel data read out on the second signal line. The signal processing apparatus according to claim 12 or 13, characterized in that it is a signal processing apparatus.

15. The difference acquisition unit acquires the difference value of the read pixel data for each pair of adjacent signal lines in a plurality of signal lines arranged in the same column. The signal processing apparatus according to any one of claims 12 to 14.

16. A photoelectric conversion device according to any one of claims 1 to 10, A signal processing device that processes the signal output from the aforementioned photoelectric converter and An imaging system characterized by having the following features.

17. It is a mobile object, A photoelectric conversion device according to any one of claims 1 to 10, Distance information acquisition means that acquires distance information to an object from a parallax image based on a signal from the aforementioned photoelectric converter, Control means for controlling the moving body based on the distance information A mobile body characterized by having the following features.

18. A photoelectric conversion device according to any one of claims 1 to 10, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A mechanical device controlled based on information obtained from the aforementioned photoelectric converter, A display device for displaying information obtained by the aforementioned photoelectric converter, and A memory device for storing information obtained by the aforementioned photoelectric converter, and at least one of the following: A device characterized by being equipped with the following features.

19. A pixel section having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each of which includes a photoelectric conversion unit, Each of the aforementioned multiple columns is provided with at least two, each connected to a pixel in the corresponding column, and the signal lines are connected to the pixels of that column. A pixel control unit that controls the reading of signals from the plurality of pixels to the plurality of signal lines in units of the row, A column circuit unit generates pixel data, which is a digital signal, by performing AD conversion on the analog signals read from each of the plurality of signal lines from the pixel unit. The system includes a signal processing unit that performs digital signal processing on the pixel data output from the column circuit unit, The plurality of signal lines include a first signal line and a second signal line arranged in the same column, and the period during which reading is performed from a pixel in one row to the first signal line overlaps with the period during which reading is performed from a pixel in another row to the second signal line. The signal processing unit, A difference acquisition unit that acquires the difference value between the pixel data read out on the first signal line and the pixel data read out on the second signal line, A correction unit that performs correction processing on the pixel data based on the difference value, It has a comparison unit that compares the difference value with a predetermined threshold, The correction unit corrects the pixel data when the difference value is greater than the threshold value. A photoelectric conversion device characterized by the following features.

20. A pixel section having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each of which includes a photoelectric conversion unit, Each of the aforementioned multiple columns is provided with at least two, each connected to a pixel in the corresponding column, and the signal lines are connected to the pixels of that column. A pixel control unit that controls the reading of signals from the plurality of pixels to the plurality of signal lines in units of the row, A column circuit unit generates pixel data, which is a digital signal, by performing AD conversion on the analog signals read from each of the plurality of signal lines from the pixel unit. The system includes a signal processing unit that performs digital signal processing on the pixel data output from the column circuit unit, The plurality of signal lines include a first signal line and a second signal line arranged in the same column, and the period during which reading is performed from a pixel in one row to the first signal line overlaps with the period during which reading is performed from a pixel in another row to the second signal line. The signal processing unit, A difference acquisition unit that acquires the difference value between the pixel data read out on the first signal line and the pixel data read out on the second signal line, It includes a correction unit that performs correction processing on the pixel data based on the difference value, The correction unit performs a correction on the pixel data with the lower value among the pixel data read out on the first signal line and the pixel data read out on the second signal line. A photoelectric conversion device characterized by the following features.

21. A pixel section having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each of which includes a photoelectric conversion unit, Each of the aforementioned multiple columns is provided with at least two, each connected to a pixel in the corresponding column, and the signal lines are connected to the pixels of that column. A pixel control unit that controls the reading of signals from the plurality of pixels to the plurality of signal lines in units of the row, A column circuit unit generates pixel data, which is a digital signal, by performing AD conversion on the analog signals read from each of the plurality of signal lines from the pixel unit. The system includes a signal processing unit that performs digital signal processing on the pixel data output from the column circuit unit, The plurality of signal lines include a first signal line and a second signal line arranged in the same column, and the period during which reading is performed from a pixel in one row to the first signal line overlaps with the period during which reading is performed from a pixel in another row to the second signal line. The signal processing unit, A difference acquisition unit that acquires the difference value between the pixel data read out on the first signal line and the pixel data read out on the second signal line, It includes a correction unit that performs correction processing on the pixel data based on the difference value, The correction unit performs a correction by subtracting a correction value obtained from the difference value and a predetermined coefficient of a linear function from the pixel data. A photoelectric conversion device characterized by the following features.

22. A pixel section having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each of which includes a photoelectric conversion unit, Each of the aforementioned multiple columns is provided with at least two, each connected to a pixel in the corresponding column, and the signal lines are connected to the pixels of that column. A pixel control unit that controls the reading of signals from the plurality of pixels to the plurality of signal lines in units of the row, A column circuit unit generates pixel data, which is a digital signal, by performing AD conversion on the analog signals read from each of the plurality of signal lines from the pixel unit. The system includes a signal processing unit that performs digital signal processing on the pixel data output from the column circuit unit, The plurality of signal lines include a first signal line and a second signal line arranged in the same column, and the period during which reading is performed from a pixel in one row to the first signal line overlaps with the period during which reading is performed from a pixel in another row to the second signal line. The signal processing unit, A difference acquisition unit that acquires the difference value between the pixel data read out on the first signal line and the pixel data read out on the second signal line, It includes a correction unit that performs correction processing on the pixel data based on the difference value, The correction unit performs a correction by searching for the range to which the difference value corresponds in a table showing the relationship between a preset range of difference values ​​and the corresponding correction value, and subtracting the obtained correction value from the pixel data. A photoelectric conversion device characterized by the following features.

23. A signal processing device for processing signals output from a photoelectric converter, comprising: a pixel section arranged in a plurality of rows and a plurality of columns, each having a plurality of pixels including a photoelectric converter; a plurality of signal lines, at least two of which are arranged in each of the plurality of columns, each connected to a pixel in the corresponding column; a pixel control section which controls the reading of signals from the plurality of pixels to the plurality of signal lines on a row-by-row basis; and a column circuit section which performs AD conversion on analog signals read from the pixel section to each of the plurality of signal lines to generate pixel data which is a digital signal, wherein the plurality of signal lines include a first signal line and a second signal line arranged in the same column, and the period during which reading is performed from a pixel in one row to the first signal line overlaps with the period during which reading is performed from a pixel in another row to the second signal line, A difference acquisition unit that acquires the difference value between the pixel data read out on the first signal line and the pixel data read out on the second signal line, A correction unit that performs correction processing on the pixel data based on the difference value, It has a comparison unit that compares the difference value with a predetermined threshold, The correction unit corrects the pixel data when the difference value is greater than the threshold value. A signal processing device characterized by the following:

24. A signal processing device for processing signals output from a photoelectric converter, comprising: a pixel unit arranged in a plurality of rows and a plurality of columns, each having a plurality of pixels including a photoelectric converter; a plurality of signal lines, at least two of which are arranged in each of the plurality of columns, each connected to a pixel in the corresponding column; a pixel control unit that controls the reading of signals from the plurality of pixels to the plurality of signal lines on a row-by-row basis; and a column circuit unit that performs AD conversion on analog signals read from the pixel unit to each of the plurality of signal lines to generate pixel data which is a digital signal, wherein the plurality of signal lines include a first signal line and a second signal line arranged in the same column, and the period during which reading is performed from a pixel in one row to the first signal line overlaps with the period during which reading is performed from a pixel in another row to the second signal line, A difference acquisition unit that acquires the difference value between the pixel data read out on the first signal line and the pixel data read out on the second signal line, It includes a correction unit that performs correction processing on the pixel data based on the difference value, The correction unit performs a correction on the pixel data with the lower value among the pixel data read out on the first signal line and the pixel data read out on the second signal line. A signal processing device characterized by the following:

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