Semiconductor equipment

Abstract

To provide a semiconductor device capable of operating a diode faster.SOLUTION: A semiconductor device according to one embodiment includes a first electrode, a second electrode, a first region, and a second region. The second electrode includes a contact part protruding toward the first electrode. The first region includes: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; a third semiconductor region of the first conductivity type; a gate electrode; a fourth semiconductor region of the first conductivity type; and a fifth semiconductor region of the second conductivity type. The third semiconductor region includes a first portion and a second portion. The fourth semiconductor region is provided between the third semiconductor region and the contact part in a first direction. The fourth semiconductor region is aligned with the first portion in a third direction. The fifth semiconductor region is provided on the third semiconductor region and is in contact with the contact part in a second direction. The fifth semiconductor region is aligned with the second portion in the third direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] One type of semiconductor device used for power conversion and other applications is the Reverse Conducting Insulated Gate Bipolar Transistor (RC-IGBT), which incorporates a diode into an Insulated Gate Bipolar Transistor (IGBT). There is a need for technology that enables faster diode operation in this type of semiconductor device. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-144998 [Overview of the project] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a semiconductor device that can operate diodes at a higher speed. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment comprises a first electrode, a second electrode, a first region, and a second region. The second electrode includes a contact portion protruding toward the first electrode and is separated from the first electrode. The first region is located between the first electrode and the second electrode and is provided on a portion of the first electrode. The first region includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a gate electrode, a fourth semiconductor region of a first conductivity type, and a fifth semiconductor region of a second conductivity type. A portion of the second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the portion of the second semiconductor region and includes a first portion and a second portion. The gate electrode faces the third semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction toward the second electrode from the first electrode. The fourth semiconductor region is provided between the third semiconductor region and the contact portion in the first direction. The fourth semiconductor region has a higher impurity concentration of the first conductivity type than the third semiconductor region. The fourth semiconductor region is aligned with the first portion in a third direction perpendicular to the first and second directions. The fifth semiconductor region is provided on the third semiconductor region and is in contact with the contact portion in the second direction. The fifth semiconductor region is aligned with the second portion in the third direction. The second region is provided on another part of the first electrode between the first electrode and the second electrode. The second region includes a sixth semiconductor region of the second conductivity type, another part of the second semiconductor region, and a seventh semiconductor region of the first conductivity type. The sixth semiconductor region has a higher impurity concentration of the second conductivity type than the second semiconductor region. The other part of the second semiconductor region is provided on the sixth semiconductor region. The seventh semiconductor region is provided on the other part of the second semiconductor region. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a plan view of a semiconductor device according to an embodiment. [Figure 2] Figure 2 is an enlarged plan view of part A of Figure 1. [Figure 3] Figure 3 is a cross-sectional view taken along line A1-A2 in Figure 2. [Figure 4] Figure 4 is a cross-sectional view of the line B1-B2 in Figure 2. [Figure 5] Figure 5 is a plan view showing a part of a semiconductor device related to a reference example. [Figure 6] Figure 6 is a plan view showing a part of a semiconductor device according to a first modified example of the embodiment. [Figure 7] Figure 7 is a plan view showing a part of a semiconductor device according to a second modified example of the embodiment. [Figure 8] Figure 8 is a cross-sectional view of the line A1-A2 in Figure 7. [Figure 9] Figure 9 is a cross-sectional view of the line B1-B2 in Figure 7. [Figure 10] Figure 10 is a plan view showing a part of a semiconductor device according to a third modified embodiment. [Figure 11] Figure 11 is a cross-sectional view of the line A1-A2 in Figure 10. [Figure 12] Figure 12 is a cross-sectional view of Figure 10, taken along the line B1-B2. [Figure 13] Figure 13 is a cross-sectional view showing a part of a semiconductor device according to a fourth modified example of the embodiment. [Figure 14] Figure 14 is a cross-sectional view showing a part of a semiconductor device according to a fifth modified example of the embodiment. [Modes for carrying out the invention]

[0007] Each embodiment of the present invention will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings. In this specification and in each figure, elements similar to those already described are denoted by the same reference numerals, and detailed explanations are omitted as appropriate. In the following explanation, n + , n, n - and p+ The notation of p represents the relative high or low impurity concentration in each conductivity type. That is, n + indicates that the impurity concentration of the n-type is relatively higher than that of the n, and n - indicates that the impurity concentration of the n-type is relatively lower than that of the n. Also, p + indicates that the impurity concentration of the p-type is relatively higher than that of the p, and p - indicates that the impurity concentration of the p-type is relatively lower than that of the p. For each embodiment described below, each embodiment may be implemented by inverting the p-type and n-type of each semiconductor region.

[0008] FIG. 1 is a plan view of a semiconductor device according to an embodiment. FIG. 2 is an enlarged plan view of part A in FIG. 1. FIG. 3 is a cross-sectional view taken along the line A1 - A2 in FIG. 2. FIG. 4 is a cross-sectional view taken along the line B1 - B2 in FIG. 2. In FIG. 2, the insulating layer 25 and the emitter electrode 32 are omitted. The semiconductor device according to the embodiment is an RC-IGBT. As shown in FIGS. 1 to 4, the semiconductor device 100 according to the embodiment includes a p + -type (first conductivity type) collector region 1 (first semiconductor region), an n - -type (second conductivity type) base region ② (second semiconductor region), a p-type base region 3 (third semiconductor region), a p + -type contact region 4 (fourth semiconductor region), an n + -type emitter region 5 (fifth semiconductor region), an n + -type cathode region 6 (sixth semiconductor region), a p-type anode region 7 (seventh semiconductor region), a p + -type anode region 8, a gate electrode 20, a conductive part 21, an insulating layer 25, a collector electrode 31 (first electrode), an emitter electrode 32 (second electrode), and a gate pad 33.

[0009] In describing the embodiments, the XYZ Cartesian coordinate system is used. The direction from the collector electrode 31 to the emitter electrode 32 is defined as the Z direction (first direction). The two directions perpendicular to the Z direction and mutually orthogonal are defined as the X direction (second direction) and the Y direction (third direction). For the sake of explanation, the direction from the collector electrode 31 to the emitter electrode 32 is referred to as "up," and the opposite direction is referred to as "down." These directions are based on the relative positional relationship between the collector electrode 31 and the emitter electrode 32 and are independent of the direction of gravity.

[0010] As shown in Figure 1, emitter electrodes 32 and gate pads 33 are provided on the upper surface of the semiconductor device 100. The emitter electrodes 32 and gate pads 33 are spaced apart from each other. For example, multiple emitter electrodes 32 are provided in the Y direction. Gate wiring 33a is provided around each emitter electrode 32. A portion of the gate wiring 33a extends in the Y direction between the emitter electrodes 32. The gate wiring 33a is electrically connected to the gate pads 33.

[0011] As shown in Figures 1 and 2, the semiconductor device 100 has an IGBT region R1 (first region) and a diode region R2 (second region). In the example shown in Figure 1, multiple IGBT regions R1 and diode regions R2 are provided in the X and Y directions, respectively. In the X direction, IGBT regions R1 and diode regions R2 are provided alternately.

[0012] As shown in Figures 3 and 4, a collector electrode 31 is provided on the lower surface of the semiconductor device 100. The collector electrode 31 and the emitter electrode 32 are separated from each other, and the multiple IGBT regions R1 and the multiple diode regions R2 are located between the collector electrode 31 and the emitter electrode 32.

[0013] As shown in Figures 2 to 4, each IGBT region R1 contains p + Shape collector region 1, n - Part of the base region 2, p-shaped base region 3, p + Shaped contact area 4, n +A shape emitter region 5 and a gate electrode 20 are provided.

[0014] p + The collector region 1 is provided on a portion of the collector electrode 31 and is electrically connected to the collector electrode 31. - Part of the shape base region 2 is p + It is located on top of the p-shaped collector region 1. The p-shaped base region 3 is n - A portion of the shaped base region 2 is provided, p + It is located above the shape collector area 1.

[0015] As shown in Figure 4, the p-type base region 3 includes a first portion 3a and a second portion 3b. The emitter electrode 32 includes a contact portion 32a that protrudes toward the collector electrode 31. The first portion 3a is in contact with the contact portion 32a in the Z direction. The second portion 3b is located above the first portion 3a and is in contact with the contact portion 32a in the X direction.

[0016] As shown in Figure 3, p + The p-shaped contact region 4 is provided between the p-shaped base region 3 and the contact portion 32a in the Z direction and is in contact with the contact portion 32a. As shown in Figure 2, + The contact region 4 is aligned with the first portion 3a in the Y direction. + The p-type impurity concentration in the contact region 4 is higher than the p-type impurity concentration in the p-type base region 3.

[0017] As shown in Figure 3, n + The type emitter region 5 is located on top of the p-type base region 3. + The shape of the emitter region 5 is p + It is located above the contact region 4 and is in contact with the contact portion 32a in the X direction. As shown in Figure 2, n + The shape emitter region 5 is aligned with the second portion 3b in the Y direction.

[0018] The gate electrode 20 faces the p-type base region 3 in the X direction via the gate insulating layer 20a. In the illustrated example, the gate electrode 20 is further connected via the gate insulating layer 20a to the n - Shape base region 2 and n + It also faces the shape emitter region 5.

[0019] The emitter electrode 32 is a p-type base region 3, p + Shaped contact area 4, and n + It is electrically connected to the emitter region 5. An insulating layer 25 is provided between the gate electrode 20 and the emitter electrode 32, and the gate electrode 20 and the emitter electrode 32 are electrically isolated from each other.

[0020] As shown in Figures 2 to 4, in one IGBT region R1, multiple p-type base regions 3, gate electrodes 20, and contact portions 32a are provided in the X direction. Each of the multiple p-type base regions 3, gate electrodes 20, and contact portions 32a is provided in a stripe shape and extends in the Y direction. The Y-direction end of the gate electrode 20 is electrically connected to the gate wiring 33a. The gate electrode 20 is electrically connected to the gate pad 33 via the gate wiring 33a.

[0021] As shown in Figure 2, p + Shaped contact area 4 and n + Each of the p-shaped emitter regions 5 is provided in multiple locations in the Y direction on a single p-shaped base region 3. + The contact region 4 and the first portion 3a are arranged alternately in the Y direction. + The shape emitter region 5 and the second portion 3b are arranged alternately in the Y direction.

[0022] Each diode region R2 has n + Shape of cathode region 6, n - Another part of the base region 2, p-shaped anode region 7, p + A shaped anode region 8 and a conductive portion 21 are provided. +The cathode region 6 is located on another part of the collector electrode 31 and is electrically connected to the collector electrode 31. - Another part of the shape base region 2 is n + It is located on top of the p-shaped cathode region 6. The p-shaped anode region 7 is n - Provided on the other part of the shaped base region 2, n + It is located above the cathode region 6.

[0023] The conductive portion 21 faces the p-type anode region 7 in the X direction via the insulating layer 21a. + The p-shaped anode region 8 is located on top of the p-shaped anode region 7. + The p-type impurity concentration in p-type anode region 8 is higher than the p-type impurity concentration in p-type anode region 7. + The anode region 8 and the conductive portion 21 are electrically connected to the emitter electrode 32.

[0024] As shown in Figures 2 to 4, the emitter electrode 32 may include a contact portion 32b that protrudes toward the collector electrode 31. A portion of the p-type anode region 7 is aligned with the contact portion 32b in the X direction. + The p-type anode region 8 is located in the Z direction between the p-type anode region 7 and the emitter electrode 32.

[0025] In one diode region R2, p-type anode region 7, p + Multiple p-shaped anode regions 8 and conductive portions 21 are provided in the X direction. Multiple p-shaped anode regions 7, multiple p + Each of the shaped anode region 8 and the plurality of conductive parts 21 is arranged in a stripe pattern and extends in the Y direction.

[0026] The operation of the semiconductor device 100 will be described. With a positive voltage applied to the collector electrode 31 relative to the emitter electrode 32, a voltage above a threshold is applied to the gate electrode 20. This forms a channel (inversion layer) in the p-type base region 3. Electrons pass through the channel,+ Shape emitter region 5 to n - The holes flow into the base region 2, p + Shape collector area 1 to n - It flows into the base region 2. - The carrier density accumulated in the base region 2 increases, causing conductivity modulation. As a result, n - The electrical resistance of the p-type base region 2 decreases significantly, and the IGBT region R1 turns on. Subsequently, when the voltage applied to the gate electrode 20 falls below a threshold, the channel in the p-type base region 3 disappears, and the IGBT region R1 switches to the off state.

[0027] After the IGBT region R1 is switched to the off state, electrons accumulated in the n-type base region 2 are discharged to the collector electrode 31 through the p+-type collector region 1. Holes are discharged to the emitter electrode 32 through the p-type base region 3.

[0028] For example, a bridge circuit is formed by multiple semiconductor devices 100. When one semiconductor device 100 switches from the ON state to the OFF state, the inductance component of the bridge circuit induces an electromotive force at the emitter electrode 32 of another semiconductor device 100. As a result, the diode region R2 in that other semiconductor device 100 operates. From the p-type anode region 7 to n - Holes flow into the base region 2, n + Shape cathode region 6 to n - Electrons flow into the base region 2. The diode region R2 functions as a freewheeling diode (FWD).

[0029] As shown in Figures 3 and 4, p + Shape collector area 1 and n - Between the shape base region 2 and n + Shape cathode region 6 and n - An n-type buffer region 9 may be provided between the n-type base region 2 and the n-type buffer region 9. The n-type impurity concentration in the n-type buffer region 9 is n + The n-type impurity concentration is lower than that of the cathode region 6, n -It is higher than the n-type impurity concentration in the base region 2. By providing the n-type buffer region 9, - The depletion layer in the base region 2 can be more reliably suppressed by the n-type buffer region 9.

[0030] In the IGBT region R1, some of the multiple gate electrodes 20 may be replaced with conductive parts 21. By replacing some of the gate electrodes 20 with conductive parts 21, when the IGBT region R1 is ON, n - The density of carriers accumulated in the base region 2 can be increased, further reducing the electrical resistance of the semiconductor device 100.

[0031] An example of the materials used for each component of the semiconductor device 100 will be described. p + Shape collector region 1, n - Shape base region 2, p-shaped base region 3, p + Shaped contact area 4, n + Shape emitter region 5, n + p-type cathode region 6, p-type anode region 7, p + The n-type anode region 8 and the n-type buffer region 9 contain silicon, silicon carbide, gallium nitride, or gallium arsenide as semiconductor materials. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as n-type impurities. Boron can be used as p-type impurities.

[0032] The gate electrode 20 and the conductive part 21 contain a conductive material such as polysilicon. The gate insulating layer 20a, insulating layer 21a, and insulating layer 25 contain an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The collector electrode 31, emitter electrode 32, gate pad 33, and gate wiring 33a contain a metal such as titanium or aluminum.

[0033] Figure 5 is a plan view showing a part of a semiconductor device related to a reference example. In the semiconductor device 100r shown in Figure 5, in the IGBT region R1, a stripe-like extension of p extends on a single p-type base region 3. +A contact area 4r is provided.

[0034] The advantages of the embodiment will be explained. The semiconductor device 100r is p + Shape collector region 1, n - Shape base region 2, p-shaped base region 3, and n + The device includes a parasitic thyristor consisting of a p-type emitter region 5. When the IGBT region R1 switches to the off state, holes flow into the p-type base region 3. When the potential of the p-type base region 3 rises due to the flow of holes, the parasitic thyristor may activate. When the parasitic thyristor activates, a large current flows through the semiconductor device 100r, destroying the semiconductor device 100r.

[0035] In semiconductor device 100r, in order to suppress the operation of the parasitic thyristor, p is placed below the contact portion 32a. + A contact area 4r is provided. + The p-type impurity concentration in the p-type contact region 4r is higher than the p-type impurity concentration in the p-type base region 3. When a hole flows into the p-type base region 3, the hole becomes p + The gas is more easily discharged to the emitter electrode 32 through the contact region 4r. This suppresses the operation of the parasitic thyristor. In other words, the latch-up tolerance of the semiconductor device 100r can be improved.

[0036] On the other hand, the IGBT region R1 is n - It also includes a parasitic diode consisting of a p-type base region 2 and a p-type base region 3. When diode region R2 is ON, the parasitic diode of IGBT region R1 operates, and n is emitted from the emitter electrode 32. - Holes can flow into the base region 2. In particular, p + When a contact area 4r is provided, p + Because the electrical resistance between the contact region 4r and the emitter electrode 32 is low, more holes are n - It flows into the base region 2. As a result, n - The carriers accumulated in the base region 2 increase. When the diode region R2 switches to the off state, n -It takes a longer time to discharge the carriers accumulated in the p-shaped base region 2. As a result, the switching from the on state to the off state of the diode region R2 is delayed, and the operating speed of the diode region R2 decreases. The switching loss of the semiconductor device 100 during the operation of the diode region R2 increases.

[0037] Regarding this problem, in the semiconductor device 100 according to the embodiment, the p + -shaped contact region 4 is aligned with the first portion 3a of the p-shaped base region 3 in the Y direction. That is, when comparing the semiconductor device 100r according to the reference example and the semiconductor device 100 according to the embodiment, the p + length of the p-shaped contact region 4 in the Y direction is shorter than the length of the p + -shaped contact region 4r in the Y direction. A part of the p + -shaped contact region 4r is replaced by the first portion 3a of the p-shaped base region 3. By providing the p + -shaped contact region 4 with a shorter length in the Y direction, when the diode region R2 is in the on state, the amount of holes flowing into the n - -shaped base region 2 through the parasitic diode can be reduced. The operation of the diode region R2 can be made faster, and the switching loss of the semiconductor device 100 can be reduced.

[0038] Also, the p + -shaped contact region 4 is located below the n + -shaped emitter region 5. Therefore, the holes flowing toward the n + -shaped emitter region 5 move to the p + -shaped contact region 4 before reaching the region near the n + -shaped emitter region 5. Since the increase in the potential in the region near the n + -shaped emitter region 5 can be suppressed, the decrease in the latch-up tolerance can also be suppressed.

[0039] According to the semiconductor device 100 according to the embodiment, the diode region R2 can be operated at a higher speed while suppressing the decrease in the latch-up tolerance.

[0040] p+ The position of at least a portion of the contact area 4 in the Y direction is n + It is preferable that the position is the same as that of at least a portion of the emitter region 5 in the Y direction. That is, as shown in Figure 2, p + Shaped contact area 4 and n + When the shape emitter region 5 is viewed in plan view, p + Shape Contact area 4 at least a portion and n + At least a portion of the shape emitter region 5 is adjacent to each other in the X direction. With this configuration, n + Holes flowing toward the emitter region 5 are more p + It moves to contact area 4 and becomes easier to discharge. + This allows for more reliable suppression of the potential rise in the region near the emitter region 5, thereby improving the latch-up tolerance of the semiconductor device 100.

[0041] For example, as shown in Figure 2, adjacent p + The distance D1 in the Y direction between two contact regions 4 is p + The length L1 in the Y direction of the contact region 4 is longer than the length of the adjacent n + The distance D2 in the Y direction between two shape emitter regions 5 is n + The shape is longer than the length L2 in the Y direction of the emitter region 5. + By providing the emitter region 5, the saturation current density of the semiconductor device 100 can be reduced. + Depending on the arrangement of the emitter region 5, p is spaced apart. + By providing a contact area 4, p + This suppresses hole injection through the contact region 4, allowing the diode region R2 to operate at a faster speed.

[0042] p-shaped base region 3 and p + The boundary between the p-type contact region 4 and the p-type base region 3 is, for example, the p-type impurity concentration of the p-type base region 3 and the p-type +This is determined by the p-type impurity concentration in the contact region 4. First, the distribution of p-type impurity concentrations in the region between the gate electrodes 20 is measured. From the distribution of p-type impurity concentrations, the p-type base region 3 and p + Determine the approximate location of the p-type contact region 4. That is, the region with a relatively low concentration of p-type impurities is defined as the p-type base region 3. The region with a relatively high concentration of p-type impurities is defined as the p-type base region 3. + Let the shape be contact region 4. Next, n - Shape base region 2 and p + Next, determine the concentration of p-type impurities in the p-type base region 3 in the region away from the p-type contact region 4. + Determine the maximum p-type impurity concentration in the p-type contact region 4. + Between the p-type contact region 4 and the p-type base region 3, the set of points having the midpoint between the two p-type impurity concentrations is the p-type base region 3 and the p-type contact region 4. + This is the boundary between the contact area 4 and the surrounding area.

[0043] (First variation) Figure 6 is a plan view showing a part of a semiconductor device according to a first modified embodiment. Note that the insulating layer 25 and the emitter electrode 32 are omitted in Figure 6. In the semiconductor device 110 according to the first modified example shown in Figure 6, p + The length L4 of the contact region 4 in the Y direction is n + It is longer than the length L5 in the Y direction of the emitter region 5. According to the semiconductor device 110 of the first modification, compared to the semiconductor device 100, n + This effectively reduces the number of holes flowing near the emitter region 5, further improving latch-up tolerance.

[0044] For example, p + The contact region 4 includes ends 4a and 4b in the Y direction. +The emitter region 5 includes ends 5a and 5b in the Y direction. To improve latch-up tolerance, it is preferable that the positions P1 of end 5a and P2 of end 5b in the Y direction are between the position P3 of end 4a and the position P4 of end 4b in the Y direction.

[0045] (Second variation) Figure 7 is a plan view showing a part of a semiconductor device according to a second modified embodiment. Figure 8 is a cross-sectional view taken along line A1-A2 in Figure 7. Figure 9 is a cross-sectional view taken along line B1-B2 in Figure 7. Note that the insulating layer 25 is omitted in Figure 7. The contact portions 32a and 32b of the emitter electrode 32 are shown by dashed lines, and other parts of the emitter electrode 32 are omitted. In semiconductor devices 100 and 110, the contact portion 32a extends in the Y direction. In contrast, in the semiconductor device 120 according to the second modified example shown in Figure 7, multiple contact portions 32a are provided in the Y direction on a single p-shaped base region 3.

[0046] As shown in Figures 7 and 8, each of the multiple contact portions 32a is a multiple p + It is provided on the contact area 4. As shown in Figure 9, the contact portion 32a is not provided on the first portion 3a. Therefore, the first portion 3a and the second portion 3b are not in contact with the contact portion 32a.

[0047] For example, the contact portion 32b extends in the Y direction. Alternatively, multiple contact portions 32b may be provided in the Y direction, similar to the contact portion 32a. In that case, p + Multiple anode regions 8 are also provided in the Y direction. Each of the multiple contact portions 32b is a multiple p + It is located above the shape of anode region 8.

[0048] According to the second modified semiconductor device 120, the contact area between the p-type base region 3 and the contact portion 32a is smaller compared to the semiconductor device 100 or 110. For example, when the IGBT region R1 is ON, the discharge of holes from the p-type base region 3 to the emitter electrode 32 can be suppressed. As a result, n - The carrier density accumulated in the base region 2 can be increased. The electrical resistance of the semiconductor device 120 when the IGBT region R1 is ON can be further reduced.

[0049] (Third variation) Figure 10 is a plan view showing a part of a semiconductor device according to a third modified embodiment. Figure 11 is a cross-sectional view taken along line A1-A2 in Figure 10. Figure 12 is a cross-sectional view taken along line B1-B2 in Figure 10. Note that the insulating layer 25 and the emitter electrode are omitted in Figure 10. In the semiconductor device 130 according to the third modified example shown in Figures 10 to 12, the p-type base region 3 includes a high-concentration region 3H (first sub-region) and a low-concentration region 3L (second sub-region). The low-concentration region 3L is aligned with the high-concentration region 3H in the Y direction. The p-type impurity concentration in the low-concentration region 3L is lower than the p-type impurity concentration in the high-concentration region 3H.

[0050] p + Shape Contact area 4 and n + The p-type emitter region 5 is located above the high-concentration region 3H. The first part 3a and the second part 3b are located in the low-concentration region 3L. That is, in the p-type base region 3, p + Shaped contact area 4 and n + The p-type impurity concentration in the region away from the emitter region 5 is p + Shape Contact area 4 and n + The p-type impurity concentration is lower than that in the region near emitter region 5.

[0051] When the diode region R2 is operating, p from the emitter electrode 32 + The holes that flowed into the contact region 4 spread not only in the Z direction but also in the X and Y directions, n -Move to p-base region 2. The lower the concentration of p-type impurities in p-base region 3, the greater the resistance to holes. When the concentration of p-type impurities in low-concentration region 3L is low, p + This increases the resistance to holes flowing from the p-type contact region 4 to the p-type base region 3. Furthermore, the low-concentration region 3L is p + Shape Contact area 4 and n + It is located away from the type emitter region 5. Therefore, even when the p-type impurity concentration in the low-concentration region 3L is low, the impact on latch-up is small.

[0052] For example, the p-type impurity concentration in the low-concentration region 3L is less than 0.5 times the p-type impurity concentration in the high-concentration region 3H. Preferably, the p-type impurity concentration in the low-concentration region 3L is less than 0.1 times the p-type impurity concentration in the high-concentration region 3H. Most preferably, the p-type impurity concentration in the low-concentration region 3L is less than 0.01 times the p-type impurity concentration in the high-concentration region 3H.

[0053] According to the semiconductor device 130 of the third modified example, compared to the semiconductor device 100, p + This suppresses hole injection through the contact region 4, allowing the diode region R2 to operate at an even faster speed.

[0054] (Fourth variation) Figure 13 is a cross-sectional view showing a part of a semiconductor device according to a fourth modified example of the embodiment. As shown in Figure 13, the semiconductor device 140 according to the fourth modified example, p + The shape of the anode region 8 is p + It may be located above the p-shaped contact region 4. The lower surface of the contact portion 32b is the upper surface of the p-shaped anode region 7 and p + It is located at the same position as the upper surface of the shape anode region 8.

[0055] (Fifth variation) Figure 14 is a cross-sectional view showing a part of a semiconductor device according to a fifth modified example of the embodiment. As shown in Figure 14, the semiconductor device 150 according to the fifth modified example, the conductive portion 21 may be omitted in the diode region R2. Also, in the diode region R2, the emitter electrode 32 does not need to include the contact portion 32b. In the diode region R2, the lower surface of the emitter electrode 32 is the upper surface of the p-type anode region 7 and p + It is located at the same position as the upper surface of the shape anode region 8.

[0056] In the semiconductor devices 100 to 150 described above, the p-type impurity concentration in the p-type anode region 7 may differ from the p-type impurity concentration in the p-type base region 3. For example, the p-type impurity concentration in the p-type anode region 7 is lower than that in the p-type base region 3. This allows n to be emitted from the emitter electrode 32 when the diode region R2 is operating. - This can reduce the amount of holes flowing into the base region 2.

[0057] The length of the p-type anode region 7 in the Z direction may be different from the length of the p-type base region 3 in the Z direction. For example, n - The pn junction surface between the p-shaped base region 2 and the p-shaped anode region 7 is n - It is located below the pn junction surface between the p-shaped base region 2 and the p-shaped base region 3.

[0058] By optimizing the surface structure of the IGBT region R1 and the diode region R2, respectively, the characteristics of semiconductor devices 100-150 can be further enhanced.

[0059] Furthermore, the sizes of the IGBT region R1 and the diode region R2 are not limited to the illustrated example and can be changed as appropriate. Narrower IGBT region R1 and narrower diode region R2 may be alternately arranged in the X direction.

[0060] Embodiments of the present invention include the following configurations. (Composition 1) First electrode and, A second electrode, which includes a contact portion protruding toward the first electrode and is separated from the first electrode, A first region provided on a part of the first electrode between the first electrode and the second electrode, The first semiconductor region of the first conductivity type, A second semiconductor region of a second conductivity type, partly provided on the first semiconductor region, A third semiconductor region of a first conductivity type is provided on the part of the second semiconductor region and includes the first and second portions, In a second direction perpendicular to the first direction toward the second electrode from the first electrode, a gate electrode facing the third semiconductor region via a gate insulating layer, A fourth semiconductor region of the first conductivity type is provided between the third semiconductor region and the contact portion in the first direction, having a higher impurity concentration of the first conductivity type than the third semiconductor region, and is aligned with the first portion in the third direction perpendicular to the first and second directions. A fifth semiconductor region of a second conductivity type is provided on the third semiconductor region, is in contact with the contact portion in the second direction, and is aligned with the second portion in the third direction, The first region including, A second region provided between the first electrode and the second electrode, on another part of the first electrode, A sixth semiconductor region of the second conductivity having a higher impurity concentration of the second conductivity than the aforementioned second semiconductor region, Another part of the second semiconductor region provided on the sixth semiconductor region, A seventh semiconductor region of a first conductivity type is provided on another part of the second semiconductor region, The second region including, A semiconductor device equipped with the following features. (Configuration 2) The semiconductor device according to configuration 1, wherein the position of at least a portion of the fourth semiconductor region in the third direction is the same as the position of at least a portion of the fifth semiconductor region in the third direction. (Composition 3) The semiconductor device according to configuration 1 or 2, wherein the length of the fourth semiconductor region in the third direction is longer than the length of the fifth semiconductor region in the third direction. (Composition 4) The first portion and the fourth semiconductor region are arranged alternately in the third direction. The semiconductor device according to any one of configurations 1 to 3, wherein the second portion and the fifth semiconductor region are arranged alternately in the third direction. (Composition 5) The distance in the third direction between adjacent fourth semiconductor regions is longer than the length of one of the adjacent fourth semiconductor regions in the third direction. The semiconductor device according to configuration 4, wherein the distance in the third direction between adjacent fifth semiconductor regions is longer than the length of one of the adjacent fifth semiconductor regions in the third direction. (Composition 6) The plurality of first portions and the plurality of fourth semiconductor regions are in contact with the contact portion in the first direction. The semiconductor device according to configuration 4 or 5, wherein the plurality of second portions and the plurality of fifth semiconductor regions are in contact with the contact portion in the second direction. (Composition 7) Multiple contact portions are provided in the third direction. The semiconductor device according to configuration 4 or 5, wherein each of the multiple contact portions is provided on each of the multiple fourth semiconductor regions. (Composition 8) The third semiconductor region includes a first sub-region and a second sub-region adjacent to the first sub-region in the third direction, The fourth semiconductor region and the fifth semiconductor region are provided on the first sub-region, The first and second portions are provided in the second sub-region, The semiconductor device according to any one of configurations 1 to 7, wherein the impurity concentration of the first conductivity type in the second sub-region is lower than the impurity concentration of the first conductivity type in the first sub-region.

[0061] According to the embodiments described above, it is possible to operate the diode region of a semiconductor device at a higher speed.

[0062] The relative levels of impurity concentrations between semiconductor regions in each embodiment can be confirmed, for example, using a scanning capacitance microscope (SCM). The carrier concentration in each semiconductor region can be considered equal to the concentration of activated impurities in that region. Therefore, the relative levels of carrier concentrations between semiconductor regions can also be confirmed using SCM. Furthermore, the impurity concentration in each semiconductor region can be measured, for example, by secondary ion mass spectrometry (SIMS).

[0063] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other. [Explanation of symbols]

[0064] 1:p + Collector area, 2:n - 3: P-type base area, 3H: High concentration area, 3L: Low concentration area, 3a: 1st part, 3b: 2nd part, 4,4r:p + Shape of contact area, 4a: end, 4b: end, 5: n + Shape of emitter region, 5a: edge, 5b: edge, 6: n + 7:p-type cathode region, 8:p-type anode region +R1: Anode region, 9: n-type buffer region, 20: Gate electrode, 20a: Gate insulating layer, 21: Conductive part, 21a: Insulating layer, 25: Insulating layer, 31: Collector electrode, 32: Emitter electrode, 32a: Contact part, 32b: Contact part, 33: Gate pad, 33a: Gate wiring, 100, 100r, 110~150: Semiconductor device, R1: IGBT region, R2: Diode region

Claims

1. First electrode and, A second electrode, which includes a contact portion protruding toward the first electrode and is separated from the first electrode, A first region provided between the first electrode and the second electrode, on a part of the first electrode, The first semiconductor region of the first conductivity type, A second semiconductor region of a second conductivity type, a portion of which is provided on the first semiconductor region, A third semiconductor region of a first conductivity type is provided on the part of the second semiconductor region and includes the first and second portions, In a second direction perpendicular to the first direction toward the second electrode, a gate electrode facing the third semiconductor region via a gate insulating layer, A fourth semiconductor region of the first conductivity type is provided between the third semiconductor region and the contact portion in the first direction, having a higher impurity concentration of the first conductivity type than the third semiconductor region, and is aligned with the first portion in the third direction perpendicular to the first and second directions. A fifth semiconductor region of a second conductivity type is provided on the third semiconductor region, is in contact with the contact portion in the second direction, and is aligned with the second portion in the third direction, The first region including, A second region provided between the first electrode and the second electrode, on another part of the first electrode, A sixth semiconductor region of the second conductivity having a higher impurity concentration of the second conductivity than the second semiconductor region, Another part of the second semiconductor region provided on the sixth semiconductor region, A seventh semiconductor region of a first conductivity type is provided on another part of the second semiconductor region, The second region including, A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, wherein the position of at least a portion of the fourth semiconductor region in the third direction is the same as the position of at least a portion of the fifth semiconductor region in the third direction.

3. The semiconductor device according to claim 1 or 2, wherein the length of the fourth semiconductor region in the third direction is longer than the length of the fifth semiconductor region in the third direction.

4. The first portion and the fourth semiconductor region are arranged alternately in the third direction. The semiconductor device according to claim 1 or 2, wherein the second portion and the fifth semiconductor region are arranged alternately in the third direction.

5. The distance in the third direction between adjacent fourth semiconductor regions is longer than the length of one of the adjacent fourth semiconductor regions in the third direction. The semiconductor device according to claim 4, wherein the distance in the third direction between adjacent fifth semiconductor regions is longer than the length of one of the adjacent fifth semiconductor regions in the third direction.

6. The plurality of first portions and the plurality of fourth semiconductor regions are in contact with the contact portion in the first direction. The semiconductor device according to claim 4, wherein the plurality of second portions and the plurality of fifth semiconductor regions are in contact with the contact portion in the second direction.

7. Multiple contact portions are provided in the third direction. The semiconductor device according to claim 4, wherein each of the multiple contact portions is provided on a plurality of the fourth semiconductor regions.

8. The third semiconductor region includes a first sub-region and a second sub-region adjacent to the first sub-region in the third direction, The fourth semiconductor region and the fifth semiconductor region are provided on the first sub-region, The first and second portions are provided in the second sub-region, The semiconductor device according to claim 1 or 2, wherein the impurity concentration of the first conductivity type in the second sub-region is lower than the impurity concentration of the first conductivity type in the first sub-region.

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