Semiconductor devices and manufacturing methods

Abstract

In one embodiment, the semiconductor device (1) comprises a semiconductor body (2), a gate electrode (33), and a first electrode (31), wherein the semiconductor body (2) comprises a first region (21) that is a source or emitter region, and a well region (22) located adjacent to the first region (21), wherein the first region (21) is of a first conductivity type and the well region (22) is of a different second conductivity type, the well region (22) is separated from the gate electrode (33) by a gate insulating layer (4), the first region (21) is in electrical contact with the first electrode (31), at least one current limiting region (5) is present in the first region (21), and the at least one current limiting region (5) is a sub-region of the first region (21) that has reduced conductivity.

Description

Technical Field

[0001] A semiconductor device is provided. A method for manufacturing such a semiconductor device is also provided.

Background Art

[0002] U.S. Patent Application Publication No. 2017 / 0243970, U.S. Patent Application Publication No. 2017 / 0229535, and U.S. Patent Application Publication No. 2015 / 0108564 refer to semiconductor devices. The U.S. Patent Application Publication No. 2020 / 0286991 refers to a semiconductor device comprising a silicon carbide semiconductor body including a source region and a body region of opposite conductivity types. A trench structure extends perpendicularly from a first surface into the silicon carbide semiconductor body and comprises a gate electrode and a gate dielectric. A contact is electrically connected to the source region at the first surface. The source region includes a first source sub-region, a second source sub-region, and a third source sub-region, which are directly adjacent to the contact in the source contact region of the first surface. The second sub-region is positioned perpendicularly between the first and third sub-regions. The doping concentration profile of the source region perpendicularly includes a minimum doping concentration in the second sub-region and a maximum doping concentration in the third sub-region. Each of the second and third sub-regions overlaps with the source contact region. U.S. Patent No. 8310006 discloses devices, structures, and related methods for IGBTs and the like that include a self-aligned series resistor at the source-body junction to avoid latch-up. The series resistor is realized by using a charged dielectric and / or by using a dielectric that provides a source of dopant atoms of the same conductivity type as the source region on the sidewall adjacent to the source region. The U.S. Patent Application Publication No. 2015 / 0108564 describes that the source region of a MOSFET includes a source contact region connected to a source pad, a source extension region adjacent to the channel region within the well region, and a source resistance control region located between the source extension region and the source contact region. The source resistance control region has a different impurity concentration than the source extension region and the source contact region. These three regions are connected in series between the source pad and the channel region within the well region.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The problem to be solved is to provide a semiconductor device having an improved trade-off between conduction loss and short-circuit withstand capability (SCWT).

Means for Solving the Problems

[0004] This object is , Germany achieved by the semiconductor device and method defined in the independent claims. Exemplary further developments form the subject matter of the dependent claims.

[0005] For example, the semiconductor device described herein includes one or more current-limiting regions that are sub-regions of the source region or the emitter region, and the sub-regions are irradiated such that there are more crystal lattice defects in the sub-regions than in the remaining regions of the source region or the emitter region. Thus, at least one current-limiting region has a reduced conductivity compared to the remaining regions of the source region or the emitter region. Due to the at least one current-limiting region, the source resistance value R S increases. This increase in R S does not significantly interfere with the device performance in normal operation but improves the short-circuit behavior.

[0006] According to at least one embodiment, the semiconductor device comprises a semiconductor body, a gate electrode, and a first electrode. For example, the semiconductor body is made of a wide-bandgap semiconductor material such as SiC, Ga2O3, or GaN. However, the semiconductor body may alternatively be made of silicon, or Si for short. The electrode can be made from at least one metal, or from a highly doped and / or ohmic conductive semiconductor material such as polySi.

[0007] According to at least one embodiment, the semiconductor body comprises a first region, for example, the first region being a source region or an emitter region.

[0008] According to at least one embodiment, the semiconductor body comprises a well region. The well region is located adjacent to a first region; that is, the first region can contact the well region and therefore can be in direct physical contact with it. The channel region is part of the well region and may have the same doping concentration. During operation, electrons flow through the channel region from the source region to the drift region along the gate insulating layer. In the operation of the semiconductor device, the channel region may be that portion of the well region adjacent to the gate insulating layer.

[0009] According to at least one embodiment, the first region is of a first conductivity type, and the well region is of a different second conductivity type. For example, the first conductivity type is n-conductive and the second conductivity type is p-conductive, or vice versa. Hereinafter, the first conductivity type will be referred to as n-conductive, and therefore, if the first conductivity type is instead p-conductive, the doping relationships described below must be reversed.

[0010] According to at least one embodiment, the well region is adjacent to the gate electrode and separated from the gate electrode by a gate insulating layer. The gate insulating layer may be directly between the gate electrode and the well region.

[0011] According to at least one embodiment, the first region is in electrical contact with a first electrode, which is, for example, a source electrode or an emitter electrode. Thus, the first electrode can be in contact with the semiconductor body in at least the first region. For example, the well is in electrical contact by the first electrode or, otherwise, by a separate electrode.

[0012] According to at least one embodiment, the first region contains either one current-limiting region or multiple current-limiting regions. The at least one current-limiting region is a sub-region of the first region with reduced conductivity. For example, the first region and the at least one current-limiting region are made of the same matrix material, such as SiC. However, the conductivity in the at least one current-limiting region is intentionally lower than in the other regions of the first region because the at least one current-limiting region has more defects in its crystal lattice than the other regions of the first region.

[0013] In at least one embodiment, the semiconductor device comprises a semiconductor body, a gate electrode, and a first electrode. - The semiconductor body comprises a first region and a well region located adjacent to the first region, wherein the first region has a first conductivity type, and the well region has a different second conductivity type. - The well region is adjacent to the gate electrode and separated from the gate electrode by the gate insulating layer. -The first region is in electrical contact with the first electrode, -The first region contains at least one current limiting region, - At least one current-limiting region is a sub-region of the first region where conductivity is reduced.

[0014] Therefore, the present application describes, for example, a metal-insulator-semiconductor field effect transistor (MISFET), a metal-oxide-semiconductor field effect transistor (MOSFET), or a junction gate field effect transistor (JFET) based on a silicon carbide (SiC) material. At least one sub-region of the source region or emitter region is damaged by irradiation to reduce its conductivity, improving the trade-off between conduction loss and short-circuit withstand capability.

[0015] SiC MOSFETs are currently available from several vendors. SiC MOSFETs provided in either planar or trench cell designs offer competitive static losses, high-speed dynamic performance, and sufficient reliability. In terms of fault handling capability, SiC MOSFETs still do not reach the typical industry standard value of about 10 μs shown by their Si counterparts. This is usually associated with a strong trade-off between conduction loss and short-circuit withstand time (SCWT). The optimal trade-off between SCWT and the on-state device resistance R DS,on One approach to is to use a slightly increased source resistance value R S .

[0016] Therefore, this specification describes, for example, SiC MOSFETs in which a portion of the source region undergoes an irradiation process. When using a suitable mask such as a SiO2 mask or an Al mask, n + Irradiation of electrons, protons, or neutrons within the source reduces mobility and thus results in the formation of defects that increase the source resistance R S , and for example, the resistivity can be changed to be in the range of 10 -2 ~10 7 Ωcm in at least one current-limiting region.

[0017] Therefore, in the proposed at least one current-limiting region, the current flows through a path with a higher resistivity and / or a narrower path. This effect increases the value of the source resistance R S . R SIncreasing the value of the saturation current I during a short circuit, or SC for short, will increase SAT The decrease changes. The depth d and length L of the irradiation region are, during conduction under nominal conditions, i.e., R DS,on It is possible to design the system appropriately to achieve the desired effect on the SC current while ignoring its effect on the total resistance between the source and drain in the on state, also known as the source-drain ratio.

[0018] According to at least one embodiment, the semiconductor device is a power device. This means, for example, that the semiconductor device is configured for a maximum current through a well region of at least 10A or at least 50A. Optionally, the maximum current is at most 500A or at most 1.5kA. Alternatively or additionally, the semiconductor device is configured for a maximum voltage of at least 0.6kV or at least 1.2kV between the source and drain or between the emitter and collector. Optionally, the maximum voltage may be at most 6.5kV.

[0019] According to at least one embodiment, when viewed from above the semiconductor body, the gate electrode and the first electrode overlap the first region. Herein, and hereafter, “top view” may refer to a view perpendicular to the top surface of the semiconductor body to which the first electrode is attached and to which the first region is located.

[0020] According to at least one embodiment, at least one current-limiting region is located away from the gate electrode and / or the first electrode when viewed from an upward viewpoint of the semiconductor body. For example, at least one current-limiting region is located away from both the gate electrode and the first electrode when viewed from an upward viewpoint.

[0021] According to at least one embodiment, at least one current limiting region is located within an allocated first region, for example, within a manufacturing tolerance, mirror-symmetrically. That is, viewed from an overhead view of the semiconductor body, the first region, together with the at least one current limiting region, has, for example, an axis of mirror symmetry with respect to the shapes of the first region and the at least one current limiting region. The axis of mirror symmetry may extend parallel to the gate electrode and / or the first electrode, and / or may be located between the gate electrode and the first electrode, as viewed from an overhead view. Otherwise, a non-mirror-symmetric arrangement of at least one current limiting region within an allocated first region is also possible, as viewed from an overhead view.

[0022] According to at least one embodiment, as viewed from an overhead view of the semiconductor body, the first region extends entirely between at least one current-limiting region and the first electrode, and between at least one current-limiting region and the gate electrode. In other words, a portion of the first region exists between at least one current-limiting region and each electrode, for example, on the upper surface of the semiconductor body, as viewed from an overhead view of the semiconductor body.

[0023] Alternatively, viewed from above the semiconductor body, at least one current-limiting region may be partially covered by the gate electrode, or at least one current-limiting region may be in contact with the gate electrode.

[0024] According to at least one embodiment, at least one current-limiting region is located between the first electrode and the gate electrode. For example, all of the at least one current-limiting region is located between the electrodes.

[0025] According to at least one embodiment, as viewed from a cross-section of the semiconductor body, the first region extends all around at least one current-limiting region in the direction toward the well region. This can mean that the first region is incorporated into the well region, and / or at least one current-limiting region is incorporated into the first region. For example, as viewed from a cross-section, in this case, a portion of the first region is located all around at least one current-limiting region, so that there are no straight connecting lines within the semiconductor body from at least one current-limiting region to the well region without crossing the first region.

[0026] The term “cross-section of the semiconductor body” can refer to a cross-section that passes through a first region, or through a current-limiting region, or through at least one of the current-limiting regions, through the gate electrode, and, for example, in a direction perpendicular to the top surface of the semiconductor body and / or perpendicular to the direction of the main range of the gate electrode.

[0027] According to at least one embodiment, as viewed from a cross-section of the semiconductor body, at least one current-limiting region is completely incorporated into a first region. For example, as viewed from a cross-section of the semiconductor body, the first region is entirely around at least one current-limiting region.

[0028] According to at least one embodiment, for example, when viewed from a cross-section of the semiconductor body, at least one current-limiting region completely penetrates the first region. Thus, the at least one current-limiting region can be the same depth as the first region or deeper than the first region. In other words, the at least one current-limiting region penetrates the first region in a direction perpendicular to the top surface of the semiconductor body. The at least one current-limiting region may begin directly on the top surface, or if not, may begin away from the top surface within the first region.

[0029] According to at least one embodiment, the volume of at least one current-limiting region is at least 5%, at least 10%, at least 20%, at least 40%, or at least 60% of the total volume of the associated first region. Alternatively or additionally, the percentage is at most 95%, at most 85%, or at most 75%. For example, the percentage is between 40% and 85%.

[0030] For example, due to at least one current-limiting region, the electrical resistance through the first region between the first electrode and the channel region increases by at least 1.1 times, at least 1.5 times, at least 2 times, or at least 5 times. Alternatively or additionally, the multiple is at most 100, at most 25, at most 15, at most 10, or at most 5. For example, the multiple is between 2 and 10. The electrical resistance through the first region may refer to the normal operating current for which the semiconductor device is designed when it is on. These multiples refer to a comparison with a device that does not have at least one current-limiting region in the first region, but otherwise has the same structure within manufacturing tolerances.

[0031] According to at least one embodiment, the conductivity of at least one current-limiting region is at least 0.1%, or at least 1%, or at least 5% of the conductivity of the remaining region of the first region. Alternatively or additionally, the values ​​are at most 95%, or at most 80%, or at most 20%, or at most 10%.

[0032] According to at least one embodiment, the crystal lattice within at least one current-limiting region has at least twice, at least five times, or at least ten times more defects than the rest of the first region. Alternatively or additionally, the multiple is at most ten 3It is either 100 or at most 10. Therefore, in at least one current-limiting region, there is a higher defect density than in the rest of the first region, which is achieved by irradiating at least one current-limiting region.

[0033] For example, at least one current-limiting region reduces the effective cross-sectional area of ​​the current flow within the first region from the first electrode to the well region adjacent to the gate insulating layer, i.e., the channel region, by at least 1.5 times, at least 2 times, or at least 5 times. Alternatively or additionally, the multiple is at most 100, at most 15, at most 10, at most 5, or at most 2. For example, the multiple is between 2 and 10.

[0034] Effective cross-sectional area A of the current flow eff This can be the minimum value of the local electrical resistance r integrated over a cross-sectional region A passing through a first region perpendicular to the principal direction of the current.

[0035]

number

[0036] According to at least one embodiment, at least one current-limiting region is terminated in alignment with the first region. Thus, the upper surface can be flat across the first region and the at least one current-limiting region, and both the at least one current-limiting region and the remaining region of the first region are terminated at the upper surface. In other words, the first region and the current-limiting region form a flat surface and are terminated in alignment with each other.

[0037] According to at least one embodiment, the semiconductor body further comprises a drift region. The drift region is of a first conductivity type and has a lower maximum doping concentration compared to, for example, the first region and the well region.

[0038] According to at least one embodiment, the semiconductor body further comprises a second region, for example, the second region being a drain region or a collector region. In the case of a drain region, the second region is also of the first conductivity type, but for example, the maximum doping concentration is higher than that of the drift region. In the case of a collector region, the second region is of the second conductivity type.

[0039] According to at least one embodiment, the drift region is located between the well region and the second region. Thus, the first region is separated from the second region by the well region.

[0040] According to at least one embodiment, the semiconductor device further comprises a second electrode, which is, for example, a collector electrode or a drain electrode. The second electrode may be located on the side far from the drift region of the second region and / or far from the first region.

[0041] According to at least one embodiment, when viewed from an overhead perspective of the semiconductor body, the gate electrode and the first electrode each extend along a straight line. If there are multiple first electrodes and / or gate electrodes, there can be multiple straight lines along which the first electrodes and / or gate electrodes extend.

[0042] According to at least one embodiment, the first region extends parallel to the gate electrode and / or the first electrode. Thus, the semiconductor device may have a stripe design that includes multiple straight stripes of the gate electrode and / or the first electrode.

[0043] According to at least one embodiment, viewed from an overhead view of the semiconductor body, the gate electrode and / or first electrode each comprises a plurality of subsections. For example, the subsections correspond to unit cells. The unit cells can be arranged, for example, in a regular two-dimensional grid. The semiconductor body can extend continuously across all unit cells and comprises a plurality of first regions arranged accordingly. Thus, the semiconductor device can be a cell design comprising a plurality of cells, each having a first electrode, a corresponding gate electrode, and a corresponding first region having at least one current-limiting region.

[0044] According to at least one embodiment, the semiconductor device is planar in design. That is, the gate insulating layer and the gate electrode are attached to a planar section of the upper surface of the semiconductor body. A first region and at least one current limiting region may be located on the upper surface.

[0045] According to at least one embodiment, the semiconductor device is a trench design. Thus, the gate insulating layer and the gate electrode are located partially or completely in a trench within the semiconductor body. For example, the depth of the trench begins from the top surface of the semiconductor body and exceeds the depth of the well region. In this case, the first region and at least one current-limiting region may be located on the top surface.

[0046] According to at least one embodiment, there is exactly one current-limiting region within the first region. In the case of multiple first regions, there can be a one-to-one assignment between the first regions and the current-limiting regions.

[0047] Otherwise, there are multiple current-limiting regions in the first region. If there are multiple first regions, there can be multiple current-limiting regions for each first region. The current-limiting regions of one or exactly one of the first regions are separated from each other when viewed from an overhead perspective of the semiconductor body.

[0048] Viewed from above the semiconductor body, each current-limiting region or one of the current-limiting regions can be completely surrounded by the first region to which it is assigned.

[0049] According to at least one embodiment, the current limiting regions are arranged along one stripe or along multiple stripes. Furthermore, optionally, the current limiting regions may be arranged along one column or along multiple columns when viewed from above, with the stripes and columns oriented perpendicular to each other. In the case of multiple first regions, this can be applied to each of the first regions, with each of the first regions being assigned to multiple current limiting regions.

[0050] According to at least one embodiment, when viewed from above the semiconductor body, the current limiting region is shaped as at least one of a triangle, square, rectangle, hexagon, or circle. When viewed from above, all current limiting regions may have the same shape and / or region content. Otherwise, and for each first region, current limiting regions of different shapes and / or sizes may be combined with each other.

[0051] A method for manufacturing a semiconductor device is further provided. The method manufactures a semiconductor device as shown in connection with at least one of the embodiments described above. Thus, the characteristics of the semiconductor device are also disclosed in relation to the method, and vice versa.

[0052] In at least one embodiment, the manufacturing method is for manufacturing a semiconductor device, and the method is, for example, in the order described. - To provide a semiconductor device, -Forming a first region and a well region in the semiconductor body, -Attaching a mask layer to the semiconductor body, - Irradiating at least one portion of a first region defined by a mask layer with at least one of X-rays, electrons, protons, neutrons, or ions, such that at least one current-limiting region is created in the irradiated portion. - The gate insulating layer, gate electrode, and first electrode are attached to the semiconductor body. Includes.

[0053] The dose for irradiating at least one portion can be used as a design parameter to adjust the resistance of at least one current-limiting region, and thus the first region, to achieve the desired effect. For example, in the case of electron irradiation, the dose is 10 10 cm -2 ~10 17 cm -2 and / or may range up to 10% of the maximum doping concentration in the first region. In the case of proton irradiation, for example, the dose may be 10 8 cm -2 ~10 14 cm -2 It is possible.

[0054] The shape of at least one current-limiting region is defined by the mask layer when viewed from an upper viewpoint on the top surface, but the depth of at least one current-limiting region depends on the thickness of the mask layer, as well as the energy used for irradiation, for example, from a minimum of 116 keV for electrons, or from a minimum of 200 keV for protons and neutrons. It is possible to have only one type of irradiation, for example, only electron irradiation, or different types of irradiation can be combined with each other.

[0055] According to at least one embodiment, the method further includes forming one or more plug regions within a semiconductor body. At least one plug region is of a second conductivity type and has a maximum doping concentration higher than the maximum doping concentration of the well region. At least one plug region is for, for example, to electrically contact the well region by a first electrode.

[0056] According to at least one embodiment, the first region extends deeper into the semiconductor body than at least one plug region.

[0057] According to at least one embodiment, creating the first region involves two different doping steps, resulting in a stepped doping profile of the first region when viewed in cross-section. That is, the first region can widen towards the top surface.

[0058] The semiconductor devices and methods described herein are described in more detail below by exemplary embodiments with reference to the drawings. The same elements in the individual figures are indicated by the same reference numerals. However, the relationships between elements are not shown to scale, and individual elements may be shown larger than they actually are to aid understanding. [Brief explanation of the drawing]

[0059] [Figure 1] This is a schematic perspective cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 2] This is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 3] This is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 4] This is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 5] This is a schematic perspective cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 6] This is a schematic perspective cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 7] This is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 8] This is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 9]This is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 10] This is a schematic diagram of the simulated electrical characteristics of an exemplary embodiment of the semiconductor device described herein, compared to a corresponding semiconductor device that does not have at least one current limiting region. [Figure 11] This is a schematic diagram of the simulated electrical characteristics of an exemplary embodiment of the semiconductor device described herein, compared to a corresponding semiconductor device that does not have at least one current limiting region. [Figure 12] This is a schematic block diagram of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. [Figure 13] This is a schematic cross-sectional view of a method step of an exemplary embodiment of the method described herein. [Figure 14] This is a schematic top view of an exemplary embodiment of a semiconductor device described herein. [Figure 15] This is a schematic top view of an exemplary embodiment of a semiconductor device described herein. [Modes for carrying out the invention]

[0060] Figure 1 shows an exemplary embodiment of semiconductor device 1. Semiconductor device 1 comprises a semiconductor body 2, which is made of, for example, SiC. The semiconductor body 2 has a first region 21, a well region 22, and a drift region 23. Furthermore, there is a plug region 25 for electrically contacting the well region 22.

[0061] Furthermore, the semiconductor device 1 includes a gate electrode 33 separated from the semiconductor body 2 by a gate insulating layer 4. Additionally, there is a first electrode 31 that electrically contacts a first region 21 and a plug region 25. The gate insulating layer 4 and the first electrode 31 are located on the upper surface 20 of the semiconductor body 2, which is planar. The gate electrode 33 and the first electrode 31 may each extend along a straight line perpendicular to the cross-section shown in Figure 1. The gate insulating layer 4 may be made of a metal oxide, semiconductor oxide, metal nitride, and / or semiconductor nitride. For example, the gate insulating layer 4 may include one or more of the following materials: SiO2, Si3N4, Al2O3, Y2O3, ZrO2, HfO2, La2O3, Ta2O5, and TiO2.

[0062] For example, the first region 21 and the drift region 23 are n-doped, and the well region 22 and the plug region 25 are p-doped. If the semiconductor device 1 is an insulated-gate bipolar transistor IGBT or a reverse-conducting insulated-gate bipolar transistor RC-IGBT, the first region 21 is the emitter region and the first electrode 31 is the emitter electrode. If the semiconductor device 1 is a junction-gate field-effect transistor JFET, a metal-insulator-semiconductor field-effect transistor MISFET, or a metal-oxide-semiconductor field-effect transistor MOSFET, the first region 21 is the source region and the first electrode 31 is the source electrode.

[0063] A current-limiting region 5 exists within the first region 21. The current-limiting region 5 is made of the same material as the rest of the first region, for example, SiC. However, due to the irradiation of a portion of the first region 21 that constitutes the current-limiting region 5, the conductivity of the current-limiting region 5 is reduced compared to the rest of the first region 21.

[0064] Thus, Figure 1 illustrates the basic concept of the proposed semiconductor device 1. After source activation, a region, namely at least one current-limiting region 5, is irradiated. Its width is defined by the mask design, but the depth of this region 5 depends on the thickness of the mask and the energy used for irradiation. During irradiation, for example, several point defects are formed. These defects, compared to G. Alfieri et al.'s "Annealing behavior between room temperature and 2000℃ of deep level defects in electron-irradiated n-type 4H silicon carbide," Journal of Applied Physics 98, 043518 (2005), doi:10.1063 / 1.2009816, and Alfieri et al.'s "Isothermal Annealing Study of the EH1 and EH3 Levels in n-type 4H-SiC," J.Phys.:Condens.Matter 32, 4657'3 (2020), doi:10.1088 / 1361-648X / abaeaf, can form electrically active levels within the band gap, such as EH1, Z1 / 2, EH3, EH4, EH5, and EH6 / 7. These levels trap charge carriers and reduce their mobility. The lower the mobility, the lower the source resistance R. S The value will increase.

[0065] The current limiting region 5 extends along a straight line parallel to the gate electrode 33 and the first electrode 31. The current limiting region 5 is located directly on the top surface 20, like the first region 21. The depth of the first region 21 into the semiconductor body 2 exceeds the depth of the current limiting region 5 into the semiconductor body 2, starting from the top surface 20. Viewed in cross-section, the first region 21 exists all around the current limiting region 5, toward the well region 22 into which the first region 21 is incorporated.

[0066] For example, at least one current-limiting region 5 is arranged mirror-symmetrically within the first region 21 when viewed from an overhead perspective and from a cross-sectional view. For example, when viewed from an overhead perspective of the top surface 20, the current-limiting region 5 is arranged symmetrically within the first region 21 and between electrodes 31 and 33. Thus, there can be a line M that is mirror-symmetric with respect to the current-limiting region 5 and the first region 21.

[0067] At least one current limiting region 5 may have different shapes and depths and may be uniform or non-uniform along the direction perpendicular to the cross-section in Figure 1; see also Figures 2 to 9 below.

[0068] In the proposed current-limiting region 5, the current flows through a path with higher resistivity and / or a narrower path. This effect is due to the source resistance R S Or it results in a corresponding increase in the value of the emitter resistor. S Increasing the value of will increase the saturation current I during a short circuit. SAT The decrease changes. The depth d and length L of the current limiting region 5 along the cross-section of Figure 1 parallel to the upper surface 20 is, for example, total R during conduction under nominal conditions. DS,on It is possible to design the system appropriately to achieve the desired effect on short-circuit current while continuing to ignore its impact on the system.

[0069] For example, the effective channel contact path length Leff of the carrier is the minimum local resistance r along all possible paths S having incremental elements s in a first region 21 that includes at least one current limiting region 5.

[0070]

number

[0071] The semiconductor device 1 in Figure 1 is a planar design. In contrast, the semiconductor device 1 in Figure 2 is a trench design. Therefore, the gate electrode 33 and the gate insulating layer 4 are located at least partially within a trench into the semiconductor body 2. Accordingly, the top surface 20 is not planar, as it is penetrated by the trench, in contrast to the case of Figure 1. The gate electrode 33, for example, starts from the top surface 20 and reaches deeper into the semiconductor body 2 than the well region 22.

[0072] Furthermore, Figure 2 shows that multiple first regions 21, and therefore current-limiting regions 5, are arranged symmetrically with respect to, for example, the gate electrode 33. The multiple units shown in Figure 2 can be adjacent to one another along a direction parallel to the top surface 20, and as a result, multiple stripes of the gate electrode 33 and the first electrodes 31 can exist that extend perpendicular to the projection plane of Figure 2 and parallel to each other.

[0073] This symmetrical arrangement in Figure 2, see also Figure 14, and / or the trench design in Figure 2 can be applied similarly to all other embodiments.

[0074] In Figure 2, one current limiting region 5 for each first region 21 is a trough with the same design as in Figure 1, i.e., a rectangular parallelepiped shape. According to Figure 2, the trough has sharp edges and corners, while according to Figure 1, the trough has rounded edges and corners. Both designs are possible in all embodiments, depending on the manufacturing process of at least one current limiting region 5.

[0075] Furthermore, Figure 2 shows the presence of a second electrode 32, and that the semiconductor body 2 comprises a second region 24. For example, the second region 24 is a substrate on which other regions 23, 22, 21, 25 are formed by growth and / or doping, such as ion implantation. In the case of an IGBT or RC-IGBT, the second electrode 32 is the collector electrode, and the second region is a collector region of the same doping type as the well region. In the case of a MOSFET or MISFET, the second electrode 32 is the drain electrode, and the second region is a drain region of the same doping type as the first region. The same applies to all other embodiments of the semiconductor device 1.

[0076] Furthermore, as shown in Figure 2, the plug region 25 starts from the top surface 20 and extends deeper into the semiconductor body 2 than the first region 21. Otherwise, referring to Figure 1, the plug region 25 may have the same depth as the first region 21, or it may be shallower or deeper than the first region 21. In all embodiments, both possibilities may apply.

[0077] Similar to Figure 1, in Figure 2, at least one current-limiting region 5 is located away from the first electrode 31, the gate electrode 33, and the gate insulating layer 4 for each first region 21.

[0078] For example, the maximum doping concentration in the first region 21, the second region 24, and at least one plug region 25 is at least 1 × 10⁻⁶ 18 cm -3 Or at least 5 x 10 18 cm -3 Or at least 1 × 10 19 cm -3 and / or at most 5 × 10 20 cm -3 Or at most 2 x 10 20 cm -3 Or at most 1 x 10 20 cm -3 Furthermore, the maximum doping concentration in the well region 22, and therefore in the channel region adjacent to the gate insulating layer 4, is at least 5 × 10⁻⁶. 16cm -3 Or at least 1 × 10 17 cm -3 and / or at most 5 × 10 19 cm -3 Or at most 5 x 10 18 cm -3 Depending on the voltage class of semiconductor device 1, the maximum doping concentration in the drift region 23 may be at least 1 × 10⁻⁶. 11 cm -3 Or at least 1 × 10 12 cm -3 Or at least 1 × 10 13 cm -3 and / or at most 1 × 10 17 cm -3 Or at most 5 x 10 16 cm -3 Or at most 1 x 10 16 cm -3 This is possible. For example, the thickness of the gate insulating layer 4 is 10 nm to 250 nm or 80 nm to 150 nm. These parameters can be applied individually or collectively to all other embodiments.

[0079] Otherwise, the same thing may apply to Figure 2 as it does to Figure 1, and vice versa.

[0080] In Figures 3 and 4, as in Figure 1, there is one current-limiting region 5 for each first region 21. The current-limiting regions 5 can be arranged mirror-symmetrically within the first region 25, with the axis of mirror symmetry extending perpendicularly to the top surface 20.

[0081] In contrast to what is shown in Figure 1, according to Figures 3 and 4, the current limiting region 5 extends beyond the gate insulating layer 4 and the gate electrode 33. Such an arrangement is also possible in all other exemplary embodiments. Otherwise, in contrast to what is shown in Figures 3 and 4, the current limiting region 5 may be located non-mirror-symmetrically within the first region 21, and as a result, the current limiting region 5 may terminate away from the gate insulating layer 4 and therefore not extend beyond the gate electrode 33. This is also possible in all other embodiments.

[0082] As shown in Figure 3, the current limiting region 5 is formed as a shallow trough within the first region 21, which also forms a single trough. The depth d of the current limiting region 5 reaches, for example, 10% to 90% or 40% to 80% of the depth D of the first region 21. The first region 21 and the plug region 25 may have the same depth, for example, within manufacturing tolerances. For example, the depth D of the first region 21 is at least 0.1 μm and / or at most 2 μm.

[0083] According to Figure 4, the current limiting region 5 is formed as a deep trough within the first region 21, which is formed as two troughs, one of which is above the other, and the trough adjacent to the top surface 20 has a larger range parallel to the projection plane of Figure 4. In this case as well, the depth d of the current limiting region 5 can reach 10% to 90% or 40% to 80% of the total depth D of the first region 21. For designs with two stacked troughs, the first region 21 can extend deeper into the semiconductor body 2 than the plug region 25. The plug region 25 can be the same depth as the trough of the first region 21 adjacent to the top surface 20, for example, within manufacturing tolerances. For example, the depth D of the first region 21 is at least 2 μm and / or at most 4 μm.

[0084] For example, the trough adjacent to the top surface 20 is first formed by corresponding doping, and then doping for the troughs away from the top surface 20 is provided, for example, by using different energies in the ion implantation process. Thus, the trough in Figure 4 has a stepped design when viewed in cross-section. Otherwise, the configuration in Figure 4 also allows for deep troughs having a rectangular shape with rounded corners, as depicted in Figure 3, for example.

[0085] Both designs having a shallow or deep first region 21, as shown in Figures 3 and 4, are also possible in all other embodiments.

[0086] For example, the length L of the current limiting region 5 is 10% to 90%, 40% to 80%, or 50% to 70% of the width B of the first region 21. This is also possible in all other embodiments.

[0087] Otherwise, the same may be true for Figures 3 and 4 with respect to Figures 1 and 2, and vice versa.

[0088] As shown in Figures 5 to 7, there are multiple current limiting regions 5 for each first region 21. The same parameters d, D, B, and L described above for the case of a single current limiting region 5 for each first region 21 also apply to the case of multiple current limiting regions 5 for each first region 21, where L corresponds to the total width of each respective current limiting region 5; see, for example, Figure 6. Multiple current limiting regions 5 provide more design parameters for achieving an optimized first region.

[0089] For one current limiting region 5 perpendicular to the gate electrode 33 and / or the first electrode 31, referring to Figure 5, the total width L is the same as the width W of the individual insulating current limiting regions 5 shown in Figure 4.

[0090] However, as shown in Figure 5, there is a stripe of current-limiting region 5 that extends parallel to electrodes 31 and 33. Viewed from above, the current-limiting region 5 is rectangular or square in shape and optionally has rounded corners, each having a width W and a length range V. For example, V is 0.5L to 100L, or 0.5L to 10L, or 0.7L to 5L.

[0091] For example, the distance Zs between adjacent current-limiting regions 5 along a stripe is 10% to 75% or 10% to 40% of the width W and / or length range V. Individual current-limiting regions 5 within a stripe can be equidistant from each other, or at different distances from each other, as shown in Figure 5. These embodiments may also apply individually or collectively to all other embodiments.

[0092] In addition to those illustrated, the current limiting region 5 does not need to be square in shape when viewed from above, but may be rectangular, hexagonal, a regular or irregular polygon, or circular in shape when viewed from above. The same applies to all other embodiments.

[0093] According to Figures 5 to 7, all current limiting regions 5 have the same shape in each first region 21. This is not necessarily required; that is, different shaped current limiting regions 5 may be combined within a single first region 21.

[0094] There can be N stripes of current-limiting regions 5 between electrodes 31 and 33, where N is a natural number greater than or equal to 2. For example, N is at most 10 or at most 4. In the example in Figure 6, N is 2. For example, 0.1B / N ≤ W ≤ 0.99B / N or 0.4B / N ≤ W ≤ 0.95B / N or 0.7B / N ≤ W ≤ 0.90B / N. Alternatively or additional, for example, the distance Zt between adjacent current-limiting regions 5 in the transverse direction perpendicular to the stripe is 10% to 75% or 10% to 40% of the length range V. Alternatively or additional, for example, 0.1B / N ≤ V ≤ 100B / N or 0.4B / N ≤ V ≤ 10B / N or 0.7B / N ≤ V ≤ 5B / N. The current-limiting regions 5 can be arranged at equidistant distances parallel and perpendicular to electrodes 31 and 33.

[0095] As shown in Figure 6, all N stripes have the same number of current-limiting regions 5, and as a result, in each case, K current-limiting regions 5 are adjacent to each other in a direction parallel to the stripes. As a result, a regular array of N × K current-limiting regions 5 is formed, and all current-limiting regions 5 have the same shape.

[0096] However, this is not mandatory. That is, current limiting regions 5 of different shapes and sizes can be combined with each other, and there can be several different K current limiting regions 5 in each stripe, and / or several different N current limiting regions 5 in a direction parallel to the width L. For example, there may be current limiting regions 5 of different widths W, and as a result, as an example, rows parallel to the direction along width L having a single wide current limiting region 5 may alternate with rows having multiple narrower current limiting regions 5.

[0097] In Figure 7, it is shown that N is 3. Optionally, the stripe furthest from the first electrode 31 extends beyond the gate insulating layer 4. However, apart from what is shown in Figure 7, all stripes may be far from the gate electrode 33, for example, when viewed from an overhead viewpoint of the top surface 20.

[0098] Each stripe in Figure 7 can consist of multiple current-limiting regions 5, as in Figures 5 and 6, or each stripe may have only a single current-limiting region 5, as in Figures 1 to 4. The same applies to all other embodiments.

[0099] The current limiting regions 5 in Figures 5 to 7 are shallower in design compared, for example, to Figure 3 above. It is also possible that all or some of the current limiting regions 5 for each first region 21 are deeper in design, as depicted in relation to Figure 4.

[0100] Otherwise, the same thing may apply to Figures 5-7 with respect to Figures 1-4, and vice versa.

[0101] In semiconductor device 1 shown in Figure 8, the current limiting region 5 completely penetrates the first region 21 from the top surface 20 to the well region 22. Therefore, all current from the first electrode 31 to the channel region of the well region 22 adjacent to the gate insulating layer 4 can only flow through the current limiting region 5, which has lower conductivity, and any small currents that may occur around the current limiting region 5 passing through the portion of the well region 22 on the side of the current limiting region 5 away from the top surface 20 are negligible.

[0102] The resistance of the first region 21 can be adjusted with particular precision by the length parallel to the projection plane in Figure 8 and by the conductivity of the current limiting region 5.

[0103] Otherwise, the same may be true for Figure 8 as well as for Figures 1-7, and vice versa.

[0104] In semiconductor device 1 of Figure 9, the current limiting region 5 is completely integrated into the remainder of the first region 21. That is, the first region 21 is entirely around the current limiting region 5. Therefore, it is possible for the current limiting region 5 to extend beyond the gate electrode 33. In addition to what is illustrated, the current limiting region 5 may not extend below the gate electrode 33.

[0105] For example, the layer thickness of the first region 21 around the current limiting region 5 is at least 5% or at least 10% and / or at most 30% or at most 45% of the total thickness of the first region 21 together with the incorporated current limiting region 5.

[0106] The design in Figure 9 is also possible with multiple current limiting regions 5 for each first region 21, as can be seen by comparing, for example, Figures 5 to 7, or with deep current limiting regions 5, as can be seen by comparing, for example, Figure 4.

[0107] Otherwise, the same thing may apply to Figure 9 as to Figures 1-8, and vice versa.

[0108] Figures 10 and 11 show the gate-source voltage V of semiconductor device 1 in Figure 8 compared to a corresponding reference MOSFET design 9 without a current-limiting region. GS Simulated isothermal power J at 15V and 300K temperature D V DS , as well as the drain-source voltage V DS =600V and V GS,Swing The short-circuit waveform for heating at -5V / +15V is shown. In semiconductor device 1 corresponding to Figure 8, the quotient d / D between the depth d of the current limiting region 5 and the depth D of the first region 21 is 1. The quotient L / B between the length L of the current limiting region 5 and the width B of the first region 21 is 0.5.

[0109] Maximum saturation current I during short circuit SAT,peak The resulting reduction is due to the resistance R in the ON state. DS,on Note that this is greater than the increase in . The energy the device receives during a short circuit is I SAT Since it is directly related to the maximum value, the semiconductor device 1 described herein improves short-circuit withstand capability without significantly affecting conduction loss.

[0110] Figure 12 shows a method for manufacturing a semiconductor device 1. In method step S1, a semiconductor body 2 is provided. For example, the semiconductor body 2 provides a drift region 23. Then, in method step S2, a first region 21 and a well region 22 are formed in the semiconductor body 2 and the plug region 25.

[0111] Next, in step S3, at least one mask layer is provided on the upper surface 20 of the semiconductor body 2. Furthermore, in step S4, at least one portion of the first region 21 defined by the mask layer is irradiated with at least one of X-rays, electrons, protons, neutrons, or ions, and as a result, at least one current-limiting region 5 is created in at least one irradiated portion. Then, in step S5, the gate insulating layer 4, the gate electrode 33, and the first electrode 31 are attached to the semiconductor body 2, and optionally to the second electrode 32 as well.

[0112] In another process not shown, the mask layer may be partially or completely removed, and semiconductor device 1 may be completed.

[0113] Steps S1 to S5 of the method do not necessarily have to be performed in the order described. Figure 13 illustrates step S5 in more detail. As can be seen from Figure 13, in step S5, the electrodes have not yet been attached, which is optional. The gate insulating layer 4 is represented by a dashed line, indicating that it can be attached immediately after the irradiation step, as symbolized in Figure 13.

[0114] Therefore, as shown in Figure 13, for example, a mask layer 6 made of silicon dioxide is attached to the top surface 20 and structured to represent at least one current-limiting region 5. In the region of at least one current-limiting region 5, radiation R can reach the first region 21 through the mask layer 6. In other parts of the semiconductor body 2, radiation R may not be able to reach the semiconductor body 2.

[0115] In contrast to what is shown in Figure 13, it is also possible to have an upper surface 20 in which the mask layer 6 is not completely absent in at least one current limiting region 5.

[0116] For example, radiation R consists of electrons, protons, or neutrons with energies exceeding approximately 0.1 MeV. Such irradiation can damage the crystal lattice of the material in the first region 21, potentially resulting in a large number of point defects. In addition to increasing the defect density, alternative or additional methods may be used to neutralize the doping in the first region 21, for example, by counter-doping, resulting in radiation R also being composed of ions.

[0117] Figure 14 shows an example of semiconductor device 1 in a top view. It can be seen that the stripes of the gate electrode 33 are located symmetrically, for example, between the two stripes of half of the first electrode 31, and therefore between the two stripes of the first region 21 having the current limiting region 5. The structure in Figure 14 corresponds to a unit cell that can be proliferated so that multiple unit cells can be arranged adjacent to one another.

[0118] This stripe design can also be applied to embodiments in Figures 1 and 3-9, and this type of symmetrical design is already shown in Figure 2.

[0119] Otherwise, the same may be true for Figure 14 as well as for Figures 1 through 13, and vice versa.

[0120] Furthermore, referring to Figure 15, the semiconductor device 1 may also be cellular in design when viewed from above, so that rectangular or square unit cells can be generated. For example, at the center of a unit cell, there is a first electrode 31 framed by a gate electrode 33. Such unit cells can be arranged two-dimensionally so that the semiconductor device 1 can have a large number of such unit cells.

[0121] Otherwise, the same thing may apply to Figure 15 with respect to Figure 14, and vice versa.

[0122] The components shown in the diagram are, unless otherwise specified, directly overlapping in the order specified illustratively. Components that are not in contact in the diagram are illustratively spaced apart from one another. Where lines are drawn parallel to each other, the corresponding surfaces may be oriented parallel to each other. Similarly, unless otherwise specified, the relative positions of the depicted components are accurately reproduced in the diagram.

[0123] The inventions described herein are not limited by the description based on exemplary embodiments. Rather, even if this feature or combination itself is not expressly specified in the claims or exemplary embodiments, the invention also encompasses any new features, and in particular any combination of features including any combination of features in the claims. [Explanation of symbols]

[0124] List of reference symbols 1. Semiconductor devices 2. Semiconductor body 20 Top surface of the semiconductor main unit 21. The first region (source region or emitter region) 22-well area 23. Drift Region 24. Second region (drain region or collector region) 25 Plug Area 31. First electrode (source electrode or emitter electrode) 32. Second electrode (drain electrode or collector electrode) 33 Potatoes 4 Gate Insulation Layer 5 Current limiting region 6 Mask Layers 9. Comparative Examples of Semiconductor Devices B Width of the first region d Depth of the current limiting region D. Depth of the first region E1 First example of a semiconductor device E2 First example of a semiconductor device E3 First example of a semiconductor device L is the length of the current limiting region. M is the line of mirror symmetry. R radiation S.. Method Step T is time in units of μs. J D A / cm 2 Current density within the drain region of a unit V DS Voltage between the drain and source electrodes in units of volts V Current limiting region length range W width of the isolation current limiting region Distance between current limiting regions along the Zs stripe Zt Distance between current limiting regions in the transverse direction

Claims

1. A semiconductor device (1) comprising a semiconductor body (2), a terminal electrode (33), and a first electrode (31), - The semiconductor body (2) comprises a first region (21) which is a source region or an emitter region, and a well region (22) located adjacent to the first region (21), wherein the first region (21) is a first conductivity type, and the well region (22) is a different second conductivity type. - The well region (22) is adjacent to the gate electrode (33) and is separated from the gate electrode (33) by the gate insulating layer (4), - The first region (21) is in electrical contact with the first electrode (31), which is the source electrode or emitter electrode. - The first region (21) contains at least one current limiting region (5), - The at least one current limiting region (5) is a sub-region of the first region (21) where conductivity is reduced. The gate insulating layer (41) and the gate electrode (33) are planarly designed so that they are attached to a planar section of the upper surface (20) of the semiconductor body (2), and the first region (21) is located on the upper surface (20). Here, Viewed from a cross-section of the semiconductor body (2) passing through the first region (21) and the gate electrode (33), the first region (21) extends around the at least one current limiting region (5) in a direction toward the well region (22), and as a result, the first region (21) is incorporated into the well region (22), and the at least one current limiting region (5) is incorporated into the first region (21), or The at least one current limiting region (5) is completely incorporated into the first region (21), and as a result, when viewed from a cross-section of the semiconductor body (2), the first region (21) is entirely around the at least one current limiting region (5). The conductivity of the at least one current limiting region (5) is 5% to 90% of the conductivity of the remaining region of the first region (21). The crystal lattice within the at least one current-limiting region (5) has at least twice as many defects as the remaining region of the first region (21). Semiconductor device (1).

2. A semiconductor device (1) comprising a semiconductor body (2), a gate electrode (33), and a first electrode (31), - The semiconductor body (2) comprises a first region (21) which is a source region or an emitter region, and a well region (22) located adjacent to the first region (21), wherein the first region (21) is a first conductivity type, and the well region (22) is a different second conductivity type. - The well region (22) is adjacent to the gate electrode (33) and is separated from the gate electrode (33) by the gate insulating layer (4), - The first region (21) is in electrical contact with the first electrode (31), which is the source electrode or emitter electrode. - The first region (21) contains at least one current limiting region (5), - The at least one current limiting region (5) is a sub-region of the first region (21) where conductivity is reduced. The gate insulating layer (41) and the gate electrode (33) are planarly designed so that they are attached to a planar section of the upper surface (20) of the semiconductor body (2), and the first region (21) is located on the upper surface (20). Here, Viewed from a cross-section of the semiconductor body (2) passing through the first region (21) and the gate electrode (33), the first region (21) extends around the at least one current limiting region (5) in a direction toward the well region (22), and as a result, the first region (21) is incorporated into the well region (22), and the at least one current limiting region (5) is incorporated into the first region (21), or The at least one current limiting region (5) is completely incorporated into the first region (21), and as a result, when viewed from a cross-section of the semiconductor body (2), the first region (21) is entirely around the at least one current limiting region (5). Multiple current limiting regions (5) exist within the first region (21), and the current limiting regions (5) are spaced apart from each other when viewed from above the semiconductor body (2). Semiconductor device (1).

3. Viewed from above the semiconductor body (2), the gate electrode (33) and the first electrode (31) overlap with the first region (21), and the at least one current limiting region (5) is separated from the gate electrode (33) and the first electrode (31). The semiconductor device (1) according to claim 1 or 2.

4. Viewed from above the semiconductor body (2), the first region (21) extends completely between the at least one current limiting region (5) and the first electrode (31), and between the at least one current limiting region (5) and the gate electrode (33), and the at least one current limiting region (5) is located between the first electrode (31) and the gate electrode (33). The semiconductor device (1) according to claim 1 or 2.

5. The at least one current limiting region (5) is completely incorporated into the first region (21), and as a result, when viewed from a cross-section of the semiconductor body (2), the first region (21) is entirely around the at least one current limiting region (5). The semiconductor device (1) according to claim 1 or 2.

6. The volume of the at least one current limiting region (5) is at least 10% and at most 95% of the total volume of the first region (21). The semiconductor device (1) according to claim 1 or 2.

7. The semiconductor body (2) further comprises the first conductivity type drift region (23) and also comprises a second region (24) which is a drain region or a collector region. The drift region is located between the well region (22) and the second region (24). The semiconductor device (1) further comprises a second electrode (32) which is a collector electrode or a drain electrode, wherein the second electrode (32) is located on the side of the second region (24) away from the drift region (23), The semiconductor body (2) is made of SiC. The semiconductor device (1) according to claim 1 or 2.

8. Viewed from above the semiconductor body (2), the gate electrode (33) and the first electrode (31) each extend along a straight line, and the first region (21) extends parallel to the gate electrode (33) and the first electrode (31), or Viewed from above the semiconductor body (2), the gate electrode (33) and the first electrode (31) each comprise a plurality of subsections arranged along at least one alignment line, and the first region (21) extends between adjacent subsections of the gate electrode (33) and the first electrode (31). The semiconductor device (1) according to claim 1 or 2.

9. There is exactly one current limiting region (5) within the first region (21), The semiconductor device (1) according to claim 1.

10. A method for manufacturing a semiconductor device (1), The semiconductor device (1) comprises a semiconductor body (2), a gate electrode (33), and a first electrode (31). - The semiconductor body (2) comprises a first region (21) which is a source region or an emitter region, and a well region (22) located adjacent to the first region (21), wherein the first region (21) is a first conductivity type, and the well region (22) is a different second conductivity type. - The well region (22) is adjacent to the gate electrode (33) and is separated from the gate electrode (33) by the gate insulating layer (4), - The first region (21) is in electrical contact with the first electrode (31), which is the source electrode or emitter electrode. - The first region (21) contains at least one current limiting region (5), - The at least one current limiting region (5) is a sub-region of the first region (21) where conductivity is reduced. The gate insulating layer (41) and the gate electrode (33) are planarly designed so that they are attached to a planar section of the upper surface (20) of the semiconductor body (2), and the first region (21) is located on the upper surface (20). Here, Viewed from a cross-section of the semiconductor body (2) passing through the first region (21) and the gate electrode (33), the first region (21) extends around the at least one current limiting region (5) in a direction toward the well region (22), and as a result, the first region (21) is incorporated into the well region (22), and the at least one current limiting region (5) is incorporated into the first region (21), or The at least one current limiting region (5) is completely incorporated into the first region (21), and as a result, when viewed from a cross-section of the semiconductor body (2), the first region (21) is entirely around the at least one current limiting region (5). The aforementioned manufacturing method - To provide the semiconductor body (2), - Forming the first region (21) and the well region (22) within the semiconductor body (2), -Attaching a mask layer (6) to the semiconductor body (2), - Irradiating at least one irradiation portion of the first region (21) defined by the mask layer (6) with at least one of X-rays, electrons, protons, neutrons, or ions, such that at least one current-limiting region (5) is created within the at least one irradiation portion. - The gate insulating layer (41), the gate electrode (33), and the first electrode (31) are attached to the semiconductor body (2). A manufacturing method that includes this.

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