Semiconductor manufacturing platform and method using in-situ electrical bias

Abstract

To provide a semiconductor manufacturing platform and a method therefor using in-situ electrical bias.SOLUTION: A method for manufacturing a semiconductor device includes placing a semiconductor wafer in a first deposition chamber of a manufacturing platform, the semiconductor wafer including a first conductive layer, depositing a dielectric layer on the first conductive layer in the first deposition chamber, placing a semiconductor wafer in a second deposition chamber of the manufacturing platform, and depositing a second conductive layer on the dielectric layer in a second deposition chamber. The method further includes placing a semiconductor wafer in a processing chamber of an electric field annealer of the manufacturing platform, applying an electrical bias voltage across the dielectric layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential in the processing chamber, and annealing the semiconductor wafer while applying the electrical bias voltage.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims priority to U.S. Nonprovisional Patent Application No. 16 / 841,342, filed on April 6, 2020, and to U.S. Nonprovisional Patent Application No. 17 / 397,159, filed on August 9, 2021, both of which are incorporated herein by reference in their entirety.

[0002] The present invention generally relates to semiconductor processing systems and methods, and in specific embodiments, to a manufacturing platform and method for semiconductor processing using an in-situ electrical bias directly applied across the conductive layer of a wafer during wafer annealing. [Background technology]

[0003] Generally, semiconductor integrated circuits (ICs) are fabricated by sequentially depositing layers of material (e.g., dielectrics, metals, semiconductors, etc.) onto a semiconductor substrate and patterning the layers using photolithography and etching to form circuit components (e.g., transistors and capacitors) and interconnection elements (e.g., lines, contacts, and vias). Their minimum feature size has been regularly reduced with innovations such as immersion lithography and multi-patterning, and costs have been reduced by increasing packing density. Miniaturization of component footprints can be enhanced by increasing the output of components per unit area. For example, the drive current of a transistor per unit width, or the stored charge density of a capacitor, can be improved by using thinner gate dielectrics or thinner capacitor dielectrics, respectively.

[0004] However, the benefits of miniaturization come with some costs in process complexity, circuit speed, and standby power consumption, which may need to be addressed. The scaling trend of narrowing trace widths and reducing the spacing between conductors and electrodes involves performance trade-offs. Some of these trade-offs can be mitigated by using new materials. For example, increased IR drop and RC delay in interconnect systems due to higher trace and via resistance, as well as increased inter-traverse capacitance, can be mitigated by using metals such as ruthenium and cobalt (instead of tungsten and copper), as well as low-k intermetallic dielectrics (IMDs) such as fluorosilicate glass and carbon-doped oxides. Standby leakage may increase by reducing the source-drain spacing of transistors and making the gate dielectric or capacitor dielectric thinner. This problem can be mitigated by using high-k dielectric or ferroelectric dielectric materials.

[0005] Incorporating new materials requires further innovation to better utilize the benefits offered by their use in integrated circuits (ICs). [Overview of the project] [Means for solving the problem]

[0006] According to one embodiment of the present invention, a method for fabricating a semiconductor device includes: placing a semiconductor wafer in a first deposition chamber of a manufacturing platform, wherein the semiconductor wafer includes a first conductive layer; depositing a dielectric layer on the first conductive layer in the first deposition chamber; placing a semiconductor wafer in a second deposition chamber of a manufacturing platform; and depositing a second conductive layer on the dielectric layer in the second deposition chamber. The method further includes: placing a semiconductor wafer in a processing chamber of an electric field annealer of a manufacturing platform; applying an electrical bias voltage across the dielectric layers in the processing chamber by coupling the first conductive layer to a first potential and the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.

[0007] According to one embodiment of the present invention, a manufacturing platform for fabricating a semiconductor device includes a first deposition chamber configured for depositing a conductive layer on a semiconductor wafer and a second deposition chamber configured for depositing a dielectric layer on a semiconductor wafer. The manufacturing platform further includes a processing chamber for an electric field annealer, the processing chamber including a substrate holder configured for supporting a semiconductor wafer, a heating element configured for heating the semiconductor wafer supported by the substrate holder, a first electrode configured to be detachably attached to a first main surface of the semiconductor wafer, and a first wiring for coupling the first electrode to a first potential node.

[0008] For a more complete understanding of the present invention and its advantages, the following description is to be referred to here in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0009] [Figure 1A] This shows a cross-sectional view of the processing chamber of an electric field annealer according to one embodiment of the present invention. [Figure 1B] A cross-sectional view of the processing chamber of an electric field annealer according to an alternative embodiment of the present invention is shown. [Figure 2]A perspective view of a load rail of an electric field annealer according to an embodiment of the present invention is shown. [Figure 3] It is an enlarged perspective view of a detail of the perspective view shown in FIG. 2. [Figure 4] A perspective view of a load rail of an electric field annealer according to an embodiment of the present invention is shown. [Figure 5A] It is an enlarged perspective view of a detail of the perspective view shown in FIG. 2. [Figure 5B] It is an enlarged perspective view from a different orientation of a detail of the perspective view shown in FIG. 2. [Figure 6A] A cross-sectional view of various semiconductor wafers disposed in a processing chamber of an electric field annealer according to an embodiment of the present invention is shown. [Figure 6B] A cross-sectional view of various semiconductor wafers disposed in a processing chamber of an electric field annealer according to an embodiment of the present invention is shown. [Figure 6C] A cross-sectional view of various semiconductor wafers disposed in a processing chamber of an electric field annealer according to an embodiment of the present invention is shown. [Figure 7] A manufacturing platform for fabricating a semiconductor device according to an embodiment of the present invention is shown. [Figure 8A] An embodiment of the present invention shows that an electric bias voltage is applied across a dielectric layer during annealing of a semiconductor wafer. [Figure 8B] An embodiment of the present invention shows that an electric bias voltage is applied across a dielectric layer during annealing of a semiconductor wafer. [Figure 8C] An embodiment of the present invention shows that an electric bias voltage is applied across a dielectric layer during annealing of a semiconductor wafer.

Mode for Carrying Out the Invention

[0010] This disclosure describes apparatus and methods for processing a semiconductor wafer while an electrical bias voltage is applied between two conductive layers of the wafer during processing. The bias is applied via electrodes that are in direct electrical contact with the wafer and connected to a power supply located outside the processing chamber. Hereinafter, the annealing process performed concurrently with the electrical bias is referred to as field annealing, and the processing apparatus used to perform field annealing is referred to as a field annealer. In exemplary embodiments, during a post-deposition annealing (PDA) process step, an electrical bias is used to expose a dielectric layer in the wafer to a DC electric field (electric field) of a desired magnitude.

[0011] In some fabrication process flows, including the fabrication of ferroelectric dielectric-based electronic components such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and / or capacitors, the use of field-effect dyes (PDAs) may be advantageous, as described below. Process steps used to form ferroelectric layers may include depositing ferroelectric oxides, such as doped hafnium oxide, or doped hafnium zirconate, or perovskite oxides such as barium strontium titanate, or bismute. Numerous dopants, including La, Al, Si, Sr, Gd, and Y, have been shown to improve ferroelectric behavior by distorting the crystal structure. However, HfO2, or HfZrO2 xIn this case, multiple phases are possible. In these materials, post-deposition annealing (PDA) conditions play a crucial role in introducing the desired non-centrosymmetric orthorhombic phase with ferroelectric behavior. A PDA step called ferroelectric annealing (FEA) can convert a deposited hafnium oxide layer into a stable or metastable polycrystalline ferroelectric hafnium oxide layer. The manufacturing flow of ICs containing electronic components using hafnium oxide-based ferroelectric dielectrics typically includes an electrical cycling step, referred to herein as wake-up cycling, to obtain stable ferroelectric properties. In embodiments of this disclosure, ferroelectric MOSFETs (FE-FETs) and ferroelectric capacitors can be constructed using, for example, a ferroelectric dielectric, including, for example, hafnium oxide, where, during crystallization FEA, the dielectric is exposed to the applied DC electric field described above using apparatus and methods described in further detail below. The electric field FEA techniques used in exemplary embodiments can offer the advantage of shortening, and in some embodiments eliminating, wake-up cycling. The wake-up effect is described in further detail below. It will be understood that the field-effect ferroelectric (FEA) techniques described using various embodiments of this disclosure can offer similar benefits when forming ferroelectric layers using materials other than hafnium oxide-based materials.

[0012] Dielectric materials can be polarized by an electric field (E). The electric polarization vector (P) in response to the electric field is generally a function of the electric field E, which is roughly linear and symmetric for a centrosymmetric dielectric. A centrosymmetric dielectric is nonferroelectric (i.e., P=0 at E=0). However, some non-centrosymmetric dielectrics are ferroelectric, i.e., they exhibit spontaneous or residual polarization, and P=P at E=0. R ≠0, and this is remanent polarization (P R This is called a forced electric field (E) of the opposite polarity in order to force P to zero in a ferroelectric dielectric. C) needs to be applied. The P-versus-E curve of a ferroelectric is non-linear and generally has a symmetric hysteresis loop. As is known to those skilled in the art, some ferroelectric films, such as hafnium oxide-based ferroelectric thin films, exhibit a wake-up effect, and the original films fabricated using conventional processes (without electric field annealing) have pinched hysteresis curves (small P R ) but this curve broadens and becomes a stable, wider hysteresis loop (larger P 2 after repeating a plurality of times, for example, about 10 5 cycles to about 10 R cycles. Usually, all ferroelectric components including the original dielectric layer having an unstable P R need to be stabilized by wake-up cycling in order for each circuit to function as designed. Thus, it can be recognized that the innovative electric field annealing technique described in the present disclosure provides a significant advantage by reducing the number of wake-up cycles and, in some embodiments, eliminating the wake-up cycling step.

[0013] The presence of hysteresis in the P-versus-E characteristic enables the use of a ferroelectric capacitor as a non-volatile memory (NVM) element. For example, by using a high positive bias voltage or a negative bias voltage to force the ferroelectric capacitor to either the upper branch or the lower branch of the P-versus-E hysteresis loop, a corresponding state of high positive polarization or negative polarization can be achieved, and a binary logic state of either "1" or "0" can be stored. After the bias is removed (E = 0), depending on whether the ferroelectric capacitor was forced to the upper branch or the lower branch of the P-versus-E hysteresis loop, a portion of the polarization becomes the remnant polarization +P R or P RIt is held as such. The maximum displacement current at each branch of the hysteresis curve (corresponding to the maximum gradient between P and E) occurs with opposite polarity, so the stored information can be read out, for example, by detecting the capacitor current in response to a voltage ramp of a given polarity. As can be understood from the data storage and reading mechanism described above, a stable high P R Due to its importance, the wake-up cycling step is typically performed in the manufacture of ICs containing hafnium oxide-based ferroelectric NVMs formed without the field-effect annealing (FEA) described above. However, using the field-effect annealer and field-effect annealing described herein can result in a reduction in the number of wake-up cycles, and in some embodiments, the elimination of the wake-up cycling step from the manufacturing flow, thereby reducing the cost of hafnium oxide-based ferroelectric NVMs.

[0014] Ferroelectric materials may be used when forming gate dielectric stacks for FE-FETs. If the residual polarization of the gate dielectric stack is sufficiently large, the transistor, like a ferroelectric capacitor, can retain its state once programmed and remain on or off even after the programming voltage has been removed. Such FE-FETs may also be used to store digital information in NVM cells. As mentioned above in relation to hafnium oxide-based ferroelectric capacitors (NVMs), the manufacturing cost of hafnium oxide-based ferroelectric FE-FETs (NVMs) can be reduced by using innovative field annealers and field FEAs.

[0015] When used in digital logic or analog circuits, FE-FETs can offer several advantages over conventional (i.e., non-ferroelectric) MOSFETs. The gate dielectric stack of FE-FETs used in digital logic and / or analog circuits includes ferroelectric and non-ferroelectric thin films. When used in circuits, for example as a digital switch, the ferroelectric portion of the gate dielectric stack provides dynamic capacitance, which can result in voltage snapback due to changes in the polarization of the ferroelectric under certain bias sweep conditions (e.g., sweep speed or frequency). This snapback allows FE-FETs to achieve desirable, steeper thresholds and higher I2s. ON / I OFF A ratio may be obtained. In this regard, FE-FETs are generally called negative capacitance field-effect transistors (NCFETs). Here, more precisely, they are called steep gradient strong field-effect transistors (SSFEFETs). However, in order to achieve IV and CV curves of a transistor without hysteresis, ferroelectric properties (e.g., P) in the gate dielectric stack are used. R ) and film thickness may need to be appropriately adjusted. As is known to those skilled in the art, IV and CV curves without hysteresis suggest stable transistor operation, but the presence of hysteresis can lead to circuit instability and unintended electrical oscillations. Considering circuit stability, in order for an SSFEFET to provide the expected circuit advantages without destabilizing the circuit, P R It will be understood that the characteristics need to be stable and remain within the design window. Therefore, while a fabrication flow for SSFEFETs that does not include an electric field FEA may incorporate a wake-up cycling step, using the electric field annealing technique of the present invention described herein can reduce wake-up cycling and, in some embodiments, eliminate wake-up cycling altogether, resulting in the advantage of cost reduction by achieving stable ferroelectric properties.

[0016] This disclosure first describes the field annealing technique using a schematic cross-sectional view of the processing chamber of a field annealer during a field annealing (e.g., field FEA) process step, as shown in Figure 1A, along with an alternative embodiment shown in Figure 1B. The field annealer is further described with reference to various perspective views of the field annealer's load rails shown in Figures 2 to 5. The electrical connections of the gate dielectric layer of FE-FET / SSFEFET and / or MOS ferroelectric capacitors during field FEA are described with reference to cross-sectional views of planar bulk complementary MOS (CMOS) and silicon-on-insulator (SOI) CMOS semiconductor wafers shown in Figures 6A and 6B, respectively. In addition to MOS capacitors, capacitor components in ICs, commonly called MIM capacitors, can be formed using metal layers for both the upper and lower electrodes of the capacitor. In this disclosure, non-ferroelectric insulators and ferroelectric insulators are distinguished by abbreviations. Non-ferroelectric insulators are abbreviated as I, and ferroelectric insulators are abbreviated as F. The electrical connections made to the electrodes of the MFM capacitor during the electric field (FEA) will be explained with reference to the cross-sectional view shown in Figure 6C.

[0017] Various combinations of material layers can be stacked for use in ferroelectric electronic devices (e.g., transistors and capacitors). The stack may include ferroelectric layers along with non-ferroelectric dielectric layers, metal layers, and semiconductors. Examples of such stacks include, but are not limited to, the following (listing the layers from top to bottom): metal-ferroelectric-metal (MFM), metal-ferroelectric-insulator-metal (MFIM), metal-ferroelectric-insulator-semiconductor (MFIS), metal-ferroelectric-metal-semiconductor (MFMS), metal-ferroelectric-metal-insulator-semiconductor (MFMIS), semiconductor-ferroelectric-semiconductor (SFS), and semiconductor-ferroelectric-insulator-semiconductor (SFIS). In this disclosure, exemplary stacks may be MFIS (e.g., in a FEFET / SSFEFET transistor) or MFM (e.g., in a capacitor with upper and lower metal electrodes).

[0018] Figure 1A schematically shows a cross-sectional view of a semiconductor wafer 50 placed on a substrate holder 10 inside a processing chamber 225 of an annealer, which is an annealer equipped to perform field annealing. The processing chamber 225 comprises a heat treatment system 235 designed to heat treat the wafer placed inside the processing chamber 225. In various embodiments, the heat treatment system 235 comprises a temperature controller that controls heating and cooling elements to maintain a desired temperature of the semiconductor wafer 50 inside the processing chamber 225 by using lamps, resistors, and others placed at various locations inside or outside the processing chamber 225.

[0019] The semiconductor wafer 50 comprises a semiconductor substrate 20, a MOS dielectric layer 30 formed on the semiconductor substrate 20, and a conductive upper electrode layer 40 formed on the MOS dielectric layer 30.

[0020] As schematically shown in Figure 1A, the first field annealer electrode is in physical and electrical contact with the conductive upper electrode layer 40. The first field annealer electrode may include a conductive material that is not affected by high-temperature processing. In one embodiment, the first field annealer electrode may include tungsten. The first field annealer electrode comprises a primary electrode 211 (e.g., a tungsten ribbon) connected to a first terminal of a DC power supply 130 using primary wiring 110 of a suitable conductor (e.g., tungsten) that can be heated to high temperatures without being damaged during annealing. The ribbon shape of the primary electrode 211 provides a spring-like action that helps prevent slippage and maintain good physical contact with the surface of the semiconductor wafer 50 as the wafer is heated during the annealing process. The potential of the conductive upper electrode layer 40 may optionally be monitored using a voltmeter 150 connected to another monitoring electrode 212, e.g., another tungsten ribbon positioned to contact the conductive upper electrode layer 40, via monitoring wiring 112 (similar to the primary wiring 110). The two electrodes are electrically short-circuited together by the conductive upper electrode layer 40. The primary electrode 211 and the monitoring electrode 212 may collectively be called the first electric field annealer electrode 210. The primary wiring 110 and the monitoring wiring 112 may collectively be called the two wirings 115.

[0021] In the exemplary embodiment shown in Figure 1A, the surface of the substrate holder 10, which is in physical contact with the back surface of the semiconductor wafer 50, is used as a second field annealer electrode. The surface of the substrate holder 10 can be coated with a suitable conductive material, such as a silicon-based, carbon-based, silicon-and-carbon composite-based, or metal nitride-based coating, to obtain a conductive surface suitable for use as an electrode at the annealing temperature. The back surface, and a portion of the semiconductor wafer 50 adjacent to the back surface, may be a conductive material such as n-type or p-type doped silicon or germanium, and may be in electrical contact with the surface of the substrate holder 10. In some embodiments, back surface etching may be used to expose a conductive surface on the back surface in order to establish electrical contact between the back surface of the semiconductor wafer 50 and the surface of the substrate holder 10.

[0022] As schematically shown in Figure 1A, the surface of the substrate holder 10, and therefore the back surface of the semiconductor wafer 50, may be connected to a reference potential, which is called ground and is indicated as GND in Figure 1A. The ground connection can be established using secondary wiring 113 similar to primary wiring 110. In this embodiment, secondary wiring 113 is electrically connected to ground wiring that connects the conductive portion of the main structure of the device to system ground. The second terminal of the DC power supply 130 is also connected to ground (GND) to apply a bias voltage across the entire semiconductor wafer 50. As will be understood by those skilled in the art and will be further described below, the voltage drop between the two terminals of the DC power supply can be adjusted to realize an electric field in the MOS dielectric layer 30 having a desired polarity and an electric field strength within a desired range. In various embodiments, the DC power supply 130 may be configured to supply an appropriate voltage, such as 1V to 100V, and in one embodiment, 3V to 10V.

[0023] The bias applied during annealing may be a fixed voltage or a time-varying voltage, and its magnitude and waveform can vary considerably depending on the material, layer thickness, annealing conditions, and specific device application. The DC bias voltages described above are for illustrative purposes only and should not be interpreted as limiting. Time-varying voltage waveforms may include pulsed DC, AC pulses, sine waves, sawtooth waves, etc. It should also be noted that the applied bias may be referenced to a common ground potential, some other fixed reference potential, a controlled variable reference potential, a time-varying potential, or a floating node potential.

[0024] The embodiment in Figure 1A shows a single semiconductor wafer 50 inside a processing chamber 225, but it will be understood that multiple wafers, including dummy wafers, may be placed inside a appropriately designed processing chamber. The field annealer electrodes and electrical connections in Figure 1A are shown as configured for single-wafer processing. However, the field annealer configuration may be modified to anneal a batch of semiconductor wafers. An exemplary embodiment suitable for batch processing is shown in Figure 1B.

[0025] Figure 1B shows multiple semiconductor wafers 50 horizontally stacked on a slotted substrate holder 14 containing an insulator (e.g., a ceramic insulator) that is unaffected by high-temperature processing. The insulating material prevents the substrate holder 14 from causing an electrical short circuit between the conductive top and back surfaces of the semiconductor wafers 50. The stacked wafers are shown loaded into the processing chamber 226 of an electric field annealer. Located inside the processing chamber 226 are two conductive buses, namely a first conductive bus 108 and a second conductive bus 109, fixed above and below the slotted substrate holder 14, respectively. The temperature inside the processing chamber 226 can be controlled by a heat treatment system 236.

[0026] The conductive top surface of each wafer is shown to be electrically connected to a first conductive bus 108 by a primary electrode 215 similar to the primary electrode 211 in Figure 1A. As shown in Figure 1B, the connection between the first conductive bus 108 and the primary electrode 215 can be established using connecting wiring that passes through the openings of the slotted substrate holder 14. In this embodiment, the first field annealer electrode comprises the primary electrode 215 and the first conductive bus 108. The first field annealer electrode is connected to a DC power supply 130 using primary wiring 110, similar to Figure 1A. The conductive back surface of each wafer can be connected to a second conductive bus 109 using a secondary electrode 216 and connecting wiring (similar to the top surface). In this embodiment, the second field annealer electrode, comprising the secondary electrode 216 and the second conductive bus 109, is connected to GND using secondary wiring 114. The potential of the upper surface of the wafer may be monitored by connecting the first conductive bus 108 to the voltmeter 150 using monitoring wiring 112, as shown in Figure 1B.

[0027] Referring to Figure 1B, the field annealer described above is suitable for batch processing wafers arranged in a horizontal stack. By modifying the design of the horizontal processing chamber 226, a similar field annealer can be provided that can stack semiconductor wafers 50 vertically.

[0028] Figure 2 shows a perspective view of a load rail 100 of an electric field annealer according to one embodiment of the present invention. The load rail 100 can be used to introduce a wafer into the processing chamber 225 of the electric field annealer. The wafer is first loaded into a slot in a substrate holder mounted on a load rail stage (Figure 2). The electrodes are then positioned to make appropriate electrical contact with the wafer / each wafer. The load rail stage is then used to position the wafer in the substrate holder into the heating zone of the oven.

[0029] In Figure 2, two wirings 115 (similar to the primary wiring 110 and monitoring wiring 112 in Figure 1A) are shown extending to region B1 (indicated by the dashed circle in Figure 2). Region B1 includes a first field annealer electrode 210 comprising two tungsten ribbons that contact the conductive upper electrode layer 40 of the semiconductor wafer 50. As mentioned above, the ribbon shape helps maintain good physical contact with the semiconductor wafer 50 during the annealing process. The first field annealer electrode 210 is attached to portions of the two wirings 115 that are exposed metal (e.g., exposed tungsten). The other portions of the two wirings 115 are electrically insulated from other conductive parts of the apparatus by an insulating material, such as insulating ceramic beads. The insulated portions of the two wirings 115 are called insulated conductive wiring 310. Figure 3 shows the conductive wiring 310 insulated with ceramic beads in an enlarged perspective view of region D1, indicated by the dashed circle in Figure 2.

[0030] As described above, the first of the two wirings 115 may pass through a power feedthrough 120 (shown in Figure 2) and be connected to a DC power supply 130 used to apply an electric field to a dielectric layer, e.g., the MOS dielectric layer 30 of the semiconductor wafer 50. As schematically shown in Figure 2, the other of the two wirings 115 (similar to the monitoring wiring 112 in Figure 1A) may be connected at one end to a first electric field annealer electrode 210 and at the opposite end to a voltmeter 150 to monitor the potential of the conductive upper electrode layer 40 of the semiconductor wafer 50. Conductive parts of the main structure of the apparatus, including a substrate holder (e.g., substrate holder 10 in Figure 1A) in contact with the back surface of the semiconductor wafer 50, are connected to earth GND by a grounding wiring 140. The substrate holder of the semiconductor wafer 50 will be described further below with reference to Figure 5A, which shows an enlarged perspective view of region B1 (shown by the dashed circle in Figure 2).

[0031] Perspective views of the road rail 100 from different angles, indicated by arrow C in Figure 2, are shown in Figure 4. Figure 4 shows the conductors of two wires 115 exposed by removing ceramic beads from each of the two insulated conductive wires 310 passing through the two respective openings. The two wires 115 connect to two tungsten ribbons of the first field annealer electrode 210, which is in contact with the upper surface of the semiconductor wafer 50. These two wires 115 in Figure 4 are the same wires shown in Figure 2, extending from the first field annealer electrode 210 to the DC power supply 130 and the voltmeter 150, respectively. In the perspective view of Figure 4, the first field annealer electrode 210 is located in region C1 (indicated by a dashed circle). In the perspective view of Figure 2, the first field annealer electrode 210 is located in region B1.

[0032] Areas B1 in Figure 2 and C1 in Figure 4 are shown in more detail in the enlarged perspective views shown in Figures 5A and 5B, respectively. The perspective view in Figure 5A more clearly shows the connection between one of the two wirings 115 and the first field annealer electrode 210. The viewing angle of the perspective view in Figure 5B more clearly shows the tungsten ribbon of the first field annealer electrode 210 in physical contact with the conductive upper electrode layer 40 of the semiconductor wafer 50. Figures 5A and 5B show that the semiconductor wafer 50 is supported from below by a support plate 230. The support plate 230 is part of the slotted substrate holder shown in Figures 2 and 3, and may also be an exemplary embodiment of the substrate holder 10 in Figure 1A. The surface of the support plate 230 may be made of metal, including, for example, stainless steel, and may be in physical and electrical contact with the conductive back surface of the semiconductor wafer 50. In one embodiment, the support plate 230 may be in the form of a ring. The ring shape supports the outer diameter of the wafer, but exposes most of the back surface to the heating element. The support plate 230 may include a conductive material connected to ground GND.

[0033] Figure 5A shows several optional buffer wafers 240 that help achieve a more uniform temperature profile across the entire surface of the semiconductor wafer 50 during annealing. The buffer wafers 240 are not shown in Figures 4 and 5B for clarity. As shown in Figure 5B, the insulating ceramic tabs 250 may be positioned along carrier rails close to the edges of the semiconductor wafer 50 and the support plate 230 to reduce the possibility of accidental undesirable electrical short circuits occurring between the semiconductor wafer 50 and the conductive surface of the field annealer.

[0034] The DC bias voltage that can be set for the DC power supply 130 during an electric field PDA is generally determined by the thickness t of the target dielectric layer (e.g., the MOS dielectric layer 30 in Figure 1A) on which the electric field PDA is being implemented, as described below. OX It also depends not only on the properties of other layers, such as the material used in the conductive upper electrode layer 40, but also on the material, thickness, and properties of the layer beneath the target dielectric layer. In some embodiments, the DC bias voltage of the DC power supply 130 can be controlled to remain constant during field annealing.

[0035] Figures 6A and 6B show cross-sectional views of the semiconductor wafer 50 during the field annealing step of a planar bulk CMOS flow and a planar SOI CMOS flow, respectively. The field annealing step in the exemplary embodiments shown in Figures 6A and 6B is a field ferroelectric annealing, or FEA, performed after a conductive upper electrode layer 40 is formed on the MOS dielectric layer 30. The conductive upper electrode layer 40 may be used as the gate electrode of an FE-FET / SSFEFET or a ferroelectric MOS capacitor and may contain one or more conductive materials such as TiN, TaN, W, or a metal alloy.

[0036] In Figures 6A and 6B, ferroelectric components (e.g., FE-FETs / SSFEFETs and ferroelectric MOS capacitors) using the MOS dielectric layer 30 may be fabricated using a gate-first process integration method. However, those skilled in the art will understand that the innovative aspects of these embodiments are applicable to each ferroelectric component fabricated using a gate-last (or substituted gate) process integration method.

[0037] In the exemplary embodiments shown in Figures 6A and 6B, the MOS dielectric layer 30 includes a doped amorphous hafnium oxide film and an interface dielectric layer (e.g., silicon oxide) adjacent to the surface of the semiconductor (e.g., silicon). The thickness t of the MOS dielectric layer 30 OXThe grain size can vary from approximately 1 nm to approximately 100 nm, depending on the application. The annealing temperature can be adjusted so that the amorphous hafnium oxide crystallizes during annealing to form a polycrystalline hafnium oxide film. For example, field annealing (FEA) can be carried out at temperatures of approximately 200°C to approximately 1200°C, for example, in an inert gas environment at low pressure. Temperatures below 200°C may be insufficient for crystallization of the amorphous layer, while temperatures above 1200°C may alter the properties of other layers formed during earlier processing steps. Although the orthorhombic phase of hafnium oxide is ferroelectric, the orthorhombic phase is unstable in pure HfO2, so pure amorphous HfO2 can spontaneously be converted into monocrystalline or cubic crystal grains. However, as is known to those skilled in the art, the orthorhombic phase of HfO2 can be stabilized by certain dopant atoms such as zirconium, silicon, or lanthanum atoms. Therefore, as the doped amorphous hafnium oxide film in the MOS dielectric layer 30 crystallizes, an orthorhombic phase of HfO2 is formed and can be stabilized by the dopant in the metastable orthorhombic phase, which is ferroelectric. The electric field strength in the electric field FEA can be adjusted from 1 MV / cm to about 100 MV / cm. If the electric field is too low, it may not provide sufficient benefit to reduce / eliminate wake-up cycling, while if the electric field is too high, it may damage the MOS dielectric layer 30 and / or reduce its lifetime. As will be further explained below, the respective DC bias voltage settings of the DC power supply 130 for applying the desired range of electric fields to the MOS dielectric layer 30 depend on whether the process flow is for the fabrication of bulk CMOS or SOI CMOS.

[0038] In Figures 6A to 6C, the layers of the semiconductor wafer 50 on which layers specific to the ferroelectric components are formed are collectively referred to as the substrate 20. Therefore, in the case of the planar FE-FET / SSFEFET or ferroelectric MOS capacitor shown in Figures 6A and 6B, the substrate 20 includes all layers formed before the MOS dielectric layer 30 is formed. In the case of the MFM ferroelectric capacitor shown in Figure 6C, the substrate 20 includes all layers formed before the MFM conductive lower electrode layer 45 is formed.

[0039] A substrate 20 for a planar FE-FET / SSFEFET or ferroelectric MOS capacitor comprises a first semiconductor region 21 of a first conductivity type (e.g., p-type), a second semiconductor region 22 of a second conductivity type (e.g., n-type), and insulating regions called shallow trench isolation (STI) regions 25, which help to electrically isolate adjacent electronic components in each of the first and second semiconductor regions 21 and 22. As is known to those skilled in the art, the conductive upper electrode layers 40 on the first and second semiconductor regions 21 and 22 may contain the same material formed by the same process, or may contain different materials formed by separate processes. If separate processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0040] As shown in Figure 6A, in bulk CMOS, the first semiconductor region 21 of the first conductivity type extends completely to the back surface of the semiconductor wafer 50, and the second semiconductor region 22 of the second conductivity type extends to a depth that forms a pn junction together with the first semiconductor region 21. The pn junction is generally called an n-well p-well junction. In SOI CMOS, the first semiconductor region 21, the second semiconductor region 22, and the STI region 25 are terminated at the bottom by an insulating region called a buried oxide (BOX) layer 15, which may contain, for example, silicon oxide, as shown in Figure 6B. Semiconductor wafers having the BOX layer 15 can be produced using several methods, as is known to those skilled in the art, such as oxygen-implanted isolation (SIMOX) processes, wafer bonding processes, and, for example, smartcut technology. The doped semiconductor region 12 beneath the BOX layer 15 extends completely to the back surface of the semiconductor wafer 50.

[0041] As described above with reference to Figures 1A and 2, the back surface of the semiconductor wafer 50 and the second terminal of the DC power supply 130 are connected to ground GND, and the first terminal of the DC power supply is connected to the primary electrode 211 of the first field annealer electrode using primary wiring 110. (For simplicity, the monitoring electrode 212 and monitoring wiring 112 are not shown in Figures 6A-6C.) The primary electrode 211 shown in Figures 6A and 6B is in physical and electrical contact with the conductive upper electrode layer 40, as in the cross-sectional view of Figure 1A and the detailed perspective views of Figures 5A and 5B. Thus, the entire DC bias voltage supplied by the DC power supply 130 is applied between the conductive upper electrode layer 40 and the back surface of the semiconductor wafer 50.

[0042] Referring again to Figure 6A, in the case of bulk CMOS, in the first semiconductor region 21, the potential on the semiconductor side of the MOS dielectric layer 30 is approximately the same as the potential on the back surface of the semiconductor wafer 50. Therefore, the voltage drop across the MOS dielectric layer 30 is determined by the DC bias voltage supplied by the DC power supply 130 and the work function difference between the first semiconductor region 21 and the conductive upper electrode layer 40 on this region. However, in the second semiconductor region 22, the voltage drop across the n-well / p-well junction must be included when determining the potential on the semiconductor side of the MOS dielectric layer 30, and therefore when determining the voltage drop across the MOS dielectric layer 30. Therefore, it may be advantageous to minimize the voltage drop across the n-well / p-well junction by selecting the polarity of the DC bias voltage supplied by the DC power supply 130 such that the pn junction is forward biased. In one embodiment, the DC bias voltage setting of the DC power supply 130 in the electric field FEA is set to approximately 10 nm of the MOS dielectric layer 30. OX The value can range from approximately 3V to approximately 10V.

[0043] Referring to Figure 6B, in SOI CMOS, a significant portion of the DC bias voltage supplied by the DC power supply 130 can drop across the BOX layer 15, depending on the ratio of the thickness and dielectric constant of the MOS dielectric layer 30 and the BOX layer 15. Therefore, the DC bias voltage used for the electric field FEA in the SOI CMOS process flow may need to be increased compared to the corresponding value in the bulk CMOS process flow.

[0044] Relatively advanced CMOS ICs may use a three-dimensional MOS structure called a FinFET structure, in which the gate and gate dielectric generally enclose three sides of a thin, elongated semiconductor fin protruding from the semiconductor substrate. Those skilled in the art can adapt the electrical connections to the FE-FET / SSFEFET and MOS ferroelectric capacitor in the field-effect analysis (FEA) described with reference to the planar MOS structure shown in Figures 6A and 6B to implement the corresponding field-effect analysis (FEA) of the FinFET structure.

[0045] Figure 6C shows the field-effect analysis (FEA) step performed in a process flow including the fabrication of an MFM ferroelectric capacitor. The MFM ferroelectric capacitor structure in Figure 6C includes a doped hafnium oxide-based ferroelectric-dielectric layer 35 sandwiched between a conductive upper electrode layer 40 and a conductive lower electrode layer 45. A primary electrode 211, shown as being in contact with the conductive upper electrode layer 40, is connected to a first terminal of a DC power supply 130 (not shown) using primary wiring 110. As with the semiconductor wafer 50 in Figures 6A and 6B, the back surface of the semiconductor wafer 50 and a second terminal of the DC power supply 130 are connected to GND. However, as will be explained below, if the conductive lower electrode layer 45 is effectively electrically isolated from the back surface GND connection of the semiconductor wafer 50 in Figure 6C due to an excessively large cumulative thickness of the dielectric layer in the substrate 20, these connections alone may not be sufficient to generate a sufficiently high electric field in the ferroelectric-dielectric layer 35 of the MFM capacitor.

[0046] The MFM capacitor layer, including the conductive lower electrode layer 45, is generally formed during the back-end of line (BEOL) of the IC fabrication flow. Since the substrate 20 in Figure 6C comprises all layers formed beneath the conductive lower electrode layer 45, the substrate may include relatively thick interlayer dielectric (ILD) and intermetallic dielectric (IMD) layers that are physically located above the conductive semiconductor and MOSFET gate layers. Therefore, in the intermediate stages of fabrication shown in Figure 6C, unless the conductive lower electrode layer 45 is connected to the conductive semiconductor and MOSFET gate layers by vias and contacts, the electrical coupling between the back surface of the semiconductor wafer 50 and the conductive lower electrode layer 45 may be too weak to generate a sufficiently high electric field in the ferroelectric-dielectric layer 35 of the MFM capacitor. In such embodiments, a substrate holder electrically in contact with the back surface of the semiconductor wafer 50, such as the substrate holder 10 in Figure 1A or the support plate 230 in Figure 5A, may not be an effective second electric field annealer electrode. In such cases, additional processing may be used to form an effective second electric field annealer electrode connection, as described below with reference to Figure 6C.

[0047] In IC designs where a conductive lower electrode layer 45 is electrically isolated from the back surface of the semiconductor wafer 50 at an intermediate stage of the process flow where an electric field FEA is desired, a masking step may be used to pattern the ferroelectric-dielectric layer 35 and the conductive upper electrode layer 40 of the MFM capacitor to expose a portion of the conductive lower electrode layer 45, as shown in Figure 6C. The exposed region of the conductive lower electrode layer 45 may be, for example, in the shape of a ring along the edge of the semiconductor wafer 50. An additional secondary electrode 214 (similar in structure to the electrodes of the first electric field annealer electrode 210 shown in the cross-sectional view of Figure 1A and the detailed perspective views of Figures 5A and 5B) may be placed in physical and electrical contact with the exposed portion of the conductive lower electrode layer 45. The secondary electrode 214, which is a direct electrical connection to the conductive lower electrode layer 45, can be an effective second electric field annealer electrode connection. As shown in Figure 6C, the additional secondary electrode 214 may be connected to GND using secondary wiring 114 (similar to primary wiring 110). Therefore, the entire DC bias voltage drops across the ferroelectric-dielectric layer 35 of the MFM capacitor. In one embodiment, the DC bias voltage setting for the DC power supply 130 in the electric field FEA is approximately 10 nm across the ferroelectric-dielectric layer 35 of the MFM capacitor. OX The value can range from approximately 3V to approximately 10V.

[0048] Figure 7 shows a manufacturing platform for fabricating semiconductor devices according to one embodiment of the present invention. The manufacturing platform 700 includes a first deposition chamber 701 configured for depositing a conductive layer on a semiconductor wafer, a second deposition chamber configured for depositing a dielectric layer on a semiconductor wafer, a processing chamber 703 of an electric field annealer, a cleaning chamber 704, and a wafer transport system 705.

[0049] The interior of the manufacturing platform 700 may be maintained under vacuum conditions to ensure that the processing conditions are clean, and the wafer transport system 705 is configured to transport the wafers to be processed between the processing chambers of the manufacturing platform 700. The cleaning chamber 704 may be configured to remove oxides and contaminants from the wafers before processing and during the processing steps.

[0050] The processing chamber 703 of the electric field annealer has been described above in various embodiments. In the embodiments, the processing chamber 703 includes a substrate holder configured to support a semiconductor wafer, a heating element configured to heat the semiconductor wafer supported by the substrate holder, a first electrode configured to be removablely attached to a first main surface of the semiconductor wafer, and a first wiring that couples the first electrode to a first potential node.

[0051] In one embodiment, the processing chamber 703 may include a second electrode coupled to a substrate holder and a second wiring that couples the second electrode to a second potential node. Furthermore, the processing chamber 703 may include a third electrode configured to be detachably mounted on a first main surface of a semiconductor wafer, a voltage monitoring meter, and a third wiring that couples the third electrode to the voltage monitoring meter. In one embodiment, the processing chamber 703 may include a second electrode configured to be detachably mounted on a second main surface of a semiconductor wafer and a second wiring that couples the second electrode to a second potential node.

[0052] Furthermore, the processing chamber 703 may include a power supply coupled to the first potential node. In one embodiment, the power supply is configured to apply an electrical bias voltage across the dielectric layer. In one embodiment, the electrical bias voltage includes a time-varying voltage waveform. In one embodiment, the power supply is configured to apply an electrical bias voltage across the dielectric layer while a heating element heats the semiconductor wafer. In one embodiment, the heating element ramps the temperature of the semiconductor wafer from a first temperature to a second temperature.

[0053] According to one embodiment, a method for fabricating a semiconductor device includes placing a semiconductor wafer in a first deposition chamber 701 of a manufacturing platform 700. In one embodiment, the semiconductor wafer comprises a first conductive layer. In one embodiment, the first conductive layer may be deposited on the wafer in a second deposition chamber 702, after which the wafer is placed in the first deposition chamber 701. In another embodiment, the wafer may be cleaned in a cleaning chamber 704 before or after the first conductive layer is deposited on the wafer.

[0054] The method further includes depositing a dielectric layer on a first conductive layer in a first deposition chamber 701. Subsequently, the method includes placing a semiconductor wafer in a second deposition chamber 702 and depositing a second conductive layer on the dielectric layer in the second deposition chamber 702.

[0055] The method further includes placing a semiconductor wafer in a processing chamber 703 of an electric field annealer. Once inside the processing chamber 703, the method includes applying an electrical bias voltage across the dielectric layers by coupling a first conductive layer to a first potential and a second conductive layer to a second potential, and annealing the semiconductor wafer while applying the electrical bias voltage.

[0056] According to one embodiment, applying an electrical bias voltage includes applying a time-varying voltage waveform across a dielectric layer. According to one embodiment, annealing includes ramping the temperature of a semiconductor wafer from a first temperature to a second temperature. In one embodiment, the second temperature is greater than the first temperature. In other embodiments, the first temperature is greater than the second temperature.

[0057] According to one embodiment, annealing includes ramping the temperature of a semiconductor wafer from a first temperature to a second temperature during a first period, and then maintaining the temperature of the semiconductor wafer at least substantially at the second temperature during a second period, wherein the second temperature is greater than the first temperature.

[0058] According to one embodiment, annealing includes maintaining the temperature of the semiconductor wafer at least substantially at a first temperature during a first period, and then ramping the temperature of the semiconductor wafer from the first temperature to a second temperature during a second period, wherein the first temperature is greater than the second temperature.

[0059] According to one embodiment, coupling a first conductive layer to a first potential includes attaching a first electrode to a first main surface of a semiconductor wafer, and coupling a second conductive layer to a second potential includes placing a second main surface of a semiconductor wafer on a substrate holder and coupling the substrate holder to a second potential.

[0060] According to one embodiment, coupling a first conductive layer to a first potential includes attaching a first electrode to a first main surface of a semiconductor wafer, and coupling a second conductive layer to a second potential includes attaching a second electrode to a second main surface of a semiconductor wafer.

[0061] The time-varying voltage waveform may include pulsed DC, AC pulse, sine wave, sawtooth wave, etc. Non-limiting embodiments of the time-varying voltage waveform are shown in Figures 8A to 8C. Figure 8A shows a combination of a sine wave voltage waveform 801 and a constant wafer temperature 802.

[0062] Figure 8B shows a combination of pulse voltage waveform 811 and wafer temperature 812, where the wafer temperature ramps up from a first temperature to a second temperature during a first period, and then during a second period, the wafer temperature is maintained at least substantially at the second temperature, where the second temperature is greater than the first temperature. According to another embodiment, the wafer temperature can be maintained at least substantially at a first temperature during a first period, and then during a second period, the wafer temperature can be ramped up from a first temperature to a second temperature, where the first temperature is greater than the second temperature.

[0063] Figure 8C shows a combination of a sawtooth waveform 821 and a wafer temperature 822, where the wafer temperature is maintained at least substantially at a first temperature during a first period, and then during a second period, the wafer temperature is ramped from the first temperature to a second temperature, with the first temperature being greater than the second temperature. According to another embodiment, the wafer temperature may be ramped from a first temperature to a second temperature during a first period, and then during a second period, the wafer temperature is maintained at least substantially at a second temperature, with the second temperature being greater than the first temperature.

[0064] Although the present invention has been described with reference to exemplary embodiments, this specification is not intended to be constrained. Those skilled in the art will find various modifications and combinations of those exemplary embodiments, as well as other embodiments of the present invention, to be apparent by reference to this specification. Accordingly, the appended claims are intended to encompass all such modifications or embodiments. [Explanation of Symbols]

[0065] 10 PCB holder 12 Doped semiconductor regions 14. PCB holder 15 BOX layer 20 circuit boards 21. The first semiconductor area 22. The Second Semiconductor Domain 25 Shallow trench isolation (STI) region 30 MOS dielectric layers 35 Ferroelectric-Dielectric Layer 40 Conductive upper electrode layer 45 Conductive lower electrode layer 50 semiconductor wafers 100 Road Rails 108 First conductive bus 109 Second conductive bus 110 Primary wiring 112 Monitoring wiring 113 Secondary wiring 114 Secondary wiring 115 Two wires 120 Power feedthrough 130 DC power supply 140 Ground wiring 150 Voltmeter 210 First electric field annealer electrode 211 Primary electrode 212 Monitoring electrode 214 Secondary electrode 215 Primary electrode 216 Secondary electrode 225 Processing Chamber 226 Processing Chamber 230 Support Plate 235 Heat Treatment Systems 236 Heat Treatment System 240 buffer wafers 250 Insulating Ceramic Tabs 310 Insulated conductive wiring 700 manufacturing platforms 701 First Deposition Chamber 702 Second Deposition Chamber 703 Processing Chamber 704 Cleaning Chamber 705 Wafer Transfer System 801 Sine wave voltage waveform 802 Constant wafer temperature 811 Pulse voltage waveform 812 Wafer temperature 821 sawtooth waveform 822 Wafer temperature

Claims

1. A method for manufacturing semiconductor devices, A step of placing a semiconductor wafer in a first deposition chamber of a manufacturing platform, wherein the semiconductor wafer comprises a first conductive layer, The steps include depositing a dielectric layer on the first conductive layer in the first deposition chamber, The steps include: placing the semiconductor wafer in the second deposition chamber of the manufacturing platform; The steps include depositing a second conductive layer on the dielectric layer in the second deposition chamber, The steps include: placing the semiconductor wafer in the processing chamber of the electric field annealer of the manufacturing platform; The process involves applying an electrical bias voltage across the dielectric layers by coupling the first conductive layer to a first potential and the second conductive layer to a second potential within the processing chamber. The steps include annealing the semiconductor wafer while applying the aforementioned electrical bias voltage, A method having

2. The method according to claim 1, wherein the step of applying the electrical bias voltage comprises the step of applying a time-varying voltage waveform across the dielectric layer.

3. The method according to claim 2, wherein the time-varying waveform includes a pulsed DC, an AC pulse, a sine wave, or a sawtooth wave.

4. The method according to claim 1, wherein the annealing step comprises changing the temperature of the semiconductor wafer from a first temperature to a second temperature.

5. The method according to claim 4, wherein the second temperature is greater than the first temperature.

6. The method according to claim 4, wherein the first temperature is greater than the second temperature.

7. The annealing step comprises, during a first period, changing the temperature of the semiconductor wafer from a first temperature to a second temperature, and thereafter, during a second period, maintaining the temperature of the semiconductor wafer at least substantially at the second temperature. The method according to claim 1, wherein the second temperature is greater than the first temperature.

8. The method according to claim 1, wherein the dielectric layer contains hafnium oxide.

9. The annealing step comprises the steps of: maintaining the temperature of the semiconductor wafer at least substantially at a first temperature during a first period; and then, during a second period, changing the temperature of the semiconductor wafer from the first temperature to a second temperature. The method according to claim 1, wherein the first temperature is greater than the second temperature.

10. The step of coupling the first conductive layer to the first potential includes the step of attaching a first electrode to the first main surface of the semiconductor wafer. The method according to claim 1, wherein the step of coupling the second conductive layer to a second potential comprises the steps of placing the second main surface of the semiconductor wafer on a substrate holder and coupling the substrate holder to the second potential.

11. The method according to claim 1, wherein the step of coupling the first conductive layer to the first potential comprises the step of attaching a first electrode to the first main surface of the semiconductor wafer, and the step of coupling the second conductive layer to the second potential comprises the step of attaching a second electrode to the second main surface of the semiconductor wafer.

12. A manufacturing platform for manufacturing semiconductor devices, wherein the manufacturing platform is A first deposition chamber configured to deposit a conductive layer on a semiconductor wafer, A second deposition chamber configured to deposit a dielectric layer on the semiconductor wafer, A processing chamber for an electric field annealer, A substrate holder configured to support the semiconductor wafer, A heating element configured to heat the semiconductor wafer supported by the substrate holder, A first electrode configured to be detachably attached to the semiconductor wafer, the first electrode having a conductive outer surface configured to physically contact the first main surface of the semiconductor wafer when the first electrode is detachably attached to the semiconductor wafer, A first wiring that connects the first electrode to the first potential node, A processing chamber having, A manufacturing platform having

13. The processing chamber of the electric field annealer further comprises: A second electrode coupled to the substrate holder, The second electrode is connected to the second potential node by a second wiring, A manufacturing platform according to claim 12, having the following features.

14. The processing chamber of the electric field annealer further comprises: A third electrode configured to be detachably attached to the first main surface of the semiconductor wafer, Voltage monitoring meter and A third wiring that connects the third electrode to a voltage monitoring meter, A manufacturing platform according to claim 13, having the following features.

15. The processing chamber of the electric field annealer further comprises: A second electrode configured to be detachably attached to the second main surface of the semiconductor wafer, The second electrode is connected to the second potential node by a second wiring, A manufacturing platform according to claim 12, having the following features.

16. The processing chamber of the electric field annealer further comprises: The manufacturing platform according to claim 12, further comprising a power supply coupled to the first potential node.

17. The manufacturing platform according to claim 16, wherein the power supply is configured to apply an electrical bias voltage across the dielectric layer.

18. The manufacturing platform according to claim 17, wherein the electrical bias voltage includes a time-varying voltage waveform.

19. The manufacturing platform according to claim 16, wherein the power supply is configured to apply an electrical bias voltage across the dielectric layer while the heating element is heating the semiconductor wafer.

20. The manufacturing platform according to claim 19, wherein the heating element changes the temperature of the semiconductor wafer from a first temperature to a second temperature.

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