Semiconductor equipment

Abstract

To provide a semiconductor device capable of reducing oscillation between blocks in the event of a short circuit.SOLUTION: The semiconductor device includes a second metal pattern 17 electrically connected to a first semiconductor element 11 and a second semiconductor element 12, a third metal pattern 22 electrically connected to the second semiconductor element, a fifth metal pattern 37 electrically connected to a third semiconductor element 31 and a fourth semiconductor element 32, a sixth metal pattern 42 electrically connected to the fourth semiconductor element, and a first conductive portion 53 electrically connecting the second metal pattern and the fifth metal pattern by straddling the third and sixth metal patterns in plan view.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] In a semiconductor device such as a power module in which a plurality of semiconductor elements are connected by wires, when the number of semiconductor elements increases, the influence of the internal inductance becomes large, and there is a problem that the main current and the oscillation of the gate voltage at the time of short circuit increase. Therefore, techniques for reducing the internal inductance have been proposed. For example, Patent Document 1 proposes a technique for reducing the inductance of the upper and lower arms by arranging a plurality of semiconductor elements symmetrically with respect to a mirror surface.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the technique of Patent Document 1, since the inductance between the upper and lower arms, that is, between the semiconductor elements connected in series to each other can be reduced, oscillation can be reduced. However, in the technique of Patent Document 1, there is a problem that the inductance between blocks cannot be reduced, so that the oscillation between blocks cannot be sufficiently reduced.

[0005] Therefore, the present disclosure has been made in view of the above problems, and an object thereof is to provide a technique capable of reducing the oscillation between blocks at the time of short circuit.

Means for Solving the Problems

[0006] The semiconductor device according to this disclosure includes a first insulating substrate and a second insulating substrate, a first semiconductor element and a second semiconductor element provided on the first insulating substrate side and connected in series with each other, a first metal pattern electrically connected to the first semiconductor element but not electrically connected to the second semiconductor element, a second metal pattern electrically connected to the first semiconductor element and the second semiconductor element, a third metal pattern electrically connected to the second semiconductor element but not electrically connected to the first semiconductor element, a third semiconductor element and a fourth semiconductor element provided on the second insulating substrate side and connected in series with each other, a fourth metal pattern electrically connected to the third semiconductor element but not electrically connected to the fourth semiconductor element, a fifth metal pattern electrically connected to the third semiconductor element and the fourth semiconductor element, and the The device comprises a sixth metal pattern that is not electrically connected to the third semiconductor element but is electrically connected to the fourth semiconductor element, a first P terminal, a first AC terminal, a first N terminal, a second P terminal, a second AC terminal, and a second N terminal that are electrically connected to the first metal pattern, the second metal pattern, the third metal pattern, the fourth metal pattern, the fifth metal pattern, and the sixth metal pattern respectively, a case in which the first P terminal, the first N terminal, the second N terminal, and the second P terminal are provided in this order along the first end, and the first AC terminal and the second AC terminal are provided along the second end opposite to the first end, and a first conductive portion that, in a plan view, straddles the third metal pattern and the sixth metal pattern and electrically connects the second metal pattern and the fifth metal pattern. [Effects of the Invention]

[0007] According to this disclosure, the first conductive portion spans the third and sixth metal patterns in a plan view and electrically connects the second and fifth metal patterns. With this configuration, oscillation between blocks during a short circuit can be reduced. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view showing the configuration of a semiconductor device according to Embodiment 1. [Figure 2] This is a circuit diagram showing the configuration of the semiconductor device according to Embodiment 1. [Figure 3] This is a plan view showing the configuration of a semiconductor device according to Embodiment 2. [Figure 4] This is a plan view showing the configuration of a semiconductor device according to Embodiment 3. [Figure 5] This is a plan view showing the configuration of the semiconductor device according to Embodiment 4. [Figure 6] This is a plan view showing a configuration that combines the configuration of a semiconductor device with a modified example. [Modes for carrying out the invention]

[0009] The embodiments will be described below with reference to the attached drawings. The features described in each of the embodiments below are illustrative, and not all features are necessarily required. In addition, in the descriptions below, the same or similar reference numerals are used for similar components in multiple embodiments, and the different components are mainly described. Also, in the descriptions below, specific positions and directions such as "top," "bottom," "left," "right," "front," or "back" do not necessarily have to coincide with the positions and directions in actual implementation.

[0010] <Embodiment 1> Figure 1 is a plan view showing the configuration of a semiconductor device according to this embodiment 1, and Figure 2 is a circuit diagram showing the configuration of the same semiconductor device.

[0011] The semiconductor device shown in Figure 1 comprises a first insulating substrate 1 and a second insulating substrate 2, a first block circuit 1a and a second block circuit 2a, a substantially rectangular case 51, and wires 52, 53, and 54. The first block circuit 1a and the second block circuit 2a are provided on the first insulating substrate 1 and the second insulating substrate 2, which are spaced apart from each other. The first block circuit 1a will be described first, followed by the second block circuit 2a.

[0012] <Block 1 Circuit 1a> The first block circuit 1a comprises a P-side semiconductor element 11, a P-side diode 11a, an N-side semiconductor element 12, an N-side diode 12a, a P-side metal pattern 13, a first P-side terminal 1P, a first P-side gate terminal 1PG, an AC-side metal pattern 17, a first P-side source terminal 1PS, a first AC-side terminal 1AC, a first N-side gate terminal 1NG, an N-side metal pattern 22, a first N-side source terminal 1NS, and a first N-side terminal 1N.

[0013] The first semiconductor element, the P-side semiconductor element 11, and the second semiconductor element, the N-side semiconductor element 12, are provided on the first insulating substrate 1 side. As shown in Figure 2, the source electrode of the P-side semiconductor element 11 and the drain electrode of the N-side semiconductor element 12 are electrically connected, so that the P-side semiconductor element 11 and the N-side semiconductor element 12 are connected in series with each other, forming an upper and lower arm.

[0014] In this embodiment 1, the P-side semiconductor element 11 and the N-side semiconductor element 12 are each MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). However, the P-side semiconductor element 11 and the N-side semiconductor element 12 are not limited to these, and may be, for example, IGBTs (Insulated Gate Bipolar Transistors) or RC-IGBTs (Reverse Conducting IGBTs).

[0015] Furthermore, in the plan view of Figure 1, the P-side semiconductor element 11 and the N-side semiconductor element 12 each have a gate electrode and a source electrode on the front side of the P-side semiconductor element 11 and the N-side semiconductor element 12, and a drain electrode on the back side of the P-side semiconductor element 11 and the N-side semiconductor element 12. However, the arrangement of the gate electrode, source electrode, and drain electrode of the P-side semiconductor element 11 and the N-side semiconductor element 12 is not limited to that shown in Figure 1.

[0016] Also, the materials of the P-side semiconductor element 11 and the N-side semiconductor element 12 may be ordinary silicon (Si), or may be wide-bandgap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), or diamond. When the materials of the P-side semiconductor element 11 and the N-side semiconductor element 12 are wide-bandgap semiconductors, stable operation at high temperatures and high voltages, and an increase in the switching speed are possible.

[0017] The P-side diode 11a and the N-side diode 12a are provided on the side of the first insulating substrate 1, and are connected in parallel to the P-side semiconductor element 11 and the N-side semiconductor element 12, respectively, as shown in FIG. 2. Each of the P-side diode 11a and the N-side diode 12a may be an SBD (Schottky Barrier Diode) or a PND (PN junction diode).

[0018] In the examples of FIGS. 1 and 2, the number of each of the P-side semiconductor element 11, the P-side diode 11a, the N-side semiconductor element 12, and the N-side diode 12a is three, but the number is not limited to this.

[0019] The P-side metal pattern 13, which is the first metal pattern, is provided on the first insulating substrate 1. The P-side metal pattern 13 is electrically connected to the drain electrode of the P-side semiconductor element 11 without being electrically connected to the N-side semiconductor element 12. The first P terminal 1P is electrically connected to the P-side metal pattern 13 by a wire 14.

[0020] The first P-side gate terminal 1PG is electrically connected to the gate electrode of the P-side semiconductor element 11 by a wire 15 or the like.

[0021] The second metal pattern, the AC-side metal pattern 17, is provided on the first insulating substrate 1. The AC-side metal pattern 17 is electrically connected to the source electrode of the P-side semiconductor element 11 by a wire 16. The AC-side metal pattern 17 is also electrically connected to the drain electrode of the N-side semiconductor element 12. As a result, as described above, the P-side semiconductor element 11 and the N-side semiconductor element 12 are connected in series with each other.

[0022] The first P-side source terminal 1PS is electrically connected to the AC-side metal pattern 17 by a wire 18, and the first AC terminal 1AC is electrically connected to the AC-side metal pattern 17 by a wire 19.

[0023] With the above configuration, the P-side semiconductor element 11 controls the current flowing between the first P-side gate terminal 1P and the first P-side source terminal 1PS and the first AC-side terminal 1AC based on the gate voltage applied to the first P-side gate terminal 1PG. The current flowing between the first P-side terminal 1P and the first AC-side terminal 1AC generally flows in the shorter direction of the case 51, so the path of this current can be made relatively short, and the inductance related to this current can be reduced. In addition, the current flowing between the first P-side terminal 1P and the first AC-side terminal 1AC flows through parts of the P-side metal pattern 13 and the AC-side metal pattern 17 that are close to each other, so the inductance related to this current can be reduced.

[0024] The first N-side gate terminal 1NG is electrically connected to the gate electrode of the N-side semiconductor element 12 by a wire 20 or the like.

[0025] The third metal pattern, the N-side metal pattern 22, is provided on the first insulating substrate 1. The N-side metal pattern 22 is not electrically connected to the P-side semiconductor element 11, but is electrically connected to the source electrode of the N-side semiconductor element 12 by a wire 21.

[0026] The first N-side source terminal 1NS is electrically connected to the N-side metal pattern 22 by a wire 23, and the first N-side terminal 1N is electrically connected to the N-side metal pattern 22 by a wire 24.

[0027] With the above configuration, the N-side semiconductor element 12 controls the current flowing between the first AC terminal 1AC and the first N-side source terminal 1NS and the first N terminal 1N based on the gate voltage applied to the first N-side gate terminal 1NG. The current flowing between the first AC terminal 1AC and the first N terminal 1N generally flows in the shorter direction of the case 51, so the path of the current can be made relatively short, and the inductance related to the current can be reduced. In addition, the current flowing between the first AC terminal 1AC and the first N terminal 1N flows through parts of the AC-side metal pattern 17 and the N-side metal pattern 22 that are close to each other, so the inductance related to the current can be reduced.

[0028] <Second Block Circuit 2a> Since the second block circuit 2a is roughly mirror-symmetric to the first block circuit 1a, the configuration of the second block circuit 2a, as described below, is essentially the same as the configuration of the first block circuit 1a.

[0029] The second block circuit 2a comprises a P-side semiconductor element 31, a P-side diode 31a, an N-side semiconductor element 32, an N-side diode 32a, a P-side metal pattern 33, a second P-side terminal 2P, a second P-side gate terminal 2PG, an AC-side metal pattern 37, a second P-side source terminal 2PS, a second AC-side terminal 2AC, a second N-side gate terminal 2NG, an N-side metal pattern 42, a second N-side source terminal 2NS, and a second N-side terminal 2N.

[0030] The third semiconductor element, the P-side semiconductor element 31, and the fourth semiconductor element, the N-side semiconductor element 32, are provided on the second insulating substrate 2 side. As shown in Figure 2, the source electrode of the P-side semiconductor element 31 and the drain electrode of the N-side semiconductor element 32 are electrically connected, so that the P-side semiconductor element 31 and the N-side semiconductor element 32 are connected in series with each other, forming an upper and lower arm. The P-side semiconductor element 31 and the N-side semiconductor element 32 are the same as the P-side semiconductor element 11 and the N-side semiconductor element 12.

[0031] The P-side diode 31a and N-side diode 32a are provided on the second insulating substrate 2 side and are connected in parallel with the P-side semiconductor element 31 and N-side semiconductor element 32, respectively, as shown in Figure 2. The P-side diode 31a and N-side diode 32a are the same as the P-side diode 11a and N-side diode 12a.

[0032] The fourth metal pattern, the P-side metal pattern 33, is provided on the second insulating substrate 2. The P-side metal pattern 33 is not electrically connected to the N-side semiconductor element 32, but is electrically connected to the drain electrode of the P-side semiconductor element 31. The second P terminal 2P is electrically connected to the P-side metal pattern 33 by a wire 34.

[0033] The second P-side gate terminal 2PG is electrically connected to the gate electrode of the P-side semiconductor element 31 by a wire 35 or the like.

[0034] The fifth metal pattern, the AC-side metal pattern 37, is provided on the second insulating substrate 2. The AC-side metal pattern 37 is electrically connected to the source electrode of the P-side semiconductor element 31 by a wire 36. The AC-side metal pattern 37 is also electrically connected to the drain electrode of the N-side semiconductor element 32. As a result, as described above, the P-side semiconductor element 31 and the N-side semiconductor element 32 are connected in series with each other.

[0035] The second P-side source terminal 2PS is electrically connected to the AC-side metal pattern 37 by a wire 38, and the second AC terminal 2AC is electrically connected to the AC-side metal pattern 37 by a wire 39.

[0036] With the above configuration, the P-side semiconductor element 31 controls the current flowing between the second P-side terminal 2P and the second P-side source terminal 2PS and second AC terminal 2AC based on the voltage applied to the second P-side gate terminal 2PG. Since the second block circuit 2a is roughly mirror-symmetric to the first block circuit 1a, the inductance related to the current flowing between the second P-side terminal 2P and the second AC terminal 2AC can be reduced, similar to the inductance related to the current flowing between the first P-side terminal 1P and the first AC terminal 1AC.

[0037] The second N-side gate terminal 2NG is electrically connected to the gate electrode of the N-side semiconductor element 32 by a wire 40 or the like.

[0038] The sixth metal pattern, the N-side metal pattern 42, is provided on the second insulating substrate 2. The N-side metal pattern 42 is not electrically connected to the P-side semiconductor element 31, but is electrically connected to the source electrode of the N-side semiconductor element 32 by a wire 41.

[0039] The second N-side source terminal 2NS is electrically connected to the N-side metal pattern 42 by a wire 43, and the second N-side terminal 2N is electrically connected to the N-side metal pattern 42 by a wire 44.

[0040] With the above configuration, the N-side semiconductor element 32 controls the current flowing between the second AC terminal 2AC and the second N-side source terminal 2NS and second N terminal 2N based on the voltage applied to the second N-side gate terminal 2NG. Since the second block circuit 2a is roughly mirror-symmetric to the first block circuit 1a, the inductance related to the current flowing between the second AC terminal 2AC and the second N terminal 2N can be reduced, similar to the inductance related to the current flowing between the first AC terminal 1AC and the first N terminal 1N.

[0041] <Configuration other than the first block circuit 1a and the second block circuit 2a> Case 51 has a first end 51a and a second end 51b on the opposite side of the first end 51a. The first P terminal 1P, the first N terminal 1N, the second N terminal 2N, and the second P terminal 2P are provided along the first end 51a in this order, while the first AC terminal 1AC and the second AC terminal 2AC are provided along the second end 51b.

[0042] Wire 52 electrically connects the portion of the first AC terminal 1AC on the AC side of the AC-side metal pattern 17 to the portion of the second AC terminal 2AC on the AC-side metal pattern 37. As a result, the source electrode of the P-side semiconductor element 11 and the source electrode of the P-side semiconductor element 31 are electrically connected, thereby reducing the inductance on the source electrode side. Consequently, oscillations of the main current and gate voltage, which are amplified by the inductance on the source electrode side during a short circuit, can be reduced.

[0043] However, wire 52 is connected to the portion of the AC-side metal patterns 17 and 37 that does not enclose the N-side metal patterns 22 and 42. Therefore, if the number of wires 52 is increased, the area of ​​the portion of the AC-side metal patterns 17 and 37 that does not enclose the N-side metal patterns 22 and 42 must be increased, which results in the problem of the size of the semiconductor device in the vertical direction of Figure 1 becoming larger.

[0044] In contrast, in this embodiment 1, the first conductive part, wire 53, spans the N-side metal pattern 22 and N-side metal pattern 42 in a plan view, electrically connecting the AC-side metal pattern 17 and AC-side metal pattern 37. With this configuration, the number of wires 53 can be increased without increasing the area of ​​the parts of the AC-side metal patterns 17 and 37 that do not sandwich the N-side metal patterns 22 and 42. As a result, the inductance between the source electrode of the P-side semiconductor element 11 and the source electrode of the P-side semiconductor element 31 can be reduced while maintaining the size of the semiconductor device, and oscillation between the first block circuit 1a and the second block circuit 2a during a short circuit can be reduced.

[0045] Furthermore, there is variation in the distance between the source electrodes of the multiple P-side semiconductor elements 11 and the connection points of the wire 52, and similarly, there is variation in the distance between the source electrodes of the multiple P-side semiconductor elements 31 and the connection points of the wire 52. As a result, the balance of inductance between the source electrodes of the multiple P-side semiconductor elements 11 and the source electrodes of the multiple P-side semiconductor elements 31 is poor. In contrast, in this embodiment 1, the wire 53 can be used to improve the balance of inductance between the source electrodes of the multiple P-side semiconductor elements 11 and the source electrodes of the multiple P-side semiconductor elements 31.

[0046] Wire 54 electrically connects the N-side metal pattern 22 and the N-side metal pattern 42.

[0047] <Summary of Embodiment 1> In the semiconductor device according to this embodiment 1 described above, the wire 53, which is the first conductive part, crosses the N-side metal pattern 22 and the N-side metal pattern 42 in a plan view, and electrically connects the AC-side metal pattern 17 and the AC-side metal pattern 37. With this configuration, it is possible to reduce the oscillation of the main current and gate voltage between the first block circuit 1a and the second block circuit 2a during a short circuit while maintaining the size of the semiconductor device.

[0048] In this embodiment 1, the first P terminal 1P, the first N terminal 1N, the second N terminal 2N, and the second P terminal 2P are provided in this order along the first end 51a. With this configuration, the AC side metal patterns 17 and 37 can be arranged so as to sandwich the N side metal patterns 22 and 42. As a result, the wire 54 that electrically connects the N side metal pattern 22 and the N side metal pattern 42 can be shortened, and the inductance between the source electrode of the N side semiconductor element 12 and the source electrode of the N side semiconductor element 32 can be reduced. This reduces oscillation between the first block circuit 1a and the second block circuit 2a during a short circuit.

[0049] In the above explanation, the first conductive part was a wire 53, but it is not limited to this; for example, the first conductive part may be a metal plate.

[0050] <Embodiment 2> Figure 3 is a plan view showing the configuration of the semiconductor device according to this second embodiment.

[0051] In this second embodiment, the AC-side metal patterns 17 and 37 each have a first recess and a second recess that open towards the first end 51a in a plan view. Of the sides of the first and second recesses, the sides electrically connected to the P-side semiconductor element 11 and the P-side semiconductor element 31 each include a first convex portion 17a and a second convex portion 37a, which widen from the first end 51a to the second end 51b.

[0052] With this configuration, the width of the first protrusion 17a and the second protrusion 37a increases as you approach the first AC terminal 1AC and the second AC terminal 2AC, reducing the impedance of the AC-side metal patterns 17 and 37. Therefore, the effect of increasing the current flowing through the parts of the AC-side metal patterns 17 and 37 that are close to the first AC terminal 1AC and the second AC terminal 2AC can be suppressed, and the main current of the P-side semiconductor elements 11 and 31 can be increased.

[0053] In this second embodiment, the N-side metal patterns 22 and 42 widen in width from the second end 51b to the first end 51a in a plan view, and have a third protrusion 22a and a fourth protrusion 42a provided within the first recess and the second recess, respectively.

[0054] With this configuration, the width of the third protrusion 22a and the fourth protrusion 42a increases as you approach the first N terminal 1N and the second N terminal 2N, reducing the impedance of the N-side metal patterns 22 and 42. Therefore, the effect of increasing the current flowing through the portion of the N-side metal patterns 22 and 42 that is close to the first N terminal 1N and the second N terminal 2N can be suppressed, and thus the main current of the N-side semiconductor elements 12 and 32 can be increased.

[0055] Furthermore, the semiconductor device according to this second embodiment includes a plurality of wires 25 which are first conductive members included in the second conductive part, and a plurality of wires 45 which are second conductive members included in the third conductive part. The plurality of wires 25 straddle the third protrusion 22a in a plan view and electrically connect the portions of the AC-side metal pattern 17 that sandwich the third protrusion 22a, thereby improving the balance of inductance between the P-side semiconductor element 11 and the N-side semiconductor element 12. Similarly, the plurality of wires 45 straddle the fourth protrusion 42a in a plan view and electrically connect the portions of the AC-side metal pattern 37 that sandwich the fourth protrusion 42a, thereby improving the balance of inductance between the P-side semiconductor element 31 and the N-side semiconductor element 32.

[0056] In this second embodiment, the multiple wires 25 are arranged from the first end 51a toward the second end 51b, and their length decreases as they move from the first end 51a toward the second end 51b, thus reducing their inductance. This configuration allows for a good balance of inductance between the multiple P-side semiconductor elements 11 and the multiple N-side semiconductor elements 12. Similarly, the multiple wires 45 are arranged from the first end 51a toward the second end 51b, and their length decreases as they move from the first end 51a toward the second end 51b, thus reducing their inductance. This configuration allows for a good balance of inductance between the multiple P-side semiconductor elements 31 and the multiple N-side semiconductor elements 32.

[0057] In this second embodiment, multiple wires 16, which are third conductive members, are arranged from the first end 51a toward the second end 51b, and their length increases from the first end 51a toward the second end 51b. With this configuration, the balance of inductance between multiple P-side semiconductor elements 11 and multiple N-side semiconductor elements 12 can be improved. In addition, multiple wires 36, which are fourth conductive members, are arranged from the first end 51a toward the second end 51b, and their length increases from the first end 51a toward the second end 51b. With this configuration, the balance of inductance between multiple P-side semiconductor elements 31 and multiple N-side semiconductor elements 32 can be improved.

[0058] In the above description, the second and third conductive parts were wires 25 and 45, but they are not limited to these. For example, the second and third conductive parts may each be metal plates. In this embodiment 2, a configuration including wire 53 as the first conductive part was described, but wire 53 is not essential. Even without wire 53, in this embodiment 2, the oscillation during a short circuit in the first block circuit 1a can be reduced by wire 25, and the oscillation during a short circuit in the second block circuit 2a can be reduced by wire 45. Therefore, oscillation in each block during a short circuit can be reduced. In addition, the portion of the AC-side metal pattern 17 on the first end 51a side and the portion of the AC-side metal pattern 37 on the first end 51a side may be electrically connected by wire 46. This connection can reduce the inductance between the source electrode of the P-side semiconductor element 11 and the source electrode of the P-side semiconductor element 31, thereby reducing oscillation between the first block circuit 1a and the second block circuit 2a during a short circuit.

[0059] <Embodiment 3> Figure 4 is a plan view showing the configuration of the semiconductor device according to this third embodiment.

[0060] Generally, when wires are provided on the upper side of a semiconductor element for circuit connection, air bubbles may remain in the sealing material between the wires or between the semiconductor element and the wires when the sealing material is injected into the case 51. Therefore, in this embodiment 3, the wire 53 is provided in a plan view that avoids the N-side semiconductor element 12 and the N-side semiconductor element 32. With this configuration, the retention of air bubbles in the sealing material can be suppressed.

[0061] <Embodiment 4> Figure 5 is a plan view showing the configuration of the semiconductor device according to this embodiment 4.

[0062] In this embodiment 4, the wire 53 electrically connects the portion of the AC-side metal pattern 17 on the first end 51a side to the portion of the AC-side metal pattern 37 on the first end 51a side. With this configuration, similar to embodiment 1, the size of the semiconductor device can be maintained while reducing the inductance between the source electrode of the P-side semiconductor element 11 and the source electrode of the P-side semiconductor element 31, thereby reducing oscillation between blocks during a short circuit. Furthermore, the balance of inductance between the source electrodes of multiple P-side semiconductor elements 11 and the source electrodes of multiple P-side semiconductor elements 31 can be improved.

[0063] <Variation> As shown in Figure 6, the wire 53 according to Embodiment 1 and the wire 53 according to Embodiment 4 may be combined. Furthermore, this is not limited to this, and for example, the wire 53 according to Embodiments 2 and 3 may be combined with the wire 53 according to Embodiment 4.

[0064] Furthermore, it is possible to freely combine each embodiment and each variation, and to modify or omit each embodiment and each variation as appropriate.

[0065] The various aspects of this disclosure are summarized below as an appendix.

[0066] (Note 1) First insulating substrate and second insulating substrate, A first semiconductor element and a second semiconductor element are provided on the first insulating substrate side and connected in series with each other, A first metal pattern electrically connected to the first semiconductor element but not electrically connected to the second semiconductor element, a second metal pattern electrically connected to the first semiconductor element and the second semiconductor element, and a third metal pattern electrically connected to the second semiconductor element but not electrically connected to the first semiconductor element, A third semiconductor element and a fourth semiconductor element are provided on the second insulating substrate side and connected in series with each other, A fourth metal pattern electrically connected to the third semiconductor element but not electrically connected to the fourth semiconductor element, a fifth metal pattern electrically connected to the third semiconductor element and the fourth semiconductor element, and a sixth metal pattern electrically connected to the fourth semiconductor element but not electrically connected to the third semiconductor element, The first metal pattern, the second metal pattern, the third metal pattern, the fourth metal pattern, the fifth metal pattern, and the sixth metal pattern are electrically connected to the first P terminal, the first AC terminal, the first N terminal, the second P terminal, the second AC terminal, and the second N terminal, respectively. In the case where the first P terminal, the first N terminal, the second N terminal, and the second P terminal are provided in this order along the first end, and the first AC terminal and the second AC terminal are provided along the second end opposite to the first end, In a plan view, a first conductive portion spans the third metal pattern and the sixth metal pattern, electrically connecting the second metal pattern and the fifth metal pattern. A semiconductor device equipped with the following features.

[0067] (Note 2) First insulating substrate and second insulating substrate, A first semiconductor element and a second semiconductor element are provided on the first insulating substrate side and connected in series with each other, A first metal pattern electrically connected to the first semiconductor element but not electrically connected to the second semiconductor element, a second metal pattern electrically connected to the first semiconductor element and the second semiconductor element, and a third metal pattern electrically connected to the second semiconductor element but not electrically connected to the first semiconductor element, A third semiconductor element and a fourth semiconductor element are provided on the second insulating substrate side and connected in series with each other, A fourth metal pattern electrically connected to the third semiconductor element but not electrically connected to the fourth semiconductor element, a fifth metal pattern electrically connected to the third semiconductor element and the fourth semiconductor element, and a sixth metal pattern electrically connected to the fourth semiconductor element but not electrically connected to the third semiconductor element, The first metal pattern, the second metal pattern, the third metal pattern, the fourth metal pattern, the fifth metal pattern, and the sixth metal pattern are electrically connected to the first P terminal, the first AC terminal, the first N terminal, the second P terminal, the second AC terminal, and the second N terminal, respectively. In the case where the first P terminal, the first N terminal, the second N terminal, and the second P terminal are provided in this order along the first end, and the first AC terminal and the second AC terminal are provided along the second end opposite to the first end, Equipped with, The second metal pattern and the fifth metal pattern are In a plan view, it has a first recess and a second recess that open to the first end side, Of the sides of the first recess and the second recess, the sides electrically connected to the first semiconductor element and the third semiconductor element each include a first convex portion and a second convex portion, respectively, which widen from the first end to the second end. The third metal pattern and the sixth metal pattern are A semiconductor device having a width that increases from the second end to the first end in a plan view, and having a third protrusion and a fourth protrusion provided within the first recess and the second recess, respectively.

[0068] (Note 3) A second conductive portion that straddles the third protrusion in a plan view and electrically connects the portions of the second metal pattern that sandwich the third protrusion, In a plan view, the third conductive portion straddles the fourth protrusion and electrically connects the portions of the fifth metal pattern that sandwich the fourth protrusion. A semiconductor device further equipped with the features described in Appendix 2.

[0069] (Note 4) The second conductive portion includes a plurality of first conductive members arranged from the first end toward the second end, the length of which decreases as it moves from the first end toward the second end. The semiconductor device according to Appendix 3, wherein the third conductive portion includes a plurality of second conductive members arranged from the first end toward the second end, and whose length decreases as they move from the first end toward the second end.

[0070] (Note 5) A plurality of third conductive members, which electrically connect the first semiconductor element and the second metal pattern, are arranged from the first end toward the second end, and their length increases from the first end toward the second end. A semiconductor device according to any one of the appendices 2 to 4, wherein a plurality of fourth conductive members that electrically connect the second semiconductor element and the fifth metal pattern are arranged from the first end toward the second end, and the length of the conductive members increases from the first end toward the second end.

[0071] (Note 6) The semiconductor device according to Appendix 1, wherein, in a plan view, the first conductive portion is provided so as to avoid the second semiconductor element and the fourth semiconductor element.

[0072] (Note 7) The semiconductor device according to Appendix 1, wherein the first conductive portion electrically connects the portion of the second metal pattern on the first end side and the portion of the fifth metal pattern on the first end side. [Explanation of symbols]

[0073] 1 First insulating substrate, 2 Second insulating substrate, 11, 31 P-side semiconductor elements, 12, 32 N-side semiconductor elements, 13, 33 P-side metal patterns, 17, 37 AC-side metal patterns, 17a First protrusion, 37a Second protrusion, 22, 42 N-side metal patterns, 22a Third protrusion, 42a Fourth protrusion, 25, 45, 53 Wires, 51 Case, 51a First end, 51b Second end, 1AC First AC terminal, 1N First N terminal, 1P First P terminal, 2AC Second AC terminal, 2N Second N terminal, 2P Second P terminal.

Claims

1. First insulating substrate and second insulating substrate, A first semiconductor element and a second semiconductor element are provided on the first insulating substrate side and connected in series with each other, A first metal pattern electrically connected to the first semiconductor element but not electrically connected to the second semiconductor element, a second metal pattern electrically connected to the first semiconductor element and the second semiconductor element, and a third metal pattern electrically connected to the second semiconductor element but not electrically connected to the first semiconductor element, A third semiconductor element and a fourth semiconductor element are provided on the second insulating substrate side and connected in series with each other, A fourth metal pattern electrically connected to the third semiconductor element but not electrically connected to the fourth semiconductor element, a fifth metal pattern electrically connected to the third semiconductor element and the fourth semiconductor element, and a sixth metal pattern electrically connected to the fourth semiconductor element but not electrically connected to the third semiconductor element. The first metal pattern, the second metal pattern, the third metal pattern, the fourth metal pattern, the fifth metal pattern, and the sixth metal pattern are electrically connected to the first P terminal, the first AC terminal, the first N terminal, the second P terminal, the second AC terminal, and the second N terminal, respectively. In the case where the first P terminal, the first N terminal, the second N terminal, and the second P terminal are provided in this order along the first end, and the first AC terminal and the second AC terminal are provided along the second end opposite to the first end, In a plan view, a first conductive portion spans the third metal pattern and the sixth metal pattern, electrically connecting the second metal pattern and the fifth metal pattern. A semiconductor device equipped with the following features.

2. A semiconductor device according to claim 1, A semiconductor device in which, in a plan view, the first conductive portion is provided so as to avoid the second semiconductor element and the fourth semiconductor element.

3. A semiconductor device according to claim 1, The first conductive portion electrically connects the portion of the second metal pattern on the first end side and the portion of the fifth metal pattern on the first end side, in a semiconductor device.

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