Micro-optoelectronic chips, their fabrication methods, and applications

Abstract

This application discloses a micro-optoelectronic chip, a method for manufacturing the same, and its applications. The micro-optoelectronic chip includes a semiconductor structure layer comprising a first doped semiconductor layer, an active layer, and a second doped semiconductor layer sequentially stacked on a substrate; ion implantation regions distributed within the semiconductor structure layer, which are used to electrically isolate a plurality of optoelectronic chip structures arranged in an array within the semiconductor structure layer; insulating trenches established within the corresponding ion implantation regions and used to isolate the second doped semiconductor layers of at least two adjacent optoelectronic chip structures from each other; and light-shielding structures provided within the insulating trenches and used to block the transmission of at least light between any two adjacent optoelectronic chip structures via the second doped semiconductor layer. This application can effectively eliminate the optical crosstalk problem in a micro-optoelectronic chip array and provide excellent photoelectric conversion efficiency and display performance.

Description

Technical Field

[0001] (Related Application) This application claims priority based on the Chinese patent application with application number 2023104628269 and application title "Micro-Opto-Electronic Chip and Its Manufacturing Method and Applications", filed on April 26, 2023.

[0002] (Technical Field) This application relates to semiconductor opto-electronic devices, specifically to micro-opto-electronic chips and their manufacturing methods and applications, and belongs to the technical field of semiconductor device manufacturing.

Background Art

[0005] In recent years, researchers have pointed out that by adopting the ion implantation isolation method, it is possible to miniaturize the LED light-emitting area while simultaneously avoiding the degradation of Micro-LED device array performance caused by sidewall damage during the etching process, reducing the impact of trench structures on the manufacturing process cost and possible yield of Micro-LED device arrays, and furthermore, the fabricated Micro-LED device array has advantages such as planarization. However, the ion implantation isolation method also has clear drawbacks in the manufacturing process of Micro-LED device arrays. For example, Micro-LED device arrays manufactured using the ion implantation isolation method cannot achieve true optical isolation and are insufficient in reducing optical crosstalk between Micro-LED devices, which may affect the display performance of the final Micro-LED microdisplay device. In particular, as the dimensions of the Micro-LED chip and adjacent pitch are miniaturized, the dimensions of the ion implantation area also need to be reduced, but lateral light diffusion exacerbates the problem of optical crosstalk between adjacent Micro-LED chips, resulting in a further decrease in the chromaticity uniformity and resolution of the Micro-LED chips. [Overview of the project] [Problems that the invention aims to solve]

[0006] The main objective of this application is to provide a micro-optoelectronic chip, a method for manufacturing the same, and its applications, in order to overcome the shortcomings of the prior art. [Means for solving the problem]

[0007] To achieve the objectives of the aforementioned application, the technical solutions employed in this application include: One aspect of this application is the provision of a micro-optoelectronic chip, which is a micro-optoelectronic chip. circuit board and A semiconductor structural layer provided on the substrate, comprising a first doped semiconductor layer, an active layer, and a second doped semiconductor layer sequentially stacked on the substrate, The ion implantation regions and insulating trenches are distributed within the semiconductor structural layer, and the ion implantation regions are used to electrically isolate a plurality of optoelectronic chip structures arranged in an array within the semiconductor structural layer. An insulating trench is established within the ion implantation region, and the insulating trench is used to isolate at least two adjacent second doped semiconductor layers of the optoelectronic chip structure from each other. The present invention includes a light-shielding structure provided within the insulating trench, the light-shielding structure being used to block at least light from being transmitted between any two adjacent optoelectronic chip structures via the second doped semiconductor layer.

[0008] Another aspect of this application provides a method for fabricating a micro-optoelectronic chip, which includes the following steps: A semiconductor structural layer is formed on a substrate, and the semiconductor structural layer includes a first doped semiconductor layer, an active layer, and a second doped semiconductor layer sequentially stacked on the substrate. Ion implantation is performed on the semiconductor structural layer to form ion implantation regions within the semiconductor structural layer, thereby electrically isolating the multiple optoelectronic chip structures arranged in an array within the semiconductor structural layer. Etching is performed on the ion implantation region to form an insulating trench within the ion implantation region, thereby isolating at least two adjacent second doped semiconductor layers of the optoelectronic chip structure from each other. A light-shielding structure is provided within the insulating trench to block at least the transmission of light between any two adjacent optoelectronic chip structures via the second doped semiconductor layer.

[0009] Another aspect of this application provides applications for the micro-optoelectronic chip in the manufacture of photoelectric devices, which include, but are not limited to, display devices, micro-display devices, and the like. [Effects of the Invention]

[0010] Compared to conventional technologies, the technical solution of this application enables the manufacture of a micro-optoelectronic chip array using an ion implantation method while simultaneously eliminating the optical crosstalk problem between chips within the array, thereby enabling the micro-optoelectronic chip array to possess both excellent photoelectric conversion efficiency and display performance. [Brief explanation of the drawing]

[0011] The drawings accompanying the specification, which constitute part of this application, are used to provide a further understanding of this application, and the exemplary embodiments and descriptions herein are for interpretive purposes only and do not unduly limit this application.

[0012] [Figure 1] This is a schematic diagram of the Micro-LED chip of Example 1. [Figure 2] This is a schematic diagram of the epitaxial wafer structure of the Micro-LED chip in Example 1. [Figure 3] Figure 2 is a schematic diagram of the structure of a device formed after ion implantation into the epitaxial wafer shown. [Figure 4] This is a schematic diagram of the device structure formed after etching grooves into the ion implantation region of the device shown in Figure 3. [Figure 5] Figure 4 is a schematic diagram of the structure of a device formed by filling an insulating trench with a light-shielding structure. [Figure 6] This is a schematic diagram of the Micro-LED chip of Example 3. [Figure 7] This is a localized, enlarged schematic diagram of region A in Figure 6. [Figure 8] This is a reflectance test diagram of the insulating layer of Example 3 for light of different wavelengths. [Figure 9] This is a reflectance test diagram of the insulating layer of Example 4 for light of different wavelengths. [Figure 10] This is a reflectance test diagram of the insulating layer of Example 5 for light of different wavelengths. [Modes for carrying out the invention]

[0013] When considering the problems such as sidewall damage that exist when forming a micro-optoelectronic chip array using a conventional etching process, and defects such as optical crosstalk that exist when forming a micro-optoelectronic chip array using an ion implantation isolation method, the applicant has proposed a technical solution for this application through long-term research and practice. While reducing the influence of optical crosstalk that may affect the final display performance, it has the advantage of being beneficial to improving the photoelectric conversion efficiency by means of ion implantation isolation. Thereby, the optoelectronic performance of the micro-optoelectronic chip array is improved and its display performance is optimized. Hereinafter, the technical solution of this application will be described in more detail.

[0014] The micro-optoelectronic chips provided by some embodiments of this application are a substrate, a semiconductor structure layer provided on the substrate, the semiconductor structure layer including a first doped semiconductor layer, an active layer, and a second doped semiconductor layer sequentially laminated on the substrate, an ion implantation region and an insulating trench distributed in the semiconductor structure layer, the ion implantation region being used to electrically isolate a plurality of optoelectronic chip structures arranged in an array in the semiconductor structure layer, an insulating trench opened in the ion implantation region, the insulating trench being used to isolate at least the second doped semiconductor layers of any two adjacent optoelectronic chip structures from each other, including a light-shielding structure provided in the insulating trench, the light-shielding structure being used to at least block the transmission of light between any two adjacent optoelectronic chip structures through the second doped semiconductor layer.

[0015] In this application, a micro-optoelectronic chip array is realized using an ion implantation isolation method, insulating trenches are created in the ion implantation region, and a light-shielding structure is provided in the insulating trenches. This allows for better miniaturization of the chips, avoids chip sidewall damage and dangling bonds caused by the etching process, ensures and improves the quantum efficiency and usable area of ​​the chips, and provides superior optical and electrical characteristics. At the same time, it effectively prevents light transmission between adjacent chips in the micro-optoelectronic chip array, eliminating optical crosstalk and thereby improving the display performance of the micro-optoelectronic chip array, such as contrast ratio and brightness.

[0016] In one embodiment, the ion implantation region extends continuously from at least the top surface of the second doped semiconductor layer to the top surface of the active layer, the entire insulating trench is located within the ion implantation region, the bottom surface of the insulating trench is higher than the bottom surface of the ion implantation region and flush with the bottom surface of the second doped semiconductor layer, or lower than the bottom surface of the second doped semiconductor layer, and the top surface of the second doped semiconductor layer is the surface of the second doped semiconductor layer away from the substrate. By adopting a method in which the entire insulating trench is located within the ion implantation region, on the one hand, the risk of damage to the semiconductor material due to etching during the manufacturing process of the insulating trench can be further reduced, and on the other hand, the conductive filler material in the insulating trench can be electrically isolated from the semiconductor material in structural layers such as the second doped semiconductor layer and the active layer using the ion implantation region, thereby ensuring the normal operation performance of the device.

[0017] Here, the implanted ions for forming the ion implantation region include, but are not limited to, H ions, F ions, N ions, or O ions.

[0018] Here, the ion implantation regions may be one or more. Exemplarily, on the surface of the semiconductor structural layer, the ion implantation regions may be in a network structure, and the regions enclosed by each network are non-ion implantation regions, which are used to fabricate an optoelectronic chip structure. Correspondingly, the insulating trenches may be one or more, and exemplarily, they may exhibit a network structure on the surface of the semiconductor structural layer.

[0019] In this application, the ion implantation region is provided surrounding a corresponding non-ion implantation region, and a photoelectron chip structure is formed in this corresponding non-ion implantation region. The dimensions of both the ion implantation region and the photoelectron chip structure can be set according to actual needs. For example, the dimensions of the ion implantation region and the photoelectron chip structure are 1 μm to 50 μm. Here, the dimensions of the ion implantation region and the photoelectron chip structure mainly refer to the dimensions in a direction parallel to the layer plane of the semiconductor structure layer, and can be considered as their length and width or diameter.

[0020] Furthermore, the bottom end face of the ion implantation region is located inside the first doped semiconductor layer, the groove opening of the insulating trench is provided on the top end face of the second doped semiconductor layer, the groove bottom is located inside the first doped semiconductor layer, and the light-shielding structure is used to prevent at least light from being transmitted between any two adjacent optoelectronic chip structures via the second doped semiconductor layer and the active layer. Such a design can better block the transmission of light within the micro-optoelectronic chip array and more thoroughly overcome the optical crosstalk problem.

[0021] In this application, there is a certain distance between the inner wall of the insulating trench and the outer wall of the corresponding ion implantation region, that is, the ion implantation region has a certain wall thickness, which can be, for example, 100 nm to 20 μm.

[0022] In one embodiment, the micro optoelectronic chip further includes at least one insulating layer, the insulating layer continuously covering at least the sidewall of the insulating trench and located between the sidewall of the insulating trench and the light-shielding structure, and the light-shielding structure includes a metallic light-isolation layer continuously covering at least the insulating layer. By providing the insulating layer, protection of the sidewall of the insulating trench can be achieved on the one hand, and the conductive filler material in the insulating trench can be electrically isolated from the semiconductor material in structural layers such as the second doped semiconductor layer and the active layer on the other hand. Furthermore, by utilizing the insulating layer, when the metallic light-isolation layer is fabricated by a process such as vapor deposition, ion escape from the ion implantation area can be prevented, thereby better ensuring the operating performance of the device.

[0023] Here, the material of the insulating layer includes, but is not limited to, silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, gallium oxide, titanium oxide, or hafnium oxide.

[0024] Here, the material of the metallic light-isolation layer includes, but is not limited to, gold, titanium, aluminum, nickel, chromium, molybdenum, or copper. Preferably, the metallic light-isolation layer is formed from a metal or alloy having excellent reflectivity and conductivity, such as Al. The metallic light-isolation layer may be a single layer or a multilayer structure.

[0025] More preferably, the micro-optoelectronic chip includes a plurality of insulating layers having different refractive indices, the plurality of insulating layers being sequentially stacked on at least the sidewalls of the insulating trench, and in combination with the ion implantation region to form a distributed Bragg reflector structure (DBR). Here, the definition of the distributed Bragg reflector structure is well known in the art and is an optical thin film mainly composed of different stacking combinations of low refractive index material and high refractive index material. For example, the low refractive index material can be selected as SiO2, but is not limited thereto, and the high refractive index material can be selected as TiO2, Ta2O5, ZrO2, etc., but is not limited thereto, and the greater the difference in refractive index between the materials, the smaller the thickness required to achieve the desired reflectivity.

[0026] Specifically, after forming an ion-implanted region by ion implantation in a selected area of ​​the semiconductor structural layer, the refractive index of the semiconductor material also changes, and a photorefracting interface is formed by combining it with the semiconductor material in the chip. Then, by alternately stacking multiple insulating layers having different refractive indices on the sidewall of the insulating trench, a DBR structure can be formed. This not only enables sidewall passivation, which better guarantees the stability and long-term reliability of the electrical performance of the optoelectronic chip, but also, in cooperation with the light-shielding structure, optically isolates and totally reflects the light emitted from the sidewall of the optoelectronic chip, allowing more light from inside the optoelectronic chip to be emitted from the front, better resolving the problem of optical crosstalk and further improving the photoelectric conversion efficiency of the chip.

[0027] Preferably, the insulating layer is formed from a thermally conductive insulating material, for example, the thermal expansion coefficient of the thermally conductive insulating material is between the thermal expansion coefficient of the material constituting the metal-optic isolation layer and the thermal expansion coefficient of the material constituting the ion isolation region, and / or the thermally conductive insulating material has good adhesion to both the material constituting the metal-optic isolation layer and the material constituting the ion isolation region. This not only allows heat generated during chip operation to be transferred more quickly, but also strengthens the bond between the metal-optic isolation layer and the chip, preventing the metal-optic isolation layer from peeling off from the chip structure under the influence of heat generated after long-term chip operation. The thermally conductive insulating material can be selected from, but is not limited to, silicon nitride, aluminum nitride, and the like.

[0028] More preferably, the insulating layer for forming the distributed Bragg mirror structure is formed from the thermally conductive insulating material and possesses both light reflection and heat conduction functions.

[0029] In this application, the thickness of the insulating layer may be 5 nm to 500 nm.

[0030] In one embodiment, the micro-optoelectronic chip further includes a thermally conductive passivation layer, which covers the surface of the semiconductor structure layer and is thermally conductively connected to the metal photoisolation layer. By utilizing the thermally conductive passivation layer, not only can the surface of the micro-optoelectronic chip array be protected, but it can also cooperate with the metal photoisolation layer to form a heat conduction path, which is advantageous in reducing the temperature of the micro-optoelectronic chip array and ensuring its operational performance and stability.

[0031] Here, the material of the thermally conductive passivation layer includes, but is not limited to, aluminum nitride, boron nitride, or diamond.

[0032] In some cases, the insulating trench may be filled in a localized area of ​​the thermally conductive passivation layer and be in direct contact with the metallic photoisolation layer. In some cases, several windows may be opened in the thermally conductive passivation layer and used to fabricate electrodes corresponding to each optoelectronic chip structure.

[0033] In one embodiment, the metal light isolation layer is further extended to the surface of the semiconductor structure layer to form a current diffusion layer.

[0034] In this application, the material of the semiconductor structural layer includes a group III-V compound, preferably a group III nitride, for example, Al x In y Ga 1-x-y N, 1≧x≧0, 1≧y≧0, 1≧(1-xy)≧0. Here, the first doped semiconductor layer and the second doped semiconductor layer have different conductivity types; for example, the first doped semiconductor layer and the second doped semiconductor layer may be an N-type semiconductor layer and a P-type semiconductor layer, respectively, or vice versa. The active layer may be a multiple quantum well layer. Furthermore, the semiconductor structural layer may further include other structural layers known in the art, such as a buffer layer. The material, thickness, etc., of these structural layers can be selected or set according to methods known in the art, and will not be explained in detail here.

[0035] In this application, the substrate includes, but is not limited to, sapphire, Si, SiC, and GaN substrates.

[0036] In this application, the optoelectronic chip structure may include a Micro-LED chip structure, or it may be an LD (laser diode), a Mini-LED chip structure, or another light-emitting semiconductor structure, but is not limited to these.

[0037] A method for fabricating the micro-optoelectronic chip provided in some embodiments of this application includes the following steps: A semiconductor structural layer is formed on a substrate, and the semiconductor structural layer includes a first doped semiconductor layer, an active layer, and a second doped semiconductor layer sequentially stacked on the substrate. For example, the first doped semiconductor layer, the active layer, and the second doped semiconductor layer can be grown sequentially on the substrate through processes such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0038] Ion implantation is performed on the semiconductor structural layer to form an ion-implanted region within the semiconductor structural layer, thereby electrically isolating a plurality of photoelectron chip structures arranged in an array within the semiconductor structural layer. The implanted ions include, but are not limited to, H ions, F ions, N ions, or O ions. Generally, the ion-implanted region is provided surrounding a non-ion-implanted region, and the photoelectron chip structures are fabricated within the non-ion-implanted region. The dimensions of the ion-implanted and non-ion-implanted regions can be set to 1 μm to 50 μm. In order to increase the usable area of ​​the semiconductor structural layer, the dimensions of the non-ion-implanted region should be as large as possible, and the dimensions of the ion-implanted region should be as small as possible within a reasonable range. This reasonable range should satisfy the conditions that it is possible to achieve electrical isolation between adjacent chip structures and that it is advantageous for opening insulating trenches.

[0039] The ion implantation region is etched to form an insulating trench within the ion implantation region, thereby isolating at least two adjacent second doped semiconductor layers of the optoelectronic chip structure from each other.

[0040] A light-shielding structure is provided within the insulating trench to block at least the transmission of light between any two adjacent optoelectronic chip structures via the second doped semiconductor layer.

[0041] In one embodiment, the manufacturing method specifically includes the following steps: Ion implantation is performed on the semiconductor structure layer from at least the top surface of the second doped semiconductor layer, and the ion implantation depth is such that it reaches at least the top surface of the active layer, thereby forming the ion implantation region. Etching is performed on the ion implantation region, such that the etching depth is less than the ion implantation depth but reaches at least the bottom edge of the second doped semiconductor layer, thereby forming the insulating trench. Here, the top surface of the second doped semiconductor layer is the surface of the second doped semiconductor layer that is away from the substrate.

[0042] In one embodiment, the manufacturing method more specifically includes the following steps: Ion implantation is performed on the semiconductor structure layer from at least the top surface of the second doped semiconductor layer, such that the ion implantation depth reaches the interior of the first doped semiconductor layer, thereby forming the ion implantation region. Etching is performed on the ion implantation region such that the etching depth is less than the ion implantation depth but reaches the interior of the first doped semiconductor layer, thereby forming the insulating trench. Furthermore, a light-shielding structure is provided within the insulating trench to block the transmission of light between any two adjacent optoelectronic chip structures via the second doped semiconductor layer and the active layer.

[0043] In the embodiments described above, a pre-patterned ion implantation mask is provided on the surface of the semiconductor structural layer, and the ion implantation is performed using the mask. The ion implantation mask may be fabricated in advance and then transferred to the surface of the semiconductor structural layer, or it may be fabricated on the surface of the semiconductor structural layer after a photoresist layer or the like has been applied to the surface of the semiconductor structural layer, using a lithography process or the like. The pattern and dimensions of the ion implantation mask correspond to the shape and dimensions of the ion implantation area and can be set according to the actual needs. For example, the ion implantation area may be annular, square-annular, or other regular or irregular shapes.

[0044] In the embodiments described above, the ion implantation region can be etched using etching operations such as RIE, ECR, and ICP to form the aforementioned insulating trench. Furthermore, by providing an etching mask on the ion implantation region and performing the etching operation using the etching mask, the position, dimensions, and shape of the insulating trench can be controlled more precisely, and damage to the sidewalls of the chip structure can be avoided. More preferably, by controlling the distance between the opening edge on the etching mask and the edge of the ion implantation region to 100 nm to 20 μm, the distance between the inner wall of the etched insulating trench and the outer wall of the corresponding ion implantation region can be set to 100 nm to 20 μm. In actual production, by changing the dimensions of the ion implantation mask, etching mask, etc., the spacing of the high-resistance ion implantation region can be precisely adjusted, the characteristic dimensions of the chip can be flexibly set, and the manufacturing of devices ranging in size from a few micrometers to several hundred micrometers can be achieved.

[0045] In one embodiment, the manufacturing method further includes the following steps: At least one insulating layer is fabricated such that the insulating layer continuously covers at least the side walls of the insulating trench. A metallic light-isolating layer is fabricated, and the light-shielding structure is formed such that the metallic light-isolating layer continuously covers at least the insulating layer.

[0046] In the embodiments described above, the insulating layer can be grown by a process such as atomic layer deposition (ALD), and its thickness can be set to 5 nm to 500 nm.

[0047] More preferably, the manufacturing method specifically includes the following steps: forming a plurality of insulating layers having different refractive indices, which are alternately stacked on at least the sidewall of the insulating trench, such that the plurality of insulating layers, in combination with the ion implantation region, form a distributed Bragg mirror structure.

[0048] More preferably, the insulating layer is formed on at least the side walls of the insulating trench using a thermally conductive insulating material, and the thermal expansion coefficient of the thermally conductive insulating material is between the thermal expansion coefficient of the material constituting the metal light isolation layer and the thermal expansion coefficient of the material constituting the ion isolation region.

[0049] In one embodiment, a thermally conductive passivation layer is formed on the surface of the semiconductor structural layer, and the thermally conductive passivation layer and the metal photoisolation layer are connected in a thermally conductive manner. The thermally conductive passivation layer may be formed by growing it through a process such as atomic layer deposition (ALD). Preferably, the entire thermally conductive passivation layer may cover the surface of the semiconductor structural layer. Of course, if it is necessary to fabricate electrodes or the like, corresponding windows or the like may be opened in the thermally conductive passivation layer.

[0050] In one embodiment, the metal light isolation layer may be stretched to cover the surface of the semiconductor structure layer, forming a current diffusion layer, which is advantageous for improving the uniformity of light emission of the micro-optoelectronic chip array.

[0051] Here, the materials for the semiconductor structural layer, insulating layer, metal light isolation layer, thermal conductive insulating material, and thermal conductive passivation layer are as described above and will not be explained again here.

[0052] The manufacturing method provided in this application is simple, reliable, and compatible with conventional process technologies, and can simultaneously improve the usable area of ​​the chip, reduce the sidewall damage effect of the material, eliminate optical crosstalk problems in the device, and improve the luminous efficiency of the device.

[0053] Some embodiments of this application further provide photoelectric devices comprising the aforementioned micro-optoelectronic chips.

[0054] Some embodiments of this application further provide a method for fabricating a photoelectric device, which includes the following steps: The aforementioned micro-optical chip was fabricated, Furthermore, electrodes are fabricated, and these electrodes are electrically connected to a first doped semiconductor layer and a second doped semiconductor layer in the optoelectronic chip structure, respectively, to form, for example, an ohmic contact. The electrodes include P-type electrodes and N-type electrodes.

[0055] For example, the photoelectric device may be a Micro-LED device. According to the manufacturing method, it is possible to manufacture smaller Micro-LED chips with superior optical and electrical characteristics more conveniently, quickly, and at a lower cost, effectively improving their resolution and brightness, and obtaining better display performance.

[0056] Furthermore, some embodiments of this application further provide Micro-LED devices, such as Micro-LED display devices, that include the aforementioned micro-optoelectronic chips.

[0057] The embodiments of this application will be described below using specific examples, but those skilled in the art should understand that other advantages and effects of this application can be easily grasped from the disclosures herein. This application may be implemented or applied in other different specific embodiments, and each detail herein may be modified or altered without departing from the spirit of this application based on different viewpoints and applications.

[0058] In describing the embodiments of this application in detail, for the sake of clarity, the cross-sectional views showing the device structure are shown with localized magnification rather than general proportions, and the schematic diagrams are merely illustrative and do not limit the scope of protection of this application. Furthermore, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0059] For the sake of clarity, spatial terms such as "below," "downward," "lower than," "underside," "upward," and "top" may be used here to describe the relationship between one element or feature and another shown in the attached drawings. It should be understood that these spatial terms are intended to include directions other than those described in the attached drawings for the device in use or operation. Furthermore, if a layer lies "between" two layers, there may be only one layer between the two layers, or there may be one or more layers interposed in between.

[0060] In the context of this application, the structure described in which the first feature is "on top of" the second feature may include embodiments in which the first and second features are in direct contact, or may include embodiments in which another feature is formed between the first and second features, so as to whether the first and second features are in direct contact.

[0061] It should be noted that the drawings provided in this embodiment are used solely to illustrate the basic concept of this application. Therefore, only components relevant to this application are shown in the drawings, and they are not drawn according to the number, shape, and dimensions of components in actual implementation. In actual implementation, the form, number, and proportion of each component can be arbitrarily deviated, and the arrangement of those components may also be more complex.

[0062] [Example 1] Referring to Figure 1, the embodiment provides a Micro-LED chip comprising a sapphire substrate 10 and a semiconductor structural layer 11, the semiconductor structural layer comprising an AlN buffer layer 111, an N-type GaN layer 112, a multiple quantum well active layer 113, and a P-type GaN layer 114 sequentially grown on the substrate. The semiconductor structural layer includes ion-implanted regions 115 and a plurality of non-ion-implanted regions distributed along the planar direction of the layer, any two adjacent non-ion-implanted regions being electrically isolated by the ion-implanted region, one Micro-LED chip structure 116 being fabricated within each non-ion-implanted region, each Micro-LED chip structure 116 functioning as a single pixel point, forming a Micro-LED chip structure within the semiconductor structural layer. Simultaneously, insulating trenches 117 are further opened within the ion-implanted regions, used to isolate the P-type GaN layers and multiple quantum well active layers of two adjacent Micro-LED chip structures from each other. Furthermore, a light-shielding structure is provided within the insulating trench to prevent light from being transmitted between two adjacent Micro-LED chip structures via the P-type GaN layer 114 and the multiple quantum well active layer 113. Here, the light-shielding structure includes one or multiple layers of opaque metallic light-isolation layer 12, the material of which includes gold (Au), titanium (Ti), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), copper (Cu), etc. or alloys thereof, and the metallic light-isolation layer covers the inner wall of the insulating trench and is mainly used to block and reflect light reflected from the multiple quantum well active layer, and is used to block the light transmission path between adjacent Micro-LED chip structures. A single or multilayer insulating layer 13 is provided between the metal light isolation layer and the inner wall of the insulating trench. The insulating layer material includes, but is not limited to, silicon oxide (SiO2), silicon nitride (SiN), aluminum nitride (AlN), aluminum oxide (Al2O3), gallium oxide (Ga2O3), titanium oxide (TiO2), or hafnium oxide (HfO2). Its thickness is 5 nm to 500 nm, and it is mainly used for passivation of the inner wall of the insulating trench and for electrical isolation between the metal light isolation layer and the inner wall of the insulating trench. More preferably, the insulating layer material can be selected from materials with high thermal conductivity, such as aluminum nitride or silicon nitride.In some cases, the insulating trench may be completely filled using a metallic light isolation layer and an insulating layer. More preferably, the metallic light isolation layer is continuously stretched to cover the surface of the semiconductor structure layer, forming a current diffusion layer to improve current injection efficiency and uniformity. Furthermore, the surface of the semiconductor structure layer is covered with a continuous thermally conductive passivation layer 14, which is in direct contact with the metallic light isolation layer, and its material includes, but is not limited to, aluminum nitride (AlN) boron nitride (BN), diamond monocrystalline material or mixture thereof, and the thermally conductive passivation layer not only performs surface passivation of the metallic light isolation layer but also serves as a thermal conductive layer for the Micro-LED.

[0063] Referring to Figures 2 to 5, the method for fabricating the Micro-LED chip includes the following steps: Using methods such as S1, MOCVD, MBE, and PECVD, an AlN buffer layer 111, an N-type GaN layer 112, a multiple quantum well active layer 113, and a P-type GaN layer 114 are sequentially grown on a sapphire substrate to obtain the epitaxial wafer shown in Figure 2.

[0064] In step S2, an ion implantation mask is formed by a process such as lithography, and the material of the ion implantation mask includes, but is not limited to, photoresist, silicon oxide, silicon nitride, and metal. Using the ion implantation mask as a barrier layer, ion implantation is performed on the semiconductor structural layer of the epitaxial wafer to adjust the area and / or shape of the light-emitting region of the Micro-LED chip structure. The depth of ion implantation is to pass through at least the P-type GaN layer and preferably reach the interior of the N-type GaN layer 112, and the types of implanted ions include, but are not limited to, H ions, F ions, N ions, O ions, etc. The dimensions of the finally formed ion implantation region 115 are 1 μm to 50 μm, and the dimensions of the non-ion implantation region 118 are 1 μm to 50 μm. In a top view, the ion implantation region 115 is preferably provided surrounding the non-ion implantation region 118, and each non-ion implantation region 118 is used to form one Micro-LED chip structure. In this step, the finally obtained device structure is shown in Figure 3. By employing electrical separation using ion implantation in this step, there are advantages such as less damage and higher control accuracy compared to electrical separation methods using etching processes.

[0065] In step S3, an etching mask is placed on the ion implantation region 115, and through holes are created on the etching mask. The dimensions of the through holes are smaller than the dimensions of the ion implantation region, and more preferably, the distance between the edge of the through hole and the edge of the ion implantation region is 100 nm to 20 μm, thereby minimizing chip sidewall damage as much as possible. Furthermore, using a dry etching process such as atomic layer etching (ALE), ion beam etching (IBE), or inductively coupled plasma etching (ICP), etching is performed on the ion implantation region through the through holes in the etching mask. The etching depth is smaller than or equal to the ion implantation depth, preferably smaller than the ion implantation depth, and particularly preferably penetrates into the interior of the N-type GaN layer 112 to form an insulating trench 117. The device structure finally obtained in this step is shown in Figure 4. By performing dry etching within the ion implantation region, this step effectively avoids sidewall damage caused by the etching process, improves photoelectric conversion efficiency, and narrows the formed etching isolation region, in particular effectively isolating light between Micro-LED pixels and eliminating the optical crosstalk effect.

[0066] S4, at least one or multiple insulating layers 14 are formed on the sidewalls of the insulating trench 117 by a process such as atomic layer deposition (ALD), and their thickness may be 5 nm to 500 nm. In some cases, the insulating layer may be used to cover the entire inner wall of the insulating trench 117. Furthermore, one or multiple layers of opaque metallic material are deposited on the insulating layer to form a metallic light isolation layer 12, and the light-shielding structure mainly formed by this metallic light isolation layer 12 can effectively reduce optical crosstalk between each pixel point. Here, the metallic light isolation layer 12 may be used to completely fill the insulating trench 117. The device structure finally obtained in this step is shown in Figure 5.

[0067] In S5, a non-metallic thermal conductive material is deposited on the metallic light isolation layer 12 to form a thermal conductive passivation layer 14, which performs surface passivation of the metallic light isolation layer 12 and simultaneously functions as a thermal conductive layer for the Micro-LED chip structure. More preferably, the thermal conductive passivation layer 14 is continuously stretched to cover the device surface, ultimately obtaining the Micro-LED chip shown in Figure 1.

[0068] [Example 2] The Micro-LED chip provided in this embodiment is basically the same as that in Embodiment 1, with the following differences: its insulating layer is formed from aluminum nitride with high thermal conductivity, while the metal-optical isolation layer is formed from metallic aluminum. The insulating layer, on the one hand, provides passivation to the side walls of its insulating trench and electrical isolation between the metal-optical isolation layer and the inner walls of the insulating trench, and on the other hand, it functions as a transition layer between the ion-implanted region of the doped GaN material and the metal-optical isolation layer, allowing the metal-optical isolation layer to bond firmly to the insulating trench. At the same time, together with the insulating layer, it forms a heat conduction path, which is advantageous in rapidly dissipating the heat generated during the operation of the Micro-LED chip, ensuring its operational stability and improving its operational performance.

[0069] [Example 3] The Micro-LED chip provided in this embodiment is basically the same as that in Embodiment 1, with the following differences: the Micro-LED chip structure is a blue LED chip structure with a central wavelength of approximately 450 nm. Referring to Figures 6 and 7, the insulating layer 13' is a structure of eight pairs of TiO2 / SiO2 composite layers, with a total thickness of approximately 895.2 nm. The TiO2 and SiO2 layers are alternately stacked to form a distributed Bragg mirror structure, with each TiO2 layer having a thickness of approximately 41.1 nm and each SiO2 layer having a thickness of approximately 70.8 nm. The reflectivity of the insulating layer 13' for light of different wavelengths is shown in Figure 8. It works in cooperation with a metallic light isolation layer (e.g., a metallic aluminum layer) to more thoroughly eliminate the problem of optical crosstalk, while also functioning as a transition layer between the ion implantation region of the doped GaN material and the metallic light isolation layer, strengthening the bonding force between the metallic light isolation layer and the insulating trench groove wall, and working in cooperation with the metallic light isolation layer to construct a new heat conduction path for the Micro-LED chip.

[0070] [Example 4] The Micro-LED chip provided in this embodiment is basically the same as that in Embodiment 3, with the following differences: the Micro-LED chip structure is a green light LED chip structure with a central wavelength of approximately 550 nm; the insulating layer is an 8-pair TiO2 / SiO2 composite layer structure with a total thickness of approximately 1112.0 nm; the TiO2 and SiO2 layers are alternately stacked to form a distributed Bragg mirror structure, with each TiO2 layer having a thickness of approximately 46.9 nm and each SiO2 layer having a thickness of approximately 92.1 nm. The reflectivity of the insulating layer for light of different wavelengths is shown in Figure 9. The insulating layer works in cooperation with the metal light isolation layer to better resolve optical crosstalk problems, improve the heat dissipation performance of the device, and enhance the photoelectric conversion efficiency and stability of the device.

[0071] [Example 5] The Micro-LED chip provided in this embodiment is basically the same as that in Embodiment 3, with the following differences: the Micro-LED chip structure is a red light LED chip structure with a central wavelength of approximately 660 nm; the insulating layer is an 8-pair TiO2 / SiO2 composite layer structure with a total thickness of approximately 1350.4 nm; the TiO2 and SiO2 layers are alternately stacked to form a distributed Bragg mirror structure, with each TiO2 layer having a thickness of approximately 54.6 nm and each SiO2 layer having a thickness of approximately 114.2 nm. The reflectivity of the insulating layer for light of different wavelengths is shown in Figure 10. The insulating layer works in cooperation with the metal light isolation layer to better resolve the problem of optical crosstalk, improve the heat dissipation performance of the device, and enhance the photoelectric conversion efficiency and stability of the device.

[0072] The above embodiments are illustrative in illustrating the principles and effects of this application and do not limit it. Those skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations obtained by those skilled in the art without departing from the spirit and technical concept disclosed herein are covered by the claims of this application.

[0073] (Note) (Note 1) circuit board and A semiconductor structural layer provided on the substrate, wherein the semiconductor structural layer includes a first doped semiconductor layer, an active layer, and a second doped semiconductor layer sequentially stacked on the substrate, The semiconductor structural layer comprises ion implantation regions and insulating trenches, and the ion implantation regions are used to electrically isolate multiple optoelectronic chip structures arranged in an array within the semiconductor structural layer. An insulating trench is established within the ion implantation region, wherein the insulating trench is used to isolate at least two adjacent second doped semiconductor layers of photoelectron chip structures from each other. A micro-optoelectronic chip characterized by including a light-shielding structure provided within the insulating trench, wherein the light-shielding structure is used to block the transmission of light between any two adjacent optoelectronic chip structures via the second doped semiconductor layer.

[0074] (Note 2) The ion implantation region extends continuously from at least the top surface of the second doped semiconductor layer to the top surface of the active layer, the entire insulating trench is located within the ion implantation region, the bottom surface of the insulating trench is higher than the bottom surface of the ion implantation region and flush with the bottom surface of the second doped semiconductor layer, or lower than the bottom surface of the second doped semiconductor layer, and the top surface of the second doped semiconductor layer is the surface away from the substrate of the second doped semiconductor layer. Preferably, the bottom end face of the ion implantation region is located inside the first doped semiconductor layer, the groove opening of the insulating trench is provided on the top end face of the second doped semiconductor layer, the groove bottom is located inside the first doped semiconductor layer, and the light-shielding structure is used to block at least light from being transmitted between any two adjacent optoelectronic chip structures via the second doped semiconductor layer and the active layer, as described in Appendix 1.

[0075] (Note 3) The micro optoelectronic chip according to Appendix 2, further comprising at least one insulating layer, wherein the insulating layer continuously covers at least the sidewall of the insulating trench and is located between the sidewall of the insulating trench and the light-shielding structure, and the light-shielding structure includes a metallic light-isolation layer that continuously covers at least the insulating layer.

[0076] (Note 4) The micro-photoelectron chip includes a plurality of insulating layers having different refractive indices, the plurality of insulating layers are sequentially stacked on at least the sidewalls of the insulating trench, and together with the ion implantation region, form a distributed Bragg mirror structure. and / or, the insulating layer is formed from a thermally conductive insulating material, the thermal expansion coefficient of the thermally conductive insulating material is between the thermal expansion coefficient of the material constituting the metal light isolation layer and the thermal expansion coefficient of the material constituting the ion isolation region, and / or, the thermally conductive insulating material has good adhesion to both the material constituting the metal light isolation layer and the material constituting the ion isolation region. and / or the micro-optoelectronic chip further comprises a thermally conductive passivation layer, the thermally conductive passivation layer covering the surface of the semiconductor structure layer and being thermally conductively connected to the metallic photoisolation layer. and / or, the metal light isolation layer is further extended to the surface of the semiconductor structure layer to form a current diffusion layer, Preferably, the insulating layer material includes silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, gallium oxide, titanium oxide, or hafnium oxide. Preferably, the material of the metallic light-isolating layer includes gold, titanium, aluminum, nickel, chromium, molybdenum, or copper. Preferably, the heat-conducting insulating material comprises aluminum nitride, boron nitride, or diamond, characterized in that the micro-optoelectronic chip is as described in Appendix 3.

[0077] (Note 5) A micro-photoelectronic chip according to any one of appendices 1 to 4, characterized in that the ion implantation region is provided surrounding a corresponding photoelectronic chip structure, the dimensions of the ion implantation region and the photoelectronic chip structure are 1 μm to 50 μm, and / or the implanted ions for forming the ion implantation region include H ions, F ions, N ions or O ions, and / or the distance between the inner wall of the insulating trench and the outer wall of the corresponding ion implantation region is 100 nm to 20 μm, and / or the material of the semiconductor structure layer includes a group III-V compound, preferably a group III nitride, and / or the photoelectronic chip structure includes a Micro-LED chip structure.

[0078] (Note 6) A method for fabricating a micro-optoelectronic chip, comprising the following steps: A semiconductor structural layer is formed on a substrate, and the semiconductor structural layer includes a first doped semiconductor layer, an active layer, and a second doped semiconductor layer sequentially stacked on the substrate. Ion implantation is performed on the semiconductor structural layer to form ion implantation regions within the semiconductor structural layer, thereby electrically isolating the multiple optoelectronic chip structures arranged in an array within the semiconductor structural layer. Etching is performed on the ion implantation region to form an insulating trench within the ion implantation region, thereby isolating at least two adjacent second doped semiconductor layers of the optoelectronic chip structure from each other. A manufacturing method characterized by providing a light-shielding structure within the insulating trench to block at least light from being transmitted between any two adjacent optoelectronic chip structures via the second doped semiconductor layer.

[0079] (Note 7) The aforementioned manufacturing method specifically includes the following steps: Ion implantation is performed on the semiconductor structure layer from at least the top surface of the second doped semiconductor layer, such that the ion implantation depth reaches at least the top surface of the active layer, thereby forming the ion implantation region. Etching is performed on the ion implantation region, such that the etching depth is less than the ion implantation depth but reaches at least the bottom edge of the second doped semiconductor layer, thereby forming the insulating trench. Here, the top surface of the second doped semiconductor layer is the surface of the second doped semiconductor layer that is away from the substrate. Preferably, the manufacturing method includes the following steps: Ion implantation is performed on the semiconductor structure layer from at least the top surface of the second doped semiconductor layer, such that the ion implantation depth reaches the interior of the first doped semiconductor layer, thereby forming the ion implantation region. Etching is performed on the ion implantation region such that the etching depth is less than the ion implantation depth but reaches the interior of the first doped semiconductor layer, thereby forming the insulating trench. The manufacturing method according to Appendix 6, further characterized by providing a light-shielding structure within the insulating trench to block the transmission of light between any two adjacent optoelectronic chip structures via the second doped semiconductor layer and the active layer.

[0080] (Note 8) The above manufacturing method further includes the following steps: At least one insulating layer is fabricated such that the insulating layer continuously covers at least the side walls of the insulating trench. A metallic light-isolating layer is fabricated, and the light-shielding structure is formed such that the metallic light-isolating layer continuously covers at least the insulating layer. Preferably, the manufacturing method includes the following steps: At least on the side walls of the insulating trench, a plurality of insulating layers having different refractive indices are formed, stacked alternately, and the plurality of insulating layers, in combination with the ion implantation region, form a distributed Bragg mirror structure. and / or, the insulating layer is formed on at least the sidewall of the insulating trench by a thermally conductive insulating material, wherein the thermal expansion coefficient of the thermally conductive insulating material is between the thermal expansion coefficient of the material constituting the metal light isolation layer and the thermal expansion coefficient of the material constituting the ion isolation region, and / or, the thermally conductive insulating material has good adhesion to both the material constituting the metal light isolation layer and the material constituting the ion isolation region. and / or, a thermally conductive passivation layer is formed on the surface of the semiconductor structural layer, and the thermally conductive passivation layer and the metal light isolation layer are connected in a thermally conductive manner. and / or, the metal light isolation layer is stretched to cover the surface of the semiconductor structure layer, forming a current diffusion layer. Preferably, the material of the insulating layer comprises silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, gallium oxide, titanium oxide, or hafnium oxide, and / or the material of the metallic light isolation layer comprises gold, titanium, aluminum, nickel, chromium, molybdenum, or copper, and / or the material of the thermally conductive passivation layer comprises aluminum nitride, boron nitride, or diamond, as described in Appendix 7.

[0081] (Note 9) The manufacturing method according to any one of the appendices 6 to 8, characterized in that the ion implantation region is provided surrounding the corresponding photoelectron chip structure, the dimensions of the ion implantation region and the photoelectron chip structure are 1 μm to 50 μm, and / or the ions used in the ion implantation process include H ions, F ions, N ions, or O ions, and / or the distance between the inner wall of the insulating trench and the outer wall of the corresponding ion implantation region is 100 nm to 20 μm, and / or the material of the semiconductor structure layer includes a group III-V compound, preferably a group III nitride, and / or the photoelectron chip structure includes a Micro-LED chip structure.

[0082] (Note 10) A Micro-LED device characterized by including a micro-photoelectronic chip as described in any one of the appendices 1 to 5.

Claims

1. circuit board and A semiconductor structural layer provided on the substrate, wherein the semiconductor structural layer includes a first doped semiconductor layer, an active layer, and a second doped semiconductor layer sequentially stacked on the substrate, An ion implantation region distributed within the semiconductor structural layer, wherein the ion implantation region extends continuously from at least the top surface of the second doped semiconductor layer to the top surface of the active layer, and is used to electrically isolate a plurality of optoelectronic chip structures arranged in an array within the semiconductor structural layer. An insulating trench is established within the ion implantation region, the insulating trench is used to isolate at least two adjacent second doped semiconductor layers of optoelectronic chip structures from each other, the entire insulating trench is located within the corresponding ion implantation region, there is a certain distance between the inner wall of the insulating trench and the outer wall of the corresponding ion implantation region, the bottom surface of the insulating trench is higher than the bottom edge surface of the corresponding ion implantation region and is flush with the bottom edge surface of the second doped semiconductor layer, or lower than the bottom edge surface of the second doped semiconductor layer, and the top edge surface of the second doped semiconductor layer is the surface of the second doped semiconductor layer away from the substrate. A plurality of insulating layers that continuously cover at least the side walls of the insulating trench, wherein the plurality of insulating layers have different refractive indices, are sequentially stacked on the side walls of the insulating trench, and, in combination with corresponding ion implantation regions, form a distributed Bragg mirror structure. A micro-optoelectronic chip characterized by comprising a light-shielding structure provided within the insulating trench, wherein the light-shielding structure is used to block the transmission of light between any two adjacent optoelectronic chip structures via the second doped semiconductor layer, and the light-shielding structure includes a light-shielding structure that includes at least a metallic light-isolation layer that continuously covers the insulating layer.

2. The micro optoelectronic chip according to claim 1, wherein the bottom end face of the ion implantation region is located inside the first doped semiconductor layer, the groove opening of the insulating trench is provided on the top end face of the second doped semiconductor layer, the groove bottom is located inside the first doped semiconductor layer, and the light-shielding structure is used to block at least light from being transmitted between any two adjacent optoelectronic chip structures via the second doped semiconductor layer and the active layer.

3. The micro optoelectronic chip according to Claim 1, characterized in that the material of the insulating layer includes silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, gallium oxide, titanium oxide, or hafnium oxide.

4. The micro-optoelectronic chip according to claim 1, further comprising a thermally conductive passivation layer, the thermally conductive passivation layer covering the surface of the semiconductor structure layer and being thermally conductively connected to the metallic photoisolation layer.

5. The micro optoelectronic chip according to claim 1, characterized in that the metallic light isolation layer is further extended to the surface of the semiconductor structure layer to form a current diffusion layer.

6. The micro-optical chip according to claim 1, characterized in that the material of the metallic light isolation layer includes gold, titanium, aluminum, nickel, chromium, molybdenum, or copper.

7. The micro-photoelectron chip according to claim 1, characterized in that the ion implantation region is provided surrounding the corresponding photoelectron chip structure, and the dimensions of the ion implantation region and the photoelectron chip structure are 1 μm to 50 μm.

8. The micro optoelectronic chip according to claim 1, characterized in that the implanted ions for forming the ion implantation region include H ions, F ions, N ions, or O ions.

9. The micro optoelectronic chip according to claim 1, characterized in that the distance between the inner wall of the insulating trench and the outer wall of the corresponding ion implantation region is 100 nm to 20 μm.

10. The micro optoelectronic chip according to claim 1, characterized in that the material of the semiconductor structural layer contains a group III-V compound.

11. The micro optoelectronic chip according to claim 10, characterized in that the material of the semiconductor structural layer is a group III nitride.

12. The micro-optoelectronic chip according to claim 1, characterized in that the optoelectronic chip structure includes a micro-LED chip structure.

13. A method for fabricating a micro-optoelectronic chip, comprising the following steps: A semiconductor structural layer is formed on a substrate, and the semiconductor structural layer includes a first doped semiconductor layer, an active layer, and a second doped semiconductor layer sequentially stacked on the substrate. Ion implantation is performed on the semiconductor structure layer from at least the top surface of the second doped semiconductor layer, and the ion implantation depth reaches at least the top surface of the active layer, thereby forming an ion implantation region within the semiconductor structure layer, electrically isolating a plurality of optoelectronic chip structures arranged in an array within the semiconductor structure layer, and the top surface of the second doped semiconductor layer is the surface of the second doped semiconductor layer away from the substrate. Etching is performed on the ion implantation region such that the etching depth is less than the ion implantation depth but reaches at least the bottom edge of the second doped semiconductor layer, thereby forming an insulating trench within the ion implantation region, and there is a certain distance between the inner wall of the insulating trench and the outer wall of the ion implantation region, thereby isolating at least two adjacent second doped semiconductor layers of any two photoelectron chip structures from each other. At least a plurality of insulating layers having different refractive indices are formed alternately on the sidewall of the insulating trench, the insulating layers at least continuously cover the sidewall of the insulating trench, and the plurality of insulating layers and the ion implantation region combine to form a distributed Bragg reflector structure. A manufacturing method characterized by creating a metallic light isolation layer, the metallic light isolation layer covering the insulating layer at least continuously, forming a light-shielding structure within the insulating trench, and blocking at least the transmission of light between any two adjacent optoelectronic chip structures via the second doped semiconductor layer.

14. Specifically includes the following steps: Ion implantation is performed on the semiconductor structure layer from at least the top surface of the second doped semiconductor layer, so that the ion implantation depth reaches the interior of the first doped semiconductor layer, thereby forming the ion implantation region. Etching is performed on the ion implantation region, such that the etching depth is less than the ion implantation depth but reaches the interior of the first doped semiconductor layer, thereby forming the insulating trench. The manufacturing method according to claim 13, further comprising providing the light-shielding structure within the insulating trench to block the transmission of light between any two adjacent optoelectronic chip structures via the second doped semiconductor layer and the active layer.

15. The manufacturing method according to claim 13, characterized in that the material of the insulating layer includes silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, gallium oxide, titanium oxide, or hafnium oxide.

16. The manufacturing method according to claim 13, further comprising the step of forming a thermally conductive passivation layer on the surface of the semiconductor structural layer and thermally conductively connecting the thermally conductive passivation layer and the metal light isolation layer.

17. The method for manufacturing according to claim 16, characterized in that the material of the thermally conductive passivation layer includes aluminum nitride, boron nitride, or diamond.

18. The manufacturing method according to claim 13, further comprising the step of stretching the metallic light isolation layer until it covers the surface of the semiconductor structure layer to form a current diffusion layer.

19. The manufacturing method according to claim 13, characterized in that the material of the metallic light-isolating layer includes gold, titanium, aluminum, nickel, chromium, molybdenum, or copper.

20. The manufacturing method according to claim 13, characterized in that the ion implantation region is provided surrounding the corresponding photoelectron chip structure, and the dimensions of the ion implantation region and the photoelectron chip structure are 1 μm to 50 μm.

21. The method for production according to claim 13, characterized in that the ions used in the ion implantation process include H ions, F ions, N ions, or O ions.

22. The method for manufacturing according to claim 13, characterized in that the distance between the inner wall of the insulating trench and the outer wall of the corresponding ion implantation region is 100 nm to 20 μm.

23. The method for manufacturing according to claim 13, characterized in that the material of the semiconductor structural layer includes a group III-V compound.

24. The method for manufacturing according to claim 23, characterized in that the material of the semiconductor structural layer is a group III nitride.

25. The method for manufacturing according to claim 13, characterized in that the photoelectronic chip structure includes a micro-LED chip structure.

26. A micro-LED device characterized by including a micro-photoelectron chip according to any one of claims 1 to 12.

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