Silicon carbide semiconductor equipment

Abstract

To provide a silicon carbide semiconductor device which can achieve a target value of THB test and has the high reliability.SOLUTION: A silicon carbide semiconductor device includes an active region in which the main current flows and a termination region which surrounds the active region on a first conductive type silicon carbide semiconductor substrate. The silicon carbide semiconductor device includes, in the termination region, a second conductive type first semiconductor region 19, a second conductive type second semiconductor region 28 which is provided on the outer side of the first semiconductor region 19 and includes a plurality of second conductive type first subregions with the same impurity density as the first semiconductor region 19 in a region with the lower impurity density than the first semiconductor region 19, a second conductive type third semiconductor region 20 which is provided on the outer side of the second semiconductor region 28 and has the lower impurity density than the first semiconductor region 19 and a second conductive type fourth semiconductor region 29 which is provided on the outer side of the third semiconductor region 20 and includes a plurality of second conductive type second subregions with the same impurity density as the third semiconductor region 20. The width of the first semiconductor region 19 is narrower than the width of the third semiconductor region 20.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] This invention relates to a silicon carbide semiconductor device. [Background technology]

[0002] Traditionally, silicon (Si) has been used as a constituent material for power semiconductor devices that control high voltages and large currents. Power semiconductor devices come in several types, including bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and these are used differently depending on the application.

[0003] For example, bipolar transistors and IGBTs have a higher current density than MOSFETs and can handle large currents, but they cannot be switched at high speeds. Specifically, bipolar transistors are limited to switching frequencies of a few kHz, and IGBTs are limited to switching frequencies of a few tens of kHz. On the other hand, power MOSFETs have a lower current density than bipolar transistors and IGBTs and are difficult to operate at large currents, but they can perform high-speed switching operations up to a few MHz.

[0004] However, there is a strong market demand for power semiconductor devices that combine high current and high speed, and efforts have been focused on improving IGBTs and power MOSFETs, with development now approaching the material limits. From the perspective of power semiconductor devices, semiconductor materials to replace silicon are being considered, and silicon carbide (SiC) is attracting attention as a semiconductor material that can be used to fabricate (manufacture) next-generation power semiconductor devices with excellent low on-voltage, high-speed, and high-temperature characteristics.

[0005] Silicon carbide is a chemically very stable semiconductor material with a wide bandgap of 3 eV, making it extremely stable as a semiconductor even at high temperatures. Furthermore, because its maximum electric field strength is more than an order of magnitude greater than that of silicon, silicon carbide is expected to be a semiconductor material that can sufficiently reduce on-resistance. These characteristics of silicon carbide also apply to wide-bandgap semiconductors with wider bandgaps than other silicon materials, such as gallium nitride (GaN). Therefore, by using wide-bandgap semiconductors, it is possible to increase the voltage resistance of semiconductor devices.

[0006] In such high-voltage semiconductor devices, a high voltage is applied not only to the active region where current flows when the device structure is formed and the device is in the ON state, but also to the edge termination region that surrounds the active region and maintains the breakdown voltage, causing the electric field to concentrate in the edge termination region. The breakdown voltage of a high-voltage semiconductor device is determined by the impurity concentration, thickness, and electric field strength of the semiconductor, and the breakdown voltage determined by these semiconductor-specific characteristics is equal from the active region to the edge termination region. Therefore, the concentration of the electric field in the edge termination region can cause an electrical load exceeding the breakdown voltage to be applied to the edge termination region, potentially leading to failure. In other words, the breakdown voltage of the high-voltage semiconductor device is limited by the breakdown voltage in the edge termination region.

[0007] As devices that improve the overall breakdown voltage of high-voltage semiconductor devices by mitigating or dispersing the electric field in the edge termination region, devices that incorporate breakdown structures such as junction termination extension (JTE) structures, field limiting ring (FLR) structures, and spatial modulation structures that reduce the impurity concentration distribution outward are known to be used in the edge termination region. Furthermore, semiconductor devices that improve reliability by arranging a floating metal electrode in contact with the FLR as a field plate (FP) to release the charge generated in the edge termination region are also known.

[0008] Regarding the breakdown voltage structure of a conventional high-voltage silicon carbide semiconductor device, a MOSFET having a JTE structure and a space modulation structure will be described as an example. FIG. 6 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device.

[0009] The conventional silicon carbide semiconductor device 170 shown in FIG. 6 includes an active region 150 and an edge termination region 160 surrounding the periphery of the active region 150 on a semiconductor substrate made of silicon carbide (hereinafter referred to as a silicon carbide substrate (semiconductor chip)). The silicon carbide substrate is an n + , + , ++ , ++ , , , + , + , ++ , ++ , ,

[0011] -type support substrate (hereinafter referred to as an n + -type silicon carbide substrate) 101, on which an n-type epitaxial layer 108 made of silicon carbide, an n ++ -type epitaxial layer 109 made of silicon carbide, an n - -type drift region 102 made of silicon carbide, and a p-type base region 105 made of silicon carbide are sequentially stacked.

[0010] Also, an n-type partial region 103 and a p - -type partial region 104 are provided in the n + -type drift region 102. The p + -type partial region 104 consists of a lower p + -type partial region 104b and an upper p + -type partial region 104a. An n ++ -type source region (not shown) and a p ++ -type contact region 106 are provided in the p-type base region 105.

[0011] In the active region 150, a MOS gate (insulated gate composed of metal-oxide-semiconductor) structure of a trench structure, which is omitted in FIG. 6, is provided on the front surface (the surface on the p-type base region 105 side) of the silicon carbide substrate. An n ++ -type source region and a p ++ -type contact region 106, a source electrode 116 is provided via a barrier metal 115, and a polyimide 130 that functions as a protective film is provided on the surface of the silicon carbide semiconductor device 170. An n + -type drain electrode 117 is provided on the back surface of the silicon carbide substrate 101.

[0012] At the end of the active region 150, p ++ A polysilicon layer 122 is provided on the type contact region 106 via an HTO (High Temperature Oxide) film 112.

[0013] In the edge termination region 160, a gate runner 118 is provided to connect the polysilicon layer 122 and the gate pad electrode (not shown). In the edge termination region 160 outside the area where the gate runner 118 is provided (towards the tip end), the p-type base region 105 is removed, and a step is formed on the surface of the silicon carbide substrate such that the edge termination region 160 is lower than the active region 150 (recessed towards the drain side), and n - The type drift region 102 is exposed. The edge termination region 160 is covered with a field oxide film 110, and an HTO film 112 and an interlayer insulating film 114 are deposited sequentially on the field oxide film 110. In addition, a spatial modulation JTE structure 131, which will be explained in Figure 7, is provided in the edge termination region 160. Furthermore, outside the spatial modulation JTE structure 131, there is an n functioning as a channel stopper. ++ A channel stopper region 121 is provided.

[0014] In the FLR edge-terminated structure, increasing the impurity concentration in the p-type region of the FLR results in the edge-terminated structure being approximately twice as long as that of the spatially modulated structure. Furthermore, an edge-terminated structure consisting solely of a JTE structure generates areas of high electric field on the surface. For this reason, high-voltage silicon carbide semiconductor devices employ an edge-terminated structure combining a spatially modulated structure and a JTE structure for cost reduction and reliability of characteristics (see, for example, Patent Documents 1 and 2 below).

[0015] Figure 7 is a cross-sectional view showing the edge termination structure of a conventional silicon carbide semiconductor device, combining the spatial modulation structure and the JTE structure. The structure combining the spatial modulation structure and the JTE structure (hereinafter referred to as the spatial modulation JTE structure 131) consists of adjacent p-type regions (p - Type JTE region 119, p --In the JTE region 120), spatial modulation regions (first spatial modulation region 128, second spatial modulation region 129) are placed, which have an impurity concentration distribution spatially equivalent to the intermediate impurity concentration between these two regions, thereby creating a structure in which the impurity concentration distribution of the entire JTE structure gradually decreases toward the outside (towards the tip edge). In Figure 7, the first spatial modulation region 128 is p - Outside the type JTE region 119, the second spatial modulation region 129 is p -- An example is shown where it is placed outside the type JTE region 120. The spatial modulation region is p - It may also be located in the type JTE region 119, p - Type JTE region 119 and p -- It may be placed in both the type JTE region 120 and p - Type JTE region 119 and p -- It may be placed between the type JTE region 120 and the surrounding area.

[0016] The spatial modulation region constituting the spatial modulation JTE structure 131 is formed by repeatedly arranging two small regions with approximately the same impurity concentration as the adjacent region on each side in a predetermined pattern. In the example in Figure 7, the first spatial modulation region 128 is p - Multiple regions with approximately the same impurity concentration as the type JTE region 119 are arranged with increasing spacing towards the outside, and the second spatial modulation region 129 is p -- Multiple regions with approximately the same impurity concentration as the type JTE region 120 are arranged, with increasing spacing towards the outside.

[0017] In the example in Figure 7, p - The width of the type JTE region 119 is 14 μm, and in the first spatial modulation region 128, four sub-regions with widths of 4.6 μm, 1.6 μm, 2.2 μm, and 2.5 μm are arranged with gaps of 1.5 μm, 1.8 μm, 1.8 μm, and 4 μm from adjacent regions. -- The width of the type JTE region 120 is 10 μm, and in the second spatial modulation region 129, four sub-regions with widths of 4.6 μm, 1.6 μm, 2.2 μm, and 2.5 μm are arranged with gaps of 1.5 μm, 1.8 μm, 1.8 μm, and 4 μm from adjacent regions. The second spatial modulation region 129 and n ++The distance between the channel stopper region 121 and the other is 10 μm. Therefore, the length of the conventional edge termination region 160 (p + From the edge of type subregion 104, n ++ The length of the channel stopper region 121 (from the channel stopper region 121 to the end on the active region 150 side) is 74 μm.

[0018] The spatial impurity concentration distribution across the entire spatial modulation region is determined by the width and impurity concentration ratio of the two sub-regions. The spatial modulation JTE structure 131 can more stably ensure the predetermined withstand voltage compared to a general JTE structure that does not have a spatial modulation region.

[0019] Furthermore, a silicon carbide semiconductor device is known that includes a silicon carbide substrate and an inorganic passivation layer structure that at least partially covers the main surface of the silicon carbide substrate in the transverse direction, wherein the silicon carbide substrate and the inorganic passivation layer are configured such that at least one region of the silicon carbide substrate contains an electric field of at least 2.3 MV / cm, while the electric field on the surface of the inorganic passivation layer structure positioned opposite the silicon carbide substrate is less than 500 kV / cm (see, for example, Patent Document 3 below). [Prior art documents] [Patent Documents]

[0020] [Patent Document 1] Japanese Patent Publication No. 2012-195519 [Patent Document 2] Patent No. 6610786 [Patent Document 3] Patent No. 6673856 [Overview of the Initiative] [Problems that the invention aims to solve]

[0021] However, conventional silicon carbide semiconductor devices may degrade in THB (Temperature Humidity Bias) tests for certain packages. For example, in a thin resin product with a polyimide 130 thickness of 4 mm instead of the usual 8 mm, a THB test conducted at 85°C, 85% humidity, Vgs=0V, and Vds=960V results in failure after approximately 410 to 750 hours, compared to a target of 1000 hours.

[0022] Figure 8 shows the fracture locations of a conventional silicon carbide semiconductor device after a THB test. The locations indicated by arrow A in Figure 8 are the fracture locations. As shown in Figure 8, fracture occurred on the gate runner 118, starting from the edge of the chip. This is thought to be because the electric field on the surface (HTO film 112 / polyimide 130 interface) exceeded 0.5 MV / cm.

[0023] This invention aims to provide a highly reliable silicon carbide semiconductor device that can achieve the target values ​​of the THB test, thereby solving the problems of the prior art described above. [Means for solving the problem]

[0024] To solve the above-mentioned problems and achieve the objectives of the present invention, the silicon carbide semiconductor device according to this invention has the following features. The silicon carbide semiconductor device comprises an active region through which a main current flows and a termination region surrounding the active region on a silicon carbide semiconductor substrate of a first conductivity type. The termination region comprises a first semiconductor region of a second conductivity type, a second semiconductor region of a second conductivity type provided outside the first semiconductor region and containing a plurality of first sub-regions of a second conductivity type having the same impurity concentration as the first semiconductor region, within a region with a lower impurity concentration than the first semiconductor region, a third semiconductor region of a second conductivity type provided outside the second semiconductor region and having a lower impurity concentration than the first semiconductor region, and a fourth semiconductor region of a second conductivity type provided outside the third semiconductor region and containing a plurality of second sub-regions of a second conductivity type having the same impurity concentration as the third semiconductor region. The width of the first semiconductor region is narrower than the width of the third semiconductor region. The spacing between the multiple first small regions of the second conductivity type decreases from large to small as you move towards the terminal region, and then becomes even larger.

[0025] Furthermore, in the silicon carbide semiconductor device according to this invention, the distance between the first semiconductor region and the first sub-region on the active region side within the second semiconductor region is 1.0 μm or less, the distance between the first sub-regions up to 9 on the active region side within the second semiconductor region is 1.0 μm or less, the width of the first sub-regions other than the 4 on the active region side within the second semiconductor region is 1.0 μm or less, and the distance between the third semiconductor region and the second sub-region on the active region side within the fourth semiconductor region is 1.0 μm or less. The fourth semiconductor area The width of the second small regions other than the three on the active region side is characterized by being 1.0 μm or less.

[0026] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, a first silicon carbide semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is provided on the front surface of the silicon carbide semiconductor substrate, and the first semiconductor region, the second semiconductor region, the third semiconductor region, and the fourth semiconductor region are provided on the surface layer of the first silicon carbide semiconductor layer.

[0027] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, a first silicon carbide semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is provided on the front surface of the silicon carbide semiconductor substrate, and the first semiconductor region, the second semiconductor region, the third semiconductor region, and the fourth semiconductor region are provided inside the first silicon carbide semiconductor layer.

[0028] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, a step is formed in the termination region such that the outer portion of the termination region is lower than the active region. Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the spacing between the multiple second small regions of the second conductivity type decreases from a large spacing to a small spacing, and then to a larger spacing, as it moves towards the terminal region.

[0029] According to the invention described above, p - The width of the type JTE region (first semiconductor region) is p --The width of the JTE region (second semiconductor region) is narrowed. This allows for mitigation of the electric field in the edge termination region without increasing its length. Furthermore, due to the characteristics of the edge termination region, the maximum electric field strength on the surface of the edge-terminated structure can be kept below 0.5 MV / cm. As a result, the target value for THB testing can be achieved, providing a highly reliable edge-terminated structure. [Effects of the Invention]

[0030] The silicon carbide semiconductor device according to the present invention can achieve the target values ​​of the THB test and exhibits the effect of high reliability. [Brief explanation of the drawing]

[0031] [Figure 1] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to an embodiment. [Figure 2] This is a cross-sectional view showing the MOS structure of a silicon carbide semiconductor device according to an embodiment. [Figure 3A] This is a cross-sectional view (part 1) showing the edge termination structure of a silicon carbide semiconductor device according to an embodiment. [Figure 3B] This is a cross-sectional view (part 2) showing the edge termination structure of a silicon carbide semiconductor device according to an embodiment. [Figure 3C] This is a cross-sectional view (part 3) showing the edge termination structure of a silicon carbide semiconductor device according to an embodiment. [Figure 4] This is a cross-sectional view showing details of the edge termination structure of a silicon carbide semiconductor device according to an embodiment. [Figure 5] This graph shows the electric field strength in the edge termination structure of a silicon carbide semiconductor device according to an embodiment and a conventional silicon carbide semiconductor device. [Figure 6] This is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. [Figure 7] This is a cross-sectional view showing an edge termination structure that combines the spatial modulation structure and JTE structure of a conventional silicon carbide semiconductor device. [Figure 8]This figure shows the fracture locations of a conventional silicon carbide semiconductor device after THB testing. [Modes for carrying out the invention]

[0032] Preferred embodiments of the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, than layers or regions without these signs. When the notation for n and p, including + and -, is the same, it indicates similar concentrations, but does not necessarily mean that the concentrations are equivalent. In the following description of embodiments and accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted. In this specification, in the notation of Miller indices, "-" indicates a bar attached to the exponent immediately following it, and placing "-" before the exponent indicates a negative exponent.

[0033] (Embodiment) The semiconductor device according to the present invention is constructed using a wide-bandgap semiconductor. In the embodiment, a silicon carbide semiconductor device fabricated using silicon carbide (SiC) as the wide-bandgap semiconductor will be described using a MOSFET as an example. Figure 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the embodiment. Figure 2 is a cross-sectional view showing the MOS structure of the silicon carbide semiconductor device according to the embodiment.

[0034] As shown in Figures 1 and 2, the silicon carbide semiconductor device 70 according to this embodiment comprises an active region 50 and an edge termination region 60 surrounding the active region 50, on a semiconductor substrate made of silicon carbide (hereinafter referred to as the silicon carbide substrate (semiconductor substrate (semiconductor chip))). The active region 50 is the region through which current flows when it is in the ON state. The edge termination region 60 is the region that mitigates the electric field on the surface side of the substrate in the drift region and maintains the breakdown voltage. Figure 1 shows the structure of the end of the active region 50 and the edge termination region 60, and Figure 2 shows the MOS structure of the active region 50.

[0035] The silicon carbide substrate is made of n + Mold support substrate (n + On the front surface of a silicon carbide substrate (first conductivity type silicon carbide semiconductor substrate) 1, there is an n-type epitaxial layer 8 made of silicon carbide and an n-type epitaxial layer made of silicon carbide. ++ A type epitaxial layer 9 and n made of silicon carbide - It is constructed by sequentially stacking a type drift region (first silicon carbide semiconductor layer of the first conductivity type) 2 and a p-type base region 5 made of silicon carbide. + The silicon carbide substrate 1 functions as a drain region.

[0036] n + The silicon carbide substrate 1 is a silicon carbide single crystal substrate. - Type drift region 2 is n + The impurity concentration is lower than that of the type silicon carbide substrate 1, for example, it is a low-concentration n-type drift layer. - Type drift region 2 and n + Between the n-type silicon carbide substrate 1 and the n-type epitaxial layer 8 and n ++ An n-type epitaxial layer 9 may be provided. n-type epitaxial layer 8 and n ++ The type epitaxial layer 9 is, each, n + This is a buffer layer that reduces the growth of crystal defects from the silicon carbide substrate 1. - n of the drift region 2 + An n-type high-concentration region 26 may be provided on the surface opposite to the silicon carbide substrate 1 side. The n-type high-concentration region 26 is n + Lower n than type silicon carbide substrate 1 - This is a high-concentration n-type drift layer with a higher impurity concentration than type drift region 2.

[0037] n - n of the drift region 2 + A p-type base region 5 is provided on the surface opposite to the silicon carbide substrate 1. The impurity concentration of the p-type base region 5 is, for example, 3.5 × 10⁻⁶. 17 / cm 3 It is partially 5 × 10 17 / cm 3 Ion implantation is performed in such a manner.

[0038] n + A drain electrode 17, which serves as a back electrode, is provided on the second main surface (back surface, i.e., the back surface of the silicon carbide substrate) of the silicon carbide substrate 1. A drain electrode pad (not shown) is provided on the surface of the drain electrode 17.

[0039] A trench structure is formed on the first main surface side (p-type base region 5 side) of the silicon carbide substrate. Specifically, the trench 25 is n + From the surface opposite to the silicon carbide substrate 1 (the first main surface side of the silicon carbide substrate), the n-type high-concentration region 26 (if the n-type high-concentration region 26 is not provided) penetrates the p-type base region 5. - The drift region reaches type 2 (hereinafter simply referred to as (2)).

[0040] A gate insulating film 11 is formed along the inner wall of the trench 25, at the bottom and side walls of the trench 25, and a gate electrode 13 is formed inside the gate insulating film 11 within the trench 25. The gate insulating film 11 insulates the gate electrode 13 from the n-type high-concentration region 26(2) and the p-type base region 5. A portion of the gate electrode 13 may protrude from the top of the trench 25 (the side where the source electrode 16, described later, is provided) toward the source electrode 16.

[0041] n-type high-concentration region 26(2) + On the surface layer opposite to the silicon carbide substrate 1 side (the first main surface side of the silicon carbide substrate), the upper p + A type subregion 4a is provided. Upper part p + The n-type subregion 4a is provided, for example, between the trenches 25. Also, within the n-type high-concentration region 26(2), the bottom and upper part p of the trench 25 + Lower part p in contact with the bottom of subregion 4a + A molded portion area 4b is provided. The lower part p is in contact with the bottom of the trench 25. +The p-type partial region 4b is provided at a position facing the bottom of the trench 25 in the depth direction (the direction from the source electrode 16 to the back electrode). The upper p-type partial region 4a between the trenches 25 and the lower p-type partial region 4b together form the p-type partial region 4. + type partial region 4a and the lower p + type partial region 4b together become the p + type partial region 4.

[0042] The lower p + type partial region 4b has a width equal to or wider than the width of the trench 25. Also, the width of the lower p + type partial region 4b is equal to or wider than the width of the upper p + type partial region 4a. The impurity concentration of the p + type partial region 4 is, for example, 6.5×10 18 / cm 3 . The bottom of the trench 25 may reach the lower p + type partial region 4b, or may be located within the n-type high-concentration region 26(2) sandwiched between the p-type base region 5 and the lower p + type partial region 4b.

[0043] Also, an n-type partial region 3 with a peak impurity concentration higher than that of the n-type high-concentration region 26(2) may be provided in the n - type drift region 2 at a position deeper than the lower p + type partial region 4b between the trenches. Note that the deep position means a position closer to the drain electrode 17 than the lower p + type partial region 4b.

[0044] Inside the p-type base region 5, an n ++ type source region 7 and a p ++ type contact region 6 are selectively provided on the first main surface side of the silicon carbide substrate. Also, the n ++ type source region 7 and the p ++ type contact region 6 are in contact with each other. The impurity concentration of the n ++ type source region 7 is, for example, 3×10 19 / cm 3 . The impurity concentration of the p ++ type contact region 6 is, for example, 3×10 20 / cm 3 .

[0045] The interlayer insulating film 14 is provided so as to cover the gate electrode 13 embedded in the trench 25 over the entire surface on the first main surface side of the silicon carbide substrate. The source electrode 16 is connected to the n ++ -type source region 7 and the p ++ -type contact region 6 through a contact hole opened in the interlayer insulating film 14. The source electrode 16 is electrically insulated from the gate electrode 13 by the interlayer insulating film 14. A source electrode pad (not shown) is provided on the source electrode 16. A barrier metal 15 may be provided between the source electrode 16 and the interlayer insulating film 14 to prevent diffusion of metal atoms from the source electrode 16 toward the gate electrode 13. A polyimide 30 that functions as a protective film is provided on the surface of the silicon carbide semiconductor device 70. In FIG. 2, only two MOS gate (insulated gate composed of metal-oxide-semiconductor) structures are shown in the active region 50, but more MOS gate structures may be arranged in parallel.

[0046] At the end of the active region 50, an HTO film 12 and an interlayer insulating film 14 are provided between the source electrode 16 and the silicon carbide substrate (for example, the p ++ -type contact region 6). The end of the active region 50 is the portion of the active region 50 that contacts the edge termination region 60, and specifically, it is the portion where the interlayer insulating film 14 is provided between the source electrode 16 and the silicon carbide substrate.

[0047] A polysilicon layer 22 is partially provided on the HTO film 12 at the end of the active region 50, and the polysilicon layer 22 is electrically connected to a gate runner 18 described later.

[0048] Also in the edge termination region 60, on the front surface of the n + -type silicon carbide substrate 1, the above-described n-type epitaxial layer 8, n ++ -type epitaxial layer 9, n - -type drift region 2, n-type high concentration region 26, p-type base region 5, n-type partial region 3, upper p + -type partial region 4a and lower p +A sub-region 4b is provided.

[0049] In the edge termination region 60, a gate runner 18 is provided to connect the polysilicon layer 22 and the gate pad electrode. In the edge termination region 60, the outer portion, for example, the portion other than the area where the gate runner 18 is provided, consists of a p-type base region 5, an n-type sub-region 3, and an upper p + Type subregion 4a and lower p + The mold subregion 4b is removed, and a step is formed on the surface of the silicon carbide substrate in which the edge termination region 60 is lower than the active region 50 (recessed towards the drain side), and n - The drift region 2 is exposed. In addition, the edge termination region 60 is provided with a spatial modulation JTE structure 31, which will be explained in detail in Figures 3A, 3B, and 3C below. Furthermore, on the outside of the spatial modulation JTE structure 31 (on the tip end side), there is an n functioning as a channel stopper. ++ A channel stopper region 21 is provided. Spatial modulation JTE structure 31 and n - The pn junction with the drift region 2 maintains high lateral pressure resistance.

[0050] The edge termination region 60 is covered with a field oxide film 10, and an HTO film 12 and an interlayer insulating film 14 are deposited sequentially on the field oxide film 10.

[0051] Figures 3A, 3B, and 3C are cross-sectional views showing the edge termination structure of a silicon carbide semiconductor device according to an embodiment. As shown in Figures 3A, 3B, and 3C, the spatial modulation JTE structure 31 is a structure that combines the spatial modulation structure and the JTE structure, and the p-type region (p - Type JTE region 19, p -- In the JTE region 20), two additional regions (first spatial modulation region 28, second spatial modulation region 29) are placed that have an impurity concentration distribution spatially equivalent to the intermediate impurity concentration between these two regions, thereby creating a structure in which the impurity concentration distribution of the entire JTE structure gradually decreases toward the outside (towards the tip edge). In Figures 3A, 3B, and 3C, the first spatial modulation region 28 is p - Outside the type JTE region 19, the second spatial modulation region 29 is p-- An example is shown where it is placed outside the type JTE region 20. The spatial modulation region is p - It may also be located in the type JTE region 19, p - Type JTE region 19 and p -- It may be placed in both the type JTE region 20 and p - Type JTE region 19 and p -- It may be placed between the type JTE region 20. Although not shown in the figure, p - Type JTE region 19 and p -- The type JTE region 20 is arranged in a concentric circle surrounding the active region 50.

[0052] The spatial modulation region constituting the spatial modulation JTE structure 31 is formed by repeatedly arranging two small regions with approximately the same impurity concentration as the adjacent region on each side of itself in a predetermined pattern. In the examples of Figures 3A, 3B, and 3C, the first spatial modulation region 28 is p - Multiple regions with approximately the same impurity concentration as the type JTE region 19 are arranged with increasing spacing towards the outside, and the second spatial modulation region 29 is p -- Multiple regions with approximately the same impurity concentration as the type JTE region 20 are arranged with increasing spacing towards the outside. The spatial impurity concentration distribution of the entire spatial modulation region is determined by the width and impurity concentration ratio of the two sub-regions. The spatial modulation JTE structure 31 can ensure a predetermined withstand voltage more stably than a general JTE structure that does not have a spatial modulation region.

[0053] Furthermore, as shown in Figure 3A, a step is formed in which the edge termination region 60 is lower than the active region 50, and the spatial modulation JTE structure 31 has n exposed at the bottom surface of the step. - It is provided on the surface layer of the drift region 2. In this case, the surface of the spatial modulation JTE structure 31 is the p of the edge termination region 60. + It will be at the same height as the surface of mold subregion 4.

[0054] Furthermore, as shown in Figure 3B, a step is formed in which the edge termination region 60 is lower than the active region 50, and the spatial modulation JTE structure 31 has n exposed at the bottom surface of the step. -It may be provided inside the drift region 2. In this case, the surface of the spatial modulation JTE structure 31 is the p of the edge termination region 60. + It becomes lower than the surface of mold subregion 4.

[0055] Furthermore, as shown in Figure 3C, etching is not required in the edge termination region 60, and a step is not formed. In this case, the spatial modulation JTE structure 31 is n - Located within the drift region 2, the surface of the spatial modulation JTE structure 31 is the p of the edge termination region 60. + It will be at the same height as the surface of mold subregion 4.

[0056] Figure 4 is a cross-sectional view showing details of the edge termination structure of the silicon carbide semiconductor device according to the embodiment. In the embodiment, the spatial modulation JTE structure 31 is p - Type JTE region (first semiconductor region of second conductivity type) 19, first spatial modulation region (second semiconductor region of second conductivity type) 28, p -- It consists of a type JTE region (third semiconductor region of the second conductivity type) 20 and a second spatial modulation region (fourth semiconductor region of the second conductivity type) 29. The first spatial modulation region 28 is p - Within the region with lower impurity concentrations than the type JTE region 19, p - The second spatial modulation region 29 is composed of 11 sub-regions (first sub-regions) with the same impurity concentration as the type JTE region 19. -- It consists of 10 sub-regions (second sub-regions) with the same impurity concentration as the type JTE region 20. Although not shown in the diagram, each sub-region within the first spatial modulation region 28 and each sub-region within the second spatial modulation region 29 are arranged in concentric circles surrounding the active region 50.

[0057] In the first configuration of the embodiment, p - The width l1 of the type JTE region 19 is 4.7 μm, p -- The width l2 of the type JTE region 20 is 12.7 μm, and the second spatial modulation region 29 and n ++ The distance l3 between the channel stopper region 21 and the channel stopper region is 10 μm.

[0058] Furthermore, the widths w1 to w11 of each sub-region of the first spatial modulation region 28 from the active region 50 side, the spacings g1 to g11 of each sub-region of the first spatial modulation region 28 from the active region 50 side, the widths w12 to w21 of each sub-region of the second spatial modulation region 29 from the active region 50 side, and the spacings g12 to g21 of each sub-region of the second spatial modulation region 29 from the active region 50 side are as shown in Table 1 below. All units are in μm. The length of the first spatial modulation region 28 is 30 μm, and the length of the second spatial modulation region 29 is 29.9 μm. Therefore, the length of the edge termination region 60 of the first configuration of the embodiment (p + From the edge of type subregion 4, n ++ The length of the channel stopper region 21 to the end on the active region 50 side is 87.3 μm.

[0059] [Table 1]

[0060] Furthermore, in the second configuration of the embodiment, p - The width l1 of the type JTE region 19 is 3.7 μm, p -- The width l2 of the type JTE region 20 is 7.6 μm, and the second spatial modulation region 29 and n ++ The distance l3 between the channel stopper region 21 and the channel stopper region is 10 μm.

[0061] Furthermore, the widths w1 to w11 of each sub-region of the first spatial modulation region 28 from the active region 50 side, the spacings g1 to g11 of each sub-region of the first spatial modulation region 28 from the active region 50 side, the widths w12 to w21 of each sub-region of the second spatial modulation region 29 from the active region 50 side, and the spacings g12 to g21 of each sub-region of the second spatial modulation region 29 from the active region 50 side are as shown in Table 2 below. All units are in μm. The length of the first spatial modulation region 28 is 26.5 μm, and the length of the second spatial modulation region 29 is 26.2 μm. Therefore, the length of the edge termination region 60 in the second configuration of the embodiment is 74 μm, which is the same as the length of the edge termination region 160 of the conventional silicon carbide semiconductor device 170.

[0062] [Table 2]

[0063] Thus, in this embodiment, both the first configuration and the second configuration are p - The width of the type JTE region 19 is p -- The width of the JTE region 20 is made narrower. This allows the electric field in the edge termination region 60 to be mitigated without increasing the length of the edge termination region 60.

[0064] Furthermore, in the embodiment, both the first and second configurations have the following characteristics. (1) p - The distance g1 between the type JTE region 19 and the small region on the most active side of the first spatial modulation region 28 is 1.0 μm or less. (2) The spacing between the first spatial modulation region 28 and the nine subregions on the active region 50 side, g2 to g9, is 1.0 μm or less. (3) The widths w5 to w11 of the small regions other than the four on the active region 50 side of the first spatial modulation region 28 are 1.0 μm or less. (4)p -- The distance g12 between the type JTE region 20 and the small region on the most active side of the second spatial modulation region 29 is 1.0 μm or less. (5) The widths w15 to w21 of the small regions other than the three on the active region 50 side of the second spatial modulation region 29 are 1.0 μm or less. Here, the interval between subregions is the distance between a subregion and the subregion adjacent to it on the active region 50 side.

[0065] Of these features (1) through (5), features (2) and (4) are the most effective in reducing the maximum electric field strength in the edge termination structure. Therefore, features (2) and (4) alone can reduce the maximum electric field strength compared to conventional designs.

[0066] Figure 5 is a graph showing the electric field strength in the edge termination structure of a silicon carbide semiconductor device according to an embodiment and a conventional silicon carbide semiconductor device. In Figure 5, the horizontal axis is p +The edge length from the type subregion 4 is shown, in units of μm. The vertical axis shows the electric field strength at the surface (HTO film 12 / polyimide 30 interface) at the edge length, in units of V / cm. In Figure 5, n is shown at the edge termination region 60. ++ This is the result of simulating the electric field strength without providing the channel stopper region 21. In Figure 5, the edge length of 20 μm corresponds to p - The 120 μm point is the end of the active region 50 side of the type JTE region 19, and the 120 μm point is the end of the edge termination region 60.

[0067] As shown in Figure 5, in conventional silicon carbide semiconductor devices, the maximum electric field strength on the surface is 0.5 MV / cm or more at an edge length of around 60 μm. However, in the silicon carbide semiconductor device according to this embodiment, the first configuration has a maximum electric field strength of approximately 0.34 MV / cm, and the second configuration has a maximum electric field strength of approximately 0.42 MV / cm, both below 0.5 MV / cm. In the first configuration, the maximum electric field strength is lower than in the second configuration because the length of the edge termination region 60 is longer. Furthermore, in the second configuration, the length of the edge termination region 60 can be made the same as the length of the conventional edge termination region 160, making the maximum electric field strength on the surface 0.5 MV / cm or less.

[0068] In this way, by setting the spacing g1 and g12 to 1.0 μm or less, and the spacing g2 to g9, widths w5 to w11, and widths w15 to w21 to 1.0 μm or less, the maximum electric field strength on the surface can be reduced to 0.5 MV / cm or less.

[0069] The silicon carbide semiconductor device according to this embodiment is, for example, n - In the surface layer or interior of the drift region 2, there is a high concentration of p - A type JTE region 19 and a first spatial modulation region 28 are formed, and thereafter, p with a low impurity concentration -- A spatial modulation JTE structure 31 can be formed by creating a type JTE region 20 and a second spatial modulation region 29. Other structures can be fabricated in the same way as, for example, when fabricating a MOSFET with a voltage rating of 1200V.

[0070] As explained above, according to the embodiment, p - The width of the type JTE region is p -- The width of the JTE region is narrower than that of the type JTE region. This allows for mitigation of the electric field in the edge termination region without increasing its length. Furthermore, due to the characteristics of the edge termination region in this embodiment, the maximum electric field strength on the surface of the edge termination structure can be reduced to 0.5 MV / cm or less. Therefore, the target value for THB testing can be achieved, and a highly reliable edge termination structure can be provided.

[0071] As described above, the present invention can be modified in various ways without departing from the spirit of the invention, and in each of the embodiments described above, for example, the dimensions of each part, the impurity concentration, etc. can be set in various ways according to the required specifications. Furthermore, although the above embodiments are described using silicon carbide as the wide bandgap semiconductor as an example, the present invention can also be applied to wide bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN). In addition, although the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, the present invention can also be similarly obtained by setting the first conductivity type to p-type and the second conductivity type to n-type. [Industrial applicability]

[0072] As described above, the silicon carbide semiconductor device according to the present invention is useful as a power semiconductor device used in power conversion devices such as inverters, power supply devices for various industrial machines, and igniters for automobiles. [Explanation of Symbols]

[0073] 1, 101 n + Silicon carbide substrate 2, 102 n - Type drift region 3, 103 n-type subregion 4, 104 p + type subregion 4a, 104a upper p + type subregion 4b, 104b lower p + type subregion 5. 105 p-type base region 6, 106 p ++ Type Contact Area 7 n ++ Type source area 8, 10⁸ n-type epitaxial layer 9, 109 n ++ Type epitaxial layer 10, 110 Field Oxide Film 11 Gate insulating film 12, 112 HTO membrane 13 gates 14, 114 Interlayer insulating film 15, 115 Barrier Metal 16, 116 source electrodes 17, 117 Drain electrodes 18, 118 Gate Runner pp. 19, 119 - Type JTE area 20, 120 p -- Type JTE area 21, 121 n ++ Type channel stopper region 22, 122 Polysilicon layer 25 Trench 26 n-type high concentration region 28, 128 First spatial modulation region 29, 129 Second spatial modulation region 30, 130 Polyimide 31, 131 Spatial Modulation JTE Structure 50, 150 active area 60, 160 edge termination region 70, 170 Silicon Carbide Semiconductor Devices

Claims

1. A silicon carbide semiconductor substrate of the first conductivity type comprises an active region through which the main current flows, and a termination region surrounding the active region. In the aforementioned terminal region, The first semiconductor region of the second conductivity type, A second semiconductor region of a second conductivity type is provided outside the first semiconductor region, within a region having a lower impurity concentration than the first semiconductor region, and includes a plurality of first small regions of the second conductivity type having the same impurity concentration as the first semiconductor region. A third semiconductor region of a second conductivity type having a lower impurity concentration than the first semiconductor region is provided outside the second semiconductor region, A fourth semiconductor region of the second conductivity type is provided outside the third semiconductor region and includes a plurality of second sub-regions of the second conductivity type having the same impurity concentration as the third semiconductor region, The first semiconductor region has a width that is narrower than the third semiconductor region. The silicon carbide semiconductor device is characterized in that the spacing between the multiple first small regions of the second conductivity type decreases from large to small and then to even larger as it moves towards the terminal region.

2. The distance between the first semiconductor region and the first subregion on the most active region side within the second semiconductor region is 1.0 μm or less. The spacing between the first nine small regions on the active region side of the second semiconductor region is 1.0 μm or less. The width of the first small regions other than the four on the active region side of the second semiconductor region is 1.0 μm or less. The distance between the third semiconductor region and the second small region on the most active side within the fourth semiconductor region is 1.0 μm or less. The silicon carbide semiconductor device according to claim 1, characterized in that the width of the second small regions other than the three on the active region side of the fourth semiconductor region is 1.0 μm or less.

3. A first silicon carbide semiconductor layer of a first conductivity type with a lower impurity concentration than that of the silicon carbide semiconductor substrate is provided on the front surface of the silicon carbide semiconductor substrate. The silicon carbide semiconductor device according to claim 1 or 2, characterized in that the first semiconductor region, the second semiconductor region, the third semiconductor region, and the fourth semiconductor region are provided on the surface layer of the first silicon carbide semiconductor layer.

4. A first silicon carbide semiconductor layer of a first conductivity type with a lower impurity concentration than that of the silicon carbide semiconductor substrate is provided on the front surface of the silicon carbide semiconductor substrate. The silicon carbide semiconductor device according to claim 1 or 2, characterized in that the first semiconductor region, the second semiconductor region, the third semiconductor region, and the fourth semiconductor region are provided inside the first silicon carbide semiconductor layer.

5. A silicon carbide semiconductor device according to any one of claims 1 to 4, characterized in that a step is formed in the termination region such that the outer portion of the termination region is lower than the active region.

6. The silicon carbide semiconductor device according to any one of claims 1 to 5, characterized in that the spacing between the plurality of second small regions of the second conductivity type decreases from a large spacing to a small spacing, and then to a larger spacing, as it moves toward the terminal region.

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