Semiconductor equipment

Abstract

To suppress current concentration in an intermediate region.SOLUTION: In a semiconductor device, a semiconductor substrate includes an element region, an intermediate region, and an outer peripheral region. In the element region, a gate type gate electrode and an emitter electrode are provided. The element region includes an n-type emitter region, a p-type contact region in ohmic contact with the emitter electrode, and a p-type body region. The intermediate region includes a p-type deep region extending from an upper surface of the semiconductor substrate to a position below a lower end of the body region and in contact with the body region from an outer peripheral side. The semiconductor substrate includes an n-type drift region and a p-type collector region extending over the element region, the intermediate region, and the outer peripheral region. The emitter electrode does not have a contact part for the deep region. The deep region includes a low-concentration region in contact with the body region from the outer peripheral side, and a high-concentration region in contact with the low-concentration region from the outer peripheral side.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed herein relates to semiconductor devices.

[0002] Patent Document 1 discloses a semiconductor device having an insulated gate field-effect transistor. Hereinafter, the insulated gate field-effect transistor may be referred to as an IGBT (insulated gate bipolar transistor). This semiconductor device has an element region where the IGBT is provided, an outer peripheral region where a breakdown structure is provided, and an intermediate region provided between them. A p-type well region (hereinafter referred to as the deep region) is provided in the intermediate region. The deep region is in contact with the body region within the element region (i.e., the body region of the IGBT) from the outer peripheral side. The emitter electrode has a contact portion that is in contact with the upper surface of the deep region in the vicinity of the element region. An n-type drift region is distributed across the lower part of the body region, the lower part of the deep region, and the outer peripheral region. A p-type collector region is also provided below the drift region.

[0003] When the IGBT is ON, holes exist within the drift region. When the IGBT turns OFF, the holes in the drift region are discharged to the emitter electrode. At this time, holes in the drift region within the outer and intermediate regions flow through the deep region to the contact area of ​​the emitter electrode. Patent Document 1 prevents the current due to the holes from concentrating in the deep region by increasing the resistance of the contact area. This improves the avalanche withstand capability of the semiconductor device. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2019-087730 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] Even when using the technology described in Patent Document 1, current concentration within the intermediate region could not always be sufficiently suppressed. This specification proposes a technology for more effectively suppressing current concentration within the intermediate region. [Means for solving the problem]

[0006] A semiconductor device disclosed herein comprises a semiconductor substrate, a gate insulating film, a gate electrode, and an emitter electrode. The semiconductor substrate has an element region on which an insulated gate bipolar transistor is provided, an intermediate region located on the outer periphery of the element region, and an outer periphery region located on the outer periphery of the intermediate region. A trench is provided on the upper surface of the semiconductor substrate within the element region. The gate insulating film covers the inner surface of the trench. The gate electrode is located within the trench and is insulated from the semiconductor substrate by the gate insulating film. The emitter electrode is in contact with the upper surface within the element region. The element region comprises an emitter region, a contact region, and a body region. The emitter region is an n-type region in contact with the gate insulating film on the side surface of the trench and in ohmic contact with the emitter electrode. The contact region is a p-type region in ohmic contact with the emitter electrode. The body region is a p-type region having a lower p-type impurity concentration than the contact region, is in contact with the emitter region and the contact region, and is in contact with the gate insulating film on the side surface of the trench below the emitter region. The intermediate region extends from the upper surface of the semiconductor substrate to a position below the lower end of the body region and has a p-type deep region that is in contact with the body region from the outer periphery. The semiconductor substrate has a drift region and a collector region. The drift region is an n-type region that extends across the element region, the intermediate region, and the outer periphery region and is in contact with the body region and the deep region from below. The collector region is a p-type region that extends across the element region, the intermediate region, and the outer periphery region and is located below the drift region. The emitter electrode does not have a contact portion with respect to the deep region. The deep region has a low-concentration p-type region that is in contact with the body region from the outer periphery, and a high-concentration p-type region that is in contact with the low-concentration region from the outer periphery and has a higher p-type impurity concentration than the low-concentration region.

[0007] In this semiconductor device, the emitter electrode does not have a contact portion with respect to the deep region. Therefore, the inflow of holes into the deep region is suppressed when the IGBT is turned off. The holes branch and flow into two paths: a first path that flows from the drift region through the deep region and body region to the contact region, and a second path that bypasses the deep region and flows from the drift region through the body region to the contact region. Since the deep region has a low-concentration region, the resistance of the first path is high. Therefore, the holes tend to disperse and flow into the first and second paths, suppressing current concentration in the intermediate region. In addition, in this semiconductor device, a high-concentration region is provided on the outer periphery of the low-concentration region. Therefore, when the IGBT is turned off, the depletion layer tends to extend from the high-concentration region to the outer periphery region. That is, even if a low-concentration region is provided in the deep region, the depletion layer can be sufficiently extended to the outer periphery region. Therefore, with this configuration, a high breakdown voltage can be ensured in the outer periphery region. With this configuration, a highly reliable semiconductor device can be realized. [Brief explanation of the drawing]

[0008] [Figure 1] Plan view of semiconductor device 10. [Figure 2] Cross-sectional view of the semiconductor device along line II-II in Figure 1. [Figure 3] A graph showing the relationship between the interval Wc and the current density Cd. [Figure 4] A graph showing the relationship between width W52a and current density Cd. [Figure 5] Cross-sectional view of the semiconductor device of the first modified example. [Figure 6] Cross-sectional view of the semiconductor device of the second modified example. [Modes for carrying out the invention]

[0009] In one example semiconductor device disclosed herein, the contact region may be located between the trench and the deep region. The distance between the contact region and the deep region in the direction toward the outer peripheral region from the element region may be 16 μm or more. The width of the low-concentration region in the said direction may be 155 μm or more. The p-type impurity concentration of the low-concentration region may be 5 × 10⁻¹⁶ 16 cm -3 The following is also acceptable.

[0010] This configuration allows for more effective suppression of current concentration within the intermediate region.

[0011] In one example of a semiconductor device disclosed herein, the lower end of the high-concentration region may be located below the lower end of the low-concentration region. The high-concentration region may be in contact with the outer periphery of the lower surface of the low-concentration region.

[0012] The semiconductor device 10 in the embodiment shown in Figures 1 and 2 has a semiconductor substrate 12. The semiconductor substrate 12 is made of silicon or other semiconductor material. The semiconductor substrate 12 has an element region 20, an intermediate region 50, and an outer peripheral region 60. The element region 20 is the region where the IGBT is provided. As shown in Figure 1, when the semiconductor substrate 12 is viewed from above, the element region 20 is located in the center of the semiconductor substrate 12. The intermediate region 50 is the region where the deep region 52, which will be described later, is provided. The intermediate region 50 is located on the outer peripheral side of the element region 20 (i.e., the side closer to the outer peripheral surface 12c of the semiconductor substrate 12). As shown in Figure 1, when the semiconductor substrate 12 is viewed from above, the intermediate region 50 encircles the element region 20. The outer peripheral region 60 is the region adjacent to the outer peripheral surface 12c of the semiconductor substrate 12. The outer peripheral region 60 is located on the outer peripheral side of the intermediate region 50. As shown in Figure 1, when the semiconductor substrate 12 is viewed from above, the outer peripheral region 60 encircles the intermediate region 50. In other words, the intermediate region 50 is located between the element region 20 and the outer peripheral region 60.

[0013] As shown in FIG. 2, a plurality of trenches 22 are provided on the upper surface 12a of the semiconductor substrate 12 within the element region 20. On the upper surface 12a, each trench 22 extends parallel to each other. The inner surface of each trench 22 is covered by a gate insulating film 24. A gate electrode 26 is disposed within each trench 22. Each gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24. The upper surface of the gate electrode 26 is covered by an interlayer insulating film 70. An emitter electrode 72 is disposed above the semiconductor substrate 12. The emitter electrode 72 is disposed within the element region 20. The emitter electrode 72 covers the interlayer insulating film 70 and the upper surface 12a of the semiconductor substrate 12. The emitter electrode 72 is insulated from the gate electrode 26 by the interlayer insulating film 70. The emitter electrode 72 is in contact with the upper surface 12a in a range where the interlayer insulating film 70 does not exist. A collector electrode 74 is disposed below the semiconductor substrate 12. The collector electrode 74 is in contact with the entire lower surface 12b of the semiconductor substrate 12.

[0014] The semiconductor substrate 12 has a plurality of emitter regions 30, a plurality of contact regions 32, and a body region 34. The plurality of emitter regions 30, the plurality of contact regions 32, and the body region 34 are disposed within the element region 20.

[0015] Each emitter region 30 is an n-type region having a high n-type impurity concentration. Each emitter region 30 is disposed in a range including the upper surface 12a of the semiconductor substrate 12 and makes an ohmic contact with the emitter electrode 72. Each emitter region 30 is in contact with the gate insulating film 24 at the upper end of the side surface of the corresponding trench 22.

[0016] Each contact region 32 is a p-type region having a high p-type impurity concentration. Each contact region 32 is disposed in a range including the upper surface 12a of the semiconductor substrate 12 and makes an ohmic contact with the emitter electrode 72. The contact region 32a closest to the middle region 50 among the plurality of contact regions 32 is disposed between the trench 22 closest to the middle region 50 and the middle region 50 (i.e., the deep region 52 described later).

[0017] The body region 34 is a p-type region having a p-type impurity concentration lower than that of the contact region 32. The body region 34 extends across the lower portions of the plurality of emitter regions 30 and the lower portions of the plurality of contact regions 32. The body region 34 contacts the plurality of emitter regions 30 and the plurality of contact regions 32 from below. The body region 34 contacts the gate insulating film 24 on the side surface of the trench 22 below the emitter region 30.

[0018] The semiconductor substrate 12 has a deep region 52 in the intermediate region 50. The deep region 52 extends from the upper surface 12a of the semiconductor substrate 12 to a depth below the lower end of each trench 22. The deep region 52 contacts the side surface of the body region 34 from the outer peripheral side. The upper surface of the deep region 52 is covered with the interlayer insulating film 70. No contact hole is provided in the interlayer insulating film 70 covering the upper surface of the deep region 52. Therefore, the emitter electrode 72 does not have a contact portion with respect to the deep region 52. The deep region 52 has a low-concentration region 52a and a high-concentration region 52b. The p-type impurity concentration of the low-concentration region 52a is 5×10 16 cm -3 or less. The p-type impurity concentration of the high-concentration region 52b is higher than the p-type impurity concentration of the low-concentration region 52a. The low-concentration region 52a extends from the upper surface 12a of the semiconductor substrate 12 to a depth below the lower end of each trench 22. The low-concentration region 52a contacts the side surface of the body region 34 from the outer peripheral side. The high-concentration region 52b extends from the upper surface 12a of the semiconductor substrate 12 to a depth below the lower end of each trench 22. The high-concentration region 52b contacts the side surface of the low-concentration region 52a from the outer peripheral side. In the direction from the element region 20 to the outer peripheral region 60, the width W52a of the low-concentration region 52a is wider than the width of the high-concentration region 52b. The width W52a of the low-concentration region 52a is 155 μm or more. A gap is provided between the low-concentration region 52a and the contact region 32a. The body region 34 is distributed in the gap. In the direction from the element region 20 to the outer peripheral region 60, the width Wc of the gap is 16 μm or more.

[0019] A drift region 36 is distributed across the element region 20, the intermediate region 50, and the outer peripheral region 60. The drift region 36 is an n-type region having a lower n-type impurity concentration than the emitter region 30. The drift region 36 is in contact with the body region 34, the low-concentration region 52a, and the high-concentration region 52b from below. The drift region 36 is separated from the emitter region 30 by the body region 34. The drift region 36 is in contact with the gate insulating film 24 on the side of the trench 22 below the body region 34.

[0020] A buffer region 38 is distributed across the element region 20, the intermediate region 50, and the outer peripheral region 60. The buffer region 38 is an n-type region having an n-type impurity concentration that is higher than that of the drift region 36 and lower than that of the emitter region 30. The buffer region 38 is in contact with the drift region 36 from below within the element region 20, the intermediate region 50, and the outer peripheral region 60.

[0021] The collector region 40 is distributed across the element region 20, the intermediate region 50, and the outer peripheral region 60. The collector region 40 is a p-type region having a higher p-type impurity concentration than the body region 34. The collector region 40 is located below the drift region 36 and the buffer region 38. The collector region 40 is in contact with the buffer region 38 from below within the element region 20, the intermediate region 50, and the outer peripheral region 60. The collector region 40 is in ohmic contact with the collector electrode 74 over the entire area of ​​the lower surface 12b.

[0022] The semiconductor substrate 12 has multiple field-limiting rings (FLRs) 62 within its outer peripheral region 60. Each FLR 62 is a p-type region. Although not shown in the figure, when the semiconductor substrate 12 is viewed from above, the FLRs 62 extend in a ring shape, encircling the element region 20 and the intermediate region 50 in multiple layers. Each FLR 62 extends from the upper surface 12a of the semiconductor substrate 12 to approximately the same depth as the lower end of the deep region 52. Each FLR 62 is separated from each other by a drift region 36. Furthermore, the FLRs 62 are separated from the high-density region 52b by the drift region 36. The drift region 36 is in contact with the side and bottom surfaces of each FLR 62.

[0023] Within the element region 20, an IGBT is formed by an emitter region 30, a body region 34, a drift region 36, a buffer region 38, a collector region 40, a gate electrode 26, and a gate insulating film 24, among other components.

[0024] Next, the operation of the semiconductor device 10 will be described. The semiconductor device 10 is used with a collector electrode 74 having a higher potential than the emitter electrode 72. When the potential of the gate electrode 26 is raised above the gate threshold, a channel is formed in the body region 34 within the range adjacent to the gate insulating film 24. Once the channel is formed, electrons flow from the emitter electrode 72 into the drift region 36 via the emitter region 30 and the channel. Also, holes flow from the collector electrode 74 into the drift region 36 via the collector region 40 and the buffer region 38. The influx of holes lowers the resistance of the drift region 36. Therefore, electrons pass through the drift region 36 with low loss. Electrons that have passed through the drift region 36 flow to the collector electrode 74 via the buffer region 38 and the collector region 40. In this way, when the potential of the gate electrode 26 is raised above the gate threshold, the IGBT turns on, and electrons flow from the emitter electrode 72 to the collector electrode 74.

[0025] As described above, when the IGBT is turned on, holes flow from the collector region 40 through the buffer region 38 into the drift region 36. Therefore, when the IGBT is turned on, there are many holes in the drift region 36. Since the collector region 40 is distributed to the intermediate region 50 and the outer region 60, when the IGBT is turned on, there are many holes not only in the drift region 36 within the element region 20, but also in the drift region 36 within the intermediate region 50 and the outer region 60.

[0026] When the potential of the gate electrode 26 is reduced to a value below the gate threshold, the channel disappears. This stops the flow of electrons, and the IGBT turns off. When the IGBT turns off, holes present in the drift region 36 are discharged to the emitter electrode 72. Thus, during turn-off, a current is generated by the holes discharged from the drift region 36 to the emitter electrode 72. This current is called the tail current.

[0027] Holes present in the drift region 36 flow to the emitter electrode 72 through the body region 34 and the contact region 32. Within the element region 20, the body region 34 is present over the entire upper part of the drift region 36. Therefore, within the element region 20, the tail current path is wide, and there is almost no concentration of tail current. On the other hand, holes present in the intermediate region 50 and the outer peripheral region 60 flow laterally through the semiconductor substrate 12 toward the element region 20, and flow to the emitter electrode 72 through the body region 34 and the contact region 32 within the element region 20. As a result, the density of tail current is high within the intermediate region 50. Conventionally, there was a problem that tail current easily flowed into the deep region 52 within the intermediate region 50, and avalanche breakdown was likely to occur around the deep region 52. In contrast, in the semiconductor device 10 of this embodiment, as described below, the concentration of tail current within the intermediate region 50 is suppressed.

[0028] Arrows 100 and 102 in Figure 2 indicate the paths of tail current within the intermediate region 50. Arrow 100 is the path of tail current flowing to the emitter electrode 72 via the deep region 52. Arrow 102 is the path of tail current flowing to the emitter electrode 72 through the drift region 36 below the deep region 52. In this embodiment, the entire upper surface of the deep region 52 is covered by the interlayer insulating film 70, and the emitter electrode 72 does not have a contact portion with respect to the deep region 52. Therefore, it is difficult for tail current to flow from the drift region 36 to the deep region 52. Also, since the emitter electrode 72 does not have a contact portion with respect to the deep region 52, in the path of arrow 100, tail current flows to the emitter electrode 72 through the low-concentration region 52a, the body region 34, and the contact region 32a. Since the p-type impurity concentration in the low-concentration region 52a is low, the resistance of the low-concentration region 52a is high. Therefore, it is difficult for tail current to flow in the path shown by arrow 100. As a result, the proportion of tail current that bypasses the deep region 52, as shown by arrow 102, becomes larger than in the conventional design. Thus, in this embodiment, the tail current tends to flow more easily distributed along the paths of arrows 100 and 102, which suppresses current concentration within the intermediate region 50. Therefore, avalanche breakdown is less likely to occur within the intermediate region 50 when the IGBT is turned off.

[0029] Furthermore, when the IGBT turns off, a depletion layer extends from the deep region 52 to the drift region 36 within the outer peripheral region 60. The depletion layer extending from the deep region 52 extends to near the outer peripheral surface 12c of the semiconductor substrate 12, passing through each guard ring 62. The depletion layer extending into the outer peripheral region 60 ensures the breakdown voltage between the emitter electrode 72 and the outer peripheral surface 12c. If the entire deep region 52 were composed of a low-concentration region 52a, the depletion layer would not easily extend from the low-concentration region 52a to the outer peripheral region 60, and there is a risk of electric field concentration occurring within the outer peripheral region 60. In contrast, in the semiconductor device 10 of this embodiment, a high-concentration region 52b is provided on the outer peripheral side of the low-concentration region 52a. Since the p-type impurity concentration in the high-concentration region 52b is high, the depletion layer easily extends from the high-concentration region 52b to the outer peripheral region 60. For this reason, electric field concentration within the outer peripheral region 60 can be suppressed in the semiconductor device 10 of this embodiment.

[0030] As described above, in the present embodiment, the emitter electrode 72 does not have a contact portion with respect to the deep region 52, and the low-concentration region 52a is provided, so that current concentration in the intermediate region 50 is suppressed. Further, in the present embodiment, the high-concentration region 52b is provided, so that electric field concentration in the outer peripheral region 60 can be suppressed. Therefore, a highly reliable IGBT can be realized.

[0031] FIG. 3 shows simulation results of calculating the current density Cd in the intermediate region 50 during turn-off while changing the interval Wc. Note that FIG. 3 shows the case where the width W52a is 155 μm. Further, FIG. 3 shows the case where the p-type impurity concentration Dp of the low-concentration region 52a is Dp = 5 × 10 16 cm -3 and the case of Dp = 1 × 10 17 cm -3 . When Dp = 5 × 10 16 cm -3 , the current density Cd becomes significantly low when the interval Wc is 16 μm or more. Further, when Dp = 1 × 10 17 cm -3 , a significant decrease in the current density Cd is not observed unless the interval Wc is widened to 20 μm. Thus, it was found that the lower the p-type impurity concentration Dp of the low-concentration region 52a, the more the current density Cd can be reduced when the interval Wc is narrow.

[0032] FIG. 4 shows simulation results of calculating the current density Cd while changing the width W52a of the low-concentration region 52a. Note that FIG. 4 shows the case where the interval Wc is 16 μm and the p-type impurity concentration Dp is 5 × 10 16 cm -3 . As shown in FIG. 4, the wider the width W52a, the lower the current density Cd.

[0033] From the results of FIGS. 4 and 5, it was found that the current density Cd can be particularly reduced when the interval Wc is 16 μm or more, the width W52a is 155 μm or more, and the p-type impurity concentration Dp is 5 × 10 16 cm -3 or less.

[0034] In the embodiment described above (i.e., Figure 2), the lower end of the low-concentration region 52a and the lower end of the high-concentration region 52b were located at approximately the same depth. However, as shown in Figure 5, the lower end of the high-concentration region 52b may be located below the lower end of the low-concentration region 52a, and the high-concentration region 52b may be in contact with the outer periphery of the lower surface of the low-concentration region 52a.

[0035] Furthermore, in the embodiment described above (i.e., Figure 2), the lower end of the low-concentration region 52a and the lower end of the high-concentration region 52b were located below the lower end of the trench 22. However, as shown in Figure 6, the lower end of the low-concentration region 52a and the lower end of the high-concentration region 52b may be located above the lower end of the trench 22 and below the lower end of the body region 34.

[0036] Furthermore, in the embodiment described above, there were no contact portions in the interlayer insulating film 70 within the range covering the deep region 52. However, contact portions of electrodes other than the emitter electrode 72 (for example, floating electrodes) may be provided in the interlayer insulating film 70 within the range covering the deep region 52.

[0037] Furthermore, in the above-described embodiment, no structure was provided on the upper part of the interlayer insulating film 70 within the range covering the deep region 52. However, gate wiring or the like may be provided on the upper part of the interlayer insulating film 70 within the range covering the deep region 52.

[0038] Furthermore, although the FLR62 was provided within the outer peripheral region 60 in the embodiment described above, other pressure-resistant structures (for example, a resurf layer) may be provided within the outer peripheral region 60.

[0039] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0040] 20: Element region, 26: Gate terminal, 30: Emitter region, 32: Contact region, 34: Body region, 36: Drift region, 50: Intermediate region, 52: Deep region, 52a: Low concentration region, 52b: High concentration region, 60: Outer region, 62: Guard ring

Claims

1. A semiconductor device, A semiconductor substrate having an element region (20) on which an insulated gate bipolar transistor is provided, an intermediate region (50) located on the outer periphery of the element region, and an outer periphery region (60) located on the outer periphery of the intermediate region, wherein a trench (22) is provided on the upper surface within the element region, A gate insulating film (24) covering the inner surface of the trench, A gate electrode (26) is disposed within the trench and is insulated from the semiconductor substrate by the gate insulating film, The emitter electrode (72) in contact with the upper surface within the element region, It has, The element region is An n-type emitter region (30) is in contact with the gate insulating film on the side surface of the trench and in ohmic contact with the emitter electrode, A p-type contact region (32) that is in ohmic contact with the emitter electrode, A p-type region having a lower p-type impurity concentration than the contact region, in contact with the emitter region and the contact region, and a body region (34) in contact with the gate insulating film on the side surface of the trench below the emitter region, It has, The intermediate region extends from the upper surface of the semiconductor substrate to a position below the lower end of the body region, and has a p-shaped deep region (52) that is in contact with the body region from the outer periphery. The aforementioned semiconductor substrate An n-type drift region (36) extends across the element region, the intermediate region, and the outer peripheral region, and is in contact with the body region and the deep region from below, A p-type collector region (40) extends across the element region, the intermediate region, and the outer peripheral region, and is located below the drift region. It has, The emitter electrode does not have a contact portion with respect to the deep region. The aforementioned deep region, A p-type low-concentration region (52a) that is in contact with the body region from the outer periphery, A high-concentration region (52b) of p-type impurities that is in contact with the low-concentration region from the outer periphery and has a higher p-type impurity concentration than the low-concentration region, It has, In the direction from the element region toward the outer peripheral region, the width of the low-concentration region is wider than the width of the high-concentration region. Semiconductor equipment.

2. The contact region is located between the trench and the deep region. The distance between the contact region and the deep region in the direction from the element region toward the outer peripheral region is 16 μm or more. The width of the low-concentration region in the aforementioned direction is 155 μm or more. The p-type impurity concentration in the low-concentration region is 5 × 10 １６ cm －３ The following is: The semiconductor device according to claim 1.

3. The lower end of the high-concentration region is located below the lower end of the low-concentration region. The high-concentration region is in contact with the outer periphery of the lower surface of the low-concentration region. A semiconductor device according to claim 1 or 2.

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