Semiconductor equipment

Abstract

To provide a technique capable of improving a short circuit resistance amount of a semiconductor device constructed by a semiconductor substrate of silicon carbide.SOLUTION: A semiconductor substrate 10 of silicon carbide, includes a super junction structure 13 in which a p-type region 13p and an n-type region 13n are alternately and repeatedly arranged along one direction of an in-surface direction of a semiconductor substrate. When a width of the p-type region is a first value, a width of the n-type region is a second value, a range where a terminal is existed onto an upper side of the semiconductor substrate is a terminal existence range 62, and a range where no terminal exists onto the upper side of the semiconductor substrate is a terminal non-existence range 64, first value / second value obtained by dividing the first value of the super junction structure provided in the terminal non-existence range by the second value is larger than first value / second value obtained by dividing the first value of the super junction structure provided in the terminal existence range by the second value.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device.

[0002] A semiconductor device includes a semiconductor substrate on which a switching element is formed, an electrode provided on the upper surface of the semiconductor substrate, and a terminal provided on the electrode. The terminal is a metal block and is provided to dissipate heat generated when the switching element operates. An example of such a semiconductor device is disclosed in Patent Document 1.

[0003] By the way, a superjunction structure may be formed on the semiconductor substrate of this type of semiconductor device in order to achieve both high breakdown voltage and low on-resistance of the switching element. The superjunction structure is a structure in which p-type regions and n-type regions are alternately and repeatedly arranged along one direction in the in-plane direction of the semiconductor substrate.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Depending on the layout of the electrode provided on the upper surface of the semiconductor substrate, the terminal may be arranged only on a part of the electrode. In this case, in the semiconductor substrate in the range where there is no terminal above, since the distance to the terminal is far, the temperature is likely to rise due to Joule heat caused by the current flowing through the switching element.

[0006] Our research has shown that the short-circuit withstand capability of a semiconductor device composed of a silicon carbide (SiC) semiconductor substrate is determined by the breakdown of electrodes with relatively low melting points. Therefore, it has been found that heat generation in the semiconductor substrate in areas where no terminals are located above it can be one of the factors that limit the short-circuit withstand capability of a semiconductor device. This specification provides a technique for improving the short-circuit withstand capability of a semiconductor device composed of a silicon carbide semiconductor substrate. [Means for solving the problem]

[0007] A semiconductor device disclosed herein may include a silicon carbide semiconductor substrate (10), an electrode (24) provided on one main surface of the semiconductor substrate, and a terminal (40) provided on a part of the electrode. The semiconductor substrate may have a superjunction structure (13) in which p-type regions (13p) and n-type regions (13n) are alternately and repeatedly arranged along one of the in-plane directions of the semiconductor substrate. If the width of the p-type region measured along the one direction is taken as a first value, and the width of the n-type region measured along the one direction is taken as a second value, and the area of ​​the semiconductor substrate in which the terminal exists above is taken as a terminal presence area (62), and the area of ​​the semiconductor substrate in which the terminal does not exist above is taken as a terminal absence area (64), then the first value / second value obtained by dividing the first value by the second value for the superjunction structure provided in the terminal absence area may be greater than the first value / second value obtained by dividing the first value by the second value for the superjunction structure provided in the terminal presence area.

[0008] In the semiconductor device described above, the heat-generating portion of the superjunction structure located in the terminal-free region is moved deeper into the semiconductor substrate than the heat-generating portion of the superjunction structure located in the terminal-present region. Therefore, even if a large current flows due to a load short circuit, the distance between the electrode and the heat-generating portion is maintained in the terminal-free region, thereby suppressing the destruction of the electrode in the terminal-free region. As a result, the semiconductor device can have high short-circuit withstand capability. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic diagram showing a cross-section of a semiconductor device. [Figure 2] This is a plan view illustrating the layout of source electrodes, source pads, and terminals on the top surface of a semiconductor substrate. [Figure 3] This diagram schematically shows a perspective view of the main part of a switching element formed on a semiconductor substrate. [Figure 4] This is an enlarged cross-sectional view of the main part of the superjunction structure of a switching element. [Modes for carrying out the invention]

[0010] Hereinafter, semiconductor devices to which the technology disclosed herein is applied will be described with reference to the drawings. In the following drawings, for illustrative purposes only, only some of the repeatedly formed components may be given reference numerals.

[0011] As shown in Figure 1, the semiconductor device 100 includes a semiconductor substrate 10 on which switching elements are formed. The material of the semiconductor substrate 10 is silicon carbide (SiC). Hereafter, one of the in-plane directions of the semiconductor substrate 10 will be referred to as the x-direction, the direction perpendicular to the x-direction of the semiconductor substrate 10 will be referred to as the y-direction, and the direction perpendicular to the semiconductor substrate 10 will be referred to as the z-direction.

[0012] A drain electrode 22 is provided on the lower surface of the semiconductor substrate 10, and a source electrode 24 (also called a source pad) and a gate pad 26 are provided on the upper surface of the semiconductor substrate 10. The drain electrode 22, source electrode 24, and gate pad 26 are made of, for example, aluminum. The drain electrode 22 covers the entire lower surface of the semiconductor substrate 10. The source electrode 24 and gate pad 26 each cover a portion of the upper surface of the semiconductor substrate 10. The layout of the source electrode 24 and gate pad 26 will be described later.

[0013] The semiconductor device 100 further includes a terminal 40, an upper heat sink 42, a lower heat sink 44, bonding wires 46, and a gate terminal 48.

[0014] Terminal 40 is a metal block (for example, a copper block). The lower surface of terminal 40 is joined to the source electrode 24 via a solder layer (not shown). The upper surface of terminal 40 is joined to the upper heat sink 42 via a solder layer (not shown). In this way, terminal 40 is provided between the source electrode 24 and the upper heat sink 42, and thermally connects the source electrode 24 and the upper heat sink 42. The upper heat sink 42 is a metal plate. The upper heat sink 42 dissipates heat transferred from the semiconductor substrate 10 and also functions as an electrode plate connected to the source electrode 24.

[0015] The lower heat sink 44 is joined to the drain electrode 22 via a solder layer (not shown). The lower heat sink 44 is a metal plate. The lower heat sink 44 dissipates heat transferred from the semiconductor substrate 10 and also functions as an electrode plate connected to the drain electrode 22.

[0016] The gate pad 26 is electrically connected to the gate terminal 48 via a bonding wire 46. The gate terminal 48 receives a gate signal for controlling a switching element formed in the semiconductor substrate 10.

[0017] A part of the semiconductor substrate 10, the terminal 40, the heat sinks 42 and 44, the bonding wires 46, and the gate terminal 48 is covered with an insulating resin 50. The semiconductor device 100 configured as described above may be used, for example, as a power module that constitutes an inverter.

[0018] As shown in FIG. 2, a source electrode 24 and a gate pad 26 are provided on the upper surface of the semiconductor substrate 10. The source electrode 24 is provided so as to cover most of the upper surface of the semiconductor substrate 10 except for the formation range of the gate pad 26. The gate pad 26 is substantially rectangular in plan view and is disposed adjacent to one side surface of the semiconductor substrate 10. Thus, the gate pad 26 is provided so as to fit into the recess of the source electrode 24 having a concave shape in plan view. Note that such a layout of the source electrode 24 and the gate pad 26 is an example, and various other layouts can be adopted. In addition to the source electrode 24 and the gate pad 26, pads for inputting and outputting signals to and from a sensor formed in the semiconductor substrate 10 may be provided on the upper surface of the semiconductor substrate 10.

[0019] The terminal 40 is substantially rectangular in plan view and is provided on a part of the source electrode 24. The terminal 40 is not provided on the source electrode 24 located on both sides of the gate pad 26. For this reason, the semiconductor substrate 10 has a terminal presence range 62 where the terminal 40 exists above it and a terminal non - existence range 64 where the terminal 40 does not exist above it. Further, the terminal non - existence range 64 has a first terminal non - existence range 66 and a second terminal non - existence range 68 that is farther from the terminal presence range than the first terminal non - existence range 66.

[0020] FIG. 3 shows a unit cell of the switching element 1 formed in the semiconductor substrate 10. The switching element 1 is a type of power device called a MOSFET. Note that the switching element 1 may be a type of power device called an IGBT.

[0021] As shown in FIG. 3, the semiconductor substrate 10 includes an n + -type drain region 11, an n - -type lower drift region 12, a super junction structure 13 (hereinafter referred to as "SJ structure 13"), an n-type upper drift region 14, a p-type deep p region 15, a p-type body region 16, an n + -type source region 17, and a p + -type contact region 18. Further, a trench gate 30 is formed in the upper layer portion of the semiconductor substrate 10.

[0022] The drain region 11 is an n-type region containing a high concentration of n-type impurities. The drain region 11 is disposed at a position exposed on the lower surface of the semiconductor substrate 10. The drain region 11 is in ohmic contact with the drain electrode 22.

[0023] The lower drift region 12 is provided on the drain region 11 and is an n-type region having an n-type impurity concentration lower than that of the drain region 11.

[0024] The SJ structure 13 is provided on the lower drift region 12 and has a plurality of p-type regions 13p containing p-type impurities and a plurality of n-type regions 13n containing n-type impurities. Each of the p-type regions 13p and the n-type regions 13n has a generally flat plate shape and extends parallel to the xz plane in this example. The p-type regions 13p and the n-type regions 13n are also alternately and repeatedly arranged along one direction (in this example, the y direction, hereinafter referred to as the "repeating direction") in the in-plane direction of the semiconductor substrate 10. Note that each of the plurality of n-type regions 13n may be formed deeper so as to cover the bottom surface of the p-type region 13p.

[0025] Figure 4 shows an enlarged cross-sectional view of the main part of the superjunction structure 13. In the repeating direction (i.e., the y-direction) of the superjunction structure 13, the width of the p-type region 13p is Wp, and the width of the n-type region 13n is Wn. The width Wp and p-type impurity concentration of the p-type region 13p, and the width Wn and n-type impurity concentration of the n-type region 13n are designed so as not to significantly disrupt the charge balance, so as to achieve both high breakdown voltage and low on-resistance of the switching element 1.

[0026] Returning to Figure 3, the upper drift region 14 is located on the SJ structure 13 and is an n-type region containing n-type impurities. The concentration of n-type impurities in the upper drift region 14 may be the same as that of the lower drift region 12, or it may be higher than that of the lower drift region 12. The upper drift region 14 is in contact with the lower portion and bottom surface of the side surface of the trench gate 30.

[0027] The deep p-region 15 extends through the upper drift region 14 and is a p-type region containing p-type impurities. The upper end of the deep p-region 15 is in contact with the body region 16, and the lower end is in contact with the SJ structure 13. When the semiconductor substrate 10 is viewed from above, the deep p-region 15 extends non-parallel to the p-type region 13p of the SJ structure 13 (in this example, in a direction perpendicular to it, the y-direction), and is in contact with each of the multiple p-type regions 13p of the SJ structure 13. As a result, the p-type region 13p of the SJ structure 13 is electrically connected to the body region 16 via the deep p-region 15. Furthermore, the deep p-region 15 extends so as to intersect with the trench gate 30 and is in contact with a part of the bottom surface of the trench gate 30. Thus, the deep p-region 15 plays the role of electrically connecting the p-type region 13p of the SJ structure 13 to the body region 16 and mitigating the electric field at the bottom surface of the trench gate 30. In this example, the upper drift region 14 and the deep p region 15 have a structure that is repeatedly arranged in the x direction. However, the deep p region 15 is formed for the reasons described above, and the repeating structure of the upper drift region 14 and the deep p region 15 is a different region from the SJ structure 13. The upper drift region 14 and the deep p region 15 are composed of different widths and densities from the n-type region 13n and p-type region 13p that constitute the SJ structure 13.

[0028] The body region 16 is located on the upper drift region 14 and the deep p region 15, and is a p-type region containing p-type impurities. The body region 16 is in contact with the side surface of the trench gate 30 and separates the upper drift region 14 from the source region 17.

[0029] The source region 17 is located on the body region 16 and is exposed on the upper surface of the semiconductor substrate 10. It is an n-type region containing a high concentration of n-type impurities. The source region 17 is in contact with the upper portion of the side surface of the trench gate 30. The source region 17 is in ohmic contact with the source electrode 24.

[0030] The contact region 18 is located on the body region 16 and is exposed on the upper surface of the semiconductor substrate 10. It is a p-type region containing a higher concentration of p-type impurities than the body region 16. The contact region 18 is in ohmic contact with the source electrode 24.

[0031] The trench gate 30 extends from the top surface of the semiconductor substrate 10, beyond the source region 17 and body region 16, to reach the upper drift region 14 and deep p region 15. The trench gate 30 extends along one of the in-plane directions of the semiconductor substrate 10 (in this example, the x-direction). The trench gate 30 has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 is insulated from the upper drift region 14, body region 16 and source region 17 by the gate insulating film 34, and is insulated from the source electrode 24 by the interlayer insulating film. A field relaxation region containing p-type impurities may be provided so as to be in contact with the bottom surface of the trench gate 30.

[0032] Note that the structure of the switching element 1 described above is just one example. The technology disclosed herein is applicable to various types of switching elements having a superjunction structure 13.

[0033] Next, the operation of the switching element 1 will be described. When a voltage greater than the gate threshold voltage is applied to the gate electrode 32 while the drain electrode 22 is at a higher potential than the source electrode 24, a channel is formed in the body region 16 adjacent to the gate insulating film 34. Electrons supplied from the source region 17 flow into the upper drift region 14 through this channel. Electrons that have flowed into the upper drift region 14 flow to the drain region 11 through the n-type region 13n and the lower drift region 12 of the SJ structure 13. As a result, conduction occurs between the drain electrode 22 and the source electrode 24, and the switching element 1 turns on. On the other hand, when a voltage less than the gate threshold voltage is applied to the gate electrode 32, the channel disappears, and the switching element 1 turns off. In this way, the switching element 1 can operate to control the current flowing between the drain electrode 22 and the source electrode 24 according to the voltage applied to the gate electrode 32.

[0034] When the load connected to the semiconductor device 100 is short-circuited, a large current flows through the semiconductor substrate 10 on which the switching element 1 is formed, causing the semiconductor substrate 10 to heat up due to Joule heating. The heat generated in the semiconductor substrate 10 is dissipated through the terminal 40. However, as shown in Figure 2, in the terminal-free region 64 of the semiconductor substrate 10 where there is no terminal 40 above, the temperature tends to rise easily due to the distance to the terminal 40.

[0035] The short-circuit withstand capability of a semiconductor device 100, which is composed of a silicon carbide (SiC) semiconductor substrate 10, is determined by the destruction of the source electrode 24, which has a relatively low melting point. Heat generated in the semiconductor substrate 10 in the terminal-free region 64 can destroy the source electrode 24 at that location and limit the short-circuit withstand capability of the semiconductor device 100.

[0036] When a large current flows through the switching element 1, the heat-generating area (hot spot) is the n-type region 13n of the superjunction structure 13. When Wp / Wn, which is obtained by dividing the width Wp of the p-type region 13p of the SJ structure 13 by the width Wn of the n-type region 13n, becomes large, the heat-generating area moves to the deeper side within the n-type region 13n.

[0037] In the switching element 1, the Wp / Wn of the superjunction structure 13 provided in the terminal non-existent region 64 is greater than the Wp / Wn of the superjunction structure 13 provided in the terminal present region 62. For example, the width Wn of each n-type region 13n in the terminal present region 62 and the terminal non-existent region 64 may be constant, and the width Wp of the p-type region 13p in the terminal present region 62 may be smaller than the width Wp of the p-type region 13p in the terminal non-existent region 64. Alternatively, the width Wp of each p-type region 13p in the terminal present region 62 and the terminal non-existent region 64 may be constant, and the width Wn of the n-type region 13n in the terminal present region 62 may be larger than the width Wn of the n-type region 13n in the terminal non-existent region 64. Alternatively, the width Wp of the p-type region 13p in the terminal presence area 62 may be smaller than the width Wp of the p-type region 13p in the non-terminal presence area 64, and the width Wn of the n-type region 13n in the terminal presence area 62 may be larger than the width Wn of the n-type region 13n in the non-terminal presence area 64.

[0038] Thus, since the Wp / Wn of the superjunction structure 13 provided in the terminal-free region 64 is configured to be relatively large, the heat-generating area in the terminal-free region 64 is moved to a relatively deeper side. Therefore, even if a large current flows due to a load short circuit, the distance between the source electrode 24 and the heat-generating area is secured in the terminal-free region 64, so the destruction of the source electrode 24 in the terminal-free region 64 is suppressed. As a result, the semiconductor device 100 can have high short-circuit withstand capability.

[0039] As shown in Figure 2, the terminal non-existent range 64 further includes a first terminal non-existent range 66 and a second terminal non-existent range 68 which is further from the terminal present range 62 than the first terminal non-existent range 66. In the switching element 1, the Wp / Wn of the superjunction structure 13 provided in the second terminal non-existent range 68 is greater than the Wp / Wn of the superjunction structure 13 provided in the first terminal non-existent range 66.

[0040] As described above, the width Wp and p-type impurity concentration of the p-type region 13p and the width Wn and n-type impurity concentration of the n-type region 13n constituting the SJ structure 13 are designed so as not to significantly disrupt the charge balance, thereby achieving both high voltage withstand capability and low on-resistance in the switching element 1. The SJ structure 13 in the terminal presence range 62 is formed based on these design values. On the other hand, the SJ structure 13 in the terminal non-present range 64 has a more disrupted charge balance than the SJ structure 13 in the terminal presence range 62 in order to improve short-circuit withstand capability. Therefore, in the SJ structure 13 in the terminal non-present range 64, achieving both high voltage withstand capability and low on-resistance may be sacrificed. In the semiconductor device 100, by adjusting the Wp / Wn of the superjunction structure 13 according to the distance from the terminal 40 even within the terminal non-present range 64, it is possible to have high short-circuit withstand capability while maintaining both high voltage withstand capability and low on-resistance.

[0041] Furthermore, in each of the first terminal non-existence area 66 and the second terminal non-existence area 68, Wp / Wn may be constant or may change according to the distance from terminal 40. That is, in the terminal non-existence area 64, Wp / Wn of the superjunction structure 13 may change continuously or in multiple stages according to the distance from terminal 40.

[0042] The features of the technology disclosed herein are summarized below. Note that the technical elements described below are independent elements that exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

[0043] (Feature 1) A silicon carbide semiconductor substrate (10), An electrode (24) provided on one main surface of the semiconductor substrate, The device includes a terminal (40) provided on a part of the electrode, The semiconductor substrate has a superjunction structure (13) in which p-type regions (13p) and n-type regions (13n) are alternately and repeatedly arranged along one of the in-plane directions of the semiconductor substrate. The width of the p-type region measured along the aforementioned one direction is taken as the first value. The width of the n-type region measured along the aforementioned one direction is taken as the second value. The area of ​​the semiconductor substrate in which the terminal is located at the top is defined as the terminal presence area (62). If the area of ​​the semiconductor substrate in which the terminal does not exist above is defined as the terminal-free area (64), A semiconductor device wherein the first value / second value obtained by dividing the first value of the superjunction structure provided in the terminal-absent region by the second value is greater than the first value / second value obtained by dividing the first value of the superjunction structure provided in the terminal-absent region by the second value.

[0044] (Feature 2) The semiconductor device according to feature 1, wherein the first value of the p-type region in the terminal presence range is smaller than the first value of the p-type region in the terminal non-present range.

[0045] (Feature 3) The semiconductor device according to feature 1, wherein the second value of the n-type region in the terminal presence range is greater than the second value of the n-type region in the terminal non-present range.

[0046] (Feature 4) The aforementioned terminal non-existent range comprises a first terminal non-existent range (66) and a second terminal non-existent range (68) that is further from the terminal-existent range than the first terminal non-existent range. The semiconductor device according to any one of features 1 to 3, wherein the first value / second value of the superjunction structure provided in the second terminal non-existent region is greater than the first value / second value of the superjunction structure provided in the first terminal non-existent region.

[0047] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0048] 1: Switching element, 10: Semiconductor substrate, 11: Drain region, 12: Lower drift region, 13: Superjunction structure, 13n: n-type region, 13p: p-type region, 14: Upper drift region, 15: Deep p-region, 16: Body region, 17: Source region, 18: Contact region, 22: Drain electrode, 24: Source electrode, 26: Gate pad, 30: Trench gate, 32: Gate electrode, 34: Gate insulating film, 40: Terminal, 42: Upper heat sink, 44: Lower heat sink, 46: Bonding wire, 48: Gate terminal, 50: Insulating resin, 62: Terminal presence region, 64: Terminal absence region, 66: First terminal absence region, 68: Second terminal absence region, 100: Semiconductor device

Claims

1. A silicon carbide semiconductor substrate (10) and An electrode (24) provided on one main surface of the semiconductor substrate, The device includes a terminal (40) provided on a part of the electrode, The semiconductor substrate has a superjunction structure (13) in which p-type regions (13p) and n-type regions (13n) are alternately and repeatedly arranged along one of the in-plane directions of the semiconductor substrate. The width of the p-type region measured along the aforementioned one direction is taken as the first value. The width of the n-type region measured along the aforementioned one direction is taken as the second value. The area of ​​the semiconductor substrate in which the terminal is located at the top is defined as the terminal presence area (62). If the area of ​​the semiconductor substrate in which the terminal does not exist above is defined as the terminal-free area (64), A semiconductor device wherein the first value / second value obtained by dividing the first value of the superjunction structure provided in the terminal-absent region by the second value is greater than the first value / second value obtained by dividing the first value of the superjunction structure provided in the terminal-absent region by the second value.

2. The semiconductor device according to claim 1, wherein the first value of the p-type region in the terminal presence range is smaller than the first value of the p-type region in the terminal non-present range.

3. The semiconductor device according to claim 1, wherein the second value of the n-type region in the terminal presence range is greater than the second value of the n-type region in the terminal non-present range.

4. The aforementioned terminal non-existent range includes a first terminal non-existent range (66) and a second terminal non-existent range (68) that is further from the terminal-existent range than the first terminal non-existent range. The semiconductor device according to any one of claims 1 to 3, wherein the first value / second value of the superjunction structure provided in the region where the second terminal is absent is greater than the first value / second value of the superjunction structure provided in the region where the first terminal is absent.

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