Semiconductor packaging equipment

Abstract

The present invention relates to a semiconductor packaging apparatus, and more particularly, to a semiconductor packaging apparatus for packaging semiconductor devices by a wafer level packaging method. A semiconductor packaging apparatus according to an embodiment of the present invention includes a loading unit having a space capable of performing a process of placing a mask member on a wafer having a plurality of semiconductor elements, a deposition unit connected to the loading unit having a space capable of receiving the wafer and the mask member from the loading unit and performing a process of forming a conductive pattern layer on the wafer, and an unloading unit connected to the deposition unit having a space capable of receiving the wafer and the mask member from the deposition unit and performing a process of separating the mask member on the wafer.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging apparatus, and more particularly, to a semiconductor packaging apparatus for packaging semiconductor elements by a wafer-level packaging method.

Background Art

[0002] The packaging process refers to the process of packaging semiconductor elements in order to protect the semiconductor elements from the external environment. Such a packaging process involves a process of forming a conductive pattern to arrange the wirings of the semiconductor elements so as to exchange signals with external devices.

[0003] In the existing packaging process, a wafer having a plurality of semiconductor elements is cut along a dicing line to be separated into individual semiconductor elements, and then the packaging process is performed for each of the separated individual semiconductor elements. Since such an existing packaging process is forced to perform the packaging process in chip units, it has taken a very long time to package all semiconductor elements.

[0004] Therefore, recently, a wafer-level packaging method has been used in which first the packaging process is performed in the state of a wafer having a plurality of semiconductor elements, and then the wafer is diced for each semiconductor element.

[0005] Semiconductor packaging equipment utilizing this wafer-level packaging method generally forms conductive patterns for arranging the wiring of semiconductor elements using a photolithography process. However, this photolithography process requires the semiconductor packaging equipment to perform complex steps such as coating the wafer with photoresist, exposure, development, and etching, and then removing the photoresist. This makes it difficult to effectively shorten the time required to package semiconductor elements. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Republic of Korea Publication Patent No. 10-2001-0061786 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] The present invention provides a semiconductor packaging apparatus that can improve the productivity of semiconductor devices. [Means for solving the problem]

[0008] A semiconductor packaging apparatus according to an embodiment of the present invention comprises: a loading section having a space capable of performing the step of placing a mask member on a wafer comprising a plurality of semiconductor elements; a deposition section having a space capable of receiving a wafer and a mask member from the loading section and performing the step of forming a conductive pattern layer on the wafer, and connected to the loading section; and an unloading section having a space capable of receiving a wafer and a mask member from the deposition section and performing the step of separating the mask member on the wafer, and connected to the deposition section.

[0009] The loading section may be connected to one side of the deposition section, and the unloading section may be connected to the other side of the deposition section, which is opposite to the one side of the deposition section.

[0010] The loading section may include a first load lock section connected to the deposition section, a first wafer storage section having a space for storing a plurality of wafers and connected to the first load lock section, a first mask storage section having a space for storing a plurality of mask members and connected to the first load lock section, and an alignment section having a space for receiving wafers and mask members from the first wafer storage section and the first mask storage section, respectively, and aligning and fixing the mask members on the wafers, and connected to the first load lock section.

[0011] The deposition unit may include: a deposition chamber that provides at least a portion of a space in which a conductive pattern layer can be formed on a wafer; a support unit disposed within the deposition chamber so as to be able to support the handed-over wafer and mask member; a sputtering target unit disposed within the deposition chamber so as to face the support unit; and a power supply unit for supplying power to the sputtering target unit.

[0012] The support portion may include a moving member for moving the received wafer and mask member.

[0013] The moving member may include a roller plate or a conveyor belt.

[0014] The support portion may have a mounting surface on which multiple wafers can be placed.

[0015] The deposition unit may include a first deposition unit connected to the loading unit for forming a lower conductive pattern layer on a passivation layer formed on a wafer, and a second deposition unit connected to the first deposition unit for forming an upper conductive pattern layer made of a different material from the lower conductive pattern layer on the lower conductive pattern layer.

[0016] The second deposition section may be provided in multiple units connected to one another.

[0017] The unloading unit may include a second load lock unit connected to the deposition unit, a second wafer storage unit having a space for storing a plurality of wafers and connected to the second load lock unit, a second mask storage unit having a space for storing a plurality of mask members and connected to the second load lock unit, and a separation unit having a space for receiving wafers and mask members from the second load lock unit and separating mask members on the wafers and connected to the second load lock unit.

[0018] The semiconductor packaging apparatus may further include a transport unit connecting the unloading unit and the loading unit in order to unload the mask member from the unloading unit and transport it into the loading unit.

[0019] The transport unit may also include a washing unit for washing the mask members that have been unloaded from the unloading unit. [Effects of the Invention]

[0020] According to the semiconductor packaging apparatus of the present invention, a conductive pattern layer can be formed on a wafer equipped with multiple semiconductor elements by a single process using a mask member provided separately from the wafer, thereby minimizing the number of processes required to form the conductive pattern layer.

[0021] This makes it possible to minimize the time required for packaging the semiconductor device, minimize the cost of materials used in the process, and improve the productivity of the semiconductor chip.

Brief Description of the Drawings

[0022] [Figure 1] It is a diagram schematically showing a semiconductor packaging apparatus according to an embodiment of the present invention. [Figure 2] It is a diagram showing a state of forming a conductive pattern layer on a wafer according to an embodiment of the present invention. [Figure 3] It is a diagram showing a state of forming a conductive pattern layer on a wafer according to an embodiment of the present invention. [Figure 4] It is a diagram showing a specific structure of a semiconductor packaging apparatus according to an embodiment of the present invention. [Figure 5] It is a diagram schematically showing a vapor deposition part according to an embodiment of the present invention.

Modes for Carrying Out the Invention

[0023] Hereinafter, embodiments of the present invention will be described in more detail based on the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and can be embodied in various different forms. The following embodiments are provided only to make the disclosure of the present invention complete and to fully inform those with ordinary knowledge of the scope of the invention. Note that the drawings may be shown exaggerated for the purpose of explaining the present invention in detail, and in the drawings, the same reference numerals indicate the same components.

[0024] FIG. 1 is a diagram schematically showing a semiconductor packaging apparatus according to an embodiment of the present invention, and FIGS. 2 and 3 are diagrams showing a state of forming a conductive pattern layer on a wafer according to an embodiment of the present invention.

[0025] Referring to Figures 1 to 3, the semiconductor packaging apparatus according to an embodiment of the present invention includes a loading unit 100 having a space capable of performing the step of placing a mask member M1 or M2 on a wafer W having a plurality of semiconductor elements; a deposition unit 200 connected to the loading unit 100, having a space capable of receiving the wafer W and the mask member M1 or M2 from the loading unit 100 and performing the step of forming a conductive pattern layer MP1 or MP2 on the wafer W; and an unloading unit 300 connected to the deposition unit 200, having a space capable of receiving the wafer W and the mask member M1 or M2 from the deposition unit 200 and performing the step of separating the mask member M1 or M2 on the wafer W.

[0026] Existing packaging processes involved cutting a wafer containing multiple semiconductor elements along a dicing line to separate them into individual semiconductor elements, and then performing a packaging process for each separated semiconductor element. Because this existing packaging process necessitated packaging on a chip-by-chip basis, it took an extremely long time to package all the semiconductor elements.

[0027] Here, the semiconductor packaging apparatus according to the embodiment of the present invention may be an apparatus that performs the packaging process using a wafer-level packaging method. Here, the wafer-level packaging method means a method in which, in the state of a wafer containing multiple semiconductor elements, the packaging process is first performed, and then the wafer is diced for each semiconductor element.

[0028] On the other hand, conventional wafer-level packaging methods used photolithography to form conductive patterns for organizing the wiring of semiconductor elements. However, this photolithography method involves a complex process of coating a wafer W with photoresist, followed by exposure, development, and etching, and then removing the photoresist. As a result, it takes a very long time to package the wafer W.

[0029] Therefore, the semiconductor packaging apparatus according to the embodiment of the present invention minimizes the number of steps required to form a conductive pattern layer by forming a conductive pattern layer on a wafer W on which a plurality of semiconductor elements are formed using a mask member M1 or M2.

[0030] For example, as shown in Figure 2, the semiconductor packaging apparatus according to an embodiment of the present invention can form a first conductive pattern layer MP1 on an exposed region formed on the first passivation layer P1.

[0031] To form the first conductive pattern layer MP1, a wafer W on which multiple semiconductor elements are formed is first prepared. Here, wafer W refers to a configuration in which multiple unit circuits are arranged on a single substrate. In this case, a unit circuit may refer to a semiconductor element and its wiring structure that performs functions such as information switching, storage, and calculation.

[0032] On the other hand, a first passivation layer P1 may be formed on the prepared wafer W, exposing at least a portion of the input / output pads D of the multiple semiconductor elements. Each of the multiple semiconductor elements may have input / output pads D for electrical connection with external devices. In this case, the first passivation layer P1 is formed on the multiple semiconductor elements D so as to expose the input / output pads D of each semiconductor element.

[0033] Here, the first passivation layer P1 can be formed by first forming a first passivation film on a wafer W, and then patterning the formed first passivation film by laser drilling or photolithography, or by patterning using a mask. At this time, the first passivation layer is made of polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), (BT: bismaleimide triazine), phenolic resin, epoxy, silicone, and oxide film (SiO x ) and nitride film (SiN x ) may be formed from at least one of the following materials.

[0034] The first conductive pattern layer MP1 may be formed on the wafer W using the first mask member M1. Here, the first conductive pattern layer MP1 may include a conductive metal pattern layer, and the first mask member M1 may include a shadow mask provided separately from the wafer W.

[0035] The first conductive pattern layer MP1 plays the role of rerouting the electrical paths of the semiconductor device. That is, the first conductive pattern layer MP1 reroutes the electrical paths of the semiconductor device to electrically connect the semiconductor chip to external devices, regardless of the position of the input / output pads D of the semiconductor device. Such a first conductive pattern layer MP1 may consist of a highly conductive metallic material such as copper, silver, aluminum, or nickel, or an alloy material containing other components.

[0036] The first conductive pattern layer MP1 may be formed by placing a first mask member M1 on a wafer W and supplying a conductive material such as a metallic substance to the wafer W so as to pass through the first mask member M1, thereby depositing the conductive material on the wafer W in the same shape as the pattern of the first mask member M1.

[0037] Furthermore, as shown in Figure 3, in the semiconductor packaging apparatus according to the embodiment of the present invention, a second conductive pattern layer MP2 may be formed on the exposed region formed on the second passivation layer P2.

[0038] To form the second conductive pattern layer MP2, first, a second passivation layer P2 is formed on the first conductive pattern layer MP1. Here, the second passivation layer P2 may be formed by first forming a second passivation film on the first conductive pattern layer MP1 and then patterning the formed second passivation film by laser drilling or photolithography, or the second passivation layer P2 may be formed by directly patterning using a mask. In this case, the second passivation layer P2 may be made of polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), (BT: bismaleimide triazine), phenolic resin, epoxy, silicone, or oxide film (SiO x ) and nitride film (SiN x It can be formed from at least one of the following materials.

[0039] In this case, the second passivation layer P2 may be formed from a different material than the first passivation layer P1. When the first passivation layer P1 and the second passivation layer P2 are formed from different materials, the penetrated moisture and other substances move along the boundary between the films made of different materials, resulting in an increased distance of movement, which in turn prevents the penetration of moisture and other substances.

[0040] After the second passivation layer P2 is formed, a second conductive pattern layer MP2 may be formed on the second passivation layer P2. The second conductive pattern layer MP2 may be formed on the exposed region formed on the second passivation layer P2, and the second conductive pattern layer MP2 may be formed using a second mask member M1. Here, as with the first conductive pattern layer MP1, the second conductive pattern layer MP2 may include a conductive metal pattern layer, and the second mask member M1 may include a shadow mask provided separately from the wafer W.

[0041] Here, the second conductive pattern layer MP2 serves as a seed layer for forming conductive bumps. Such a second conductive pattern layer MP2 may consist of metallic materials such as copper, silver, aluminum, nickel, chromium, titanium, and tungsten, or alloy materials containing other components. The second conductive pattern layer MP2 may also be formed by laminating multiple layers, in which case it may be formed by laminating multiple layers of chromium, a chromium-copper alloy, and copper, multiple layers of titanium-tungsten alloy and copper, or multiple layers of aluminum, nickel, and copper.

[0042] The second conductive pattern layer MP2 may be formed on the second passivation layer P2 by placing a second mask member M2 on the wafer W on which the second passivation layer P2 is formed, and supplying a conductive material onto the wafer W so as to pass through the second mask member M2, thereby forming the second conductive pattern layer MP2 on the second passivation layer P2 in the same shape as the pattern of the second mask member M2. Although not shown in the figures, after forming the second conductive pattern layer MP2, conductive bumps may be formed on the second conductive pattern layer MP2, and after forming the conductive bumps, the wafer W may be cut for each semiconductor element to form a plurality of semiconductor chips.

[0043] As described above, the semiconductor packaging apparatus according to the embodiment of the present invention may form a first conductive pattern layer MP1 or a second conductive pattern layer MP2 on a wafer on which a plurality of semiconductor elements are formed using a mask member M1 or M2. The detailed structure of the semiconductor packaging apparatus according to the embodiment of the present invention for forming the first conductive pattern layer MP1 or the second conductive pattern layer MP2 will be described in detail below with reference to Figures 4 and 5.

[0044] Figure 4 shows a specific structure of a semiconductor packaging apparatus according to an embodiment of the present invention, and Figure 5 is a schematic diagram showing a vapor deposition section according to an embodiment of the present invention.

[0045] As described above, the semiconductor packaging apparatus according to an embodiment of the present invention includes a loading unit 100 having a space capable of performing the step of placing a mask member M (M1 or M2) on a wafer W having a plurality of semiconductor elements; a deposition unit 200 connected to the loading unit 100, having a space capable of receiving the wafer W and the mask member M from the loading unit 100 and performing the step of forming a conductive pattern layer MP1 or MP2 on the wafer W; and an unloading unit 300 connected to the deposition unit 200, having a space capable of receiving the wafer W and the mask member M from the deposition unit 200 and performing the step of separating the mask member M on the wafer W.

[0046] In an embodiment of the present invention, the semiconductor packaging apparatus may have a loading unit 100, an evaporation unit 200, and an unloading unit 300 arranged in a cluster type. However, to increase the process speed and improve productivity, the loading unit 100 may be connected to one side of the evaporation unit 200 and the unloading unit 300 may be connected to the other side of the evaporation unit 200 in an in-line type arrangement. In this case, one side and the other side of the evaporation unit 200 may be in opposite directions.

[0047] The loading unit 100 has a space capable of performing the process of placing a mask member M on a wafer W having multiple semiconductor elements. For this purpose, the loading unit 100 may include a first load lock unit 150 connected to the deposition unit 200, a first wafer storage unit 110 having a space for storing multiple wafers W and connected to the first load lock unit 150, a first mask storage unit 120 having a space for storing multiple mask members M and connected to the first load lock unit 150, and an alignment unit 140 having a space for receiving wafers W and mask members M from the first wafer storage unit 110 and the first mask storage unit 120, respectively, and aligning and fixing the mask members M on the wafers W, and connected to the first load lock unit 150. Here, the alignment unit 140 may include a first robotic arm (not shown) for moving the wafer W and mask member M between the first wafer storage unit 110 and the first mask storage unit 120 and the first load lock unit 150.

[0048] The first wafer storage unit 110 may include a first wafer storage chamber and a first wafer storage cassette disposed inside the first wafer storage chamber. The first wafer storage cassette may store wafers W on which a plurality of unit circuits are formed. In this case, the wafer W may be a wafer W on which a first passivation layer P1 is formed so as to cover the plurality of unit circuits, or a wafer W on which a first conductive pattern layer MP1 and a second passivation layer P2 are further formed on the first passivation layer P1. Multiple such wafers W may be stored in the first wafer storage cassette in the vertical direction.

[0049] The first mask storage unit 120 may include a first mask storage chamber and a first mask storage cassette disposed inside the first mask storage chamber. The first mask storage cassette may store a first mask member M1 or a second mask member M2. Multiple such mask members M may be stored in a vertical direction.

[0050] The alignment unit 140 has a space for receiving wafers W and mask members M from the first wafer storage unit 110 and the first mask storage unit 120, respectively, and aligning and fixing the mask members M on top of the wafers W. Such an alignment unit 140 may include an alignment chamber, or it may include a first robot arm positioned within the alignment chamber. Here, the first robot arm may pull out the wafers W and mask members M from the first wafer storage unit 110 and the first mask storage unit 120, respectively, and move them to the first load lock unit 150. In the following description, we will use as an example a configuration in which the alignment unit 140, equipped with a first robot arm, moves the wafer W and mask member M, respectively, pulled out from the first wafer storage unit 110 and the first mask storage unit 120 to the first load lock unit 150, while aligning the mask member M on top of the wafer W. However, it goes without saying that the alignment unit 140 can also be provided separately from the space where the first robot arm is positioned, and can receive the wafer W and mask member M from the first robot arm, align the mask member M on top of the wafer W, and fix it in place.

[0051] The alignment unit 140 pulls out wafers W and mask members M from the first wafer storage unit 110 and the first mask storage unit 120, respectively, aligns the mask members M on the wafers W, and then hands over the aligned wafers W and mask members M to the first load lock unit 150. Various configurations can be applied to the alignment unit 140 for aligning and fixing the mask members M on the wafers W. For example, as shown in Figure 5, the wafers W may be placed on a tray T, the mask members M may be aligned on the wafers W, and then the tray T and mask members M may be fixed together by magnetic force to align and fix the mask members M on the wafers W. At this time, multiple trays T may be stored within the alignment unit 140, or trays T may be pulled into the alignment unit 140 via a first robot arm from a tray storage unit (not shown) located separately from the alignment unit 140.

[0052] The first load lock section 150 may have one side connected to the alignment section 140 and the other side connected to the deposition section 200. Such a first load lock section 150 may receive the tray T from the alignment section 140 under atmospheric pressure conditions, and after switching to a vacuum state, may receive the tray T from the deposition section 200. Although not shown in the figures, for example, the first load lock section 150 may include a first atmospheric pressure load lock with one side connected to the alignment section 140, and a first vacuum load lock with one side connected to the other side of the first atmospheric pressure load lock and the other side connected to the deposition section 200.

[0053] The first atmospheric pressure load lock is heated to atmospheric pressure inside, and the first wafer storage unit 110, the first mask storage unit 120, the alignment unit 140, and the first robot arm unit 140, which are directly or indirectly connected to the first atmospheric pressure load lock, may also be heated to atmospheric pressure inside. The first atmospheric pressure load lock may receive trays T on which mask members M are fixed onto wafers W from the first robot arm and pass them to the first vacuum load lock. At this time, the first atmospheric pressure load lock may receive a plurality of trays T on which mask members M are fixed onto wafers W simultaneously or sequentially and pass a plurality of trays T to the first vacuum load lock simultaneously. On the other hand, the first vacuum load lock is adjusted so that its internal state changes from atmospheric pressure to a vacuum state, and receives a plurality of trays T from the first atmospheric pressure load lock and passes them to the deposition unit 200.

[0054] The deposition unit 200 is connected to the loading unit 100 and has a space in which a wafer W and a mask member M placed on a tray T are received from the loading unit 100 and a conductive pattern layer MP1 or MP2 is formed on the wafer W. For this purpose, as shown in Figure 5, the deposition unit 200 may include a deposition chamber 201 that provides at least a portion of the space in which a conductive pattern layer MP1 or MP2 is formed on the wafer W, a support unit 202 disposed within the deposition chamber 201 to support the received wafer W and mask member M, a sputtering target unit 204 disposed within the deposition chamber 201 opposite the support unit 202, and a power supply unit 205 for supplying power to the sputtering target unit 204.

[0055] The deposition chamber 201 forms a process space in which the deposition process is carried out, and the deposition chamber 201 is connected to a predetermined vacuum pump (not shown) to maintain a vacuum state inside it.

[0056] The deposition chamber 201 may be connected to a gas supply pipe (not shown) for supplying an inert gas, such as argon (Ar) gas. The gas supply pipe may be connected to the deposition chamber 201 so as to supply the inert gas to the region where plasma discharge occurs, i.e., the region between the sputtering target section 204 and the wafer W.

[0057] The support unit 202 is located inside the deposition chamber 201 and transports the wafer W being loaded into the deposition chamber 201 while supporting it. As described above, when the wafer W and mask member M placed on the tray T are handed over from the loading unit 100, the support unit 202 may transport the tray T on which the wafer W and mask member M are placed while supporting it. For this purpose, the support unit 202 may be equipped with a moving member for moving the handed-over wafer W and mask member M or tray T, and such a moving member may be equipped with a roller plate or a conveyor belt. Furthermore, when multiple trays T on which wafers W are placed are handed over simultaneously from the loading unit 100, the support unit 202 may have a mounting surface on which multiple wafers W can be placed. This makes it possible to perform the deposition process on multiple wafers W simultaneously, and as a result, productivity can be improved.

[0058] Furthermore, the deposition unit 200 may further include a backing plate 203. The backing plate 203 supports the sputtering target unit 204 and ensures that power is supplied to the sputtering target unit 204. For this purpose, the backing plate 203 may be electrically connected to a power supply unit 205, for example, a DC power supply, an AC power supply, or an RF power supply, and the plasma power supplied from the power supply unit 205 may be supplied to the sputtering target unit 204.

[0059] The sputtering target portion 204 is disposed inside the deposition chamber 201 so as to face the support portion 202. In this case, the sputtering target portion 204 may be formed from a conductive material for forming a conductive pattern layer MP1 or MP2 on the wafer W, and may have a larger area than the wafer W. Such a sputtering target portion 204 may be disposed on the back surface of the backing plate 203, at a predetermined distance from the wafer W, and facing it.

[0060] It goes without saying that, although not shown in the diagram, the deposition unit 200 may further include magnetic field forming means disposed inside the deposition chamber 201.

[0061] Such a magnetic field forming means vibrates with a constant period (or width) during the sputtering process and moves in a predetermined direction while forming a magnetic field on the surface of the sputtering target portion 204. This allows the erosion region of the sputtering target portion 204 caused by the magnetic field to be uniformly distributed over the entire area of ​​the sputtering target portion 204, thereby maximizing the utilization efficiency of the sputtering target portion 204. Furthermore, the magnetic field forming means can improve the deposition speed of the conductive pattern layer MP1 or MP2 deposited on the wafer W by forming a high-density plasma on the surface of the sputtering target portion 204 using the magnetic field. For this purpose, the magnetic field forming means may include a magnet module and a magnet movement module.

[0062] Such a deposition unit 200 may include a first deposition unit 210 connected to a loading unit 100 for forming a lower conductive pattern layer on a passivation layer P1 or P2 formed on a wafer W, and a second deposition unit 220 connected to the first deposition unit 210 for forming an upper conductive pattern layer made of a different material from the lower conductive pattern layer on the lower conductive pattern layer. In this case, it goes without saying that the first deposition unit 210 and the second deposition unit 220 may each include the aforementioned deposition chamber 201, support unit 202, backing plate 203, sputtering target unit 204, and power supply unit 205, respectively.

[0063] The first deposition unit 210 may be connected to the loading unit 100 via a first transport unit 410 which plays a role in adjusting the movement speed of the tray T. Here, the first deposition unit 210 may form an underconductive pattern layer on top of a passivation layer P1 or P2 formed on the wafer W. In this case, the underconductive pattern layer is for the purpose of increasing the adhesion strength of the first conductive pattern layer MP1 or the second conductive pattern layer MP2 formed on the first passivation layer P1 or the second passivation layer P2, and may be made of a material such as titanium (Ti).

[0064] The second deposition unit 220 may be directly connected to the first deposition unit 210, or it may be connected to the first deposition unit 210 via a buffer unit 500. The first deposition unit 210 is for forming a lower conductive pattern layer on a passivation layer P1 or P2 formed on a wafer W, and the second deposition unit 220 is for forming an upper conductive pattern layer on the lower conductive pattern layer formed by the first deposition unit 210, as will be described later. In this case, the first deposition unit 210 and the second deposition unit 220 may have different conditions for forming the lower conductive pattern layer or the upper conductive pattern layer, but if the pressure conditions of the first deposition unit 210 and the second deposition unit 220 are different, for example, if the pressure difference is large, the pressure may be adjusted in the buffer unit 500 between the first deposition unit 210 and the second deposition unit 220.

[0065] The second vapor deposition section 220 is for forming an upper conductive pattern layer on top of the lower conductive pattern layer formed by the first vapor deposition section 210. The upper conductive pattern layer may be made of a metallic material such as copper, silver, aluminum, nickel, chromium, titanium, or tungsten, or an alloy material containing other components. In this case, the upper conductive pattern layer may be made of a different material from the lower conductive pattern layer, which enhances adhesion and allows for the formation of a conductive pattern layer MP1 or MP2 with excellent conductivity.

[0066] Furthermore, the upper conductive pattern layer needs to be formed with a thickness greater than the lower conductive pattern layer to enhance adhesion. For this reason, multiple second deposition units 220 for forming the upper conductive pattern layer may be provided connected to one another. In this case, the tray T will pass through multiple second deposition units 220 in sequence, making it possible to form an upper conductive pattern layer of sufficient thickness on the passivation layer P1 or P2. It goes without saying that the number of second deposition units 220 can be set in various ways depending on the thickness of the upper conductive pattern layer.

[0067] The unloading unit 300 has a space that allows it to receive the tray T from the deposition unit 200 and perform the process of separating the mask member M on the wafer W. For this purpose, the unloading unit 300 may include a second load lock unit 310 connected to the deposition unit 200, a second wafer storage unit 340 having a space for storing a plurality of wafers W and connected to the second load lock unit 310, a second mask storage unit 350 having a space for storing a plurality of mask members M and connected to the second load lock unit 310, and a separation unit 320 having a space for receiving the wafer W and mask member M from the second load lock unit 310 and separating the mask member M on the wafer W and connected to the second load lock unit 310.

[0068] The second load lock unit 310 may be connected to the deposition unit 200, for example, the second deposition unit 220, via a second transport unit 420 that plays a role in adjusting the movement speed of the tray T. The second load lock unit 310 may have one side connected to the second deposition unit 220 and the other side connected to the separation unit 320. Such a second load lock unit 310 may receive the tray T from the second deposition unit 220 in a vacuum state, and after switching to an atmospheric pressure state, it may receive the tray T to the separation unit 320. Although not shown, for example, the second load lock unit 310 may include a second vacuum load lock connected to the second deposition unit 220, and a second atmospheric pressure load lock, one side of which is connected to the second vacuum load lock and the other side of which is connected to a second robot arm described later.

[0069] The second vacuum load lock is adjusted so that its interior changes from a vacuum state to an atmospheric pressure state, and it receives a plurality of trays T on which wafers W with conductive pattern layers MP1 or MP2 formed on them are placed from the deposition unit 200 and passes them to the second atmospheric pressure load lock. The second atmospheric pressure load lock is heated to atmospheric pressure inside, and the interiors of the separation unit 320 connected to the second atmospheric pressure load lock, the second wafer storage unit 340 and the second mask storage unit 350 may also be heated to atmospheric pressure.

[0070] The separation unit 320 has a space for receiving the wafer W and mask member M placed on the tray T from the second atmospheric pressure load lock and separating the mask member M on the wafer W. Such a separation unit 320 may include a separation chamber, and may include a second robot arm positioned within the separation chamber. Here, the second robot arm may receive the wafer W and mask member M placed on the tray T from the second atmospheric pressure load lock and move the wafer W and mask member M to the second wafer storage unit 340 and the second mask storage unit 350, respectively. In the following description, we will use as an example a configuration in which the separation unit 320 is equipped with a second robot arm to separate the wafer W and mask member M, which have been received from the second atmospheric pressure load lock and placed and fixed on the tray T, and move them to the second wafer storage unit 340 and the second mask storage unit 350, respectively. However, it goes without saying that the separation unit 320 can also be provided separately from the space in which the second robot arm is located, and can receive the wafer W and mask member M, which have been placed and fixed on the tray T, from the second robot arm and separate the wafer W and mask member M.

[0071] Within such a separation chamber, the mask member M can be separated from the wafer W. For example, the separation unit 320 can release the fixing of the tray T and the mask member M and separate them, and the separated tray T can be stored in the separation unit 320 or moved from the separation unit 320 to the aforementioned tray storage unit.

[0072] The second wafer storage unit 340 may include a second wafer storage chamber and a second wafer storage cassette disposed inside the second wafer storage chamber. The second wafer storage cassette may store wafers W on which the conductive pattern layer has been deposited and which have been handed over from the second robot arm, or it may store multiple wafers W on which the deposition has been completed in this manner.

[0073] The second mask storage unit 350 may include a second mask storage chamber and a second mask storage cassette disposed inside the second mask storage chamber. The second mask storage cassette may store used first mask members M1 or second mask members M2 that have been used up during the deposition process. Multiple such mask members M may be stored in a vertical direction.

[0074] On the other hand, the semiconductor packaging apparatus according to the embodiment of the present invention may further include a transport unit 600 that connects the unloading unit 300 and the loading unit 100 in order to transport used mask members M from the unloading unit 300 to the loading unit 100. In this case, the transport unit 600 may also connect the second mask storage unit 350 of the unloading unit 300 and the first mask storage unit 120 of the loading unit 100 to each other. Furthermore, the transport unit 600 may include a transport means (not shown) for transporting the mask members M and a washing unit (not shown) for washing the mask members M transported out of the unloading unit 300. In this case, it goes without saying that the transport means of the transport unit 600 may include a roller plate or conveyor belt capable of transporting the mask members M into the loading unit 100. On the other hand, the washing unit plays the role of wet washing or dry washing the used mask members M. In this way, by washing the used mask material M and transporting it to the loading section 100, it is possible to prevent the conductive pattern layer from becoming contaminated with impurities in the subsequent deposition process and to improve the uniformity of the deposition.

[0075] Thus, according to the semiconductor packaging apparatus according to the embodiment of the present invention, a conductive pattern layer can be formed on a wafer equipped with multiple semiconductor elements by a single process using a mask member provided separately from the wafer, thereby minimizing the number of processes required to form the conductive pattern layer.

[0076] This minimizes the time required to package semiconductor elements, reduces the cost of materials used in the process, and improves the productivity of semiconductor chips.

[0077] Although preferred embodiments of the present invention have been described and illustrated using specific terminology, these terms are merely for the purpose of clearly explaining the present invention, and it is clear that various modifications and changes can be made to the embodiments and described terminology of the present invention without departing from the technical idea and scope of the claims. These modified embodiments should not be understood individually from the idea and scope of the present invention, but should be considered to fall within the scope of the claims of the present invention.

Claims

1. A loading section having a space capable of performing the process of placing a mask member on a wafer containing multiple semiconductor elements, A space is provided from the loading section to which a wafer and mask member can be received and a process of forming a conductive pattern layer on the wafer can be carried out, and a deposition section is connected to the loading section, An unloading section connected to the deposition section has a space in which a wafer and a mask member can be received from the deposition section and a process of separating the mask member on the wafer can be performed, Equipped with, The aforementioned vapor-deposited portion is A first deposition unit connected to the loading unit for forming an underconductive pattern layer on a passivation layer formed on a wafer, A second vapor deposition unit is connected to the first vapor deposition unit for forming an upper conductive pattern layer made of a different material from the lower conductive pattern layer on the lower conductive pattern layer, Equipped with, The aforementioned vapor-deposited portion is A deposition chamber that provides at least a portion of a space in which a process of forming a conductive pattern layer on a wafer can be carried out, A support unit is provided within the deposition chamber so as to be able to support the handed-over wafer and mask component, A sputtering target section is disposed within the deposition chamber so as to face the support section, A power supply unit for supplying power to the sputtering target section, A semiconductor packaging apparatus equipped with [the following features].

2. The semiconductor packaging apparatus according to claim 1, wherein the loading section is connected to one side of the deposition section, and the unloading section is connected to the other side of the deposition section, which is opposite to the one side of the deposition section.

3. The aforementioned loading unit is A first load lock portion connected to the aforementioned vapor deposition portion, A first wafer storage unit having space for storing multiple wafers and connected to the first load lock unit, A first mask storage section having a space for storing multiple mask members and connected to the first load lock section, The first wafer storage unit and the first mask storage unit, respectively, have spaces for receiving wafers and mask members, and for aligning and fixing the mask members on the wafers, and the alignment unit is connected to the first load lock unit, A semiconductor packaging apparatus according to claim 1, comprising:

4. The semiconductor packaging apparatus according to claim 1, wherein the support portion includes a moving member for moving the received wafer and mask member.

5. The semiconductor packaging apparatus according to claim 4, wherein the moving member comprises a roller plate or a conveyor belt.

6. The semiconductor packaging apparatus according to claim 1, wherein the support portion has a mounting surface on which a plurality of wafers can be placed.

7. The semiconductor packaging apparatus according to claim 1, wherein the second deposition section is provided by connecting a plurality of units to one another.

8. A loading unit having a space capable of performing the step of placing a mask member on a wafer equipped with multiple semiconductor elements, A space is provided from the loading section to which a wafer and mask member can be received and a process of forming a conductive pattern layer on the wafer can be carried out, and a deposition section is connected to the loading section, An unloading section connected to the deposition section has a space in which a wafer and a mask member can be received from the deposition section and a process of separating the mask member on the wafer can be performed, Equipped with, The aforementioned vapor-deposited portion is A first deposition unit connected to the loading unit for forming an underconductive pattern layer on a passivation layer formed on a wafer, A second vapor deposition unit is connected to the first vapor deposition unit for forming an upper conductive pattern layer made of a different material from the lower conductive pattern layer on the lower conductive pattern layer, Equipped with, The aforementioned unloading unit, A second load lock portion connected to the aforementioned vapor deposition portion, A second wafer storage section having a space for storing multiple wafers and connected to the second load lock section, A second mask storage section having a space for storing multiple mask members and connected to the second load lock section, A separation unit is connected to the second load lock unit and has a space for receiving the wafer and mask member from the second load lock unit and separating the mask member on the wafer, A semiconductor packaging apparatus equipped with [the following features].

9. A loading unit having a space capable of performing the step of placing a mask member on a wafer equipped with multiple semiconductor elements, A space is provided from the loading section to which a wafer and mask member can be received and a process of forming a conductive pattern layer on the wafer can be carried out, and a deposition section is connected to the loading section, An unloading section connected to the deposition section has a space in which a wafer and a mask member can be received from the deposition section and a process of separating the mask member on the wafer can be performed, Equipped with, The aforementioned vapor-deposited portion is A first deposition unit connected to the loading unit for forming an underconductive pattern layer on a passivation layer formed on a wafer, A second vapor deposition unit is connected to the first vapor deposition unit for forming an upper conductive pattern layer made of a different material from the lower conductive pattern layer on the lower conductive pattern layer, Equipped with, A semiconductor packaging apparatus further comprising a transport unit connecting the unloading unit and the loading unit for the purpose of unloading a mask member from the unloading unit and transporting it into the loading unit.

10. The loading unit includes a first mask storage unit having a space for storing multiple mask members, The unloading unit includes a second mask storage unit having a space for storing multiple mask members, The semiconductor packaging apparatus according to claim 9, wherein the transport unit connects the first mask storage unit and the second mask storage unit.

11. The semiconductor packaging apparatus according to claim 9, wherein the transport unit includes a washing unit for washing the mask members discharged from the unloading unit.

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