Electronic devices and chip packaging methods
The chip packaging method forms a Faraday cage using a substrate, adapter board, and shielding metals to isolate components, addressing electromagnetic interference and maintaining performance in miniaturized electronic devices.
JP7842192B2Active Publication Date: 2026-04-07HONOR DEVICE CO LTD
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2026-04-07
Smart Images
Figure 0007842192000001 
Figure 0007842192000002 
Figure 0007842192000003
Abstract
To provide, in a field of chip packaging, an electronic device and a chip packaging method.SOLUTION: The electronic device includes a housing. A substrate is arranged in the housing. A first crystal device and an adapter board are arranged in parallel on a side surface of the substrate. A first ground pad is arranged on a surface of the adapter board facing the substrate, and the adapter board is electrically connected to the substrate by the first ground pad, so that the adapter board is grounded. A first part of a first plastic packaging layer is arranged on a surface of the first crystal device, and a second part of the first plastic packaging layer is arranged between the adapter board and the substrate. The first part and the second part are integrally formed. A first shielding metal covers a surface of the first part and is electrically connected to the first ground pad, so that the first shielding metal is grounded.SELECTED DRAWING: Figure 3
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Citation Information
Patent Citations
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