Photoelectric conversion devices and equipment

Abstract

To solve the problem occurring at a time when a signal processing circuit returns.SOLUTION: A photoelectric conversion device includes an input switch connected in series between an input node and a holding unit and an output switch connected in series between an amplifier and an output node. In a first operation mode, the output switch is in an ON state, the input switch holds a signal in the holding unit by being turned on or off at a predetermined timing, in a second operation mode, the input and output switches are in an OFF state, and the amplifier outputs a constant voltage.SELECTED DRAWING: Figure 3

Description

Technical Field

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[0001] The present invention relates to a photoelectric conversion device and equipment.

Background Art

[0002] A photoelectric conversion device includes a plurality of signal processing circuits, and techniques for controlling each signal processing circuit have been devised. The technique described in Patent Document 1 reduces the current of unused signal processing circuits in a plurality of signal processing circuits to reduce power consumption.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, when the power supply current of an unused signal processing circuit is lowered, the recovery time of the signal processing circuit becomes longer. Furthermore, image quality degradation may occur due to current fluctuations during recovery.

[0005] The present invention has been made in view of the above problems, and aims to solve the problems during the recovery of the signal processing circuit. <OO00029>

Means for Solving the Problems

[0006] According to one embodiment of the present disclosure, a pixel that outputs a signal according to the amount of received light, an input node that receives the signal, a holding unit that holds the signal input to the input node, an amplifier that receives the signal held by the holding unit, an output node that outputs the signal from the amplifier, an input switch connected in series between the input node and the holding unit, and an output switch connected in series between the amplifier and the output node, It includes a short-circuit switch that short-circuits the input node and the output node, and is in a high-gain readout mode.In the first operating mode, the output switch is in the ON state, and the input switch is turned ON or OFF at predetermined timings to hold the signal in the holding unit. This is a low-gain readout mode. In the second operating mode, the input switch and the output switch are in the off state. , and the short-circuit switch is in the ON state. The present invention provides a photoelectric conversion device characterized in that the amplifier outputs a constant voltage.

[0007] According to another embodiment of the present disclosure, a pixel that outputs a signal corresponding to the amount of light received, an input node that receives the signal, a holding unit that holds the signal input to the input node, an amplifier that receives the signal held by the holding unit, an output node that outputs the signal from the amplifier, an input switch connected in series between the input node and the holding unit, and an output switch connected in series between the amplifier and the output node, It includes a short-circuit switch that short-circuits the input node and the output node, and is in a high-gain readout mode. In the first operating mode, the output switch is in the ON state, and the input switch is turned ON or OFF at predetermined timings to hold the signal in the holding unit. This is a low-gain readout mode. In the second operating mode, the output switch is in the off state. , and the short-circuit switch is in the ON state. The present invention provides a photoelectric conversion device characterized in that the input switch is turned ON, thereby inputting the signal from the input node to the amplifier. [Effects of the Invention]

[0008] According to the present invention, it is possible to solve the problem of the signal processing circuit during recovery. [Brief explanation of the drawing]

[0009] [Figure 1] This is a block diagram of the photoelectric converter in the first embodiment. [Figure 2] This is a circuit diagram of a pixel in the first embodiment. [Figure 3] This is a circuit diagram of the signal processing circuit in the first embodiment. [Figure 4]This is a timing chart showing the driving method of the photoelectric converter in the first embodiment. [Figure 5] This is a timing chart showing the driving method of the photoelectric converter in the first embodiment. [Figure 6] This is a circuit diagram of the signal processing circuit in the second embodiment. [Figure 7] This is a timing chart showing the driving method of the photoelectric converter in the second embodiment. [Figure 8] This is a timing chart showing the driving method of the photoelectric converter in the second embodiment. [Figure 9] This is a timing chart showing the driving method of the photoelectric converter in the third embodiment. [Figure 10] This is a block diagram of the equipment in the fourth embodiment. [Figure 11] This is a block diagram of the equipment related to the in-vehicle camera in the fifth embodiment. [Modes for carrying out the invention]

[0010] [First Embodiment] Figure 1 is a block diagram of the photoelectric converter in this embodiment. The photoelectric converter is configured on a semiconductor substrate, for example, a CMOS image sensor. On the semiconductor substrate, a pixel array 10, a vertical scanning circuit 11, a readout circuit 12, a signal processing circuit 13, an AD (Analog to Digital) conversion circuit 14, a column memory 15, a horizontal scanning circuit 16, a DFE (Digital Front End) circuit 17, an output circuit 171, a timing generator 18, circuit sections 125, 135, 145, a reference signal generation circuit (ramp) 142, a PLL (Phase Locked Loop) circuit 151, and a counter 152 are formed.

[0011] The pixel array 10 is arranged in a matrix and includes a plurality of pixels 100 that output pixel signals according to the amount of received light. Each pixel 100 includes a photoelectric conversion unit that generates and accumulates signal charges based on incident light. In this specification, the row direction refers to the horizontal direction (direction D2) in FIG. 1, and the column direction refers to the vertical direction (direction D1) that intersects the row direction D2 in FIG. 1. A microlens and a color filter can be arranged on the pixel 100. The color filter is, for example, a primary color filter of red, blue, and green, and is provided for each pixel 100 according to the Bayer arrangement.

[0012] The pixel array 10 includes an aperture pixel region and a light-shielding pixel region where a light-shielding film is formed. The light-shielding film is not formed on the pixels 100 included in the aperture pixel region, and it is possible to output pixel signals according to incident light. The light-shielding pixel region is a horizontal optical black (HOB) pixel region arranged adjacent to the aperture pixel region in the row direction D2. A dark signal corresponding to a noise component can be obtained from the pixels 100 in the light-shielding pixel region.

[0013] In addition, the pixel array 10 may be provided with a distance measurement row in which focus detection pixels that output pixel signals for focus detection are arranged, and a plurality of imaging rows in which imaging pixels that output pixel signals for generating an image are arranged. The signal line L is connected to the columns of the plurality of pixels 100, and the plurality of pixels 100 in the same column sequentially output pixel signals to the common signal line L.

[0014] The vertical scanning circuit 11 is composed of a shift register, a gate circuit, a buffer circuit, etc., outputs a control signal to the pixel 100 based on a vertical synchronization signal, a horizontal synchronization signal, a clock signal, etc., and drives the pixel 100 for each row.

[0015] The readout circuit 12 includes a current source for reading out the pixel signal of the pixel 100, a clamp circuit for clamping the pixel signal to a predetermined potential, a column amplifier circuit for signal amplification, and the like. The column amplifier circuit includes a plurality of switchable feedback circuits, and the readout circuit 12 can change the amplification factor (gain) of the pixel signal according to the readout mode. For example, the readout circuit 12 can switch between a high-gain mode and a low-gain mode. The readout circuit 12 reads out the pixel signal from the pixel 100 via the signal line L. The circuit section 125 includes a pulse generation circuit for controlling the readout circuit 12 and a reference bias circuit for generating the bias voltage and the clamp voltage of the readout circuit 12.

[0016] The signal processing circuit 13 includes a holding section for sample-holding the analog signal output from the readout circuit 12 and an amplifier for buffering (buffering and amplifying) the held signal. This amplifier is an amplifier circuit that performs non-inverting amplification. The circuit section 135 includes a pulse generation circuit for controlling the signal processing circuit 13 and a reference bias circuit for the signal processing circuit 13. As will be described later, the signal processing circuit 13 can switch the signal path within the signal processing circuit 13 according to the high-gain mode and the low-gain mode.

[0017] The AD conversion circuit 14 includes a comparison circuit, a latch circuit, etc., and converts the analog signal from the signal processing circuit 13 into a digital signal. The circuit section 145 includes a pulse generation circuit for controlling the AD conversion circuit 14 and a reference bias circuit for generating the bias voltage of the AD conversion circuit 14. The reference signal generation circuit (RAMP) 142 generates a reference signal to be compared with the pixel signal by the AD conversion circuit 14. The reference signal is a signal that changes depending on time and is also referred to as a RAMP signal. The reference signal generation circuit 142 can be configured using various methods such as a capacitance charge / discharge method, a DAC method, a current steering method, etc. The reference signal may be not only an upslope where the voltage increases with time but also a downslope where the voltage decreases with time. Further, the reference signal may include a plurality of slope waveforms with different voltage change rates per unit time. The comparison circuit of the AD conversion circuit 14 compares the reference signal and the pixel signal and outputs a comparison signal representing the comparison result.

[0018] The column memory 15 holds the value of the counter 152 in accordance with the inversion of the comparison signal of the AD conversion circuit 14. The counter 152 counts up or down in synchronization with the reference signal. The counter 152 starts counting clock pulses simultaneously with the start of the voltage change of the reference signal of the reference signal generation circuit 142 and outputs the count value. The PLL circuit 151 includes a clock circuit that generates a reference clock for the counter 152 and outputs a reference clock synchronized with the reference signal.

[0019] The horizontal scanning circuit 16 includes a decoder and a shift register, and sequentially reads the count values ​​held in the column memory 15 as digital signals and outputs them to the DFE 17.

[0020] The DFE17 is equipped with a digital signal processor and performs digital signal processing such as digital gain, digital correlation double sampling, digital offset, and linearity correction. The output circuit 171 is equipped with an LVDS (Low Voltage Differential Signaling) serial output circuit and outputs the processed digital signal to the outside of the photoelectric converter at high speed and with low power consumption.

[0021] The timing generator 18 includes a clock circuit, logic circuits, etc., and generates control signals to control each part of the photoelectric converter.

[0022] Figure 2 is an equivalent circuit diagram of a pixel 100 in this embodiment. The pixel 100 includes a photoelectric conversion unit 101, a transfer transistor 102, a floating diffusion region (Floating Diffusion) 103, an amplification transistor 104, a selection transistor 105, and a reset transistor 106. The following description shows an example where the transistors constituting the pixel 100 are N-channel MOS transistors. The photoelectric conversion unit 101 is composed of, for example, a photodiode and performs photoelectric conversion and charge accumulation using incident light. Note that the photoelectric conversion unit 101 is not limited to a photodiode, but can be any material that produces a photoelectric effect. The number of photoelectric conversion units 101 per pixel 100 is also not limited, and two, four or more photoelectric conversion units 101 may be provided so as to share a single microlens. Furthermore, by configuring an embedded photodiode, dark current noise can be reduced. A microlens is provided in the photoelectric conversion unit 101, and light focused by the microlens is incident on the photoelectric conversion unit 101.

[0023] The transfer transistor 102 is provided in correspondence with the photoelectric conversion unit 101, and a control signal pTX is applied to its gate from the vertical scanning circuit 11. When the control signal pTX becomes high level, the transfer transistor 102 turns ON (conducts), and the signal charge accumulated in the photoelectric conversion unit 101 is transferred to the floating diffusion region 103 formed on the gate of the amplification transistor 104. When the control signal pTX becomes low level, the transfer transistor 102 turns OFF (non-conducts). The floating diffusion region 103 converts the signal charge into a voltage, and the amplification transistor 104 outputs a signal voltage corresponding to the gate voltage from its source to the signal line L via the selection transistor 105. The drain of the amplification transistor 104 is connected to the power supply VDD.

[0024] The source of the reset transistor 106 is connected to the floating diffusion region 103, its drain is connected to the power supply VDD, and the control signal pRES is applied to its gate from the vertical scanning circuit 11. When the control signal pRES reaches a high level, the reset transistor 106 turns on, and the voltage of the power supply VDD is supplied to the floating diffusion region 103. The selection transistor 105 is located between the amplification transistor 104 and the signal line L, and the control signal pSEL is applied to the gate of the selection transistor 105 from the vertical scanning circuit 11. When the control signal pSEL reaches a high level, the amplification transistor 104 and the signal line L become electrically conductive. A current source 111 is connected to the signal line L, and the current source 111 supplies a constant bias current to the source of the amplification transistor 104 via the signal line L. The amplification transistor 104 functions as a source follower transistor.

[0025] Note that the pixel 100 is not limited to the configuration shown in Figure 2, and each pixel 100 may be provided with multiple selection transistors. Furthermore, an additional capacitance may be provided in the floating diffusion region, and the capacitance of the floating diffusion region may be selectable.

[0026] Figure 3 is an equivalent circuit diagram of the signal processing circuit 13 in this embodiment, showing one row of circuits. In reality, the signal processing circuit 13 may include the same number of circuits as the number of signal lines L. The signal processing circuit 13 includes an amplifier 130, switches SW1 to SW7, holding units 131 and 132, an input node IN, and an output node OUT, and can function as a signal holding unit that holds the signal from the readout circuit 12.

[0027] The amplifier 130 is composed of multiple transistors and includes an inverting input terminal, a non-inverting input terminal, and an output terminal. Switches SW1 to SW7 are composed of transistors and are controlled to be on (conducting) or off (non-conducting) by the voltage applied to the control node (gate node). The retaining part 131 (first retaining part) and retaining part 132 (second retaining part) are composed of electrodes such as metal or polysilicon or transistors and constitute a capacitive element (capacitor).

[0028] Switch SW1 (input switch, first switch) is connected in series between the input node IN and the holding unit 131. That is, the first node of switch SW1 is connected to the input node IN (output node of the read circuit 12), and the second node is connected to the first electrode of the holding unit 131. A control signal pSH1 is input to the control node of switch SW1. When the control signal pSH1 becomes high level and switch SW1 is turned on, the signal from the read circuit 12 is input to the holding unit 131. When the control signal pSH1 becomes low level and switch SW1 is turned off, the holding unit 131 holds the signal.

[0029] Similarly, switch SW2 (input switch, second switch) is connected in series between input node IN and holding unit 132. That is, the first node of switch SW2 is connected to input node IN (output node of read circuit 12), and the second node is connected to the first electrode of holding unit 132. A control signal pSH2 is input to the control node of switch SW2. When the control signal pSH2 becomes high level and switch SW2 is turned on, the signal from read circuit 12 is input to holding unit 132. When the control signal pSH2 becomes low level and switch SW2 is turned off, the holding unit 132 holds the signal.

[0030] Switch SW3 (the third switch) is connected between the holding units 131 and 132. That is, the first node of switch SW3 is connected to the second node of switch SW1 and the first electrode of the holding unit 131, and the second node of switch SW3 is connected to the second node of switch SW2 and the first electrode of the holding unit 132. The control node of switch SW3 receives the control signal pAVE. When the control signal pAVE becomes high and switch SW3 is turned on, the holding units 131 and 132 are short-circuited, and the signals of the holding units 131 and 132 are averaged. When the control signal pAVE becomes low, switch SW3 is turned off, and the holding units 131 and 132 can hold different signals from each other.

[0031] The first node of switch SW4 (the fourth switch) is connected to the output terminal (node ​​A) of amplifier 130, and the second node is connected to the inverting input terminal of amplifier 130. The control node of switch SW4 receives the control signal pAMP_FB. When the control signal pAMP_FB becomes high level and switch SW4 is turned on, the output terminal and the inverting input terminal of amplifier 130 are connected. At this time, the gain of amplifier 130 becomes 1, and amplifier 130 operates as a voltage follower. The non-inverting input terminal of amplifier 130 is connected to a constant voltage line, and amplifier 130 outputs a constant voltage V1. When the control signal pAMP_FB becomes low level and switch SW4 is turned off, the output terminal and the inverting input terminal of amplifier 130 are disconnected.

[0032] The first node of switch SW5 (the fifth switch) is connected to the output terminal of amplifier 130, and the second node of switch SW5 is connected to the connection node between the holding unit 131 and switch SW1. A control signal pAMP_O is applied to the control node of switch SW5. When the control signal pAMP_O becomes high level and switch SW5 is turned on, the first electrode of the holding unit 131 and the output terminal of amplifier 130 are short-circuited. When the control signal pAMP_O becomes low level and switch SW5 is turned off, the first electrode of the holding unit 131 and the output terminal of amplifier 130 are disconnected.

[0033] Switch SW6 (output switch) is connected in series between amplifier 130 and output node OUT. That is, the first node of switch SW6 is connected to the output terminal (node ​​A) of amplifier 130, and the second node is connected to output node OUT (input node of AD conversion circuit 14). The control node of switch SW6 receives the control signal pAMP_SEL. When the control signal pAMP_SEL becomes high level and switch SW6 is turned on, node A and output node OUT are connected. When the control signal pAMP_SEL becomes low level and switch SW6 is turned off, node A and the input node of AD conversion circuit 14 are disconnected.

[0034] Switch SW7 (short-circuit switch) is connected in series between the input node IN and the output node OUT. That is, the first node of switch SW7 is connected to the input node IN, and the second node of switch SW7 is connected to the output node OUT. The control node of switch SW7 receives the control signal pAMP_TH. When the control signal pAMP_TH goes high and switch SW7 is turned on, the input node IN and the output node OUT are short-circuited, forming a signal path from the input node IN to the output node OUT. When the control signal pAMP_TH goes low and switch SW7 is turned off, the input node IN and the output node OUT are disconnected.

[0035] With the above configuration, it is possible to switch the signal path in the signal processing circuit 13 according to the readout mode. In high-gain mode (first operating mode), noise reduction is performed using the holding units 131, 132 and amplifier 130, and in low-gain mode (second operating mode), the holding units 131, 132 and amplifier 130 are disconnected from the signal path.

[0036] Figure 4 is a timing chart showing the driving method of the photoelectric converter in this embodiment, and represents the driving method in which the holding units 131, 132 and the amplifier 130 are used in high-gain mode.

[0037] The timing chart in Figure 4 shows the time evolution of the control signals pRES, pSEL, pTX, pSH1, pSH2, pAVE, pAMP_FB, pAMP_O, pAMP_TH, pAMP_SEL, the voltage VL of the signal line L, the voltage at input node IN (output node of readout circuit 12), and the voltage at node A (output terminal of amplifier 130).

[0038] At time t101, the control signal pRES is at a high level, the reset transistor 106 of pixel 100 turns on, and the floating diffusion region 103 is reset. Also, the control signal pSEL transitions from a low level to a high level, the selection transistor 105 of pixel 100 turns on, and the amplification transistor 104 and the signal line L conduct. As a result, the signal at the time of reset is output from pixel 100 to the signal line L. At this time, when the reset level of the floating diffusion region 103 is Vres, the threshold voltage of the amplification transistor 104 is Vth, and the overdrive voltage for flowing the desired current I is Vov, the voltage VL in the signal line L is expressed by equation (1). VL = Vres - Vth - Vov ... (1)

[0039] In the readout circuit 12, the voltage VL of the signal line L is clamped to a predetermined voltage, for example, voltage V1. Therefore, the voltage VL in equation (1) is output from the readout circuit 12 as voltage V1.

[0040] In the signal processing circuit 13, the control signals pSH1 and pSH2 are at a low level, and switches SW1 and SW2 are in the off state, so the input node IN and the holding units 131 and 132 are not conducting. Also, since the control signals pAVE, pAMP_FB, and pAMP_TH are at a low level, switches SW3 and SW7 are in the off state. Since the control signals pAMP_O and pAMP_SEL are at a high level, switches SW5 and SW6 are in the on state. The holding unit 131 is connected between the output terminal and the inverting input terminal of amplifier 130. At this time, if no charge is held in the holding unit 131, a voltage V1 may be output from node A.

[0041] At time t102, the control signal pRES transitions from a high level to a low level, the reset transistor 106 turns off, and the floating diffusion region 103 enters a floating state. At this time, the potential of the floating diffusion region 103 may fluctuate due to the gate of the reset transistor 106 and the parasitic capacitance of the diffusion layer. However, in the following explanation, the potential of each node is assumed not to fluctuate due to the on or off transition of the reset transistor 106.

[0042] Between times t102 and t103, the readout circuit 12 clamps the pixel signal at the time of reset to a predetermined voltage, for example, voltage V1. Here, the clamp voltage is the same voltage V1 as the voltage input to the non-inverting input terminal of amplifier 130, but it may be a different voltage.

[0043] At time t103, the control signal pAMP_O transitions from a high level to a low level, and switch SW5 turns off. Also, the control signal pAMP_FB transitions from a low level to a high level, and switch SW4 turns on, causing conduction between the output terminal and the inverting input terminal of amplifier 130. Amplifier 130 operates as a voltage follower and outputs voltage V1 from its output terminal. Here, if amplifier 130 has an offset voltage Voffset, the voltage Va at the output terminal (node ​​A) is expressed by equation (2). Note that since the inverting input terminal of amplifier 130 is connected to node A, the voltage at the inverting input terminal is also voltage V1-Voffset. Va = V1 - Voffset ... (2)

[0044] At time t104, the control signals pSH1 and pSH2 transition from low level to high level, and switches SW1 and SW2 are turned on. The input node IN and the holding units 131 and 132 become conductive, and the reset signal is output from the read circuit 12 to the holding units 131 and 132.

[0045] At time t105, the control signal pSH1 transitions from a high level to a low level, the switch SW1 turns off, and the holding unit 131 holds the voltage of the input node. At this time, if the gain of the readout circuit 12 is Gain and the voltage of the signal (noise signal) at time t105 is Na, the voltage of the input node IN is expressed by equation (3). As mentioned above, the gain of the readout circuit 12 can be changed depending on the readout mode. V1 + Gain × Na ···(3)

[0046] The voltage between the first and second electrodes of the holding unit 131 is the difference between the voltage at input node IN at time t105 and the voltage at the inverting input terminal of amplifier 130. Therefore, the voltage between the first and second electrodes of the holding unit 131 is expressed by equation (4). Equation (3) - Equation (2) =V1+Gain×Na-(V1-Voffset) =Gain × Na + Voffset ···(4)

[0047] At time t106, the control signal pSH2 transitions from a high level to a low level, the switch SW2 turns off, and the holding unit 132 holds the voltage at input node IN. If the voltage of the signal (noise signal) at time t106 is Nb, the voltage at input node IN is expressed by equation (5). V1+ Gain × Nb ···(5)

[0048] The voltage between the first and second electrodes of the holding section 131 is the difference between the voltage at input node IN at time t106 (equation (5)) and the voltage at the inverting input terminal of amplifier 130 (equation (2)). The voltage between the first and second electrodes of the holding section 132 is expressed by equation (6). Equation (5) - Equation (2) =V1+Gain×Nb-(V1-Voffset) =Gain × Nb + Voffset ···(6)

[0049] Here, if the capacitance values ​​of the holding parts 131 and 132 are C1[F] and C2[F] respectively, the charges Q1 and Q2 held in the holding parts 131 and 132 are expressed by equations (7) and (8). Q1=C1×Equation (4) =C1×(Gain×Na+Voffset) ···(7) Q2=C2×Equation (6) =C2×(Gain×Nb+Voffset) ···(8)

[0050] At time t107, the control signal pAVE transitions from a low level to a high level, switch SW3 turns on, and the aforementioned charges Q1 and Q2 are added together. The added charge (Q1+Q2) is expressed by equation (9). Q1+Q2 =Formula (7)+Formula (8) =C1 × (Gain × Na + V offset) +C2×(Gain×Nb+Voffset) ···(9)

[0051] When the capacitance values ​​of the holding parts 131 and 132 are both C1[F], equation (9) is expressed as equation (10). Note that the offset voltage Voffset is omitted for the sake of simplicity. Q1+Q2 =C1×(Gain×(Na+Nb)) ···(10)

[0052] The charge (Q1+Q2) in equation (10) is expressed as the voltage in equation (11). (C1 × (Gain × (Na + Nb))) / (2 × C1) =(Gain×Na+Gain×Nb) / 2...Equation (11)

[0053] Since the noise signals Na and Nb have random components, the sum of the squares of the noise signals Na and Nb can be expressed as the sum of squares. Here, if Na = Nb, the sum of squares (mean square) of the noise signals Na and Nb, Nave, can be expressed by equation (12). Nave=(Gain×Na) / √2 ··· (12)

[0054] Equation (12) can reduce high-frequency noise with a period shorter than the time from the falling edge of control signal pSH1 (time t105) to the falling edge of control signal pSH2 (time t106) to (1 / √2). On the other hand, equation (12) cannot average out low-frequency noise with a period longer than the time from time t105 to t106. Therefore, low-frequency noise can be greater than the root mean square (1 / √2).

[0055] At time t108, the control signal pAMP_FB transitions from a high level to a low level, and switch SW4 turns off. Also, the control signal pAMP_O transitions from a low level to a high level, and switch SW5 turns on. As a result, amplifier 130 outputs a voltage Va corresponding to the voltages of the holding units 131 and 132. Here, the voltage Va is expressed by equation (13), which is the sum of the root mean square Nave of equation (12) and the voltage V1. Va = V1 + Nave ··· (13)

[0056] Between times t108 and t109, the AD conversion circuit 14 performs AD conversion on the signal at the output node OUT, i.e., the voltage Va in equation (13). The reference signal generation circuit 142 changes the reference signal over time, and the comparator in the AD conversion circuit 14 compares the reference signal with the voltage Va and outputs a comparison signal. The column memory 15 stores the value of the counter 152 as a digital value of the voltage Va in accordance with the inversion of the comparison signal from the AD conversion circuit 14.

[0057] At time t109, the control signal pAVE transitions from a high level to a low level, and switch SW3 turns off.

[0058] At time t110, the control signal pTX transitions from a low level to a high level, the transfer transistor 102 in pixel 100 turns on, and the charge accumulated in the photoelectric conversion unit 101 is transferred to the floating diffusion region 103. The potential of the floating diffusion region 103 decreases in accordance with the transferred charge, and the voltage VL of the signal line L also decreases. Let Vsig be the amount of change (amplitude) of the voltage VL of the signal line L at this time.

[0059] At time t111, the control signal pTX changes from a high level to a low level, the transfer transistor 102 turns off, and the charge transfer to the floating diffusion region 103 ends. At this time, the voltage VL across the signal line L is expressed by equation (14). VL=Vres-Vth-Vov-Vsig (14)

[0060] The voltage at the output node of the readout circuit 12, that is, the voltage at the input node IN of the signal processing circuit 13, is expressed by equation (15). V1 + Gain × Vsig ... (15)

[0061] At time t112, the control signal pAMP_FB transitions from a low level to a high level, and switch SW4 turns ON. Also, the control signal pAMP_O transitions from a high level to a low level, and switch SW5 turns OFF. As a result, similar to the operation at time t103, the inverting input terminal and output terminal of amplifier 130 are connected, and the voltage Va at node A becomes (V1-Voffset) in equation (2).

[0062] At time t113, the control signals pSH1 and pSH2 transition from low level to high level, switches SW1 and SW2 turn on, and the input node IN is connected to the first electrodes of the holding units 131 and 132, respectively. That is, the voltage (V1 + Gain × Vsig) of equation (15) is output to the first electrodes of the holding units 131 and 132, respectively.

[0063] At time t114, the control signal pSH1 transitions from a high level to a low level, and switch SW1 turns off. At this time, the voltage at the first electrode of the holding unit 131 includes the voltage (V1 + Gain × Vsig) given by equation (15) and the voltage of the noise signal at time t114. If the noise signal at time t114 is Nc, the voltage at the first electrode of the holding unit 131 is given by equation (16). V1+Gain×Nc+Gain×Vsig (16)

[0064] The voltage held by the holding unit 131 is the difference between the voltages of the first electrode and the second electrode. That is, the voltage held by the holding unit 132 is the difference between the voltage at input node IN at time t114 (equation (16)) and the voltage at the inverting input terminal of amplifier 130 (equation (2)). Therefore, the voltage held by the holding unit 131 is expressed by equation (17). Equation (16)-Equation (2)= Gain×Nc+Gain×Vsig+Voffset (17)

[0065] At time t115, the control signal pSH2 changes from a high level to a low level, and switch SW2 turns off. When the noise signal at time t115 is Nd, the voltage at the first electrode of the holding unit 132 is expressed by equation (18). V1+Gain×Nd+Gain×Vsig (18)

[0066] The voltage held by the holding unit 132 is the difference between the voltages of the first electrode and the second electrode. That is, the voltage held by the holding unit 132 is the difference between the voltage at input node IN at time t115 (equation (18)) and the voltage at the inverting input terminal of amplifier 130 (equation (2)). Therefore, the voltage held by the holding unit 132 is expressed by equation (19). Equation (18)-Equation (2)= Gain×Nd+Gain×Vsig+Voffset (19)

[0067] At time t116, the control signal pAVE changes from a low level to a high level, switch SW3 is turned on, and the signals held in holding units 131 and 132 (see equations (17) and (19)) are averaged. The averaged signal can be calculated in the same way as described at time t107. That is, if Nc = Nd, the sum of the squares (mean squares) of the noise signals Nc and Nd is expressed by equation (20). Gain × Vsig + (Gain × Nc) / √2 ... (20)

[0068] In equation (20), the noise signal Nc is reduced to 1 / √2. However, as explained in equation (12), the reduction effect of the noise signal Nc decreases for low-frequency components, but noise of higher frequency components from time t115 to t116 can be reduced by the mean square method.

[0069] At time t117, the control signal pAMP_FB transitions from a high level to a low level, and switch SW4 turns off. Also, the control signal pAMP_O transitions from a low level to a high level, and switch SW5 turns on. As a result, amplifier 130 outputs a voltage Va corresponding to the voltages of the holding units 131 and 132. The voltage Va is expressed by equation (21). The voltage Va at this time represents the signal during photoelectric conversion of pixel 100. Va=V1+Gain×Vsig+(Gain×Nc) / √2 =V1+Gain×Vsig+Nave2 (21)

[0070] Between times t117 and t118, the AD conversion circuit 14 performs AD conversion of the voltage Va described in equation (21). That is, the reference signal generation circuit 142 changes the reference signal over time, and the comparator in the AD conversion circuit 14 compares the reference signal with the voltage Va and outputs a comparison signal. The column memory 15 holds the value of the counter 152 as the digital value of the voltage Va in accordance with the inversion of the comparison signal from the AD conversion circuit 14. The DFE 17 calculates the difference between the digital value at the time of reset (equation (13)) and the digital value at the time of photoelectric conversion (equation (21)) and performs correlated double sampling. The difference value is output as a pixel signal from the output circuit 171.

[0071] In the timing chart of Figure 4, the control signal pAMP_TH is at a low level at all times, and switch SW7 remains in the off state. The control signal pAMP_SEL is at a high level at all times, and switch SW6 remains in the on state. Therefore, no path is formed that shorts the input node IN and the output node OUT, i.e., a path that bypasses the holding units 131, 132 and amplifier 130. The signal from the readout circuit 12 is averaged by the holding units 131, 132 and amplifier 130 and output from the signal processing circuit 13. In other words, random noise generated in the circuit before the signal processing circuit 13 is averaged, and a noise reduction effect can be achieved.

[0072] However, since the holding parts 131 and 132 are capacitive elements, kTC noise may be generated when the holding parts 131 and 132 hold the signal. In low-gain mode, the kTC noise from the holding parts 131 and 132 cannot be ignored, and there is a risk of increased noise. For this reason, in low-gain mode, it is preferable that the input node IN and output node OUT in the signal processing circuit 13 are short-circuited and the holding parts 131 and 132 and the amplifier 130 are not used. On the other hand, in high-gain mode, the kTC noise becomes relatively small with respect to the signal, and the noise reduction effect by averaging in the signal processing circuit 13 becomes larger. Therefore, by switching the signal path according to the gain mode, it is possible to suppress kTC noise while achieving noise reduction by averaging.

[0073] Figure 5 is a timing chart showing the driving method of the photoelectric converter in this embodiment, and represents the driving method in low-gain mode. The following explanation will focus on the differences from the timing chart in Figure 4.

[0074] The control signals pSH1, pSH2, and pAMP_SEL are always at a low level, and switches SW1, SW2, and SW6 remain in the off state. Furthermore, the control signal pAMP_TH is always at a high level, and switch SW7 remains in the on state. Therefore, a signal path is formed that shorts the input node IN and output node OUT of the signal processing circuit 13, and the holding units 131, 132, and amplifier 130 are disconnected from the signal path. Consequently, the signal from the output node of the readout circuit 12 is output directly to the AD conversion circuit 14 via switch SW7.

[0075] The control signals pAVE, pAMP_FB, and pAMP_O are always at a high level, and switches SW3, SW4, and SW5 remain in the ON state. The inverting input terminal of amplifier 130 is connected to the output terminal, and the voltage at the non-inverting input terminal is fixed at voltage V1. Therefore, amplifier 130 continues to operate as a voltage follower that outputs a constant voltage (V1-Voffset). However, the voltage of amplifier 130 is not output outside the signal processing circuit 13.

[0076] In the timing chart of Figure 5, the holding units 131 and 132 and the amplifier 130 are not used in any circuit other than the signal processing circuit 13. The readout circuit 12 and the AD conversion circuit 14 process the signal without passing it through the signal processing circuit 13, as described below.

[0077] At time t201, the control signal pRES is at a high level, the reset transistor 106 of pixel 100 turns on, and the floating diffusion region 103 is reset. Also, the control signal pSEL transitions from a low level to a high level, the selection transistor 105 of pixel 100 turns on, and the amplification transistor 104 and the signal line L conduct. As a result, the pixel signal at the time of reset is output from pixel 100 to the signal line L. The voltage VL of the signal line L is (Vres - Vth - Vov) as expressed in equation (1) above.

[0078] At time t202, the control signal pRES transitions from high level to low level, and the reset transistor 106 turns off. The readout circuit 12 clamps the pixel signal at the time of reset to voltage V1. The voltage at the output node of the readout circuit 12 is (V1 + Gain × Na), as shown in equation (3) above. At some point between time t202 and time t210, the AD conversion circuit 14 performs AD conversion on the pixel signal output from the readout circuit 12.

[0079] At time t210, the control signal pTX transitions from a low level to a high level, the transfer transistor 102 in pixel 100 turns on, and the charge accumulated in the photoelectric conversion unit 101 is transferred to the floating diffusion region 103. The potential of the floating diffusion region 103 decreases in accordance with the transferred charge, and the voltage VL of the signal line L also decreases.

[0080] At time t211, the control signal pTX changes from a high level to a low level, the transfer transistor 102 turns off, and the charge transfer to the floating diffusion region 103 ends. At this time, the voltage VL becomes (Vres-Vth-Vov-Vsig) as shown in equation (14) above. Also, the voltage at the output node of the readout circuit 12 becomes (V1+Gain×Vsig) as in equation (15).

[0081] At any time between t211 and t218, the AD conversion circuit 14 performs AD conversion on the pixel signal output from the readout circuit 12. The DFE 17 calculates the difference between the digital value at reset and the digital value at photoelectric conversion. The difference value is output as a pixel signal from the output circuit 171.

[0082] As described above, in this embodiment, the amplifier 130 continues to operate even when the signal processing circuit 13 is not used. It is also conceivable to cut off or reduce the power supply current to unused circuits to disable them. In this case, the time it takes for the circuits to recover would be longer, making it difficult to seamlessly switch imaging modes. Furthermore, current fluctuations may occur when the circuits recover, potentially leading to image quality degradation such as signal fluctuations in other circuits and the superposition of false signals. According to this embodiment, the amplifier 130 is maintained in operation even when the signal processing circuit 13 is not used. This allows for seamless switching of imaging modes and suppresses image quality degradation during imaging mode switching. If the recovery time of the amplifier 130 is sufficiently short, the power supply current to the amplifier 130 may be cut off. In this case, current consumption can be reduced.

[0083] Furthermore, in this embodiment, the input voltage of the amplifier 130 is kept constant when not in use. If the voltage at the input terminal were undefined, the output voltage of the amplifier 130 would exceed the operating range, resulting in a longer recovery time for the amplifier 130. According to this embodiment, since the input voltage of the amplifier 130 is kept constant when not in use, the photoelectric converter can immediately start imaging without requiring a recovery time for the signal processing circuit 13 when switching from low-gain mode to high-gain mode. Therefore, it is also possible to switch the gain mode on a frame-by-frame basis of the video.

[0084] Furthermore, since amplifier 130 operates as a voltage follower and buffer amplifier, the gain in signal processing circuit 13 remains "1" whether signal processing circuit 13 is in use or not. Therefore, it is possible to reduce the amplitude fluctuation of the signal when signal processing circuit 13 is in use or not.

[0085] As described above, when the signal processing circuit is not used, the amplifier 130 maintains its operating state and outputs a constant voltage. Therefore, when the signal processing circuit 13 is not in use, the signal processing circuit 13 does not generate noise. In addition, the time required for mode switching can be shortened, enabling seamless mode switching.

[0086] Therefore, according to this embodiment, it is possible to solve the problem of the signal processing circuit during recovery.

[0087] [Second Embodiment] Next, the photoelectric conversion device in this embodiment will be described. The photoelectric conversion device in this embodiment differs from the first embodiment in the configuration and driving method of the signal processing circuit 13. The following description will focus on the differences from the first embodiment.

[0088] Figure 6 is an equivalent circuit diagram of the signal processing circuit 13 in this embodiment. The signal processing circuit 13 includes an amplifier 130, switches SW1 to SW3, SW6 to SW9, and holding units 131 and 132. The inverting input terminal of the amplifier 130 is connected to node A, and the amplifier 130 can operate as a voltage follower.

[0089] Switch SW1 (input switch, first switch) is connected in series between the input node IN and the holding unit 131. The first node of switch SW1 is connected to the input node IN, i.e., the output node of the read circuit 12. The second node of switch SW1 is connected to the first electrode of the holding unit 131, the first node of switch SW3, and the first node of switch SW8. The second electrode of the holding unit 131 is connected to the ground node. A control signal pSH1 is input to the control node of switch SW1. When the control signal pSH1 becomes high and switch SW1 is turned on, the signal from the read circuit 12 is input to the holding unit 131. When the control signal pSH1 becomes low and switch SW1 is turned off, the holding unit 131 holds the signal.

[0090] Switch SW2 (input switch, second switch) is connected in series between the input node IN and the holding unit 132. The first node of switch SW2 is connected to the input node IN, i.e., the output node of the read circuit 12, and the second node of switch SW2 is connected to the first electrode of the holding unit 132, the second node of switch SW3. The second electrode of the holding unit 132 is connected to the ground node. A control signal pSH2 is input to the control node of switch SW2. When the control signal pSH2 goes high and switch SW2 is turned on, the signal from the read circuit 12 is input to the holding unit 132. When the control signal pSH2 goes low and switch SW2 is turned off, the holding unit 132 holds the signal.

[0091] Switch SW3 (the third switch) is connected between the holding units 131 and 132. The first node of switch SW3 is connected to the second node of switch SW1 and the first electrode of the holding unit 131, and the second node of switch SW3 is connected to the second node of switch SW2 and the first electrode of the holding unit 132. The control node of switch SW3 receives the control signal pAVE. When the control signal pAVE becomes high and switch SW3 is turned on, the holding units 131 and 132 are short-circuited, and the signals from the holding units 131 and 132 are averaged. When the control signal pAVE becomes low, switch SW3 is turned off, and the holding units 131 and 132 can hold different signals from each other.

[0092] Switch SW8 (the sixth switch) is connected in series between the holding unit 131 (132) and the non-inverting input terminal of the amplifier 130. That is, the first node of switch SW8 is connected to the second node of switch SW1, the first node of switch SW3, and the first electrode of the holding unit 131, while the second node of switch SW8 is connected to the non-inverting input terminal of the amplifier 130 and the second node of switch SW9. The control signal pAMP_FIX_B is input to the control node of switch SW8. When the control signal pAMP_FIX_B becomes high level and switch SW8 is turned on, the signal held by the holding unit 131 (132) is input to the non-inverting input terminal of the amplifier 130. When the control signal pAMP_FIX_B becomes low level and switch SW8 is turned off, the non-inverting input terminal of the amplifier 130 is disconnected from the holding unit 131 (132).

[0093] Switch SW9 (the seventh switch) is connected in series between the non-inverting input terminal of amplifier 130 and the voltage V1 wiring (constant voltage line). Voltage V1 is applied to the first node of switch SW9, and the second node of switch SW9 is connected to the non-inverting input terminal of amplifier 130 and the second node of switch SW8. The control node of switch SW9 is input to the control signal pAMP_FIX. When the control signal pAMP_FIX becomes high level and switch SW9 is turned on, voltage V1 is applied to the non-inverting input terminal of amplifier 130. When the control signal pAMP_FIX becomes low level and switch SW9 is turned off, voltage V1 is no longer applied to the non-inverting input terminal of amplifier 130. The control signal pAMP_FIX is the inverse signal of the control signal pAMP_FIX_B. That is, when switch SW8 is on, switch SW9 is off, and when switch SW8 is off, switch SW9 is on.

[0094] Switches SW6 and SW7 are configured in the same way as in the first embodiment. Switch (output switch) SW6 is connected in series between the output terminal (node ​​A) of amplifier 130 and the output node OUT. Switch (short-circuit switch) SW7 is connected in series between the input node IN and the output node OUT.

[0095] In this embodiment, as in the first embodiment, it is possible to switch the signal path in the signal processing circuit 13 according to the readout mode. That is, in the high-gain mode (first operating mode), noise reduction is performed using the holding units 131, 132 and the amplifier 130, and in the low-gain mode (second operating mode), the holding units 131, 132 and the amplifier 130 are disconnected from the signal path.

[0096] Figure 7 is a timing chart showing the driving method of the photoelectric converter in this embodiment, and represents the driving method in high-gain mode. In high-gain mode, the control signal pAMP_TH is always low level, and the control signal pAMP_SEL is always high level. Therefore, the signal path that shorts the input node IN and the output node OUT, i.e., the signal path that bypasses the holding units 131, 132 and amplifier 130, is blocked. Also, the control signal pAMP_FIX is always low level, and switch SW9 is off. The control signal pAMP_FIX_B, which is the inverse signal of the control signal pAMP_FIX, is always high level, and switch SW8 is on. Therefore, in high-gain mode, voltage V1 is not input to the non-inverting input terminal of amplifier 130.

[0097] At time t301, the control signal pRES is at a high level, the reset transistor 106 of pixel 100 turns on, and the floating diffusion region 103 is reset. Also, the control signal pSEL transitions from a low level to a high level, the selection transistor 105 of pixel 100 turns on, and the amplification transistor 104 and the signal line L conduct. As a result, the pixel signal at the time of reset is output from pixel 100 to the signal line L. At this time, if the reset level of the floating diffusion region 103 is Vres, the threshold value of the amplification transistor 104 is Vth, and the overdrive voltage for flowing the desired current I is Vov, then the voltage VL on the signal line L is given by equation (1) above, which is (Vres-Vth-Vov). In the signal processing circuit 13, since the control signals pSH1 and pSH2 are at a low level, switches SW1 and SW2 are off. At this time, if the voltage V1 is held in the holding unit 131, the voltage Va at node A is (V1+Voffset).

[0098] At time t302, the control signal pRES transitions from a high level to a low level, the reset transistor 106 turns off, and the floating diffusion region 103 enters a floating state.

[0099] At time t304, the control signals pSH1 and pSH2 transition from low level to high level, and switches SW1 and SW2 are turned on. The input node IN and the holding units 131 and 132 become conductive, and the reset signal is output from the read circuit 12 to the holding units 131 and 132.

[0100] At time t305, the control signal pSH1 transitions from a high level to a low level, the switch SW1 turns off, and the voltage at input node IN is held in the holding unit 131. At this time, the voltage held in the holding unit 131 is the voltage (V1 + Gain × Na), as in equation (3) above. If the amplifier 130 has an offset voltage Voffset and the voltage of the pixel signal (noise signal) at time t305 is Na, the voltage at node A is expressed by equation (22). V1+Gain×Na+Voffset ···(22)

[0101] At time t306, the control signal pSH2 transitions from a high level to a low level, switch SW2 turns off, and the voltage at the output node of the readout circuit 12 is held in the holding unit 132. If the voltage of the pixel signal (noise signal) at time t306 is Nb, the voltage held in the holding unit 132 will be (V1 + Gain × Nb), as in equation (5) above. At this time, switch SW3 is off, and the holding unit 132 is not connected to the non-inverting input terminal of the amplifier 130. Therefore, node A maintains the voltage of equation (22).

[0102] At time t307, the control signal pAVE transitions from a low level to a high level, the switch SW3 turns on, and the signals held in the holding unit 131 and the holding unit 132 are averaged. That is, the voltage (V1 + Gain × Na) in equation (3) and the voltage (V1 + Gain × Nb) in equation (5) are averaged. The averaged voltage is expressed by equation (23), which includes V1, unlike equation (12) in the first embodiment. V1+ formula (12) =V1+(Gain×Na) / √2 ··· (23)

[0103] Similar to the first embodiment, equation (23) can reduce high-frequency noise with a period shorter than the time from the falling edge of control signal pSH1 (time t305) to the falling edge of control signal pSH2 (time t306) to (1 / √2). On the other hand, equation (23) cannot average out low-frequency noise with a period longer than the time from time t305 to t306. Therefore, low-frequency noise can actually be greater than the root mean square (1 / √2).

[0104] By replacing (Gain × Na) / √2 in equation (12) with Nave, the voltage Va at node A of amplifier 130 is expressed in equation (24). Va = V1 + Nave + Voffset ... (24)

[0105] Between times t308 and t309, the AD conversion circuit 14 performs AD conversion on the output signal from the signal processing circuit 13, i.e., the voltage Va in equation (24).

[0106] At time t309, the control signal pAVE transitions from a high level to a low level, and switch SW3 turns off.

[0107] At time t310, the control signal pTX transitions from a low level to a high level, the transfer transistor 102 in pixel 100 turns on, and the charge accumulated in the photoelectric conversion unit 101 is transferred to the floating diffusion region 103. The potential of the floating diffusion region 103 decreases in accordance with the transferred charge, and the voltage VL of the signal line L also decreases. Let Vsig be the amount of change in the voltage VL of the signal line L at this time.

[0108] At time t311, the control signal pTX changes from a high level to a low level, the transfer transistor 102 turns off, and the charge transfer to the floating diffusion region 103 ends. At this time, the voltage VL across the signal line L is expressed by the voltage (Vres-Vth-Vov-Vsig) in equation (14). The voltage at the input node IN, that is, the voltage at the output node of the readout circuit 12, is the voltage (V1+Gain×Vsig) in equation (15).

[0109] At time t313, the control signals pSH1 and pSH2 transition from low level to high level, switches SW1 and SW2 turn on, and the first electrodes of the holding units 131 and 132 are connected to the input node IN. The voltage (V1 + Gain × Vsig) of equation (15) is output to the first electrodes of the holding units 131 and 132.

[0110] At time t314, the control signal pSH1 transitions from a high level to a low level, the switch SW1 turns off, and the holding unit 131 holds the voltage of the input node IN. At this time, the voltage held by the holding unit 131 is the voltage (V1 + Gain × Nc + Gain × Vsig) given by equation (16). The voltage Va at node A is given by equation (25). Va=V1+Gain×Nc+Gain×Vsig+Voffset ···(25)

[0111] At time t315, the control signal pSH2 changes from a high level to a low level, switch SW2 turns off, and the holding unit 132 holds the voltage of the input node. At this time, the voltage held by the holding unit 132 is (V1 + Gain × Nd + Gain × Vsig), as in equation (18). At this time, since switch SW3 is off, the holding unit 132 is not connected to the non-inverting force node of amplifier 130. Therefore, node A maintains the voltage of equation (25).

[0112] At time t316, the control signal pAVE changes from a low level to a high level, switch SW3 is turned on, and the signals held in holding units 131 and 132 are averaged. The averaged signal is represented by equation (26), which is equation (20) with the voltage V1 added. V1+ formula (20) =V1+Gain×Vsig+(Gain×Nc) / √2 ···(26)

[0113] If we replace the noise component ((Gain × Nc) / √2) in equation (26) with Nave2, the voltage Va at node A can be expressed in equation (27). Va=V1+Gain×Vsig+Nave2+Voffset ···(27)

[0114] Between times t316 and t318, the AD conversion circuit 14 performs AD conversion of the voltage Va described in equation (27). At time t318, the control signal pAVE transitions from a high level to a low level, and switch SW3 is turned off. Subsequently, DFE 17 calculates the difference between the digital value at the time of reset (equation (24)) and the digital value at the time of photoelectric conversion (equation (27)), and performs correlated double sampling. The difference value is output as a pixel signal from output circuit 171.

[0115] In this embodiment as well, signal noise reduction can be achieved by using the amplifier 130 and the holding units 131 and 132 in the high-gain mode. As described above, in the low-gain mode, the kTC noise in the holding units 131 and 132 cannot be ignored. For this reason, in this embodiment as well, it is preferable that the amplifier 130 and the holding units 131 and 132 are not used in the low-gain mode.

[0116] Figure 8 is a timing chart showing the driving method of the photoelectric converter in this embodiment, and represents the driving method in low-gain mode. In low-gain mode, the control signal pAMP_TH is always at a high level, and switch SW7 remains in the ON state. Also, the control signal pAMP_SEL is always at a low level, and switch SW6 remains in the OFF state. As a result, a signal path is formed that short-circuits the input node IN of the signal processing circuit 13 to the output node OUT, and the holding units 131, 132 and amplifier 130 are disconnected from the signal path. Therefore, the signal from the output node of the readout circuit 12 is output directly to the AD conversion circuit 14 via switch SW7.

[0117] The control signal pAMP_FIX is always at a high level, and switch SW9 remains in the ON state. The control signal pAMP_FIX_B is always at a low level, and switch SW8 remains in the OFF state. As a result, the non-inverting input terminal of amplifier 130 is disconnected from the holding units 131 and 132 and connected to voltage V1. Therefore, amplifier 130 continues to operate as a voltage follower that outputs a voltage (V1-Voffset). However, the voltage at node A is not output outside the signal processing circuit 13.

[0118] In the timing chart of Figure 8, the holding units 131 and 132 and the amplifier 130 are not used, and the readout circuit 12 and the AD conversion circuit 14 process the signal without passing it through the signal processing circuit 13. At time t401, the control signal pSEL transitions from a low level to a high level, and the pixel signal at the time of reset is output from pixel 100 to signal line L. The voltage VL of signal line L is (Vres-Vth-Vov) as expressed in equation (1) above.

[0119] At time t402, the control signal pRES transitions from high level to low level, and the reset transistor 106 turns off. The readout circuit 12 clamps the pixel signal at the time of reset to voltage V1. The voltage at the output node of the readout circuit 12 is (V1 + Gain × Na), as shown in equation (3) above. At some point between time t402 and time t410, the AD conversion circuit 14 performs AD conversion on the pixel signal output from the readout circuit 12.

[0120] Between times t410 and t411, the control signal pTX becomes high level, and the pixel signal during photoelectric conversion is read out. At time t411, the voltage VL of the signal line L is (Vres-Vth-Vov-Vsig) as expressed by equation (14) above. Also, the voltage at the output node of the readout circuit 12 is (V1+Gain×Vsig) as in equation (15).

[0121] At any time between t411 and t418, the AD conversion circuit 14 performs AD conversion on the pixel signal output from the readout circuit 12. The DFE 17 calculates the difference between the digital value at reset and the digital value at photoelectric conversion. The difference value is output as a pixel signal from the output circuit 171.

[0122] In this embodiment, as in the embodiment described above, it is possible to solve the problem of the signal processing circuit 13 during recovery. When the signal processing circuit 13 is not used, the amplifier 130 is in operation, and the voltage at the input terminal of the amplifier 130 is kept constant. Therefore, when the signal processing circuit 13 is not used, the signal processing circuit 13 does not generate noise. Furthermore, seamless mode switching can be achieved without requiring time for mode switching. Note that if the recovery time of the amplifier 130 is sufficiently short, the power supply current to the differential amplifier 130 may be cut off. In this case, it is possible to reduce the current consumption.

[0123] In Figure 8, the control signals pSH1 and pSH2 are always at a low level, but the control signals pSH1 and pSH2 may be set to a high level at all times, and switches SW1 and SW2 may remain in the ON state. In this case, the frequency bandwidth of the signal from the readout circuit 12 is shifted to the low-frequency side, and high-frequency noise can be reduced. On the other hand, in the first embodiment, each of the holding units 131 and 132 is connected in series with the signal path. Here, in order to connect the holding units 131 and 132 in parallel between the signal path and the ground wiring, a new switch would be required, which could increase the circuit size. According to this embodiment, it is possible to enhance the noise reduction effect in low-gain mode while suppressing the circuit size.

[0124] [Third Embodiment] Next, the photoelectric converter in this embodiment will be described. The photoelectric converter in this embodiment differs from the second embodiment in its driving method in low-gain mode. The circuit configuration and driving method in high-gain mode of the photoelectric converter in this embodiment are the same as in the second embodiment. The following description of this embodiment will focus on the differences from the second embodiment.

[0125] Figure 9 is a timing chart showing the driving method of the photoelectric converter in this embodiment, and represents the driving method in low-gain mode. The control signal pAMP_TH is always at a high level, and switch SW7 remains in the ON state. Also, the control signal pAMP_SEL is always at a low level, and switch SW6 remains in the OFF state. As a result, a signal path is formed that connects directly from the input node IN of the signal processing circuit 13 to the output node OUT, and the holding units 131, 132 and amplifier 130 are disconnected from the signal path. Therefore, the signal from the output node of the readout circuit 12 is output directly to the AD conversion circuit 14 via switch SW7.

[0126] On the other hand, unlike the second embodiment, the control signals pSH1, pSH2, and pAVE are always at a high level, and the control signal pAMP_FIX is always at a low level. Also, the control signal pAMP_FIX_B, which is the inverted signal of the control signal pAMP_FIX, is always at a high level. Switches SW1, SW2, and SW3 are turned on, and input node IN is connected to the non-inverting input terminal of amplifier 130. As a result, amplifier 130 operates as a voltage follower and outputs a voltage corresponding to the voltage of the readout circuit 12. In this embodiment as well, the voltage of node A is not output outside the signal processing circuit 13.

[0127] At time t501, the control signal pSEL transitions from a low level to a high level, and the pixel signal at reset is output from pixel 100 to signal line L. At time t502, the control signal pRES transitions from a high level to a low level, and the reset transistor 106 turns off. The readout circuit 12 clamps the pixel signal at reset to voltage V1. As described above, switches SW1, SW2, and SW3 remain in the ON state, so the voltage V1 from the readout circuit 12 is input to the non-inverting input terminal of amplifier 130. Amplifier 130 outputs a voltage (V1 + Voffset). At some point between time t502 and t510, the AD conversion circuit 14 performs AD conversion on the pixel signal output from the readout circuit 12.

[0128] Between times t510 and t511, the control signal pTX becomes high level, and the signal during photoelectric conversion is read out. At time t511, the voltage VL of the signal line L is (Vres-Vth-Vov-Vsig) as shown in equation (14). Also, the voltage at the output node of the readout circuit 12, i.e., the voltage at the input node IN, is (V1+Gain×Vsig) as shown in equation (15). The voltage at node A is (V1+Gain×Vsig+Voffset).

[0129] At any time between t511 and t518, the AD conversion circuit 14 performs AD conversion on the pixel signal output from the readout circuit 12. The DFE 17 calculates the difference between the digital value at reset and the digital value at photoelectric conversion. The difference value is output as a pixel signal from the output circuit 171.

[0130] As described above, the signal processing circuit 13 is not used in low-gain mode, but the signal from the readout circuit 12 is input to the non-inverting input terminal of the amplifier 130. Therefore, the output voltage of the amplifier 130 changes according to the input signal. However, since switch SW6 is off, the output terminal (node ​​A) of the amplifier 130 is disconnected from the output node OUT. Also, the output voltage of the amplifier 130 changes in phase with the output voltage of the readout circuit 12. Therefore, the influence of the amplifier 130 on the subsequent circuit is small.

[0131] In this embodiment as well, since the amplifier 130 is always in operation, imaging can be started without requiring circuit recovery time when switching from low-gain mode to high-gain mode. If the circuit recovery time when switching imaging modes is sufficiently short, the power supply current to the amplifier 130 may be cut off or reduced.

[0132] [Fourth Embodiment] The solid-state photoelectric converter in the above-described embodiment is applicable to various devices. Examples of such devices include digital still cameras, digital camcorders, camera heads, photocopiers, fax machines, mobile phones, in-vehicle cameras, observation satellites, and surveillance cameras. Figure 10 shows a block diagram of a digital still camera as an example of such a device.

[0133] The device 7 shown in Figure 10 includes a barrier 706, a lens 702, an aperture 704, an imaging device 70 (an example of a photoelectric converter), a signal processing unit (processing unit) 708, a timing generation unit 720, an overall control / calculation unit 718 (control device), a memory unit 710 (storage device), a recording medium control I / F unit 716, a recording medium 714, and an external I / F unit 712. At least one of the barrier 706, lens 702, and aperture 704 is an optical device corresponding to the device. The barrier 706 protects the lens, and the lens 702 forms an optical image of the subject on the imaging device 70. The aperture 704 varies the amount of light passing through the lens 702. The imaging device 70 is configured as in the embodiment described above, and converts the optical image formed by the lens 702 into image data (image signal). Here, it is assumed that an AD (analog-to-digital) conversion unit is formed on the semiconductor substrate of the imaging device 70. The signal processing unit 708 performs various corrections and data compression on the imaging data output from the imaging device 70. The timing generation unit 720 outputs various timing signals to the imaging device 70 and the signal processing unit 708. The overall control / calculation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The recording medium control I / F unit 716 is an interface for recording or reading image data to or from the recording medium 714, which is a removable recording medium such as a semiconductor memory for recording or reading imaging data. The external I / F unit 712 is an interface for communicating with an external computer or the like. Timing signals and the like may be input from outside the device. Furthermore, the device 7 may also include a display device (monitor, electronic viewfinder, etc.) for displaying information obtained from the photoelectric converter. The device includes at least a photoelectric converter. Furthermore, the device includes at least one of an optical device, a control device, a processing device, a display device, a storage device, and a mechanical device that operates based on information obtained from the photoelectric converter. The mechanical device is a movable part (for example, a robot arm) that operates in response to signals from the photoelectric converter.

[0134] The imaging device 70 and the AD conversion unit may be provided on separate semiconductor substrates, or they may be formed on the same semiconductor substrate. Alternatively, the imaging device 70 and the signal processing unit 708 may be formed on the same semiconductor substrate.

[0135] Furthermore, each pixel may include a first photoelectric conversion unit and a second photoelectric conversion unit. The signal processing unit 708 may be configured to process a pixel signal based on the charge generated in the first photoelectric conversion unit and a pixel signal based on the charge generated in the second photoelectric conversion unit, and to acquire distance information from the imaging device 70 to the subject.

[0136] [Fifth Embodiment] Figure 11 is a block diagram of the equipment related to the in-vehicle camera in this embodiment. Equipment 8 includes an imaging device 80 (an example of a photoelectric converter) as described above, and a signal processing device (processing device) that processes signals from the imaging device 80. Equipment 8 includes an image processing unit 801 that performs image processing on a plurality of image data acquired by the imaging device 80, and a parallax calculation unit 802 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by Equipment 8. Equipment 8 also includes a distance measurement unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 804 may use any of this distance information to determine the possibility of collision. The distance information acquisition means may be implemented by specially designed hardware or by a software module. Furthermore, it may be implemented using FPGAs (Field Programmable Gate Arrays), ASICs (Application Specific Integrated Circuits), or a combination thereof.

[0137] Device 8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Device 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate braking force on the vehicle based on the collision determination result of the collision determination unit 804. Furthermore, device 8 is connected to a warning device 830 that issues a warning to the driver based on the collision determination result of the collision determination unit 804. For example, if the collision determination unit 804 determines that there is a high probability of collision, the control ECU 820 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 830 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seatbelt or steering wheel. As described above, device 8 functions as a control means that controls the actions that control the vehicle.

[0138] In this embodiment, the equipment 8 images the area around the vehicle, for example, in front of or behind it. Figure 11(B) shows the equipment when imaging the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810, acting as an imaging control means, sends instructions to the equipment 8 or imaging device 80 to perform the operations described in the first to fourth embodiments above. This configuration makes it possible to further improve the accuracy of distance measurement.

[0139] The above example described controlling a vehicle to avoid collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles or automatically drive a vehicle to prevent it from straying from its lane. Furthermore, the equipment is not limited to vehicles such as automobiles, but can be applied to mobile objects (mobile devices) such as ships, aircraft, satellites, industrial robots, and consumer robots. In addition, it can be applied not only to mobile objects, but also to a wide range of devices that utilize object recognition or biometric recognition, such as intelligent transportation systems (ITS) and surveillance systems.

[0140] [Other embodiments] The amplifier 130 in the signal processing circuit 13 may have either single-ended or differential input. Furthermore, the signal processing circuit 13 is not limited to a sample-and-hold circuit. For example, the signal processing circuit 13 may include a clamping circuit for clamping the signal read from the pixel 100, an amplification circuit for amplitude amplification of the signal, a circuit for generating a reference signal, and a constant voltage circuit for generating a bias voltage. Moreover, the signal processing circuit 13 is not limited to an analog circuit, but may also be a pulse circuit or a digital circuit. [Explanation of symbols]

[0141] 10-pixel array 11 Vertical scanning circuit 12 Readout circuit 13 Signal Processing Circuits 14 AD conversion circuit 15-column memory 16 Horizontal scanning circuit 18 Timing Generator (TG) 100 pixels 130 Amplifier 131, 132 Holding part SW1~SW9 Switches

Claims

1. A pixel that outputs a signal corresponding to the incident light, An input node that receives the aforementioned signal, A holding unit that holds the signal input to the input node, An amplifier that receives the signal held in the holding part, An output node that outputs the signal from the amplifier, An input switch connected in series between the input node and the holding unit, An output switch connected in series between the amplifier and the output node, The system includes a short-circuit switch that short-circuits the input node and the output node, In the first operating mode, which is a high-gain readout mode, the output switch is in the ON state, and the input switch is turned ON or OFF at predetermined timings to hold the signal in the holding unit. A photoelectric converter characterized in that, in a second operating mode which is a low-gain readout mode, the input switch and the output switch are in the off state, the short-circuit switch is in the on state, and the amplifier outputs a constant voltage.

2. A pixel that outputs a signal corresponding to the incident light, An input node that receives the aforementioned signal, A holding unit that holds the signal input to the input node, An amplifier that receives the signal held in the holding part, An output node that outputs the signal from the amplifier, An input switch connected in series between the input node and the holding unit, An output switch connected in series between the amplifier and the output node, The system includes a short-circuit switch that short-circuits the input node and the output node, In the first operating mode, which is a high-gain readout mode, the output switch is in the ON state, and the input switch is turned ON or OFF at predetermined timings to hold the signal in the holding unit. A photoelectric converter characterized in that, in a second operating mode which is a low-gain readout mode, the output switch is in the off state, the short-circuit switch is in the on state, and the input switch is in the on state, thereby inputting the signal from the input node to the amplifier.

3. With additional signal lines, The pixel includes a photoelectric conversion unit that generates an electric charge based on incident light, and an amplifying transistor that outputs the signal corresponding to the electric charge to the signal line. The photoelectric converter according to claim 1 or 2, characterized in that the input node is electrically connected to the signal line and receives the signal.

4. The photoelectric conversion device according to any one of claims 1 to 3, characterized in that, in the second operating mode, the holding unit and the amplifier are not used in any circuit other than the holding unit and the amplifier.

5. The system further includes a readout circuit that reads the signal from the pixel, amplifies the readout signal with a predetermined gain, and outputs it to the input node. The photoelectric converter according to any one of claims 1 to 4, characterized in that the gain in the first operating mode is greater than the gain in the second operating mode.

6. The system further comprises a short-circuit switch connected in series between the input node and the output node, The photoelectric converter according to any one of claims 1 to 5, characterized in that the short-circuit switch is in the ON state in the second operating mode.

7. The holding portion includes a first holding portion and a second holding portion. The photoelectric converter according to any one of claims 1 to 6, characterized in that the input switch includes a first switch connected in series with the input node and the first holding part, and a second switch connected in series with the input node and the second holding part.

8. The photoelectric conversion device according to claim 7, characterized in that the timing at which the first switch turns off and the timing at which the second switch turns off are different.

9. The device further includes a third switch that connects the first holding part and the second holding part in parallel. The photoelectric conversion device according to claim 7 or 8, characterized in that the third switch is turned on after the first switch and the second switch are turned off.

10. The system further includes a conversion circuit that converts the signal output from the output node into a digital signal. The photoelectric converter according to claim 9, characterized in that when the third switch is in the ON state, the conversion circuit converts the signal into the digital signal.

11. The photoelectric conversion device according to claim 1, characterized in that the holding portion is connected in series between the input node and the amplifier.

12. A fourth switch connected in series between the inverting input terminal and the output terminal of the amplifier, The photoelectric converter according to claim 11, further comprising a fifth switch connected in series between the holding portion and the connection node of the input switch and the output terminal.

13. The photoelectric converter according to claim 12, characterized in that when the input switch is in the ON state, the fourth switch is in the ON state and the fifth switch is in the OFF state.

14. The photoelectric conversion device according to claim 2, characterized in that the holding portion is connected between the input node and the ground node.

15. The output terminal of the aforementioned amplifier is connected to the inverting input terminal. A sixth switch connected in series between the non-inverting input terminal of the amplifier and the holding part, The photoelectric converter according to claim 14, further comprising a seventh switch connected in series between the non-inverting input terminal and a predetermined constant voltage line.

16. In the first operating mode, the sixth switch is in the ON state and the seventh switch is in the OFF state. The photoelectric converter according to claim 15, characterized in that in the second operating mode, the sixth switch is in the off state and the seventh switch is in the on state.

17. The photoelectric conversion device according to any one of claims 1 to 16, characterized in that the amplifier operates as a voltage follower.

18. A photoelectric conversion device according to any one of claims 1 to 17, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A display device that displays information obtained by the aforementioned photoelectric converter. A storage device for storing information obtained by the aforementioned photoelectric converter, and A device characterized by comprising at least one of the following: a mechanical device that operates based on information obtained from the photoelectric converter.

19. The aforementioned pixel includes a plurality of photoelectric conversion units, The apparatus according to claim 18, characterized in that the processing device processes the signals generated by the plurality of photoelectric conversion units and obtains distance information from the photoelectric conversion device to the subject.

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