Semiconductor processing components

Abstract

To provide a semiconductor processing component that suppresses the generation of slip dislocations in a ring-shaped semiconductor processing component that holds a semiconductor wafer when performing thermal oxidation processing on the semiconductor wafer, and reduces the variation in the thickness of the oxide film deposited on the wafer surface.SOLUTION: A ring-shaped semiconductor processing component comprises a silicon carbide base material 4 and holds a semiconductor wafer, a wafer holding portion 3 in contact with the semiconductor wafer has a convex shape and the R value of the inner circumference of the convex shape is between 0.1 mm and 0.3 mm.SELECTED DRAWING: Figure 2

Description

Technical Field

[0005] ,

[0004] , , , , ,

[0003]

[0001] The present invention relates to a semiconductor processing member, and more particularly, to a semiconductor processing member suitable for use as a ring for holding a semiconductor wafer, for example, in an RTP apparatus (rapid thermal processing apparatus).

Background Art

[0002] In the semiconductor manufacturing process, an RTP apparatus is used as a heat treatment apparatus for heat-treating a semiconductor wafer. The RTP apparatus uses a heating method using lamp heating, rapidly heats the wafer to 1000°C or higher in several tens of seconds, and eliminates the temperature difference on the wafer surface by feedback control of the infrared lamps arranged in an equidistant manner to form a good in-plane uniform oxide film.

[0003] In the method using an RTP apparatus, by holding the semiconductor wafer near the center of the processing chamber with a good light irradiation balance, the entire wafer can be uniformly heated without passing through a heat medium. Therefore, it can be instantaneously heated with a minimum heat capacity, and the possibility of destroying the wafer structure is small, which is particularly effective for annealing the wafer.

[0004] In such a thermal oxidation process of the wafer, a silicon carbide-based ring-shaped semiconductor processing member having high heat resistance and thermal conductivity is used. The frame portion of the ring-shaped semiconductor processing member is adjusted to a size that can fit and fix a semiconductor wafer inside it, and the wafer holding portion inside the frame portion holds the wafer parallel and horizontally with respect to the grounding surface of the semiconductor processing member. When high-speed heating is performed on the wafer held by the wafer holding portion in this way, the entire wafer can be heated.

[0005] However, conventional semiconductor processing members support the wafer with the entire wafer holding portion, resulting in a large contact area between the wafer and the wafer holding portion. This creates a temperature difference between the outer edge and the center of the wafer, leading to problems such as slippage due to uneven heating. To resolve these problems and heat the entire wafer uniformly, a semiconductor heat treatment member has been reported in which the inner wall that supports and fixes the wafer is composed of a vertical surface and a sloped surface. In this semiconductor heat treatment member, at least three protrusions are formed on the inner wall that supports and fixes the wafer, thereby reducing the contact area between the wafer and the wafer holding portion (Patent Document 1).

[0006] To ensure a uniform oxide film thickness on a wafer, the lamps installed above and below the wafer must be parallel to the wafer. Furthermore, since heat conduction from the semiconductor processing equipment affects the uniformity of the oxide film, the area of ​​the wafer holder in contact with the wafer needs to be reduced. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2002-231713 [Overview of the project] [Problems that the invention aims to solve]

[0008] The present invention has been made under the circumstances described above, and aims to provide a semiconductor processing member that can suppress the occurrence of slip when thermal oxidation treatment is applied to a semiconductor wafer, and reduce variations in the thickness of the oxide film formed on the wafer surface, in a ring-shaped semiconductor processing member for holding a semiconductor wafer. [Means for solving the problem]

[0009] The semiconductor processing member of the present invention is For RTP equipment that performs heat treatment on the surface of semiconductor wafers Made from a silicon carbide base material ru a ring-shaped semiconductor processing member that holds a semiconductor wafer, It comprises a ring-shaped frame and a wafer holding portion formed on the lower inner side of the frame for holding a semiconductor wafer. , The wafer holding portion is provided with a slope that slopes downward toward the frame portion, and a convex shape that contacts the semiconductor wafer is provided at the uppermost part of the slope of the wafer holding portion. The R value of the convex shape is 0.1 mm or more and 0.3 mm or less. By making the wafer holding portion convex, the contact area with the semiconductor wafer is reduced, and by further rounding the convex portion, wafer slip dislocations can be suppressed, and variations in oxide film thickness can also be reduced. Preferably, the geometric deviation (parallelism) between the surface of the semiconductor wafer when held in the wafer holding portion and the lower surface of the frame portion formed on the outside of the wafer holding portion is 0.05 mm or less, in accordance with JIS B0621:1984. By placing the semiconductor wafer horizontally to its outer edge in this manner, the effect of suppressing slippage and variations in oxide film thickness becomes even more pronounced. Preferably, the top of the convex shape of the wafer holding portion is located 5 mm or less from the outer edge of the semiconductor wafer toward the center. By ensuring that the contact point between the wafer holder and the semiconductor wafer is within 5 mm of the outer edge of the semiconductor wafer, the semiconductor wafer can be heated uniformly. Preferably, the surface of the substrate made of silicon carbide is coated with silicon oxide with a thickness of 0.5 μm to 5 μm. The surface of the semiconductor wafer is coated with a dense and highly adhesive silicon oxide film, which has a very beneficial effect when assembling the wafer into semiconductor devices. [Effects of the Invention]

[0010] According to the present invention, a ring-shaped semiconductor processing member for holding a semiconductor wafer can be provided that suppresses the occurrence of slip when forming an oxide film on the semiconductor wafer by heat treatment and reduces variations in the oxide film formed on the wafer surface. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is a plan view of the semiconductor processing member of the present invention. [Figure 2] Figure 2 is a cross-sectional view taken along the line AA in Figure 1. [Figure 3] Figure 3 is a schematic perspective view of the semiconductor processing member of the present invention. [Figure 4] Figure 4 is a schematic cross-sectional view showing an RTP apparatus using the semiconductor processing member shown in Figure 1. [Modes for carrying out the invention]

[0012] Hereinafter, an embodiment of the semiconductor processing member of the present invention will be described with reference to Figures 1 to 3. Figure 1 is a plan view of the ring as a semiconductor heat treatment member of the present invention, and Figure 2 is a cross-sectional view taken along the line AA in Figure 1. Figure 3 is a perspective view of the ring, which is a semiconductor heat treatment member. The figures are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc., are not accurately illustrated. Furthermore, in this embodiment, an example of a ring used in an RTP apparatus as a semiconductor heat treatment member of the present invention, which holds a semiconductor wafer in order to perform oxide film deposition on the surface of the semiconductor wafer, will be described.

[0013] As shown in Figure 1, the semiconductor heat treatment member consists of a ring-shaped frame portion 2 and a wafer holding portion 3 formed on the lower inside of the frame portion 2 for holding a semiconductor wafer.

[0014] The frame portion 2 and the wafer holding portion 3 are made of a material in which an oxide film 5 with a thickness of approximately 0.3 to 3 μm is formed on the surface of a silicon carbide substrate 4. By providing the oxide film, compressive stress is applied in the four directions of the substrate, preventing damage due to thermal stress even if the substrate is thin. The substrate is preferably silicon carbide, or a porous material in which a silicon carbide coating is formed on the surface of a substrate other than silicon carbide. By using such a material for the semiconductor processing member, high strength and heat resistance can be obtained, and a temperature gradient is less likely to occur between the semiconductor processing member and the wafer even when heated by lamp.

[0015] The wafer holding portion 3 is provided with an inclination so as to be lower toward the frame portion 2, and the semiconductor wafer contacts the wafer holding portion 3 at the convex portion at the uppermost part of the inclination of the wafer holding portion 3. By adopting such a shape, the contact area between the semiconductor wafer and the wafer holding portion 3 becomes small, and when the semiconductor wafer is heated, the amount of heat diffusing to the outside through the wafer support surface is reduced, and the surface of the wafer can be heated uniformly. The inclination angle of the inclined surface is 1° or more and 20° or less, preferably 1° or more and 10° or less. When the inclination angle exceeds 20°, in the case of a large-diameter wafer, distortion may occur during heat treatment due to its own weight.

[0016] Furthermore, the R value of the convex portion of the wafer holding portion 3 is set to 0.1 mm or more and 0.3 mm or less, preferably 0.1 mm or more and 0.15 mm or less. By chamfering so that the R surface of the convex portion is within the above range, it is possible to prevent the wafer from being damaged when the semiconductor wafer is held, and to prevent the occurrence of slip dislocations due to heat treatment. The method of R chamfering is not particularly limited, but for example, cutting using an electroplating tool is used.

[0017] In the RTP apparatus, heating lamps are installed above or below the wafer. In order to heat the wafer surface uniformly, the lamp and the wafer are made parallel as much as possible. In the present invention, it is preferable that the geometric deviation (parallelism) conforming to JIS B0621:1984 between the semiconductor wafer holding surface of the wafer holding portion 3 and the lower surface of the frame portion 2 formed outside the wafer holding portion 3 is 0.05 mm or less, and more preferably 0.025 mm or more and 0 mm or less. Note that parallelism is one of the geometric deviations conforming to JIS B0621:1984 Postural deviation is referred to.

[0018] Also, the height difference between the top of the convex portion of the wafer holding portion (the uppermost part of the inclined surface) and the upper surface of the frame portion outside the wafer holding portion 3 is preferably 1 mm or less. When the height difference between the convex portion of the wafer holding portion 3 and the upper surface of the frame portion outside it is within the above range, an oxide film with a uniform thickness can be formed. Furthermore, if the wafer is slightly tilted when fitted into the semiconductor heat treatment component and heat treatment is performed with the wafer tilted, variations in the thickness of the formed oxide film will occur.

[0019] The thickness t of the wafer holding portion 3 (the combined thickness of the substrate 4 and the oxide film 5) is usually 1 mm or less, preferably 0.5 mm or less. By making the wafer holding portion 3 thin in this way, the heat capacity of the substrate 4 is reduced, and the thermal responsiveness is improved. On the other hand, in order to ensure strength, the thickness t is preferably 0.20 mm or more. If the thickness of the wafer holding portion 3 is greater than 1 mm, the heat capacity of the substrate 4 increases, and the thermal responsiveness decreases.

[0020] Furthermore, it is preferable that the outer wall of the frame portion 2 is vertical or has a nearly vertical incline. When the inner wall is nearly vertical, the gap between the side surface of the semiconductor wafer and the outer wall is small. When heat treatment is performed in this state, there is almost no heat diffusing from the side surface of the semiconductor wafer to the outer wall, and a decrease in temperature near the outer edge of the wafer can be prevented. In addition, the nearly vertical shape of the outer wall also contributes to the stability of holding the wafer after it has been fitted. The distance from the top surface of the frame portion 2 to the position where it contacts the wafer holding portion 3 is about 1 mm.

[0021] Next, the method for manufacturing the semiconductor processing member of the present invention will be described. First, silicon carbide is molded into a predetermined ring shape, and this molded body is sintered to obtain a silicon carbide substrate 4 having high thermal conductivity. Alternatively, silicon carbide is grown on the surface of a carbon substrate by the CVD method, and then the carbon substrate is removed to obtain a ring-shaped silicon carbide substrate 4 having high thermal conductivity.

[0022] Next, the surface of the ring-shaped substrate 4 is processed using a diamond grinding wheel so that the arithmetic mean roughness Ra is approximately 0.3 μm or less and the average element length RSm is approximately 40 μm or less. Furthermore, the substrate 4 is heat-treated at 1000 to 1300°C in an oxidizing atmosphere to form an oxide film 5 on the entire surface of the substrate 4, thereby obtaining a semiconductor processed member.

[0023] Figure 4 shows one embodiment of an RTP apparatus equipped with the semiconductor processing member of the present invention. As shown in Figure 4, the RTP apparatus 10 comprises a chamber (reaction tube) 20 equipped with an atmospheric gas inlet 20a and an atmospheric gas outlet 20b, a plurality of lamps 30 spaced apart above the chamber 20, and a substrate support section 40 for supporting a semiconductor wafer W in the reaction space 25 within the chamber 20. Although not shown, it also includes a rotating means for rotating the semiconductor wafer W around its central axis at a predetermined speed.

[0024] The substrate support section 40 comprises a semiconductor processing member of the present invention that supports the outer periphery of the semiconductor wafer W, and a stage 40a that supports the semiconductor processing member. The chamber 20 is made of, for example, quartz. The lamp 30 is made of, for example, a halogen lamp. The stage 40a is made of, for example, quartz. This RTP apparatus can uniformly heat and process the entire semiconductor wafer W with a temperature gradient of 10 to 300°C / second for heating or cooling.

[0025] Temperature control in the reaction space 25 of the RTP apparatus 10 is performed by measuring the average temperature of multiple points (e.g., 9 points) in the substrate surface in the radial direction of the substrate below the semiconductor processing member using multiple radiation thermometers embedded in the stage 40a of the substrate support section 40 (not shown in the figure). Based on the measured temperature, multiple halogen lamps 30 are controlled (individually ON-OFF control of each lamp, control of the light emission intensity, etc.).

[0026] The heat treatment method for semiconductor wafer W will be explained according to Figure 4. First, the semiconductor wafer W is fitted into the wafer holding portion 3 of the semiconductor processing member, and the ring-shaped semiconductor processing member is fixed to the upper part of the stage 40a, which is installed in the reaction space 25 under an oxidizing atmosphere, so that the upper surface of the semiconductor wafer W is approximately parallel to it.

[0027] Process gas is introduced through the atmospheric gas inlet 20a, and the gas in the reaction space 25 is exhausted through the atmospheric gas outlet 20b, forming a predetermined airflow on the semiconductor wafer W. Next, halogen lamps 30 arranged in an equal array are individually controlled by feedback from the surface temperature of the semiconductor wafer W to rapidly heat the semiconductor wafer W (for example, to about 1000°C in several tens of seconds) while controlling its surface temperature, thereby performing a heat treatment on the semiconductor wafer W. As a result, a desired oxide film is formed on the surface of the semiconductor wafer W.

[0028] As described above, the semiconductor processing member of this embodiment is made of a silicon carbide substrate, and the wafer holding portion that contacts the semiconductor wafer is convex, with the R value of the convex portion being 0.1 mm or more and 0.3 mm or less. The geometric deviation (parallelism) between the holding surface of the wafer holding portion and the lower surface of the outer edge of the wafer holding portion, in accordance with JIS B0621:1984, is 0.05 mm or less, and it is preferable that the top of the convex portion is within 5 mm from the outer circumference of the semiconductor wafer. This makes the heat transfer to the semiconductor wafer W held in the wafer holding portion 3 uniform, and when an oxide film is formed on the semiconductor wafer W by heat treatment, it is possible to reduce the variation in the thickness of the oxide film formed on the wafer surface and suppress the occurrence of slip dislocations.

[0029] In the above embodiment, a ring was used as an example to describe the semiconductor heat treatment member of the present invention. However, the present invention is not limited to this form and can be broadly applied to semiconductor heat treatment members having an oxide film coating on the surface of a silicon carbide substrate. [Examples]

[0030] The present invention will be described in detail below based on examples, but the present invention is not limited to the examples shown below. [Example of experiment] Multiple ring-shaped semiconductor processing substrates with different R values ​​for the convex portions of the wafer holding portion (wafer mounting surface) were fabricated (Examples 1-4, Comparative Examples 1-2). Semiconductor wafers held on these semiconductor processing substrates were heat-treated, and the variation in the thickness of the oxide film deposited on the semiconductor wafer surface and the occurrence of slip were investigated. In the manufacturing of the ring, the semiconductor wafer holding surface of the wafer holding portion and the frame portion Bottom surfaceThe orientation tolerance (parallelism) was adjusted to 0.01 to 0.08 mm in accordance with JIS B0621:1984. Next, the convex parts of the wafer holder were rounded using a diamond grinding wheel, and the R value was set to 0.02 to 0.7 mm.

[0031] In the preparation of the aforementioned semiconductor processing substrate, the surface of the substrate was ground using a diamond grinding wheel so that the arithmetic mean roughness Ra was 0.3 μm or less and the average element length RSm was 40 μm or less. The R value of the convex portion of the wafer holder was measured using an R gauge. Surface roughness Ra and the average element length RSm were measured using a non-contact roughness meter. Specifically, four points on the surface of the wafer holder were measured at 90-degree intervals, and the average value was calculated. The difference ΔRa of the arithmetic mean roughness Ra, which is an index in the height direction, was calculated by subtracting the minimum value Ra from the maximum value Ra of the four points. Next, the substrate was heat-treated in an oxidizing atmosphere at a temperature between 1000°C and 1300°C to obtain a semiconductor-treated substrate.

[0032] Next, the semiconductor wafer was held in the wafer holder (wafer mounting surface) and heat treatment was performed. The heat treatment conditions were a dry oxidation atmosphere at 1000°C to 1150°C for 60 seconds to 300 seconds. Table 1 shows the conditions and results for the examples and comparative examples. Slip evaluation was performed by measuring the wafer surface using X-ray topography and observing the presence or absence of slip. The evaluation criteria were as follows: ○ if the maximum slip length was less than 10 mm or no slip was observed, and × if a slip of 10 mm or more was observed. The film thickness variation was evaluated as the uniformity of the oxide film thickness formed on the semiconductor wafer. A variation of 0.1 μm or less was considered small, a variation between 0.1 μm and 0.15 μm was considered medium, and a variation greater than 0.15 μm was considered large. The presence or absence of slip on the semiconductor wafer was evaluated visually.

[0033] [Table 1]

[0034] Slip occurred when the R value of the convex portion was 0.08 mm. In Comparative Example 2, where the R value was 0.5 mm and the parallelism was 0.08 mm, the occurrence of slip was suppressed, but the variation in oxide film thickness increased. This is because while the occurrence of slip is suppressed when the corners of the convex portion are rounded and gentle, if the wafer holder 3 supports the wafer at an angle, the growth of a uniform oxide film across the entire wafer surface is impaired. Furthermore, the variation in oxide film thickness on the semiconductor wafer was uniform for parallelisms of 0 to 0.05 mm, but began to vary at a parallelism of 0.06 mm, and became significant at 0.08 mm. [Explanation of symbols]

[0035] 1. Semiconductor processing component 2 Frame section 3. Wafer holding section 4 Base material 5. Oxide film 10 RTP device 30 Halogen Lamps 20 chambers 20a Atmospheric gas inlet 20b Atmosphere gas outlet 25 Reaction space 40 Base material support part 40a Stage W Semiconductor wafer

Claims

1. A ring-shaped semiconductor processing member for holding a semiconductor wafer, comprising a silicon carbide substrate for an RTP apparatus that performs heat treatment on the surface of a semiconductor wafer, It comprises a ring-shaped frame and a wafer holding portion formed on the lower inner side of the frame for holding a semiconductor wafer. The wafer holding portion is provided with a slope that slopes downward toward the frame portion, and a convex shape that contacts the semiconductor wafer is provided at the uppermost part of the slope of the wafer holding portion. A semiconductor processing member characterized in that the R value of the convex shape is 0.1 mm or more and 0.3 mm or less.

2. The semiconductor processing member according to claim 1, characterized in that the geometric deviation (parallelism) between the surface of the semiconductor wafer when held in the wafer holding portion and the lower surface of the frame portion formed on the outside of the wafer holding portion is 0.05 mm or less, in accordance with JIS B0621:1984.

3. The semiconductor processing member according to claim 1, characterized in that the top of the convex portion of the wafer holding portion is located within a range of 5 mm from the outer circumference toward the center of the semiconductor wafer.

4. The semiconductor processing member according to claim 1, characterized in that the inclination angle of the inclination is 1° or more and 20° or less.

Images