High-resolution imager for night vision

Abstract

An image sensor has a set of pixels that form an image sensor for capturing an image. Two or more pixels in the set of pixels each have an architecture including a plurality of photodiodes that can be configured to form individual pixels. A control system can cooperate with the plurality of photodiodes to form the individual pixels. Each of the plurality of photodiodes can have a transfer gate electrically coupled to the photodiode. The common region can hold or transfer charge during at least an integration time or afterward. A readout gate electrically coupled to the common region and the sense node can supply charge from the common region through the readout gate to the sense node.

Description

Background Art

[0001] Incorporation by Reference This application claims the benefit under 35 U.S.C. § 120 of patent application Ser. No. 16 / 375,059, filed Apr. 4, 2019, entitled “Multiple Window, Multiple Mode Image Sensor,” and a portion thereof as a continuation application, which in turn claims the benefit under 35 U.S.C. § 120 of U.S. application Ser. No. 16 / 175,662, filed Oct. 30, 2018, entitled “Extended dynamic range imaging sensor and operating mode of the same,” and a portion thereof as a continuation application, which in turn claims the benefit as a continuation of U.S. patent application Ser. No. 15 / 238,063, filed Aug. 16, 2016, entitled “Extended dynamic range imaging sensor and operating mode of the same,” which in turn claims the benefit under 35 U.S.C. § 119 of U.S. provisional patent application Ser. No. 62 / 206,417, filed Aug. 18, 2015, entitled “Extended dynamic range (XDR) CMOS pixel and operating mode.” All of these applications mentioned in this specification are hereby incorporated by reference in their entirety to the same extent as if each individual document was specifically and individually indicated to be incorporated by reference.

[0002] Government Rights This invention was made with government support under other transaction agreement W909MY-18-9-0001 awarded by the U.S Army Contracting Command. The government has certain rights in the invention.

[0003] Background Art The field of the present invention generally relates to imaging devices. More specifically, one embodiment of the present disclosure relates to an imaging sensor using complementary metal-oxide-semiconductor ("CMOS") capable of a wide range of operations.

[0004] Imaging sensors typically contain an array of pixels that include photosensitive elements known as photodetectors, such as CMOS or charge-coupled device ("CCD") sensors. Generally, photodetectors accumulate charge in response to incident light during what is known as the integration period.

[0005] Previous quad-pixel imagers had a sense node that needed to be large enough for four photodiodes to sequentially transfer signal charge directly to the sense node through four transfer gates. As a result of this configuration, some sense nodes can have higher capacitance compared to non-quad-pixel imagers, due to the four sequential transfers and the transfer gates coupled to the sense node. In addition, the sense node must be large to receive charge directly from the photodiodes. Therefore, readout noise can be higher than in non-quad-pixel imagers.

[0006] A rolling shutter can capture a single frame of a still image or video, rather than capturing a snapshot of the entire scene at a single moment (like a global shutter), by rapidly scanning across multiple rows of pixels and then performing a readout operation.

[0007] summary

[0008] A machine, method, and system for a night vision multi-resolution imager is discussed. The image sensor has a set of pixels that constitute the image sensor for capturing an image. Two or more pixels in the set of pixels have an architecture that includes multiple photodiodes, each of which can be formed into individual pixels by a controller. The control system is configured to cooperate with the multiple photodiodes in the individual pixels, including a first photodiode and a second photodiode from the multiple photodiodes. Each photodiode may have a transfer gate electrically coupled to it. A common region can hold or transfer charge for at least an integration time or thereafter. A readout gate electrically coupled to the common region and a sense node can supply charge from the common region to the sense node through the readout gate. Thus, the common region can be made to act as a charge transfer channel for moving charge from the transfer gate output to the sense node. Each pixel may have at least one of the following for holding or transferring charge received from at least the first photodiode for at least an integration time or thereafter: 1) a common region electrically coupled to a sense node, 2) one or more readout gates electrically coupled to a sense node, and 3) any combination of both.

[0009] These and other features of the design provided herein can be better understood by referring to the drawings, descriptions and claims, all of which constitute the disclosure of this patent application. [Brief explanation of the drawing]

[0010] [Figure 1]This figure shows one embodiment of an exemplary pixel block diagram, which comprises a plurality of photodiodes that simultaneously collect charge which will be moved to a common region through an associated photodiode transfer gate during or after integration time, and a read gate electrically coupled to the common region for transferring the binned charge from the common region to a sense node through the read gate during a read operation.

[0011] [Figure 2] This diagram illustrates one embodiment of an exemplary pixel block diagram, in which multiple photodiodes simultaneously collect charge during integration time, which is then transferred to multiple common regions through each transfer gate, and the charge in each common region is then supplied through a read gate coupled to that common region to be binned together at a sense node.

[0012] [Figure 3] This figure shows one embodiment of a block diagram of an exemplary image sensor having a set of pixels that constitute an image sensor for capturing an image.

[0013] [Figure 4] This figure shows one embodiment of a control system and block diagram of a pixel array for an image sensor having a set of pixels that constitute an image sensor for capturing images, wherein each pixel has an architecture that includes multiple photodiodes forming individual pixels similar to the exemplary pixels shown in Figures 1-2. [Modes for carrying out the invention]

[0014] Detailed discussion As will be discussed in more detail later, a control system for pixels and their components can change how those components operate by sending control signals to alter the imaging mode of the component's operation. The architecture of pixels and their components supports an exemplary imaging mode of operation, which is a low-light mode using a rolling shutter process that incorporates several aspects of a global shutter process. The low-light mode using a rolling shutter process with pixels and their components allows the imager to trade resolution for sensitivity at low light levels while providing an extended dynamic range. The low-light mode using a rolling shutter process with pixels and their components improves dynamic range and sensitivity at low light levels by using simultaneous charge binning from multiple photodiodes in rolling shutter mode during integration time. Baseline imager pixels for night vision cameras with reduced readout noise at the lowest light levels and a longer detection range can use a low-light mode using a rolling shutter process with pixels and their components, where charge binning from multiple photodiodes occurs simultaneously during integration time. Here, too, other imaging modes of operation using this pixel architecture are possible and will be discussed later, but first we will discuss how the pixel architecture and control system operate their components using a rolling shutter process in low-light modes to simultaneously bin charges from multiple photodiodes during integration time.

[0015] Figure 1 shows one embodiment of an exemplary pixel block diagram, which comprises a plurality of photodiodes that simultaneously collect charge which will be moved to a common region through an associated photodiode transfer gate during or after integration time, and a read gate electrically coupled to the common region for transferring the binned charge from the common region to a sense node through the read gate during a read operation.

[0016] Each pixel in the image sensor may have an architecture that includes multiple photodiodes and other components that form an individual pixel 100.

[0017] Pixel 100 is a light "detector" for the image sensor. They can be individual photodiode readouts that pass through a common output stage. In addition, charges from multiple photodiodes can be readout through this common output stage. The controller can send control signals to the photodiodes so that, in the absence of binning, one photodiode can be in one pixel, but in the presence of binning, up to, for example, four photodiodes can bin their respective charges to form one pixel. Thus, in the absence of binning, one photodiode and other components that make up pixel 100 can constitute one pixel in the display. This is how a simple camera would view it. Also, an image sensor in an exemplary video camera may be described as a 24-megapixel image sensor. The measure of a pixel in an image sensor usually refers to the smallest displayable unit, and therefore this refers to the case without binning, in which case each "pixel" is operated to be one photodiode. However, as discussed in the various operating modes of more advanced cameras or video cameras, the controller can operate such, for example, 24 megapixels in various ways to form each pixel that detects light. If the controller binns all four photodiodes, then the four photodiodes and other components that make up pixel 100 can form a single pixel in the display. Therefore, essentially, four photodiodes become a single pixel in the display. There are photodiodes and pixels that are displayed. A common output stage does not always define a pixel. A pixel is how the photodiodes appear in the output to form an image. An imager sensor with N pixels (in this case, N are individual photodiodes) has the ability to charge bin those photodiodes, for example, in a 4:1 or 2:1 ratio. The group of binned pixels becomes the displayed pixel.

[0018] Here too, in the operating mode controlled by the controller, the multiple photodiodes constituting pixel 100 are read out through a common output stage. For example, in a quad pixel, all four photodiodes convert charge to voltage and send it to a single signal line through the common output stage. The photodiodes may or may not be binned, but they all pass through the common output stage. The common output stage can be thought of as consisting of a sense node SN, a source follower buffer SF, a row selection transistor SEL, and a reset transistor RST integrated with the sense node. All of these components are involved in reading out the signal.

[0019] Each individual pixel 100 may have multiple photodiodes, for example PD1 to PD4, each of which has associated transfer gates TG1 to TG4 electrically coupled to that photodiode. Multiple photodiodes PD1 to PD4 can form an individual pixel 100, collecting photons during integration time to generate charge, and then inducing that charge signal through its associated transfer gates (TG1 to TG4, respectively). Charges from two or more of the photodiodes PD1 to PD4 can essentially be binned simultaneously "without noise" in a common region SR during the phase of integration time.

[0020] Each of two or more pixels in a set of pixels has an architecture that includes multiple photodiodes which can be formed into individual pixels 100 by a controller. The control system is configured to work with the multiple photodiodes in individual pixels 100 to include at least a first photodiode PD1 and a second photodiode PD2 among the multiple photodiodes. The multiple photodiodes are read out through a common output stage which includes a sense node SN. Pixel 100 may further include at least one of the following: 1) a common region SR electrically coupled to the sense node SN for holding or transferring charge received from at least one photodiode for at least an integration time or thereafter; 2) one or more read gates TX electrically coupled to the sense node SN for holding or transferring charge received from at least one photodiode for at least an integration time or thereafter; and 3) any combination of both 1) and 2) for holding or transferring charge received from at least one photodiode for at least an integration time or thereafter.

[0021] This common region SR is electrically coupled to each transfer gate TG1-TG4. This common region SR is also coupled to the sense node SN via the read gate TX. One or more common regions SR may be implemented, each configured to either i) temporarily transfer charge over a single clock cycle (see, e.g., Figure 2), or ii) hold charge over a long duration, such as being able to store charge over many clock cycles (see, e.g., Figure 1). The common region SR generally bins / sums charges from multiple photodiodes PD1-PD4 simultaneously during integration time when in low-light mode using a rolling shutter process. The read gate TX is electrically coupled to the common region SR and the sense node SN to supply charge from the common region SR to the sense node SN via the read gate TX during read operations.

[0022] The common region SR is used to bin charge from two or more photodiodes PD1-PD4 during integration time and to transfer charge during readout operation. In the first case, if the charge passes through the common region SR, the final binning occurs at the sense node SN. When operated in this manner, some binning occurs in the common region SR. In the second case, if the charge is stored in the common region SR, all binning occurs in the common region SR. Note that in other operating modes, the common region SR is also used for single photodiode readout for high resolution. In this case, there is no binning, but the signal follows the same path as when binning multiple diodes. Single pixel readout differs from global shutter. Charge is held in the common region SR for a fraction of the row time. In global shutter operation, charge is held in the common region SR for at least the total row time, but more likely for multiple row times.

[0023] The sense node SN is used to read out the charge during the read operation. The sense node SN can achieve higher conversion gain and lower read noise by converting the charge into a voltage signal when the sense node SN has a lower capacitance. The size of the sense node SN can be set to be sufficient in this example to accommodate connections to only one read gate TX for all four transfer gates TG1-TG4, in order to lower the noise threshold required during the read operation. Note that to complete the read operation, a sense node reset occurs when the reset gate RST is turned on after the read operation.

[0024] During the read operation, the charge in the sense node SN is read using the source follower transistor SF and the row selection transistor SEL to generate a voltage signal on the column bus (which has a current source load). The group of read transistors that cooperate for the read operation are denoted as read gate (TX), source follower (SF), row selection (SEL), and reset (RST).

[0025] The first step of the read operation can be to transfer the charge held in the common region SR to the sense node SN, which is split into two separate steps (e.g., 1) the transfer gates TG1 - TG4 are switched off, and then 2) the read gate TX is turned on).

[0026] Thus, the charge is binned in a potential well, preferably formed by an embedded channel well. The charge is transferred from the plurality of photodiodes to a common region SR having its own potential well. In the common region SR, two or more photodiodes can be totaled / binned within the well. Next, a second transfer from the potential well to the sense node SN generates a voltage output. This low light mode enables a smaller sense node, so that the voltage / electron charge conversion is higher, and thus the read noise is lower.

[0027] In an exemplary low-light operation, the control system sends control signals to at least the two upper photodiodes PD1-PD2 and their associated transfer gates TG1-TG2 to "switch on" their transfer gates in order to simultaneously supply their charges to the common region SR during integration time. In the common region SR, the charges from at least these two photodiodes PD1-PD2 are binned during integration time. Furthermore, for the lowest noise and most extended range imaging operation mode, control signals are sent to all four photodiodes PD1-PD4 and their associated transfer gates TG1-TG4 to simultaneously "switch on" to transfer their respective charges to the common region SR during integration time, so that the common region SR simultaneously bins the charges from all four photodiodes PD1-PD4. Once all four photodiodes have simultaneously binned their respective charges in the common region, a single readout operation then occurs for the sense node SN to read out its binned charges. In contrast, typically, noise associated with four sequential readout operations is required to obtain the total charge from all four photodiodes PD1-PD4. Therefore, the noise is reduced by three readout operations compared to some other quad-pixel designs. In addition, the common region holds (and potentially stores) the charge from multiple photodiodes PD1-PD4, and then transfers the binned / summed charge to the sense node SN, in order to keep the size dimensions of the sense node SN small and to keep the parasitic transfer gate capacitance that may exist to reduce readout noise small. By transferring charge in the common region SR during readout operations, the sense node SN and its readout gate TX can be made smaller and have less capacitance. Instead of four transfer gates TG1-TG4, each adding parasitic capacitance to the sense node SN, only one readout gate TX (two readout gates in some architectures) is coupled to the area that makes up the sense node SN.Lower capacitance allows for improved noise levels during readout operations, thereby enabling detection in low-light conditions (e.g., moonless nights with only starlight) and lowering the noise threshold level at which usable signals become undetectable.

[0028] Structurally, each transfer gate TG1-TG4 has its own channel formed beneath each of the transfer gates TG1-TG4 to supply charge to a common region. At least a portion of the well forming the common region SR is located below each transfer gate TX when two or more are implemented. The potential well is preferably formed by an embedded channel well. Each photodiode's transfer gate TG1-TG4, such as a transistor or metal oxide device, controls the integration time of its particular photodiode by sending control signals to it from a control system, thereby controlling how long its associated photodiode, e.g., PD1-PD4, collects photons before its associated transfer gates TG1-TG4 transfer the accumulated charge from the photodiode to the common region SR.

[0029] It should be noted that in one embodiment, the common region SR is constructed with wells built to store charge over many cycles. The common region may be wells that store charge potentials, which may be formed by virtual gates or polygates. One of the challenges associated with the pixel architecture in Figure 1 is that, since the charge is stored in the common region, its area must be large enough to hold the desired maximum charge. This reduces the space available for photodiodes PD1-PD4, thus lowering quantum efficiency. This approach may not seem logical without the idea that this architecture may result in lower noise. Also, if the common region SR is too large, the transfer of charge to the sense node SN may take longer than required / allowed in its operating mode. Therefore, in one embodiment, the charge capacity of the common region SR can be set to only the minimum required to support actually storing the expected amount of charge, and to allow the required charge transfer time to the sense node SN.

[0030] The common region SR can have charge channels. The common region SR can have charge channels from the photodiode outputs of each of the photodiodes PD1-PD4, and these charge channels pass below the transfer gates TG1-TG4 associated with that photodiode, through the well in the common region SR, and to the read gate TX. Note that the problem of the sense node SN becoming too large can be solved by adding these charge channels from the photodiode outputs, passing below the transfer gates TG, through the well, and to the read gate TX. This allows the sense node SN to be separated from the four photodiodes PD1-PD4, but still within the pixel. The addition of channels from the photodiode outputs, through the well of the sense node SN, and to the read gate eliminates the need for the well to be large enough to simultaneously handle direct charge transfers from all four photodiodes PD1-PD4. Again, this technique can reduce noise to or near the noise threshold level of an imager that does not use a quad-pixel architecture.

[0031] A common region SR between the transfer gates TG1-TG4 and the sense node may be a charge binning region with a readout gate for holding / storing its charge in the common region SR. The common region SR is where the charge from the four photodiodes PD1-PD4 is binned and then transferred to the sense node SN through a single readout gate TX1. This charge binning region can hold / storage charge for one frame time to enable global shutter operation, or it can hold charge for less than one row time for rolling shutter operation.

[0032] An image sensor containing pixels has a control system that can operate in various imaging modes, including rolling shutter and global shutter. The control system can send control signals to operate the image sensor in a mixed global shutter and rolling shutter mode. In this rolling shutter mode, which has several global shutter configurations, the control system initiates integration time by sending a control signal to collect charge simultaneously from multiple photodiodes, and another signal to transfer the charge accumulated in the multiple photodiodes to a common region SR through associated transfer gates TG coupled to the photodiodes. During integration time, the common region SR sums / binns the charge supplied by two or more photodiodes PD1-PD4. During readout operation, the control system sends control signals to transfer the binned charge in the common region SR to a sense node SN through a readout gate TX. In an image sensor with a rolling shutter, instead of reading all rows simultaneously, rows of photodiodes in the image sensor are read row by row.

[0033] The advantage of the pixel architecture in Figure 1 is that the 4X binned pixels can operate in either a global shutter mode of simultaneous binning of all photodiodes, where all rows are read simultaneously, or a rolling shutter mode, which preferably involves a configuration of simultaneous binning of multiple photodiodes, but on a row-by-row basis, thereby reducing geometric distortion in the displayed image with respect to moving objects.

[0034] A quad-pixel architecture may be a CMOS pixel in which there are four photodiodes PD1 to PD4 within 100 pixels on the substrate.

[0035] Figure 2 shows one embodiment of an exemplary pixel block diagram, where multiple photodiodes simultaneously collect charge during integration time, which is then transferred to multiple common regions through each transfer gate, and the charge in each common region is then supplied through a read gate coupled to that common region to be binned together at the sense node. Note that, as illustrated, the common region is actually part of each read gate TX1-TX2. Thus, one or more read gates are configured to function as a common region, including at least a first read gate TX1 and a second read gate TX2. The common region (SR in Figure 1) is thus divided into a first common region (TX1 shown in Figure 2) for transferring charge from the first photodiode PD1 and the second photodiode PD2 during integration time, and a second common region (TX2 shown in Figure 2) for transferring charge from the third photodiode PD3 and the fourth photodiode PD4 during integration time. The read gates TX1-TX2 here act as conductors leading the charge to the sense node. They can only transfer electric charge, but they cannot store it.

[0036] The pixel architecture in Figure 2 has two read gates, TX1 and TX2. Each read gate TX1 or TX2 is coupled to two transfer gates TG1-TG2 or TG3-TG4, and then to the sense node SN. Unlike the common region SR in Figure 2, which can store charge until it is slowly and reliably transferred to the sense node SN, some of the transfer gates TG1-TG4 here only temporarily hold charge. The two read gates TX1-TX2 act as charge transfer gates to the sense node SN. The charge from the four photodiodes PD1-PD4 is actually binned within the sense node. Thus, this architecture allows charge binning of two, three, or all four photodiodes to occur simultaneously, but in the sense node SN, not in the common region. Note that the common region can act as a channel from the associated TG gate outputs TG1-TG4 directly to the sense node SN.

[0037] The readout gates TX1 and TX2 can be implemented by using polygates. The small size of the readout gates TX1 and TX2 also allows for larger photodiodes PD1-PD4 within a given quad area, resulting in higher quantum efficiency. The area of ​​the sense node SN is still much smaller than in previous designs. Only two small readout gates TX, rather than four transfer gates TG1-TG4, each adding parasitic capacitance to the sense node SN, are coupled to the area of ​​the sense node SN. Overlapping capacitance is further reduced by the small size of the sense node SN.

[0038] In Figure 2, in one embodiment, the architecture does not require a read gate TX. Instead, the architecture may have a common region coupled to a sense node and one or more transfer gates (TG). The common region may be configured to transfer and move charge to the sense node during integration time. The common region does not need to hold the charge, but simply needs to transfer it.

[0039] Referring to Figure 1, an exemplary pixel having multiple photodiodes simultaneously collects charges transferred to multiple common regions through each transfer gate for summing / binning the charges supplied by two or more photodiodes during integration time, and then during readout operation, supplies the binned charge from each common region to the sense node through the readout gate.

[0040] Pixel 100 has four transfer gates TG1-TG4, each located at the edge of its associated photodiodes PD1-PD4. The central channel between the two upper transfer gates TG1-TG2 acts as a common region SR1 for storing the charge of the two photodiodes PD1-PD2, and also bins the charge from those two photodiodes PD1-PD2. Similarly, the central channel between the two upper transfer gates TG3-TG4 acts as a common region SR2 for storing the charge of the two photodiodes PD3-PD4, and also bins the charge from those two photodiodes PD3-PD4. All four transfer gates TG1-TG4 are electrically coupled to the read gate TX through their respective channels. The read gate TX is coupled to the sense node SN. The sense node SN also has a gain capacitor GC electrically coupled to it.

[0041] In one embodiment, the first storage area SR1 is a well formed by a long, deep central channel between the two upper transfer gates TG1 and TG2. The second storage area SR2 is a well formed by a long, deep central channel between the two lower transfer gates TG3 and TG4.

[0042] During the read operation, the read gate TX1 transfers charges from the first common region SR1 and the second common region SR2 to the sense node SN via the read gate TX1.

[0043] Figure 3 shows one embodiment of an exemplary image sensor block diagram having a set of pixels that constitute an image sensor for capturing an image. The image sensor has an array 500 comprising columns and rows of pixels. In this example, the image sensor is configured to capture an image and has five rows and columns of pixels (rows 1-5), including an exemplary pixel 100.

[0044] Figure 4 shows one embodiment of a block diagram of a control system and pixel array for an image sensor having a set of pixels constituting an image sensor for capturing an image, each architecture including photodiodes similar to the exemplary pixels shown in Figures 1-2. The control system may include components such as a controller having two or more decoders implemented in an analog / ADC circuit, column and row control circuits for each transfer gate of the photodiodes in the quad pixel array of 500 pixels, MIM gain capacitors, read gates, reset switches, and row selection switches, column logic drivers, and timing circuits.

[0045] The control system may use two or more decoders. The two or more decoders, in cooperation with a timer, direct control signals to control i) the frame rate, ii) the integration time of the multiple photodiodes, and iii) the binning of the multiple photodiodes per pixel, in order to enable multiple pixels of the array of 500 pixels to operate in various imaging modes. Here again, the control system is configured to work with the multiple photodiodes to configure multiple photodiodes to form detectors for individual pixels, and / or to configure a single photodiode to form detectors for individual pixels.

[0046] In night vision / low light mode, the control system may be configured such that multiple photodiodes simultaneously collect charge during integration time, and an associated transfer gate sends a first control signal to switch off. Upon receiving the second control signal, the associated transfer gate then simultaneously transfers the charge accumulated in at least two of the multiple photodiodes to one or more common regions through its own associated transfer gates coupled to those photodiodes to hold the charge for a subsequent readout operation. In many architectures, one or more common regions bin the charge supplied by two or more photodiodes during integration time. The readout gate is also switched off to hold the charge in the common region until the readout operation occurs. The control system then transfers the binned charge from the common region to the sense node through the readout gate by sending a third control signal during the readout operation, which switches on the readout gate. The transfer gate may also receive a signal to prevent charge leakage back to the photodiodes. When operating in rolling shutter mode, the control system is configured to perform the above sequence row by row of photodiodes, with all rows completed within a one-hour frame of a single image frame. The control system may terminate the read operation by sending control signals to the remaining set of read transistors (discussed earlier) and the gain capacitor.

[0047] The control system is configured to analyze the scene being captured within the image. Based on imaging conditions of the scene content, such as different light intensities and required frame rates, within the scene being captured by multiple image pixels, the control system selects different imaging modes for two or more pixels in a row. The controller, Based on the imaging conditions captured within pixel 100, select different imaging modes for at least two pixels. By using the collected data signals, which reflect the accumulated charge obtained from multiple pixels through readout and other imaging conditions, to assemble the image, It is possible to operate the imaging sensor.

[0048] All of the pixel architectures in Figures 1 and 2 can include an additional MIM capacitor GC that allows for switchable capacitance to the sense node SN to change the capacitance and the resulting gain.

[0049] The control system may be configured to transfer charge to a common area, store the charge there for longer than a row time, and then read it out by a read gate TX. The control system may also be configured to transfer charge to a common area to binn the charge and store only a fraction of a row of charge there. The purposes are entirely different.

[0050] The image sensor has wiring / conductor paths for control signals to enable various operating modes using exemplary quad-pixel / electrical circuits. The controller may control the timing of control signals to each pixel in each row of the imager to realize the imaging modes of the conceivable operation, which include:

[0051] 1.) Sequential, unbinned photodiode readout of photodiodes PD1-PD4. In some cases, the integration time differs for each photodiode due to the need for higher resolution. Each transfer gate associated with its own photodiode is sequentially switched on to transfer the charge from that photodiode to a common region through its associated transfer gate. In the highest resolution readout mode, the control system, during the integration time, signals to sequentially collect charge from a single photodiode and transfers that charge to the potential well in the common region using its associated transfer gate. The charge in the common region is then transferred to a sense node using a transfer gate. Alternatively, the charge is transferred to the sense node simply by using a transfer gate. Again, the control system sequentially repeats this process for the other three photodiodes.

[0052] 2.) In the highest sensitivity mode, all four photodiodes sequentially binn their respective charges in a single common region without noise, forming a superpixel using a 4X signal. Then, during the readout operation, the binned charges stored in the storage region are transferred to the sense node using a readout gate.

[0053] 3.) Binned photodiode readout of multiple photodiodes, either simultaneously or each in one or more storage regions. For example, 1) all photodiodes, e.g., PD1-PD4, are binned into one common region simultaneously, or 2) each pair, e.g., PD1-PD2, then e.g., PD3-PD4, binn their respective accumulated charges from their respective integration times together in their own common region during the integration time. If not all charges from the photodiodes are binned into one common storage region during the integration time, the binned photodiode readout mode can allow multiple photodiodes, each with their respective accumulated charges from their respective integration times, to be binned together at the sense node. The controller can bin any combination of, for example, two, three, or four photodiodes, e.g., PD1-PD4, to collect and read out charge / signal levels. The controller and timer work together to switch on the transfer gates of the binned photodiodes and switch off the readout gates of the common regions, all simultaneously via pulses. Binning of charges from multiple photodiodes in the common region and then at the sense node increases effective exposure and sensitivity, resulting in better resolution.

[0054] 4.) A high frame rate operating imaging mode for motion adaptive signal integration (MASI), and / or a short integration time with high gain for motion blur reduction. A high frame rate for motion adaptive signal integration (MASI) can be an operating imaging mode that uses photodiode readout from pixel 100 having multiple photodiodes. A high frame rate MASI algorithm achieves a high dynamic range by combining high frame rate images of different exposures. The high frame rate mode can also implement binning, non-binning, and an extended dynamic range in a given pixel 100. It should be noted that a high frame rate can also exclude a certain number of rows or even individual pixels from being read out in order to match the data throughput of the image sensor. Thus, the first decoder can select a subset of rows, such as 60 rows, and have them read out their respective charges from the total number of rows constituting the image sensor, such as 80 rows.

[0055] 4) Extended dynamic range from low-light conditions to sunny conditions. An imaging mode for extended dynamic range operation may be an imaging mode for operation that uses readouts from multiple photodiodes from pixel 100. Dynamic range can be a measure of how well and accurately the sensor can measure the signal up to the full well capacitance at low light intensity. Extended dynamic range may be achieved by adjusting the effective integration time of the four photodiodes.

[0056] In one embodiment, the quad-pixel design discussed herein can result in a 2x (or more) reduction in readout noise compared to several other conventional designs. In one embodiment, the system consists of a quad design in which four 8x8um pixels are either read out individually or their charges are combined / binned to form a 16x16um superpixel. The 16x16um pixel collects more than four times the signal for the lowest light levels. This design enables improved imaging with starlight illumination alone while reducing readout noise by a factor of two.

[0057] Although the present invention has been described in terms of one or more embodiments, it should be understood that many equivalent forms, alternative forms, modifications, and changes other than those expressly described are possible and fall within the scope of the invention.

Claims

1. It is a device, The image sensor comprises a set of pixels that constitute an image sensor for capturing an image, Each of the set of pixels has an architecture comprising multiple photodiodes configurable to form individual pixels, and the multiple photodiodes are read out through a common output stage including a sense node. The control system is configured to cooperate with the plurality of photodiodes to configure the plurality of photodiodes to form the individual pixels, wherein the plurality of photodiodes includes a first photodiode and a second photodiode. The first photodiode and the second photodiode each have a transfer gate electrically coupled to the photodiode, and the apparatus further comprises: A device comprising a common region electrically coupled to the sense node for binning the charge received from at least the first photodiode for at least the integration time, and one or more readout gates electrically coupled to the sense node and directly coupled to the common region for binning the charge received from at least the first photodiode and the second photodiode for at least the integration time.

2. The apparatus according to claim 1, wherein the one or more read gates include at least a first read gate and a second read gate and are configured to function as a common region, the common region being divided into a first common region for transferring the charge from the first photodiode and the second photodiode during the integration time, and a second common region for transferring the charge from the third photodiode and the fourth photodiode during the integration time.

3. The apparatus according to claim 1, wherein the plurality of photodiodes are configured to collect charge during the integration time, the common region is configured to hold the charge from the first photodiode and the second photodiode, and the read gate is configured to supply the held charge from the common region to the sense node through the read gate during a read operation.

4. The apparatus according to claim 3, wherein the first and second photodiodes are configured to simultaneously supply their respective charges to the common region during the integration time so that the common region may bin the charges from the first and second photodiodes for at least the duration of the integration time or thereafter, the control system is configured to send a control signal to operate the image sensor in a rolling shutter operation mode so that during the integration time the plurality of photodiodes simultaneously collect charges, the charges are moved to the common region through the transfer gates of the associated photodiodes and binned, the readout gate is configured to then supply the charges from the common region to the sense node through the readout gate during the readout operation, and the image sensor in the rolling shutter operation mode is configured to read out rows of photodiodes in the image sensor, row by row, instead of all the photodiodes transferring their respective signals simultaneously.

5. The apparatus according to claim 3, wherein the plurality of photodiodes in the individual pixels include a third photodiode and a fourth photodiode, and the common region is configured to store the charge from the first photodiode, the second photodiode, the third photodiode, and the fourth photodiode during the integration time.

6. The common region is configured to hold or transfer charge for at least the duration of the integration time or thereafter. The apparatus according to claim 1, wherein the one or more read gates electrically coupled to the common region and the sense node are configured to supply charge from the common region to the sense node through the read gates.

7. The apparatus according to claim 1, wherein the control system is configured to send a first control signal to the plurality of photodiodes to simultaneously collect charge during an integration time, and to send a second control signal to the associated transfer gates to simultaneously move the charge accumulated in at least the first and second photodiodes to the common region through their respective associated transfer gates coupled to the photodiodes, in order to bin the charge supplied by the first and second photodiodes, at least during or after the integration time, the charge supplied by the first and second photodiodes, and the control system is further configured to send a third control signal for a read operation to transfer the binned charge in the common region to the sense node through the read gate, and when operating in rolling shutter mode, the control system is configured to perform the above sequence of the three control signals on a row-by-row basis of the photodiodes, so that all rows are performed within a one-hour frame of one image frame.

8. In order to lower the noise threshold required during a read operation, the area of ​​the sense node is set small enough to be directly coupled to the read gate instead of all the associated transfer gates, The apparatus according to claim 1, wherein the control system is configured to reconfigure the plurality of photodiodes in cooperation with each of the plurality of photodiodes so that each photodiode forms its own individual pixel.

9. The apparatus according to claim 1, wherein the common region has a charge channel from the photodiode output of the first photodiode and the photodiode output of the second photodiode, and the charge channel reaches the read gate through the well of the common region via the associated transfer gate electrically coupled to the photodiode.

10. A method for an image sensor having a control system that implements a rolling shutter, To bin the charge supplied by two or more photodiodes during integration time, the charge from multiple photodiodes forming a pixel is simultaneously moved to a common region through associated transfer gates, A method comprising: then transmitting control signals to one or more read gates; and during a read operation, supplying the binned charge from the common region to a sense node through the read gates via the one or more read gates directly coupled to the common region.

11. During the aforementioned integration time, charge is collected using the plurality of photodiodes, During the integration time, the charges from the two or more photodiodes are stored in the common region and binned. Next, during the read operation, the binned charge from the common region is supplied to the sense node through the read gate, The method according to claim 10, further comprising:

12. Sending a control signal to operate the image sensor in rolling shutter mode, thereby during the integration time, the plurality of photodiodes simultaneously collect charge, the charge is moved to the common region and binned through associated photodiode transfer gates, the readout gate then supplies the charge from the common region to the sense node through the readout gate during the readout operation, and the image sensor in rolling shutter mode reads out the photodiodes row by row instead of all rows being read out simultaneously. The method according to claim 11, further comprising reading out rows of photodiodes.

13. The plurality of photodiodes within each of the individual pixels include at least four photodiodes, The method according to claim 10, comprising moving the charge from all of the plurality of photodiodes to the common region to store the charge during the integration time.

14. The further includes holding or transferring the charge to the common region at least during or after the integration time, The method according to claim 10, wherein the one or more read gates are electrically coupled to the common region and the sense node, and the read gates supply charge from the common region to the sense node through the read gates.

15. The method according to claim 10, wherein the one or more read gates include at least a first read gate and a second read gate and are configured to function as a common region, the common region being divided into a first common region for transferring the charge from a first photodiode and a second photodiode during the integration time, and a second common region for transferring the charge from a third photodiode and a fourth photodiode during the integration time.

16. Sending a first control signal to the plurality of photodiodes and their respective associated transfer gates so that charges are simultaneously collected during the integration time, Next, in order to bin the charge supplied by the first and second photodiodes among the plurality of photodiodes, a second control signal is sent to the associated transfer gates so as to simultaneously move the charge accumulated in at least the first and second photodiodes to the common region through their respective associated transfer gates coupled to the photodiodes, at least during the integration time or thereafter. The further includes sending a third control signal for the read operation, which transfers the binned charge in the common region to the sense node through the read gate, The method according to claim 10, wherein the control system, when operating in rolling shutter mode, is configured to perform the sequence of the three control signals on a row-by-row basis of the photodiodes, so that all rows are performed within a one-hour frame of one image frame.

17. To lower the noise threshold required during the read operation, the area of ​​the sense node is set small enough to be directly coupled to the read gate instead of all the associated transfer gates. The method according to claim 10, wherein the control system is configured to reconfigure the plurality of photodiodes in cooperation with each of the plurality of photodiodes so that each photodiode forms its own individual pixel.

18. The method according to claim 10, wherein the common region has a charge channel from a photodiode output from a first photodiode and a photodiode output from a second photodiode among the plurality of photodiodes, and the charge channel reaches the read gate through a well in the common region, below the transfer gate electrically coupled to the photodiode.

19. A method for an image sensor having a set of pixels that constitute an image sensor for capturing an image, Creating two or more pixels in the set of pixels such that each has an architecture comprising multiple photodiodes configurable to form individual pixels, The control system is configured to cooperate with the plurality of photodiodes to form the individual pixels, wherein the first photodiode and the second photodiode among the plurality of photodiodes each have a transfer gate electrically coupled to the photodiode. A method comprising: creating a common region electrically coupled to a sense node and directly coupled to one or more read gates for binning the charge received from at least the first photodiode for at least the integration time; and creating one or more read gates electrically coupled to the sense node for binning the charge received from at least the first photodiode and the second photodiode for at least the integration time.

20. The method according to claim 19, wherein the plurality of photodiodes in the individual pixels include a third photodiode and a fourth photodiode, and the common region is configured to hold the charge from the first photodiode, the second photodiode, the third photodiode, and the fourth photodiode during the integration time.

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