Semiconductor equipment

Abstract

To provide a semiconductor device capable of suppressing degradation of device characteristics.SOLUTION: A semiconductor device according to an embodiment includes a first electrode, a semiconductor layer, a second electrode, an insulating first resin, and an insulating second resin. The semiconductor layer is provided on the first electrode. The semiconductor layer includes a first region, and a second region provided around the first region along a first face perpendicular to a first direction from the first electrode toward the semiconductor layer. The second electrode includes a first portion, and a second portion that is thinner than the first portion and provided in the first direction around the first portion along the first face. The first portion and the second portion contain copper or aluminum. The second electrode is provided on the first region. The first resin is provided on the second region and covers an outer periphery of the first portion, and the second portion. The second resin is provided on the second electrode and the first resin and contains a resin material different from that of the first resin.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] Semiconductor devices such as diodes and metal oxide semiconductor field effect transistors (MOSFETs) are used for applications such as power conversion. For semiconductor devices, there is a demand for improved reliability, for example. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2013-239607 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] Embodiments of the present invention provide a semiconductor device capable of suppressing the degradation of device characteristics. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment comprises a first electrode, a semiconductor layer, a second electrode, an insulating first resin, and an insulating second resin. The semiconductor layer is provided on the first electrode. The semiconductor layer includes a first region and a second region provided around the first region along a first plane perpendicular to a first direction from the first electrode toward the semiconductor layer. The second electrode includes a first portion and a second portion that is thinner than the first portion and provided around the first portion along the first plane. The first portion and the second portion contain copper or aluminum. The second electrode is provided on the first region. The first resin is provided on the second region and covers the outer periphery of the first portion and the second portion. The second resin is provided on the second electrode and the first resin and contains a resin material different from the first resin. [Brief explanation of the drawing]

[0006] [Figure 1] This is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 2] This is a plan view showing a semiconductor device according to the first embodiment. [Figure 3] This is a cross-sectional view showing a part of a semiconductor device related to a reference example. [Figure 4] This is a cross-sectional view showing a part of a semiconductor device related to a reference example. [Figure 5] This is a cross-sectional view showing a part of a semiconductor device related to a reference example. [Figure 6] This is a cross-sectional view showing a part of the semiconductor device according to the first embodiment. [Figure 7] This is a cross-sectional view showing a part of a semiconductor device according to a modified example of the first embodiment. [Figure 8] This is a cross-sectional view showing a part of a semiconductor device according to a modified example of the first embodiment. [Figure 9] This is a cross-sectional view showing a part of a semiconductor device according to a modified example of the first embodiment. [Figure 10] This is a cross-sectional view showing a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as the actual ones. Even when representing the same part, there are cases where the dimensions and ratios are represented differently in the drawings. In the specification of the present application and each figure, the same reference numerals are given to elements similar to those already described, and the detailed description will be omitted as appropriate. In the following description and drawings, n + 、n - And the notations of p represent the relative levels of the respective impurity concentrations. That is, the notation with “+” has a relatively higher impurity concentration than the notation without either “+” or “-”, and the notation with “-” indicates that the impurity concentration is relatively lower than the notation without any of them. These notations represent the relative levels of the net impurity concentration after the p-type and n-type impurities in each region compensate for each other when both p-type and n-type impurities are included in each region. For each embodiment described below, each embodiment may be implemented by inverting the p-type and n-type of each semiconductor region.

[0008] FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment. FIG. 2 is a plan view showing the semiconductor device according to the first embodiment. FIG. 1 is a cross-sectional view taken along the line I-I of FIG. 2. As shown in FIGS. 1 and 2, the semiconductor device 100 according to the first embodiment includes a lower electrode 1 (first electrode), an upper electrode 2 (second electrode), a metal layer 5, a semiconductor layer 10, an insulating layer 20, a first resin 21, a second resin 22, and a wiring 23. The semiconductor device 100 is a Schottky barrier diode. In FIG. 1, the metal layer 5 is omitted. In FIG. 2, each semiconductor region of the semiconductor layer 10 and the insulating layer 20 are omitted, and the first resin 21 is shown by a dashed line. Also, the second resin 22 is shown transparently.

[0009] In the description of the embodiments, an XYZ orthogonal coordinate system is used. The direction from the lower electrode 1 toward the semiconductor layer 10 is defined as the Z direction (the first direction). Two directions perpendicular to the Z direction and orthogonal to each other are defined as the X direction (the second direction) and the Y direction (the third direction). Also, for the sake of description, the direction from the lower electrode 1 toward the semiconductor layer 10 is referred to as "upward", and the opposite direction is referred to as "downward". These directions are independent of the direction of gravity and are based on the relative positional relationship between the lower electrode 1 and the semiconductor layer 10.

[0010] As shown in FIG. 1, the semiconductor layer 10 is provided above the lower electrode 1. The semiconductor layer 10 includes a first region 10a and a second region 10b. The second region 10b is provided around the first region 10a along the X - Y plane (the first plane). The first region 10a includes the central portion of the semiconductor layer 10 in the X - Y plane. The area of the first region 10a in the X - Y plane is larger than the area of the second region 10b in the X - Y plane.

[0011] The semiconductor layer 10 is + composed of an n - -type semiconductor region 11, an n + -type semiconductor region 12, a p - type semiconductor region 13, a p - type semiconductor region 14, and an n - type semiconductor region 15. The n - -type semiconductor regions 11 and n + -type semiconductor region 12 are provided in the first region 10a and the second region 10b. The n - -type semiconductor region 11 is electrically connected to the lower electrode 1. The n + -type semiconductor region 12 is located above the n - -type semiconductor region 11. The n - type impurity concentration of the n + -type semiconductor region 12 is lower than the n - type impurity concentration of the n - -type semiconductor region 11. The p - type semiconductor region 13 is selectively provided above the n - -type semiconductor region 12 in the second region 10b. The p - type impurity concentration of the p - type semiconductor region 13 is higher than the n - type impurity concentration of the n

[0012] The p-type semiconductor region 14 is provided around a plurality of p-type semiconductor regions 13 along the XY plane and is located at the boundary between the first region 10a and the second region 10b. The p-type semiconductor region 14 may be separate from the p-type semiconductor regions 13 or may be in contact with any of the p-type semiconductor regions 13. The p-type impurity concentration in the p-type semiconductor region 14 decreases towards the radial direction. For example, the p-type semiconductor region 14 includes an inner circumferential portion 14a, an intermediate portion 14b, and an outer circumferential portion 14c. The inner circumferential portion 14a is located in the first region 10a. The outer circumferential portion 14c is located in the second region 10b. The intermediate portion 14b is located between the inner circumferential portion 14a and the outer circumferential portion 14c. The p-type impurity concentration in the intermediate portion 14b is lower than that of the inner circumferential portion 14a and higher than that of the outer circumferential portion 14c.

[0013] The n-type semiconductor region 15 is located around the p-type semiconductor region 14 along the XY plane and is situated near the outer periphery of the upper surface of the semiconductor layer 10. The n-type impurity concentration in the n-type semiconductor region 15 is n - It is higher than the n-type impurity concentration in the semiconductor region 12.

[0014] The upper electrode 2 is provided on the first region 10a. The upper electrode 2 includes a first portion 2a and a second portion 2b. The second portion 2b is provided around the first portion 2a along the XY plane. The thickness of the second portion 2b is less than the thickness of the first portion 2a. "Thickness" corresponds to the length in the Z direction.

[0015] The lower surface of the first part 2a and the lower surface of the second part 2b are at the same height. "Height" corresponds to the position in the Z direction. The upper surface of the first part 2a and the upper surface of the second part 2b are at different heights. The upper surfaces of the first part 2a and the upper surface of the second part 2b are parallel to the XY plane. There is a step between the upper surface of the first part 2a and the upper surface of the second part 2b.

[0016] As shown in Figure 6, which will be described later, the metal layer 5 is provided between the first region 10a and the first portion 2a, and between the first region 10a and the second portion 2b. -A Schottky barrier is formed between the p-type semiconductor region 12 and the metal layer 5. The p-type semiconductor region 13 is in ohmic contact with the metal layer 5.

[0017] The upper surface of the semiconductor layer 10 and the lower surface of the upper electrode 2 are flat and parallel to the XY plane. The metal layer 5 is formed along the XY plane.

[0018] The insulating layer 20 is provided on the second region 10b. A portion of the insulating layer 20 may cover the outer circumference of the upper electrode 2. The first resin 21 has insulating properties. The first resin 21 is provided on the insulating layer 20 and is located on the second region 10b. Furthermore, the first resin 21 covers a portion of the upper electrode 2. Specifically, the first resin 21 covers the entire second portion 2b and the outer circumference of the first portion 2a.

[0019] The wiring 23 is conductive and is located on the first portion 2a. The wiring 23 is electrically connected to the upper electrode 2. The wiring 23 is used to electrically connect the semiconductor device 100 to external electronic equipment.

[0020] The second resin 22 is insulating and is provided on the upper electrode 2, the first resin 21, and the wiring 23. For example, the second resin 22 is provided around the lower electrode 1, the upper electrode 2, the semiconductor layer 10, the first resin 21, the second resin 22, and a portion of the wiring 23, sealing them together.

[0021] As shown in Figure 2, the second portion 2b is provided over the entire outer circumference of the upper electrode 2. The first resin 21 is provided over the entire outer circumference (second region 10b) of the semiconductor layer 10 and covers the entire second portion 2b.

[0022] When a positive voltage is applied to the upper electrode 2 relative to the lower electrode 1, current flows from the upper electrode 2 to the lower electrode 1 through the semiconductor layer 10. When a positive voltage is applied to the lower electrode 1 relative to the upper electrode 2, no current flows through the semiconductor layer 10, and n - The interface between the shaped semiconductor region 12 and the upper electrode 2 and n -From the interface between the p-type semiconductor region 12 and the p-type semiconductor region 13, n - The depletion layer extends into the semiconductor region 12.

[0023] An example of the materials used for each component is described below. The lower electrode 1 contains a metallic material such as copper, aluminum, nickel, titanium, or gold. The upper electrode 2 contains copper or aluminum. For the upper electrode 2, both the first portion 2a and the second portion 2b contain copper or aluminum. The metal layer 5 contains a metallic material capable of forming a Schottky barrier with the semiconductor layer 10. For example, the metal layer 5 contains a metallic material such as titanium, platinum, molybdenum, or vanadium. The semiconductor layer 10 contains single-crystal silicon, silicon carbide, gallium nitride, or gallium arsenide as the semiconductor material. The insulating layer 20 contains an insulating material such as silicon oxide or silicon nitride. The wiring 23 contains a metallic material such as aluminum and is formed by wire bonding.

[0024] The first resin 21 contains an insulating resin material such as polyimide. The second resin 22 contains a different resin material from the first resin 21. For example, the second resin 22 contains an insulating resin material such as epoxy resin or silicone gel. The first resin 21 has higher insulating properties than the second resin 22. The first resin 21 has effects such as suppressing surface discharge on the surface of the second region 10b and suppressing ion migration to the upper surface of the second region 10b. The second resin 22 constitutes the outer casing of the semiconductor device 100. The second resin 22 is preferably thermoplastic. In that case, the shape of the second resin 22 can be processed more easily than that of the first resin 21.

[0025] The advantages of the first embodiment will be explained. Figures 3(a), 3(b), 4(a), 4(b), and 5 are cross-sectional views showing a part of a semiconductor device according to a reference example. In the semiconductor device 100r shown in the reference example in Figure 3(a), the upper electrode 2 includes only the first portion 2a and does not include the second portion 2b. The thickness of the upper electrode 2 is constant in the XY plane.

[0026] When an electric current flows through the semiconductor layer 10, heat is generated in the semiconductor layer 10. This causes the temperatures of the semiconductor layer 10, the first resin 21, the second resin 22, etc., to rise. The thermal expansion of the first resin 21 and the second resin 22 is greater than that of the semiconductor layer 10. In particular, if the second resin 22 is thermoplastic, the second resin 22 expands more significantly at temperatures above its glass transition point. For example, the glass transition point of epoxy resin is approximately 150 to 170 degrees Celsius.

[0027] When the temperature of the first resin 21 and the second resin 22 rises, the first resin 21 and the second resin 22 expand due to heat. In particular, the amount of thermal expansion of the second resin 22 is greater than that of the first resin 21. When these thermally expanded resins cool, the first resin 21 and the second resin 22 contract due to heat in the direction of arrow A1 shown in Figure 3(a). In particular, the amount of thermal contraction of the second resin 22 is greater than that of the first resin 21. The first resin 21 receives a force from the second resin 22 in the direction of arrow A1, and the force applied to the first resin 21 is transmitted to the upper electrode 2.

[0028] The upper electrode 2 contains copper or aluminum. Copper and aluminum have high thermal conductivity and low electrical resistivity, making them preferable materials for electrodes. On the other hand, copper and aluminum are relatively soft metals. Therefore, when the upper electrode 2 is subjected to force from the first resin 21, a large stress is applied to the side surface of the upper electrode 2, as shown in Figure 3(b), causing the outer circumference of the upper electrode 2 to deform.

[0029] Subsequently, when the temperatures of the first resin 21 and the second resin 22 rise again, the first resin 21 and the second resin 22 expand in the direction of arrow A2 shown in Figure 4(a). The amount of thermal expansion of the second resin 22 is greater than that of the first resin 21. The upper electrode 2 and the first resin 21 are subjected to a force from the second resin 22 in the direction of arrow A2. A large stress is applied from the center of the upper electrode 2 toward the outer circumference of the upper electrode 2, and as a result, the thickness of the outer circumference of the upper electrode 2 increases.

[0030] As temperature cycles (temperature increases and decreases) are repeated, the phenomena shown in Figures 3(b) and 4(a) repeatedly occur. As the thickness of the outer circumference of the upper electrode 2 increases, the stress applied from the first resin 21 to the upper electrode 2 increases during cooling. As a result of repeated increases in thickness and stress, the outer circumference of the upper electrode 2 peels off from the metal layer 5, as shown in Figure 4(b). Furthermore, along with the peeling of the upper electrode 2, the first resin 21 peels off from the insulating layer 20.

[0031] During subsequent temperature cycles, as the first resin 21 and the second resin 22 undergo thermal expansion, stress is applied from the center of the upper electrode 2 toward the outer circumference of the upper electrode 2, as shown in Figure 4(a). At this time, as shown in Figure 5, a portion of the upper electrode 2 penetrates into the gap between the insulating layer 20 and the first resin 21. The size of the upper electrode 2 in the XY plane increases, and the characteristics of the semiconductor device 100 change. For example, the depletion layer in the second region 10b changes, and the breakdown voltage of the semiconductor device 100 changes.

[0032] To suppress deformation of the upper electrode 2 due to temperature cycling, one possible method is to reduce the thickness of the upper electrode 2. According to this method, the surface area of ​​the side of the upper electrode 2 that receives stress from the first resin 21 during thermal contraction of the first resin 21 and the second resin 22 can be reduced. The stress applied to the upper electrode 2 from the first resin 21 can be reduced. However, if the thickness of the upper electrode 2 is small, the electrical resistance of the upper electrode 2 in the X or Y direction increases. The electrical resistance of the semiconductor device 100 increases, and the heat generation and power consumption of the semiconductor device 100 increase.

[0033] Figure 6 is a cross-sectional view showing a part of the semiconductor device according to the first embodiment. In the semiconductor device 100 according to the first embodiment, the upper electrode 2 includes a second portion 2b. The second portion 2b is provided around the first portion 2a. Furthermore, the thickness of the second portion 2b is smaller than the thickness of the first portion 2a. When the first resin 21 and the second resin 22 undergo thermal contraction, the stress applied from the first resin 21 to the upper electrode 2 in the direction of arrow A1 can be distributed to the side surface of the first portion 2a and the side surface of the second portion 2b. This reduces the stress on one surface and alleviates the stress applied from the first resin 21 to the upper electrode 2. This suppresses peeling of the upper electrode 2, changes in the size of the upper electrode 2, and other issues, thereby suppressing deterioration of the characteristics of the semiconductor device 100. As a result, the reliability of the semiconductor device 100 can be improved.

[0034] Furthermore, in the semiconductor device 100, the upper electrode 2 includes a first portion 2a that is thicker than the second portion 2b. By including the first portion 2a in the upper electrode 2, an increase in the electrical resistance of the upper electrode 2 in the X or Y direction can be suppressed. According to the first embodiment, it is possible to suppress the deterioration of the characteristics of the semiconductor device 100 while suppressing an increase in the electrical resistance of the semiconductor device 100.

[0035] If the thickness of the second portion 2b is too large, the stress applied from the first resin 21 to the upper electrode 2 becomes difficult to distribute. If the thickness of the second portion 2b is too small, the electrical resistance of the second portion 2b increases excessively. For this reason, the thickness T2 of the second portion 2b is preferably greater than 0.4 times and less than 0.7 times the thickness T1 of the first portion 2a. The thickness T2 is sufficiently greater than the thickness of the metal layer 5. For example, the second portion 2b is formed by first forming an upper electrode 2 of uniform thickness, and then etching only the outer circumference of the upper electrode 2.

[0036] The invention according to the first embodiment is particularly suitable when the semiconductor layer 10 contains silicon carbide. For semiconductor devices 100 (SiC devices) in which the semiconductor layer 10 contains silicon carbide, a higher operating temperature is required compared to semiconductor devices 100 (silicon devices) in which the semiconductor layer 10 contains silicon. Therefore, when the semiconductor layer 10 contains silicon carbide, the semiconductor device 100 can reach higher temperatures than when the semiconductor layer 10 contains silicon. Also, when the semiconductor layer 10 contains silicon carbide, the thermal expansion coefficient of the semiconductor layer 10 is smaller than when the semiconductor layer 10 contains silicon. The difference between the thermal expansion of the semiconductor layer 10 and the thermal expansion of the upper electrode 2 becomes larger than when the semiconductor layer 10 contains silicon. As a result, peeling of the upper electrode 2, peeling of the first resin 21, etc., are more likely to occur. According to the first embodiment, even when the semiconductor layer 10 contains silicon carbide, peeling of the upper electrode 2 can be effectively suppressed, and deterioration of the characteristics of the semiconductor device 100 can be suppressed.

[0037] Figures 7 to 9 are cross-sectional views showing a part of a semiconductor device according to a modified example of the first embodiment. In the semiconductor device 110 shown in Figure 7, the upper electrode 2 further includes a third portion 2c. The third portion 2c is provided around the second portion 2b in the XY plane. The thickness of the third portion 2c is smaller than the thickness of the second portion 2b. The provision of the third portion 2c allows for a greater distribution of the stress applied from the first resin 21 to the upper electrode 2.

[0038] In the semiconductor device 120 shown in Figure 8, the upper surface of the second portion 2b is inclined with respect to the XY plane. The thickness of the second portion 2b decreases continuously in the longitudinal direction. For example, the angle θ of the upper surface of the second portion 2b with respect to the XY plane is 50 degrees or more and less than 90 degrees. More preferably, from the viewpoint of suppressing the increase in electrical resistance and the degradation of characteristics, the angle θ is preferably 60 degrees or more and 80 degrees or less.

[0039] When the upper surface of the second portion 2b is inclined with respect to the XY plane, the first resin 21 moves along the upper surface of the second portion 2b during thermal contraction of the first resin 21 and the second resin 22. As a result, stress is less likely to be applied from the first resin 21 to the upper electrode 2. The structure of the semiconductor device 120 effectively relieves the stress applied from the first resin 21 to the upper electrode 2.

[0040] In the semiconductor device 130 shown in Figure 9, the upper electrode 2 has a stacked structure of multiple metal layers 2x and 2y. Metal layer 2y is provided on top of metal layer 2x. The size of metal layer 2y in the XY plane is smaller than the size of metal layer 2x in the XY plane. Part of metal layer 2x and metal layer 2y correspond to the first part 2a. The other part of metal layer 2x corresponds to the second part 2b.

[0041] The metal layers 2x and 2y contain copper or aluminum. The metal contained in metal layer 2x and the metal contained in metal layer 2y may be different. As shown in the figure, a portion of the insulating layer 20 may be provided between the outer periphery of metal layer 2x and the outer periphery of metal layer 2y. If the upper electrode 2 includes a third portion 2c as shown in Figure 7, the upper electrode 2 may contain more metal layers.

[0042] According to the modified examples shown in Figures 7 to 9, the stress from the first resin 21 to the upper electrode 2 can be relieved, similar to the semiconductor device 100, and the degradation of the characteristics of the semiconductor devices 110 to 130 can be suppressed. In addition, since the thickness of the first portion 2a is greater than the thickness of the second portion 2b, the increase in the electrical resistance of the upper electrode 2 can be suppressed.

[0043] (Second Embodiment) Figure 10 is a cross-sectional view showing a semiconductor device according to the second embodiment. As shown in Figure 10, in the semiconductor device 200 according to the second embodiment, the semiconductor layer 10 is n + It further includes a shaped semiconductor region 16 and a gate electrode 17. The semiconductor device 200 does not have a metal layer 5. The semiconductor device 200 is a MOSFET.

[0044] The gate electrode 17 is located in the second region 10b. The gate electrode 17 faces the p-type semiconductor region 13 in the X direction via the gate insulating layer 17a. + The p-type semiconductor region 16 is selectively provided on the p-type semiconductor region 13. + The shaped semiconductor region 16 is electrically connected to the upper electrode 2.

[0045] p-type semiconductor region 13, n + Each of the shaped semiconductor region 16 and the gate electrode 17 extends in the Y direction, and multiple electrodes are provided in the X direction.

[0046] With a positive voltage applied to the upper electrode 2 relative to the lower electrode 1, a voltage above a threshold is applied to the gate electrode 17. This forms a channel (inversion layer) in the p-type semiconductor region 13, and the semiconductor device 200 turns on. Electrons flow through the channel from the upper electrode 2 to the lower electrode 1. When the voltage applied to the gate electrode 17 falls below the threshold, the channel in the p-type semiconductor region 13 disappears, and the semiconductor device 200 turns off.

[0047] In the semiconductor device 200, a p-type semiconductor region 14 and an n-type semiconductor region 15 may be provided, similar to the semiconductor device 100. In that case, the p-type semiconductor region 14 is provided around the p-type semiconductor region 13 along the XY plane. The n-type semiconductor region 15 is provided around the p-type semiconductor region 14 along the XY plane and is located near the outer periphery of the upper surface of the semiconductor layer 10.

[0048] In the semiconductor device 200, similar to the semiconductor devices 100 to 130, the upper electrode 2 includes a first portion 2a and a second portion 2b. Therefore, according to the second embodiment, similar to the first embodiment, it is possible to suppress the increase in the electrical resistance of the semiconductor device 200 while suppressing the deterioration of the characteristics of the semiconductor device 200.

[0049] Furthermore, the invention according to the first embodiment has superior advantages compared to the invention according to the second embodiment. In the semiconductor device 200, the p-type semiconductor region 13, n +The semiconductor regions, such as the shaped semiconductor region 16, and the upper surface of the gate insulating layer 17a are at different heights. As a result, irregularities exist on the upper surface of the semiconductor layer 10 and the lower surface of the upper electrode 2. Consequently, when the first resin 21 and the second resin 22 shrink, and stress is applied from the first resin 21 to the upper electrode 2, the stress is distributed across multiple gate insulating layers 17a. As a result, the increase in thickness of the outer periphery of the upper electrode 2 is suppressed, and the increase in stress applied from the first resin 21 to the outer periphery of the upper electrode 2 is also suppressed.

[0050] On the other hand, in the semiconductor devices 100 to 130 according to the first embodiment, the upper surface of the semiconductor layer 10 and the lower surface of the upper electrode 2 are flat, and the thickness of the outer circumference of the upper electrode 2 is more likely to increase compared to the semiconductor device 200 according to the second embodiment. According to the first embodiment, even when the upper surface of the semiconductor layer 10 and the lower surface of the upper electrode 2 are flat and peeling of the upper electrode 2 is more likely to occur, peeling of the upper electrode 2 can be effectively suppressed.

[0051] The embodiments may include the following configurations. (Composition 1) First electrode and, A semiconductor layer provided on the first electrode, comprising a first region and a second region provided around the first region along a first plane perpendicular to a first direction toward the semiconductor layer from the first electrode, A second electrode provided on the first region comprises a first portion and a second portion that is thinner than the first portion and provided around the first portion along the first surface, wherein the first portion and the second portion contain copper or aluminum, An insulating first resin is provided on the second region and covers the outer periphery of the first portion and the second portion, An insulating second resin, provided on the second electrode and the first resin, containing a resin material different from the first resin, A semiconductor device equipped with the following features. (Configuration 2) The semiconductor device according to configuration 1, wherein the upper surface of the second portion is parallel to the first surface. (Composition 3) The semiconductor device according to configuration 1, wherein the upper surface of the second portion is inclined with respect to the first surface. (Composition 4) The semiconductor device according to any one of configurations 1 to 3, wherein the second resin is provided around the first electrode, the semiconductor layer, the second electrode, and the first resin. (Composition 5) The semiconductor device according to any one of configurations 1 to 4, wherein the upper surface of the semiconductor layer and the lower surface of the second electrode are parallel to the first surface. (Composition 6) The semiconductor device according to any one of configurations 1 to 5, wherein the second resin is thermoplastic. (Composition 7) The semiconductor device according to any one of configurations 1 to 6, wherein the semiconductor layer contains silicon carbide.

[0052] The relative levels of impurity concentrations between semiconductor regions in each embodiment described above can be confirmed, for example, using a scanning capacitance microscope (SCM). The carrier concentration in each semiconductor region can be considered equal to the concentration of activated impurities in that region. Therefore, the relative levels of carrier concentrations between semiconductor regions can also be confirmed using SCM. Furthermore, the impurity concentration in each semiconductor region can be measured, for example, by secondary ion mass spectrometry (SIMS).

[0053] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other. [Explanation of symbols]

[0054] 1: lower electrode, 2: upper electrode, 2a: first part, 2b: second part, 2c: third part, 2x: metal layer, 2y: metal layer, 5: metal layer, 10: semiconductor layer, 10a: first region, 10b: second region, 11: n + Semiconductor region, 12:n - 13,14: p-type semiconductor region, 15: n-type semiconductor region, 16: n + Semiconductor region, 17: gate electrode, 17a: gate insulating layer, 20: insulating layer, 21: first resin, 22: second resin, 23: wiring, 100, 100r, 110~130, 200: semiconductor device

Claims

1. First electrode and A semiconductor layer provided on the first electrode, comprising a first region and a second region provided around the first region along a first plane perpendicular to a first direction toward the semiconductor layer from the first electrode, A first portion and a second portion that is thinner than the first portion and is provided around the first portion along the first surface, wherein the first portion and the second portion contain copper or aluminum, the upper surface of the second portion is inclined with respect to the first surface, and a second electrode is provided on the first region, An insulating layer covering the outer periphery and the second portion of the second electrode from the second region of the semiconductor layer, An insulating first resin is provided on the insulating layer and covers the outer periphery of the first portion and the second portion, An insulating second resin, provided on the second electrode and the first resin, containing a resin material different from the first resin, A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, wherein the second resin is provided around the first electrode, the semiconductor layer, the second electrode, and the first resin.

3. The semiconductor device according to claim 1 or 2, wherein the upper surface of the semiconductor layer and the lower surface of the second electrode are parallel to the first surface.

4. The semiconductor device according to claim 1 or 2, wherein the second resin is thermoplastic.

5. The semiconductor device according to claim 1 or 2, wherein the semiconductor layer contains silicon carbide.

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