Chip body and its manufacturing method

Abstract

To provide a method for manufacturing a chip body.SOLUTION: An active surface 120 of a chip 100 is attached to a carrier T2, and a heat dissipation layer 150 is formed on the back surface 110 of the chip 100. When the heat dissipation layer 150 is formed, a half groove 140a surrounding the active surface 120 prevents metal residues from accumulating in a gap between the active surface 120 and the carrier and contaminating the chip 100.SELECTED DRAWING: Figure 7D

Description

Technical Field

[0001] The present invention relates to a chip body and a method for manufacturing the same, and more particularly, to a chip body for forming a heat dissipation layer on the back surface of a chip and a method for manufacturing the same.

Background Art

[0002] FIG. 9 shows that the active surfaces 11a of a plurality of chips 11 on a wafer 10 are adhered to the surface 21 of a tape 20, and there are groove portions 30 between adjacent chips 11, and the surface 21 is exposed in the groove portions 30. Next, a heat dissipation layer 12 is formed on the back surface 11b of each chip 11 by a sputtering process.

Summary of the Invention

Problems to be Solved by the Invention

[0003] However, in the above-described conventional technology, when the heat dissipation layer 12 is formed on the back surface 11b by a sputtering process, a gap 40 is generated between the active surface 11a and the tape 20 due to the physical properties of the chip 11 and the tape 20 or the process environment (temperature, etc.). By the accumulation of sputtering target atoms on the tape 20 and the gap 40, a plurality of metal residues 50 are formed. When each metal residue 50 adheres to the active surface 11a, it affects the quality and yield of the chip 11.

[0004] Therefore, the inventor of the present invention considered that the above-mentioned drawbacks can be improved, and as a result of intensive studies, the present invention was proposed to effectively improve the above-mentioned problems by a reasonable design.

[0005] The present invention has been made in view of such conventional problems. For the purpose of solving the above problems, the main object of the present invention is to provide a chip body and a method for manufacturing the same. That is, when forming a heat dissipation layer on the back surface of a chip, it is possible to prevent a situation in which metal residues accumulate in a gap between the active surface of the chip and the carrier, and to prevent the quality and yield of the chip from being affected.

Means for Solving the Problems

[0006] To solve the above problems, a chip body according to one embodiment of the present invention comprises a chip and a heat dissipation layer, wherein the chip has a back surface, an active surface, a side surface, and a semi-groove, and the heat dissipation layer covers the back surface. The semi-groove surrounds the active surface and is located between the active surface and the side surface, and the semi-groove has a first edge adjacent to the active surface and a second edge adjacent to the side surface. A first virtual line extending along the side surface passes through the second edge, and a second virtual line extending along the active surface passes through the first edge. The first distance from the first edge to the first virtual line is 3 μm or more and 10 μm or less. The second distance from the second edge to the second virtual line is 5 μm or more and 120 μm or less. The ratio of the second distance to the first distance is 0.5 or more and 40 or less.

[0007] Another aspect of the present invention is a method for manufacturing chip bodies. This method for manufacturing chip bodies includes the step of attaching a plurality of chips to a second carrier, each chip having a back surface, an active surface, a side surface, and a semi-groove, and forming a heat dissipation layer on the back surface to constitute a plurality of chip bodies. The semi-groove surrounds the active surface and is located between the active surface and the side surface, and the semi-groove has a first edge adjacent to the active surface and a second edge adjacent to the side surface. By attaching each chip to the second carrier by the active surface, the semi-groove is formed as a shielding space located between each chip and the second carrier. A first virtual line extending along the side surface passes through the second edge, and a second virtual line extending along the active surface passes through the first edge. The first distance from the first edge to the first virtual line is 3 μm or more and 10 μm or less. The second distance from the second edge to the second virtual line is 5 μm or more and 120 μm or less. The ratio of the second distance to the first distance is 0.5 or more and 40 or less.

[0008] The semi-groove surrounding the active surface is defined as the shielding space located between the chip and the second carrier. In the process of forming the heat dissipation layer, this prevents sputtering target atoms from accumulating in the gap between the second carrier and the active surface and forming metal residue, thereby preventing the metal residue from contaminating or damaging the chip. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view showing a wafer according to one embodiment of the present invention. [Figure 2] This is a cross-sectional view showing a wafer according to one embodiment of the present invention. [Figure 3]This is a plan view showing a part of a wafer according to one embodiment of the present invention. [Figure 4A] This is a cross-sectional view showing a method for manufacturing a chip body according to one embodiment of the present invention. [Figure 4B] This is a cross-sectional view showing a method for manufacturing a chip body according to one embodiment of the present invention. [Figure 4C] This is a cross-sectional view showing a method for manufacturing a chip body according to one embodiment of the present invention. [Figure 4D] This is a cross-sectional view showing a method for manufacturing a chip body according to one embodiment of the present invention. [Figure 5A] This is a cross-sectional view showing a method for manufacturing a chip body according to one embodiment of the present invention. [Figure 5B] This is a cross-sectional view showing a method for manufacturing a chip body according to one embodiment of the present invention. [Figure 5C] This is a cross-sectional view showing a method for manufacturing a chip body according to one embodiment of the present invention. [Figure 5D] This is a cross-sectional view showing a method for manufacturing a chip body according to one embodiment of the present invention. [Figure 6A] This is a cross-sectional view showing a method for manufacturing a chip body according to one embodiment of the present invention. [Figure 6B] This is a cross-sectional view showing a method for manufacturing a chip body according to one embodiment of the present invention. [Figure 6C] This is a cross-sectional view showing a method for manufacturing a chip body according to one embodiment of the present invention. [Figure 6D] This is a cross-sectional view showing a method for manufacturing a chip body according to one embodiment of the present invention. [Figure 7A] This is a cross-sectional view showing a method for manufacturing a chip body according to one embodiment of the present invention. [Figure 7B] This is a cross-sectional view showing a method for manufacturing a chip body according to one embodiment of the present invention. [Figure 7C] This is a cross-sectional view showing a method for manufacturing a chip body according to one embodiment of the present invention. [Figure 7D] This is a cross-sectional view showing a method for manufacturing a chip body according to one embodiment of the present invention. [Figure 8A] This is a cross-sectional view showing a method for manufacturing a chip body according to one embodiment of the present invention. [Figure 8B] It is a cross-sectional view showing a method for manufacturing a chip body according to an embodiment of the present invention. [Figure 8C] It is a cross-sectional view showing a method for manufacturing a chip body according to an embodiment of the present invention. [Figure 8D] It is a cross-sectional view showing a method for manufacturing a chip body according to an embodiment of the present invention. [Figure 9] It is a cross-sectional view showing a conventional chip body.

Mode for Carrying Out the Invention

[0010] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0011] First, an embodiment of a method for manufacturing a chip body according to the present invention will be described in detail with reference to FIGS. 1 and 2.

[0012] First, a wafer 200 is provided. The wafer 200 has a plurality of unseparated chips 100, and each chip 100 has a back surface 110 and an active surface 120. In the present embodiment, a plurality of contact pads 121 are provided on the active surface 120, and each contact pad 121 is electrically connected to a redistribution layer (RDL, not shown). Next, the wafer 200 is attached to a first carrier T1, and the wafer 200 is attached to the first carrier T1 by the back surface 110 of each chip 100, and the active surface 120 of the chip 100 is exposed.

[0013] As shown in Figures 3 and 4A, a groove 140 is then formed on the active surface 120, with the groove 140 surrounding the active surface 120. Preferably, the first tool K1 cuts the wafer 200 along the scribe line C, forming a groove 140 surrounding the active surface 120. The groove 140 has a bottom surface 143 and two opposing first edges 141, each of which is adjacent to the active surface 120. The cross-sectional shape of the groove 140 differs depending on the shape of the first tool K1 (see Figures 4A to 4D).

[0014] As shown in Figures 4A to 4C, the groove 140 has two opposing groove side surfaces 144, each first edge 141 is located on each groove side surface 144, each groove side surface 144 is connected to the bottom surface 143, and there is an angle A between each groove side surface 144 and the bottom surface 143, and the angle A is 90 degrees or more. As shown in Figure 4A, the groove side surface 144 is perpendicular to the bottom surface 143, and the angle A is 90 degrees. Referring to Figures 4B and 4C, the angle A is greater than 90 degrees. Unlike Figures 4A, 4B, and 4C, the groove side surface 144 shown in Figure 4D has an arc-shaped surface.

[0015] As shown in Figures 5A to 5D, after forming the groove 140, the second tool K2 cuts the wafer 200 along the bottom surface 143 and scribe line C of the groove 140, separating each chip 100, each chip 100 having a side surface 130, and dividing the groove 140 into two semi-grooves 140a. The semi-grooves 140a surround the active surface 120 and are located between the active surface 120 and the side surface 130, and the semi-grooves 140a have a first edge 141 and a second edge 142, the first edge 141 is close to the active surface 120 and the second edge 142 is close to the side surface 130.

[0016] As shown in Figures 5A to 5D, the first virtual line Y extending along the side surface 130 passes through the second edge 142, and the second virtual line X extending along the active surface 120 passes through the first edge 141. The first distance S1 between the first edge 141 and the first virtual line Y is between 3 μm and 10 μm (3 μm ≤ S1 ≤ 10 μm), the second distance S2 between the second edge 142 and the second virtual line X is between 5 μm and 120 μm (5 μm ≤ S2 ≤ 120 μm), and the ratio of the second distance S2 to the first distance S1 (S2 / S1) is between 0.5 and 40 (0.5 ≤ S2 / S1 ≤ 40).

[0017] As shown in Figures 5A and 5B, when separating each chip 100, the second tool K2 cuts the wafer 200 along the bottom surface 143 of the groove 140, dividing the bottom surface 143 into two groove bottom surfaces 143a, the groove side surface 144 is joined to the groove bottom surface 143a, and there is a clamping angle A between the groove side surface 144 and the groove bottom surface 143a. In this embodiment, the second edge 142 is located on the groove bottom surface 143a, the groove side surface 144 is oriented toward the first virtual line Y, and the groove bottom surface 143a is oriented toward the second virtual line X. In other embodiments, the groove side surface 144 is an arc-shaped surface and is joined to the groove bottom surface 143a (see Figure 5D).

[0018] In another embodiment, the second tool K2 cuts the wafer 200 along the bottom surface 143 of the groove 140 and removes the bottom surface 143 (see Figure 5C). After each chip 100 is separated, the groove side surface 144 is retained in the half groove 140a, the second edge 142 is located on the groove side surface 144, and the groove side surface 144 is directed towards the intersection O of the first virtual line Y and the second virtual line X.

[0019] Next, the active surface 120 of each chip 100 is attached to the second carrier T2, and the semi-groove portion 140a is made into a shielding space B located between the chip 100 and the second carrier T2 (see Figures 6A to 6D). There is a gap G between the side surfaces 130 of adjacent chips 100, and the gap G is between 20 μm and 1 mm (20 μm ≤ G ≤ 1 mm). Next, the first carrier T1 is removed, and the back surface 110 is exposed. The first carrier T1 and the second carrier T2 may be selected from adhesive tapes, glass substrates, silicon substrates, etc.

[0020] Next, a heat dissipation layer 150 is formed on the back surface 110 to constitute multiple chip bodies 100A (see Figures 7A to 7D). Preferably, the heat dissipation layer 150 covers the back surface 110 and the side surface 130 to form a heat sink. The heat dissipation layer 150 is formed by a sputtering process, and in the process of forming the heat dissipation layer 150, the shielding space B located between the chip 100 and the second carrier T2 prevents sputtering target atoms from accumulating in the gap (not shown) between the second carrier T2 and the active surface 120, thereby preventing the formation of metal residues that contaminate or damage the chip 100.

[0021] As shown in Figures 8A to 8D, the device finally performs a pick-and-place process to detach each chip 100A from the second carrier T2.

[0022] The difference between each chip body 100A shown in Figures 8A to 8D lies in the shape of the semi-groove 140a. Each chip body 100A comprises a chip 100 and a heat dissipation layer 150. The semi-groove 140a surrounds the active surface 120, is located between the active surface 120 and the side surface 130, has a first edge 141 adjacent to the active surface 120 and a second edge 142 adjacent to the side surface 130, and the heat dissipation layer 150 covers the back surface 110. Preferably, the heat dissipation layer 150 also covers the side surface 130.

[0023] As shown in Figures 8A and 8B, the semi-groove 140a has a groove side surface 144 and a groove bottom surface 143a, with the first edge 141 located on the groove side surface 144 and the second edge 142 located on the groove bottom surface 143a. The groove side surface 144 is oriented toward the first imaginary line Y, and the groove bottom surface 143a is oriented toward the second imaginary line X. The groove side surface 144 is connected to the groove bottom surface 143a, and there is an angle A between the groove side surface 144 and the groove bottom surface 143a, and the angle A is 90 degrees or more. The groove side surface 144 is perpendicular to the groove bottom surface 143a, and the angle A is 90 degrees (see Figure 8A). The angle A is greater than 90 degrees (see Figure 8B). Referring to Figure 8D, the groove side surface 144 is an arc-shaped surface and is connected to the groove bottom surface 143a.

[0024] As shown in Figure 8C, the semi-groove portion 140a has only the groove side surface 144, the first edge 141 and the second edge 142 are located on the groove side surface 144, and the groove side surface 144 is directed towards the intersection O of the first virtual line Y and the second virtual line X.

[0025] In this invention, before separating each chip 100, a groove 140 is first formed on the active surface 120, surrounding the active surface 120. After separating each chip 100, the groove 140 is converted into a semi-groove 140a surrounding the active surface 120, and each active surface 120 of each chip 100 is attached to the second carrier T2, with the semi-groove 140a becoming a shielding space B. In the process of forming the heat dissipation layer 150 by sputtering, the shielding space B prevents sputtering target atoms from accumulating in the gap (not shown) between the second carrier T2 and the active surface 120, thereby preventing the formation of metal residues that contaminate or damage the chip 100.

[0026] The embodiments described above are provided to facilitate understanding of the present invention and are not intended to limit its interpretation. The present invention may be modified and improved without departing from its spirit, and it goes without saying that equivalents thereof are included. [Explanation of Symbols]

[0027] 10 wafers 11 chips 11a Active surface 11b Back 12 Heat dissipation layer 20 tapes 21 Surface 30 groove 40 Gap 50 Metal residue 100 chips 100A chip body 110 Back 120 Active Surfaces 121 Contact Pads 130 Side view 140 groove section 140a Half groove part 141 1st edge 142 Second edge 143 Bottom 143a Bottom surface of groove 144 Side view of groove 150 Heat dissipation layer 200 wafers A inclusion angle B Shielded space C Scribeline G interval K1 1st Tool K2 2nd Tool O intersection S1 1st distance S2 2nd distance T1 First Carrier T2 Second Carrier X Second virtual line Y First virtual line

Claims

1. A chip having a back surface, an active surface, a side surface, and a semi-groove, wherein the semi-groove surrounds the active surface and is located between the active surface and the side surface, and the semi-groove has a first edge adjacent to the active surface and a second edge adjacent to the side surface. It comprises a heat dissipation layer covering the rear surface, A chip body characterized in that a first virtual line extending along the side surface passes through the second edge, a second virtual line extending along the active surface passes through the first edge, the first distance from the first edge to the first virtual line is 3 μm or more and 10 μm or less, the second distance from the second edge to the second virtual line is 5 μm or more and 120 μm or less, and the ratio of the second distance to the first distance is 0.5 or more and 40 or less.

2. The chip body according to claim 1, characterized in that the semi-groove portion has a groove side surface and a groove bottom surface, the first edge is located on the groove side surface, the second edge is located on the groove bottom surface, the groove side surface is directed toward the first imaginary line, the groove bottom surface is directed toward the second imaginary line, the groove side surface is coupled to the groove bottom surface, there is an angle between the groove side surface and the groove bottom surface, and the angle is 90 degrees or more.

3. The chip body according to claim 1, characterized in that the semi-groove portion has a groove side surface, the first edge and the second edge are located on the groove side surface, and the groove side surface is directed toward the intersection of the first virtual line and the second virtual line.

4. The chip body according to claim 1, characterized in that the semi-groove portion has a groove side surface and a groove bottom surface, the groove side surface is an arc-shaped surface, the groove side surface is connected to the groove bottom surface, the groove side surface is located between the groove bottom surface and the active surface, and the second edge is located on the groove bottom surface.

5. The chip body according to claim 4, characterized in that the groove side surface is coupled to the active surface, and the first edge is located on the groove side surface.

6. A step of attaching a plurality of chips to a second carrier, wherein each chip has a back surface, an active surface, a side surface, and a semi-groove, the semi-groove surrounds the active surface and is located between the active surface and the side surface, the semi-groove has a first edge adjacent to the active surface and a second edge adjacent to the side surface, and each chip is attached to the second carrier by the active surface, thereby creating a shielding space between each chip and the second carrier in the semi-groove. The process includes forming a heat dissipation layer on the back surface to constitute multiple chip bodies, A method for manufacturing a chip body, characterized in that a first virtual line extending along the side surface passes through the second edge, a second virtual line extending along the active surface passes through the first edge, a first distance between the first edge and the first virtual line is 3 μm or more and 10 μm or less, a second distance between the second edge and the second virtual line is 5 μm or more and 120 μm or less, and the ratio of the second distance to the first distance is 0.5 or more and 40 or less.

7. The method for manufacturing a chip body according to claim 6, characterized in that, before attaching each chip to the second carrier, a wafer having a plurality of unseparated chips is attached to a first carrier, the wafer is attached to the first carrier by the back surface of each chip and the active surface is exposed, a groove is formed on the active surface that surrounds the active surface and has a bottom surface and two opposing first edges, the wafer is cut along the bottom surface of the groove to separate each chip, the groove is divided into two half-grooves, the active surface of each chip having the side surface, first edge, second edge and half-grooves is attached to the second carrier, and then the first carrier is removed to expose the back surface.

8. The method for manufacturing a chip body according to claim 7, characterized in that there is a gap between the sides of each adjacent chip that is attached to the second carrier, and the gap is 20 μm or more and 1 mm or less.

9. The method for manufacturing a chip body according to claim 7, characterized in that the groove portion has two opposing groove portion sides, each first edge is located on each groove portion side, each groove portion side is connected to the bottom surface, there is a binding angle between each groove portion side and the bottom surface, the binding angle is 90 degrees or more, and after separating each chip, the bottom surface is made into two groove portion bottom surfaces, each groove portion side is connected to each groove portion bottom surface, the second edge is located on each groove portion bottom surface, and there is the binding angle between each groove portion side and each groove portion bottom surface.

10. The method for manufacturing a chip body according to claim 7, characterized in that the groove portion has two opposing groove portion sides, each first edge is located on each groove portion side, each groove portion side is connected to the bottom surface, there is an angle between each groove portion side and the bottom surface, the angle of being greater than 90 degrees, when separating each chip the bottom surface is removed, after separating each chip each groove portion side is retained in each half groove portion, and the second edge is located on each groove portion side.

11. The method for manufacturing a chip body according to claim 7, characterized in that the groove portion has two opposing groove portion sides, each groove portion side is an arc-shaped surface, each groove portion side is connected to the bottom surface, each chip is separated, the bottom surface becomes two groove portion bottom surfaces, the second edge is located on each groove portion bottom surface, each groove portion side is connected to each groove portion bottom surface, and each groove portion side is located between each groove portion bottom surface and the active surface.

12. The method for manufacturing a chip body according to claim 11, characterized in that each groove side surface is connected to the active surface, and the first edge is located on each groove side surface.

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