Semiconductor equipment

Abstract

A semiconductor device (1) includes a third active region (130) in which both ends of the fingers of a plurality of isolated FETs (11, 12) are connected. A third nitride-semiconductor layer (131) containing a P-type impurity is provided above the third active region (130).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device having a nitride semiconductor layer, and particularly to a semiconductor device used in a switching power supply circuit operating at high voltage and high frequency.

Background Art

[0002] III-V nitride-based compound semiconductors represented by gallium nitride (GaN), so-called nitride semiconductors, have a general formula of In x Ga y Al 1-x-y N (0≦x≦1, 0≦y≦1, x + y≦1), which is a compound semiconductor composed of aluminum (Al), gallium (Ga), and indium (In), which are group III elements, and nitrogen (N), which is a group V element.

[0003] Nitride semiconductors can form various mixed crystals and can easily form a heterojunction interface. The heterojunction of nitride semiconductors is characterized in that a high-concentration two-dimensional electron gas layer (2DEG layer) is generated at the interface due to spontaneous polarization and piezopolarization. A field effect transistor (FET: Field Effect Transistor) using this high-concentration 2DEG layer as a carrier has attracted attention as a device for high frequency and high power. The FET using a nitride semiconductor is expected to be applied to a high-output power supply operating at high voltage and high frequency by taking advantage of advantages such as a large bandgap and high electron mobility.

[0004] When the FET operates at high frequency, a large amount of heat may be generated. If the temperature of the FET rises excessively, the performance of the FET deteriorates and the power supply performance deteriorates. Specifically, it is due to output limitation due to a decrease in the saturation current of the FET and a decrease in reliability due to a decrease in the breakdown voltage of the FET.

[0005] To suppress such temperature rise in FETs, a semiconductor device has been proposed in which multiple active regions containing FETs are formed at a distance from each other, and each FET is connected in parallel (see Patent Documents 1 and 2). With such a semiconductor device structure, the heat-generating region of the FET can be dispersed, and the temperature rise of the FET can be suppressed. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2012-69966 [Patent Document 2] Special Publication No. 2017-526169 [Overview of the project] [Problems that the invention aims to solve]

[0007] Figure 12(a) shows a plan view of a conventional FET 9 using a nitride semiconductor, and Figure 12(b) shows a cross-section of Figure 12(a) along A-A. In a conventional FET 9, multiple active regions 910, each having a source electrode 911, a drain electrode 912, a P-type nitride semiconductor layer 913, and a gate electrode 914, are arranged in parallel and spaced apart. The inert region 990 is necessary for defining the active region 910, separating it from other elements, and reducing parasitic capacitance in the formation areas of electrode pads and wiring. The P-type nitride semiconductor layer 913 and the gate electrode 914 extend from the active region 910 to the inert region 990.

[0008] Multiple FETs 9 are connected in parallel by the following connections: the source electrode 911 is connected to the source aggregation wiring 975 via the source wiring 915, the drain electrode 912 is connected to the drain aggregation wiring 976 via the drain wiring 916, and the gate electrode 914 is connected to the gate aggregation wiring 974.

[0009] However, the nitride semiconductor FET9 shown in Figure 12(a) has the problem of a large drain leakage current when the gate voltage is below the threshold voltage. When considering the power supply application of the FET, the drain leakage current needs to be sufficiently small.

[0010] The leakage path of this drain leakage current is thought to be the interface between the active region 910 and the inactive region 990. Figure 12(c) shows the BB cross section of Figure 12(a). In the FET 9, the carrier concentration is controlled by the potential of the P-type nitride semiconductor layer 913 on top of the two-dimensional electron gas 905 to create on and off states. However, at the interface 980 between the inactive region 990 and the active region 910, the potential is different from that within the active region 910, so it is thought that the carriers are not completely eliminated. Figure 12(d) shows the CC cross section of Figure 12(a). The carriers remaining at the interface 980 shown in Figure 12(c) are connected to the source electrode 911 via the two-dimensional electron gas 905 shown in Figure 12(d), and this is observed as drain leakage current.

[0011] Therefore, the present disclosure aims to provide a semiconductor device that suppresses drain leakage current in an FET using a nitride semiconductor. [Means for solving the problem]

[0012] To achieve the above objective, a semiconductor device according to one embodiment of the present disclosure comprises a substrate, a first nitride semiconductor layer formed on the substrate, a second nitride semiconductor layer formed on the first nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer, a first field-effect transistor, and a second field-effect transistor, wherein the first nitride semiconductor layer and the second nitride semiconductor layer have, in a plan view with respect to the substrate, a first active region where a two-dimensional electron gas is formed, a second active region, and an inert region where a two-dimensional electron gas is not formed, the first field-effect transistor comprises a first source electrode and a first drain electrode included in the first active region and extending in a first direction in a plan view with respect to the substrate, a first P-type nitride semiconductor layer between the first source electrode and the first drain electrode and extending in the first direction in a plan view with respect to the substrate, and a first gate electrode formed on the first P-type nitride semiconductor layer, and the second field-effect transistor is included in the second active region The first active region and the second active region further have the first active region at both ends in the first direction The semiconductor device has a third active region connected to the first active region and the second active region in a second direction different from the direction, and in a plan view with respect to the substrate, a two-dimensional electron gas is formed thereon, the third active region includes a third nitride semiconductor layer having p-type impurities that extends in the second direction in a plan view with respect to the substrate, and within the first, second, and third active regions, the first p-type nitride semiconductor layer and the second p-type nitride semiconductor layer are connected via the third nitride semiconductor layer. In other words, in the semiconductor device, active regions are connected at both ends of the fingers of a plurality of spaced-apart FETs, and a third nitride semiconductor layer containing p-type impurities is formed on the active regions. In a plan view of the substrate, a first inert region is formed as part of the inert region between the first active region and the second active region, and in a plan view of the substrate, the first inert region is surrounded by the first active region, the second active region and the third active region. .

Advantages of the Invention

[0013] In the semiconductor device of the present disclosure, by suppressing the two-dimensional electron gas below the third nitride semiconductor layer containing P-type impurities, there is an effect of suppressing the drain leakage current.

Brief Description of the Drawings

[0014] [Figure 1] FIG. 1 is a diagram showing an example of a semiconductor device in the first embodiment. [Figure 2] FIG. 2 is a box plot of the drain leakage current of a conventional semiconductor device and the semiconductor device of the present disclosure. [Figure 3] FIG. 3 is a diagram showing another example of a semiconductor device in the first embodiment. [Figure 4] FIG. 4 is a diagram showing another example of a semiconductor device in the first embodiment. [Figure 5] FIG. 5 is a diagram showing another example of a semiconductor device in the first embodiment. [Figure 6] FIG. 6 is a diagram showing another example of a semiconductor device in the first embodiment. [Figure 7] FIG. 7 is a diagram showing another example of a semiconductor device in the first embodiment. [Figure 8] FIG. 8 is a diagram showing an example of a semiconductor device in the first modification of the first embodiment. [Figure 9] FIG. 9 is a diagram showing an example of a semiconductor device in the second modification of the first embodiment. [Figure 10] FIG. 10 is a diagram showing an example of a semiconductor device in the second embodiment. [Figure 11] FIG. 11 is a diagram showing an example of a semiconductor device in the third embodiment. [Figure 12] FIG. 12 is a diagram showing an example of a conventional semiconductor device.

Modes for Carrying Out the Invention

[0015] The embodiments of this disclosure will be described in detail below with reference to the drawings. However, the same reference numerals will be used for identical components, and redundant descriptions will be omitted. Unless otherwise specified, "top" and "bottom" refer to the top and bottom in a cross-sectional view, including cases where they are in contact and cases where they are not.

[0016] (Embodiment 1) Figure 1 shows an example of a semiconductor device in the first embodiment. Figure 1(a) shows a plan view of the semiconductor device 1 according to the first embodiment. The semiconductor device 1 has a first active region 110 and a second active region 120. A finger-shaped (i.e., extended with the first direction as the longer side) first source electrode 111 and a first drain electrode 112 are formed in the first active region 110, and a first P-type GaN layer (an example of a first P-type nitride semiconductor layer) 113 and a first gate electrode 114 are extended from the first active region 110 across the interface between the first active region 110 and the inert region 190 to the inert region 190, thereby forming a first FET 11. Furthermore, a second finger-shaped source electrode 121 and a second drain electrode 122 are formed within the second active region 120, and a second P-type GaN layer (an example of a second P-type nitride semiconductor layer) 123 and a second gate electrode 124 are extended from the second active region 120 across the interface between the second active region 120 and the inert region 190 to the inert region 190, thereby forming the second FET 12. Here, the first active region 110 and the second active region 120 are regions where a two-dimensional electron gas is formed, and are formed side by side in the direction of the short side of the finger (i.e., the second direction), and an inert region 190 where a two-dimensional electron gas is not formed is formed between the first active region 110 and the second active region 120.

[0017] The first source electrode 111 and the second source electrode 121 are connected to the source aggregation wiring 175 via the first source wiring 115 and the second source wiring 125, respectively; the first drain electrode 112 and the second drain electrode 122 are connected to the drain aggregation wiring 176 via the first drain wiring 116 and the second drain wiring 126, respectively; and the first gate electrode 114 and the second gate electrode 124 are connected to the gate aggregation wiring 174, respectively, thereby connecting the first FET 11 and the second FET 12 in parallel.

[0018] Figure 1(b) shows a cross-sectional view of AA in Figure 1(a). A buffer layer 102, a GaN channel layer (an example of a first nitride semiconductor layer) 103, and an AlGaN barrier layer (an example of a second nitride semiconductor layer) 104 with a larger band gap than the GaN channel layer 103 are formed in this order on a Si substrate 101. Here, the buffer layer 102 is composed of a multilayer structure made of, for example, AlN and AlGaN, and the total film thickness is, for example, about 2.1 μm. The composition of the AlGaN barrier layer 104 is, for example, Al 0.17 Ga 0.83 It consists of N and has a layer thickness of approximately 60 nm. At the interface between the GaN channel layer 103 and the AlGaN barrier layer 104, a high-concentration 2DEG layer 105 is formed due to the effects of piezoelectric polarization and spontaneous polarization. The inert region 190 consists of the GaN channel layer 103 and the AlGaN barrier layer 104, which have been made highly resistive by ion implantation of non-conductive impurities.

[0019] The first FET 11 is formed by forming a first source electrode 111, a first drain electrode 112, and a first P-type GaN layer 113 on the AlGaN barrier layer 104 of the first active region 110, and a first gate electrode 114 on the first P-type GaN layer 113. The second FET 12 is formed by forming a second source electrode 121, a second drain electrode 122, and a second P-type GaN layer 123 on the AlGaN barrier layer 104 of the second active region 120, and a second gate electrode 124 on the second P-type GaN layer 123. The first source electrode 111, the first drain electrode 112, the second source electrode 121, and the second drain electrode 122 are, for example, laminates of titanium (Ti) and aluminum (Al), and each makes ohmic contact with the 2DEG layer 105. The first gate electrode 114 and the second gate electrode 124 are, for example, laminates of titanium (Ti) and aluminum (Al), and are in ohmic contact with the first P-type GaN layer 113 and the second P-type GaN layer 123, respectively.

[0020] In the semiconductor device 1 according to the first embodiment, as shown in Figure 1(a), a third active region 130 is formed at both longitudinal ends of the finger between the first FET 11 and the second FET 12, where a two-dimensional electron gas is formed. The third active region 130 connects the first active region 110 and the second active region 120. A third nitride semiconductor layer 131 containing p-type impurities is formed on the third active region 130, and the third nitride semiconductor layer 131 is connected to the first p-type GaN layer 113 and the second p-type GaN layer 123 within the first active region 110, the second active region 120, and the third active region 130. It is desirable that the third nitride semiconductor layer 131 containing p-type impurities is made of the same material as the first p-type GaN layer 113 and the second p-type GaN layer 123.

[0021] Figure 1(c) shows the BB cross section of Figure 1(a). The first P-type GaN layer 113 and the first gate electrode 114 of the first FET 11 are formed on the AlGaN barrier layer 104. They extend from the first active region 110, across the interface 180 between the first active region 110 and the inactive region 190, to the inactive region 190. Although not shown, the second FET 12 similarly has a second P-type GaN layer 123 and a second gate electrode 124 extending from the second active region 120 to the inactive region 190. Figure 1(d) shows the CC cross section of Figure 1(a). A third nitride semiconductor layer 131 is formed on the AlGaN barrier layer 104 of the first active region 110, which is connected to the third active region 130. The third nitride semiconductor layer 131 extends to the inactive region 190.

[0022] Here, we consider the drain leakage current in the semiconductor device 1 according to the first embodiment. When the gate voltage Vgs relative to the source is less than or equal to the threshold voltage Vth, the FET is in an off state, and as shown in Figure 1(a), the 2DEG layer 105 does not occur below the first P-type GaN layer 113 and the second P-type GaN layer 123. Also, as shown in Figures 1(c) and 1(d), although no clear carriers remain at the interface 180 between the first active region 110 and the inactive region 190, a leakage path is generated through crystal defects caused by ion implantation, etc. A leakage current flows through this leakage path in the off state where a high electric field is generated. On the other hand, as shown in Figure 1(d), in the first active region 110 below the third nitride semiconductor layer 131 containing P-type impurities, the 2DEG layer 105 disappears due to the depletion layer generated from the P-type third nitride semiconductor layer 131 in the off state. Therefore, the leakage path generated at the interface 180 between the 2DEG layer 105 located below the first drain electrode 112 and the first source electrode 111 ceases to connect as a current path in the off state. As a result, the drain leakage current can be significantly suppressed compared to conventional examples.

[0023] Figure 2 shows box plots of the drain leakage current of a semiconductor device according to the conventional example and the embodiment. In the semiconductor device according to this embodiment, a reduction in drain leakage current of about an order of magnitude is observed compared to the conventional example.

[0024] Figure 3 shows another example of the semiconductor device in the first embodiment. In the first embodiment, as shown in the plan view of Figure 3(a), a third gate electrode 132 may be formed on the third nitride semiconductor layer 131, and the third gate electrode 132 may be connected to the first gate electrode 114 and the second gate electrode 124. Figure 3(b) shows a cross-sectional view of AA in Figure 3(a). Figure 3(c) shows the BB cross-section of Figure 3(a). Figure 3(d) shows the CC cross-section of Figure 3(a). With this configuration, as shown in Figure 3(d), the potential of the third nitride semiconductor layer 131 is stabilized by the third gate electrode 132, and the generation of the 2DEG layer 105 in the first active region 110 below the third nitride semiconductor layer 131 is reliably suppressed, thereby reliably preventing high voltage leakage.

[0025] In the first embodiment, as shown in Figure 1(a), it is desirable to form an inert region 190 as a first inert region between the first active region 110 where the first FET 11 is formed and the second active region 120 where the second FET 12 is formed. The inert region 190 as the first inert region is surrounded by the first active region 110, the second active region 120, and the third active region 130 in a plan view with respect to the substrate 101. By doing so, the heat-generating region of the FET can be separated and the temperature rise of the semiconductor device can be suppressed.

[0026] Figure 4 shows another example of the semiconductor device in the first embodiment. In the first embodiment, as shown in the plan view of Figure 4(a), the finger-shaped first P-type GaN layer 113 may be terminated inside the first active region 110, and the second P-type GaN layer 123 may be terminated inside the second active region 120. Alternatively, the third nitride semiconductor layer 131 may be connected to the first P-type GaN layer 113 and the second P-type GaN layer 123 inside the first active region 110, the second active region 120, and the third active region 130. Figure 4(b) shows a cross-sectional view of AA in Figure 4(a). Figure 4(c) shows the BB cross-section in Figure 4(a). Figure 4(d) shows the CC cross-section in Figure 4(a). As shown in Figure 4(d), the generation of the 2DEG layer 105 in the first active region 110 below the third nitride semiconductor layer 131 can be suppressed. In this way, the leakage path connecting the first drain electrode 112 to the first source electrode 111 via the 2DEG layer 105 is suppressed, and therefore the drain leakage current can be suppressed compared to the conventional example.

[0027] In the first embodiment, as shown in Figure 1(a), it is desirable that the longitudinal length La of the fingers of the first P-type GaN layer 113 (i.e., the length in the stretching direction) is longer than the length Lb of the third nitride semiconductor layer 131 (i.e., the length in the second direction). By doing so, parasitic capacitance generated between the third nitride semiconductor layer 131 and the first source electrode 111 and between the third nitride semiconductor layer 131 and the second source electrode 121 can be suppressed, and the increase in gate drive power can be suppressed.

[0028] In the first embodiment, it is desirable that the FET be normally off. Normally off means that Vth > 0[V], and at Vgs = 0[V], the 2DEG layer 105 does not occur below the first P-type GaN layer 113, the second P-type GaN layer 123, and the third nitride semiconductor layer 131. When the FET is normally off, the FET can be turned off by shorting the gate and source with a pull-down resistor or the like outside the FET, making it easy to protect the FET.

[0029] Figure 5 shows another example of the semiconductor device in the first embodiment. In the first embodiment, recess structures 117, 127, and 137 may be formed in the AlGaN barrier layer 104 below the first P-type GaN layer 113, the second P-type GaN layer 123, and the third nitride semiconductor layer 131, as shown in Figure 5(a) and Figure 5(b), which shows the AA cross-section of Figure 5(a). This makes the FET normally off. It is desirable that the recess structures 117 and 137 are formed continuously and connected, and that the recess structures 127 and 137 are formed continuously and connected. Figures 5(c) and 5(d) show the BB cross-section and CC cross-section of Figure 5(a), respectively. It is desirable that the recess structure 117 extends from the active region to the inactive region as shown in Figure 5(c), and that the recess structure 137 extends from the active region to the inactive region as shown in Figure 5(d). This structure effectively suppresses the leakage pathway through the interface 180 between the active and inactive regions.

[0030] Figure 6 shows another example of a semiconductor device in the first embodiment. In this example, as shown in Figure 6, when n is an integer of 2 or more, (n+1) (e.g., 3) first source electrodes 111, n (e.g., 2) first drain electrodes 112, 2 × n (e.g., 4) first P-type GaN layers 113 and a first gate electrode 114 are formed in the first active region 110, and (n+1) (e.g., 3) second source electrodes 121, n (e.g., 2) second drain electrodes 122, 2 × n (e.g., 4) second P-type GaN layers 123 and a second gate electrode 124 are formed in the second active region 120. This configuration allows for the formation of multiple source electrodes, drain electrodes, and gate electrodes in a finger-like shape within a single active region. This configuration makes it possible to simultaneously ensure the drain current capability of the FET and distribute the heat-generating area.

[0031] Here, of the (n+1) first source electrodes 111 constituting the FET 11, it is desirable that the (n-1) (e.g., one) first source electrode 111 sandwiched between the first drain electrode 112 be surrounded by the first P-type GaN layer 113 inside the first active region 110. Similarly, for the second FET 12, it is desirable that the (n-1) (e.g., one) second source electrode 121 sandwiched between the second drain electrode 122 of the (n+1) second source electrodes 121 be surrounded by the second P-type GaN layer 123 inside the second active region 120. By doing so, the leakage path of the drain leakage current connected to the source electrode sandwiched between the drain electrodes is eliminated, and the drain leakage current can be suppressed.

[0032] Figure 7 shows another example of a semiconductor device in the first embodiment. In the first embodiment, we will describe a third FET 14 formed in the fourth active region 140, which is a region where a two-dimensional electron gas is formed at both ends of the semiconductor device 1, among a plurality of arranged active regions. As shown in Figure 7(a), a finger-shaped third source electrode 141 and a third drain electrode 142 are formed in the fourth active region 140, and a third P-type GaN layer (an example of a third P-type nitride semiconductor layer) 143 and a third gate electrode 144 are extended from the fourth active region 140 across the interface between the fourth active region 140 and the inert region 190 to the inert region 190, thereby forming the fourth FET 14. The third source wiring 145 and the third drain wiring 146 correspond to the first source wiring 115 and the first drain wiring 116 in the first embodiment, respectively. Figure 7(b) shows the AA cross-section of Figure 7(a). In the FET 14 formed in the fourth active region 140, it is desirable that the third P-type GaN layer 143 located at the end in the direction in which multiple active regions are aligned surrounds the third source electrode 141 adjacent to the third P-type GaN layer 143 (i.e., located at the end in the second direction). Figure 7(c) shows the BB cross section of Figure 7(a), and Figure 7(d) shows the CC cross section of Figure 7(a). As shown in Figures 7(c) and 7(d), carriers remain at the interface 180 between the first active region 110 and the inert region 190, but as shown in Figure 7(d), the 2DEG layer 105 does not form in the first active region 110 below the third P-type GaN layer 143. In this way, the leakage path connecting the third drain electrode 142 to the third source electrode 141 via the 2DEG layer 105 is suppressed, and the drain leakage current of the third FET 14 formed at both ends of the semiconductor device 1 can be suppressed.

[0033] Furthermore, as shown in Figures 7(a) and 7(b), it is desirable that the electrode widths of the third source electrode 141 and the first source electrode 111 are equal. By using this configuration, the resistance of the source electrodes of the FETs 14 at both ends and the other FETs can be matched, the drain current flowing through each FET can be matched, and the concentration of heat generation in the FETs can be suppressed.

[0034] (Modification 1 of Embodiment 1) A first modification of the first embodiment will be described. Figure 8 shows an example of a semiconductor device in the first modification of the first embodiment. Figure 8(a) shows a plan view of the semiconductor device 1 according to the first modification of the first embodiment. A gate wiring 152 is formed between the first FET 11 formed in the first active region 110 and the second FET 12 formed in the second active region 120, and is connected to the third gate electrode 132 at both ends of the finger. The gate wiring 152 may also be connected to the gate aggregation wiring 174.

[0035] In the semiconductor device 1 according to the first modification of the first embodiment, it becomes possible to apply a gate voltage from both ends of the fingers of the first gate electrode 114 and the second gate electrode via the gate wiring 152 and the third gate electrode 132, thereby enabling high-speed switching of the FET.

[0036] In the first modified example of the first embodiment, it is desirable that the gate wiring 152 be formed on an inert region 190, which is a second inactive region, as shown in Figure 8(b), which is a cross-sectional view of AA in Figure 8(a). The inert region 190, which is a second inactive region, is formed between the first active region 110 and the second active region 120 in a plan view with respect to the substrate 101, and is surrounded by the first active region 110, the second active region 120 and the third active region 130. By doing so, the gate parasitic capacitance caused by the gate wiring 152 can be suppressed, and the increase in gate drive power can be suppressed.

[0037] In the first modified example of the first embodiment, the material of the gate wiring 152 is the same as that of the first gate electrode 114. By doing so, the formation process for the gate wiring 152 and the first gate electrode 114 can be made the same, and the gate wiring 152 can be easily formed.

[0038] In the first modification of the first embodiment, as shown in Figure 8(a), it is desirable that the length of the gate wiring 152 in the short-side direction is longer than the length of the first gate electrode 114 in the short-side direction. By doing so, the resistance per unit length of the gate wiring 152 can be reduced, and the switching of the FET can be made faster.

[0039] In the first modified example of the first embodiment, as shown in Figure 8(a), a third nitride semiconductor layer 151 containing P-type impurities is formed below the gate wiring 152. This suppresses the step difference between the gate wiring 152 and the third gate electrode 132, thereby suppressing disconnection of the gate wiring 152.

[0040] (Modification 2 of Embodiment 1) Figure 9 shows an example of a semiconductor device in a second modification of the first embodiment. In the second modification of the first embodiment, as shown in Figure 9(a), the gate wiring 152 is formed from the same material as the first source wiring 115. Figure 9(b) shows a cross-sectional view of AA in Figure 9(a). Generally, the resistance per unit length of the first source wiring 115 is lower than that of the first gate electrode 114. Therefore, by forming the gate wiring 152 from the same material as the first source wiring 115, the resistance of the gate wiring 152 can be reduced, and the switching of the FET can be made faster.

[0041] (Embodiment 2) A semiconductor device 1 according to a second embodiment will be described. Figure 10 shows a plan view of the semiconductor device 1 according to the second embodiment. Multiple first active regions 110 and second active regions 120 are formed spaced apart in the longitudinal direction of the finger. Between the multiple first active regions 110, an inert region 190 is formed as a third inert region, and between the multiple second active regions 120, an inert region 190 is formed as a fourth inert region. A first FET 11 is formed in each of the multiple first active regions 110, and a second FET 12 is formed in each of the multiple second active regions 120. Multiple third active regions 130 and a third nitride semiconductor layer 131 containing P-type impurities are formed spaced apart in the longitudinal direction of the finger, and within the first active region 110, the second active region 120, and the third active region 130, the third nitride semiconductor layer 131 is connected to the first P-type GaN layer 113 and the second P-type GaN layer 123.

[0042] In the semiconductor device 1 according to the second embodiment, a plurality of first source electrodes 111 are connected via a single first source wiring 115, a plurality of first drain electrodes 112 are connected via a single first drain wiring 116, a plurality of first P-type GaN layers 113 are extended and connected in the longitudinal direction of the fingers, and a plurality of first gate electrodes 114 are extended and connected in the longitudinal direction of the fingers. In addition, a plurality of second source electrodes 121 are connected via a single second source wiring 125, a plurality of second drain electrodes 122 are connected via a single second drain wiring 126, a plurality of second P-type GaN layers 123 are formed continuously in the longitudinal direction of the fingers, and a plurality of first gate electrodes 114 are formed continuously in the longitudinal direction of the fingers.

[0043] By forming the first FET 11 and the second FET 12 by dividing them in the longitudinal direction of the finger, the heat-generating regions of the FETs can be dispersed, thereby suppressing the temperature rise of the semiconductor device 1. Furthermore, by forming a plurality of third active regions 130 and third nitride semiconductor layers 131 between the first FET 11 and the second FET 12, which are formed by dividing them in the longitudinal direction of the finger, the increase in drain leakage current of each FET divided in the longitudinal direction of the finger can be suppressed.

[0044] In the semiconductor device 1 according to the second embodiment, multiple first source electrodes are connected by a single first source wire 115, and multiple first drain electrodes are connected by a single first drain wire 116. This reduces the parasitic resistance and capacitance of the source and drain wires, thereby suppressing heat generation in the FET.

[0045] Furthermore, in the semiconductor device 1 according to the second embodiment, as shown in Figure 10, the first P-type GaN layer 113 is extended and connected in the longitudinal direction of the finger, and the first gate electrode 114 is formed on the first P-type GaN layer 113, eliminating the step of the first gate electrode 114 and improving the reliability of the first gate electrode 114.

[0046] (Embodiment 3) A semiconductor device according to the third embodiment will be described. Figure 11 is a diagram showing an example of a semiconductor device in the third embodiment. Figure 11(a) shows a plan view of the semiconductor device 2 according to the third embodiment. Figure 11(b) shows a cross-section AA of Figure 11(a). The semiconductor device 2 has a first active region 210, a second active region 220, and a third active region 230 formed therein.

[0047] A first double-gate FET 21 is formed by the following: a finger-shaped first source electrode 211 and a second source electrode 212 are formed within a first active region 210; a first P-type GaN layer (an example of a first P-type nitride semiconductor layer) 213 and a first gate electrode 214 extend across the interface between the first active region 210 and the inactive region 290 to the inactive region 290; and a second P-type GaN layer (an example of a second P-type nitride semiconductor layer) 215 and a second gate electrode 216 extend across the interface between the first active region 210 and the inactive region 290 to the inactive region 290.

[0048] A second double-gate FET 22 is formed by the following: a finger-shaped third source electrode 221 and a fourth source electrode 222 are formed within the second active region 220; a third P-type GaN layer (an example of a third P-type nitride semiconductor layer) 223 and a third gate electrode 224 extend across the interface between the second active region 220 and the inactive region 290 to the inactive region 290; and a fourth P-type GaN layer (an example of a fourth P-type nitride semiconductor layer) 225 and a fourth gate electrode 226 extend across the interface between the second active region 220 and the inactive region 290 to the inactive region 290.

[0049] A third double-gate FET 23 is formed by the following: a finger-shaped fifth source electrode 231 and a sixth source electrode 232 are formed within the third active region 230; a fifth P-type GaN layer (an example of a fifth P-type nitride semiconductor layer) 233 and a fifth gate electrode 234 extend across the interface between the third active region 230 and the inactive region 290 to the inactive region 290; and a sixth P-type GaN layer (an example of a sixth P-type nitride semiconductor layer) 235 and a sixth gate electrode 236 extend across the interface between the third active region 230 and the inactive region 290 to the inactive region 290. Here, the first active region 210, the second active region 220, and the third active region 230 are each formed in the direction of the short side of the finger, and inactive regions 290 are formed between the first active region 210 and the second active region 220, and between the second active region 220 and the third active region 230.

[0050] The first source electrode 211, the third source electrode 221, and the fifth source electrode 231 are connected to the first source aggregation wiring 277 via the first source wiring 217, the third source wiring 227, and the fifth source wiring 237, respectively; the second source electrode 212, the fourth source electrode 222, and the sixth source electrode 232 are connected to the second source aggregation wiring 278 via the second source wiring 218, the fourth source wiring 228, and the sixth source wiring 238, respectively; the first gate electrode 214, the third gate electrode 224, and the fifth gate electrode 234 are connected to the first gate aggregation wiring 274; and the second gate electrode 216, the fourth gate electrode 226, and the sixth gate electrode 236 are connected to the second gate aggregation wiring 276, respectively. Thus, the first double-gate FET 21, the second double-gate FET 22, and the third double-gate FET 23 are connected in parallel.

[0051] In the semiconductor device 2 according to the third embodiment, as shown in Figure 11(a), a fourth active region 240 is formed at both longitudinal ends of the finger between the first double-gate FET 21 and the second double-gate FET 22, and the fourth active region 240 connects the first active region 210 and the second active region 220. A third nitride semiconductor layer 241 containing P-type impurities is formed on the fourth active region 240, and the third nitride semiconductor layer 241 is connected to the second P-type GaN layer 215 and the fourth P-type GaN layer 225 within the first active region 210, the second active region 220, and the fourth active region 240. Furthermore, a fifth active region 250 is formed at both longitudinal ends of the finger between the second double-gate FET 22 and the third double-gate FET 23, where a two-dimensional electron gas is formed. The fifth active region 250 connects the second active region 220 and the third active region 230. A fourth nitride semiconductor layer 251 containing P-type impurities is formed on the fifth active region 250, and within the second active region 220, the third active region 230, and the fifth active region 250, the fourth nitride semiconductor layer 251 is connected to the third P-type GaN layer 223 and the fifth P-type GaN layer 233.

[0052] Here, the operation of the FET will be described using the second double-gate FET 22 as an example. When the voltage Vgs1 of the third gate electrode 224 relative to the third source electrode 221 is less than or equal to the threshold voltage Vth, the double-gate FET 22 will be in the off state if the voltage of the fourth source electrode 222 is higher than that of the third source electrode 221. Also, since the fourth nitride semiconductor layer 251 is connected to the third P-type GaN layer 223, a 2DEG layer 205 does not occur in the second active region 220 below the fourth nitride semiconductor layer 251. In this way, the leakage path connecting the fourth source electrode 222 to the third source electrode 221 via the 2DEG layer 205 is suppressed, and therefore, when the voltage of the fourth source electrode 222 is higher than that of the third source electrode 221, the leakage current flowing from the fourth source electrode 222 can be suppressed. On the other hand, when the voltage Vgs2 of the fourth gate electrode 226 relative to the fourth source electrode 222 is less than or equal to the threshold voltage Vth, the double-gate FET 22 is turned off when the voltage of the third source electrode 221 is higher than that of the fourth source electrode 222. Also, since the third nitride semiconductor layer 241 is connected to the fourth P-type GaN layer 225, the 2DEG layer 205 does not form in the second active region 220 below the third nitride semiconductor layer 241. In this way, the leakage path connecting the third source electrode 221 to the fourth source electrode 222 via the 2DEG layer 205 is suppressed, and therefore, when the voltage of the third source electrode 221 is higher than that of the fourth source electrode 222, the leakage current flowing from the third source electrode 221 can be suppressed. Thus, the semiconductor device 2 according to the third embodiment can suppress bidirectional leakage current.

[0053] In the semiconductor device 2 according to the third embodiment, a seventh gate electrode 242 is formed on the third nitride semiconductor layer 241, and the seventh gate electrode 242 is connected to the second gate electrode 216 and the fourth gate electrode 226. Alternatively, an eighth gate electrode 252 may be formed on the fourth nitride semiconductor layer 251, and the eighth gate electrode 252 is connected to the third gate electrode 224 and the fifth gate electrode 234. With such a configuration, the potential between the third nitride semiconductor layer 241 and the fourth nitride semiconductor layer 251 is stabilized, and bidirectional leakage current can be reliably prevented. [Industrial applicability]

[0054] The semiconductor device described herein can be used in switching power supply circuits that operate at high voltage and high frequency. [Explanation of symbols]

[0055] 1 Semiconductor device 101 circuit board 102 Buffer Layer 103 GaN channel layer (an example of the first nitride semiconductor layer) 104 AlGaN barrier layer (an example of a second nitride semiconductor layer) 105 2DEG layer 11. First FET (First Field-Effect Transistor) 110 First active region 111 First source electrode 112 First drain electrode 113 First P-type GaN layer (an example of a first P-type nitride semiconductor layer) 114 First gate 115 First source wiring 116 First drain wiring 117 Recessed structure 12. The second FET (second field-effect transistor) 120 Second active region 121 Second source electrode 122 Second drain electrode 123 Second P-type GaN layer (an example of a second P-type nitride semiconductor layer) 124 Second gate electrode 125 Second source wiring 126 Second drain wiring 127 Recessed structure 130 Third active region 131 Third nitride semiconductor layer containing P-type impurities 132 Third gate 137 Recessed structure 14. The third FET 140 Fourth active region 141 Third source electrode 142 Third drain electrode 143 Third P-type GaN layer (an example of a third P-type nitride semiconductor layer) 144 Third Gate 145 Third source wiring 146 Third drain wiring 151 Third nitride semiconductor layer containing P-type impurities 152 Gate Wiring 174 Gate-to-Gate Wiring 175 Source Consolidation Wiring 176 Drain Consolidation Wiring 180 Interface between active and inactive regions 190 Inactive area 2 Semiconductor devices 205 2DEG layer 21. First double-gate FET 210 First active region 211 First source electrode 212 Second source electrode 213 First P-type GaN layer (an example of a first P-type nitride semiconductor layer) 214 First gate electrode 215 Second P-type GaN layer (an example of a second P-type nitride semiconductor layer) 216 Second gate electrode 217 First source wiring 218 Second source wiring 22. Second Double-Gate FET 220 Second active region 221 Third source electrode 222 Fourth source electrode 223 Third P-type GaN layer (an example of a third P-type nitride semiconductor layer) 224 Third Tetragrammal Thread 225. Fourth P-type GaN layer (an example of a fourth P-type nitride semiconductor layer) 226 The fourth gate electrode 227 Third source wiring 228 Fourth source wiring 23. The third type of double-gate FET 230 Third active region 231 Fifth source electrode 232 Sixth source electrode 233. Fifth P-type GaN layer (an example of a fifth P-type nitride semiconductor layer) 234 The fifth gate 235. The sixth P-type GaN layer (an example of the sixth P-type nitride semiconductor layer) 236 Sixth Term Indicator 237 Fifth source wiring 238 Sixth source wiring 240 Fourth active region 241 Third nitride semiconductor layer containing P-type impurities 242 The 7th Gate 250 Fifth active region 251 Fourth nitride semiconductor layer containing P-type impurities 252 Eighth gate electrode 274 First gate aggregation wiring 276 Second gate aggregation wiring 277 First source aggregation wiring 278 Second source aggregation wiring 290 Inactive area

Claims

1. circuit board and A first nitride semiconductor layer formed on the substrate, A second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer and formed on the first nitride semiconductor layer, The first field-effect transistor and It comprises a second field-effect transistor, The first nitride semiconductor layer and the second nitride semiconductor layer have, in a plan view with respect to the substrate, a first active region where a two-dimensional electron gas is formed, a second active region, and an inactive region where a two-dimensional electron gas is not formed. The first field-effect transistor comprises a first source electrode and a first drain electrode included in the first active region in a plan view with respect to the substrate and extending in a first direction in a plan view with respect to the substrate, a first P-type nitride semiconductor layer extending in the first direction between the first source electrode and the first drain electrode in a plan view with respect to the substrate, and a first gate electrode formed on the first P-type nitride semiconductor layer. The second field-effect transistor comprises a second source electrode and a second drain electrode included in the second active region in a plan view with respect to the substrate and extending in the first direction in a plan view with respect to the substrate, a second P-type nitride semiconductor layer extending in the first direction between the second source electrode and the second drain electrode in a plan view with respect to the substrate, and a second gate electrode formed on the second P-type nitride semiconductor layer. The first nitride semiconductor layer and the second nitride semiconductor layer further have a third active region at both ends of the first active region and the second active region in the first direction, connected to the first active region and the second active region in a second direction different from the first direction in a plan view with respect to the substrate, where a two-dimensional electron gas is formed. The third active region includes a third nitride semiconductor layer having p-type impurities that extends in the second direction. Within the first active region, the second active region, and the third active region, the first p-type nitride semiconductor layer and the second p-type nitride semiconductor layer are connected via the third nitride semiconductor layer. In a plan view of the substrate, the first inactive region is formed as part of the inactive region between the first active region and the second active region. In a plan view of the substrate, the first inactive region is surrounded by the first active region, the second active region, and the third active region. Semiconductor equipment.

2. A third gate electrode is formed on the third nitride semiconductor layer. The first gate electrode and the second gate electrode are connected via the third gate electrode. The semiconductor device according to claim 1.

3. The third nitride semiconductor layer extends to the inert region. The semiconductor device according to claim 1 or 2.

4. The length of the first P-type nitride semiconductor layer in the stretching direction is longer than the length of the third nitride semiconductor layer in the second direction. The semiconductor device according to any one of claims 1 to 3.

5. When the potential difference of the first gate electrode with respect to the first source electrode is 0V, and the potential difference of the second gate electrode with respect to the second source electrode is 0V, a two-dimensional electron gas is not formed in the first active region below the first P-type nitride semiconductor layer, the second active region below the second P-type nitride semiconductor layer, and the third active region below the third nitride semiconductor layer. A semiconductor device according to any one of claims 1 to 4.

6. Recesses are formed in the second nitride semiconductor layer below the first p-type nitride semiconductor layer and the third nitride semiconductor layer. The semiconductor device according to claim 5.

7. The recess formed in the lower part of the third nitride semiconductor layer extends to the inert region. The semiconductor device according to claim 6.

8. When n is an integer greater than or equal to 2, The first source electrode has (n+1) elements, The first drain electrode has n electrodes, The first P-type nitride semiconductor layer consists of (2 × n) layers. The first gate electrode has (2 × n) elements, The second source electrode has (n+1) elements, The aforementioned second drain electrode has n electrodes, The second P-type nitride semiconductor layer consists of (2 × n) layers. The second gate electrode has (2 × n) elements, A semiconductor device according to any one of claims 1 to 7.

9. Of the (n+1) first source electrodes, the first source electrode sandwiched between the first drain electrodes is surrounded by the first P-type nitride semiconductor layer within the first active region. Of the (n+1) second source electrodes, the second source electrode sandwiched between the second drain electrodes is surrounded by the second P-type nitride semiconductor layer within the second active region. The semiconductor device according to claim 8.

10. The first nitride semiconductor layer and the second nitride semiconductor layer further have a fourth active region formed at both ends of the extension line in the second direction, separated from the first active region and the second active region in a plan view with respect to the substrate, where a two-dimensional electron gas is formed. The fourth active region described above includes: A third source electrode and a third drain electrode extending in the first direction in a plan view with respect to the substrate, A third P-type nitride semiconductor layer, extending in the first direction in a plan view with respect to the substrate, is located between the third source electrode and the third drain electrode. A fourth gate electrode is formed on the third P-type nitride semiconductor layer, Within the fourth active region, The third P-type nitride semiconductor layer located at the end in the second direction surrounds the third source electrode located at the end in the second direction. The semiconductor device according to claim 1.

11. The width of the third source electrode and the width of the first source electrode are equal. The semiconductor device according to claim 10.

12. In a plan view of the substrate, a gate wiring is formed between the first field-effect transistor and the second field-effect transistor. The gate wiring is electrically connected to the third gate electrode. The semiconductor device according to claim 2.

13. In a plan view of the substrate, a second inactive region is formed between the first active region and the second active region as part of the inactive region. In a plan view of the substrate, the second inactive region is surrounded by the first active region, the second active region, and the third active region. The gate wiring is formed on the second inert region. The semiconductor device according to claim 12.

14. The length of the gate wiring in the short-side direction is longer than the length of the first gate electrode in the short-side direction. The semiconductor device according to claim 12 or 13.

15. The first source wiring is electrically connected to the first source electrode, The electrode material of the gate wiring is the same as the electrode material of the first source wiring. A semiconductor device according to any one of claims 12 to 14.

16. Multiple unit cells, each consisting of a first field-effect transistor formed in the first active region, a second field-effect transistor formed in the second active region, and a third nitride semiconductor layer formed in the third active region, are formed spaced apart in the first direction. The multiple first source electrodes, each spaced apart, are connected by a single first source wire. Multiple spaced-apart first drain electrodes are connected by a single first drain wire. Multiple of the first P-type nitride semiconductor layers are connected in the first direction, Multiple first gate electrodes are each connected in the first direction, The multiple spaced-apart second source electrodes are connected by a single second source wire. Multiple spaced-apart second drain electrodes are connected by a single second drain wire. Multiple of the second P-type nitride semiconductor layers are connected in the first direction, Each of the multiple second gate electrodes is connected in the first direction. The semiconductor device according to claim 1.

17. Between the multiple first active regions formed in the first direction, a third inactive region is formed as part of the inactive region. Between the multiple second active regions formed in the first direction, a fourth inactive region is formed as part of the inactive region. The semiconductor device according to claim 16.

18. circuit board and A first nitride semiconductor layer formed on the substrate, A second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer and formed on the first nitride semiconductor layer, The first double-gate field-effect transistor and The second double-gate field-effect transistor, It comprises a third double-gate field-effect transistor, The first nitride semiconductor layer and the second nitride semiconductor layer have, in a plan view with respect to the substrate, a first active region, a second active region, a third active region where a two-dimensional electron gas is formed, and an inactive region where a two-dimensional electron gas is not formed. The first double-gate field-effect transistor comprises a first source electrode and a second source electrode included in the first active region and extending in a first direction in a plan view with respect to the substrate; a first P-type nitride semiconductor layer and a second P-type nitride semiconductor layer formed spaced apart between the first source electrode and the second source electrode and extending in the first direction in a plan view with respect to the substrate; a first gate electrode formed on the first P-type nitride semiconductor layer; and a second gate electrode formed on the second P-type nitride semiconductor layer. The second double-gate field-effect transistor comprises a third source electrode and a fourth source electrode included in the second active region and extending in the first direction in a plan view with respect to the substrate; a third P-type nitride semiconductor layer and a fourth P-type nitride semiconductor layer formed spaced apart between the third source electrode and the fourth source electrode and extending in the first direction in a plan view with respect to the substrate; a third gate electrode formed on the third P-type nitride semiconductor layer; and a fourth gate electrode formed on the fourth P-type nitride semiconductor layer. The third double-gate field-effect transistor comprises a fifth source electrode and a sixth source electrode included in the third active region and extending in the first direction in a plan view with respect to the substrate; a fifth p-type nitride semiconductor layer and a sixth p-type nitride semiconductor layer formed spaced apart between the fifth source electrode and the sixth source electrode and extending in the first direction in a plan view with respect to the substrate; a fifth gate electrode formed on the fourth p-type nitride semiconductor layer; and a sixth gate electrode formed on the sixth p-type nitride semiconductor layer. The first nitride semiconductor layer and the second nitride semiconductor layer further have, in a plan view with respect to the substrate, rectangles extending in a second direction different from the first direction at both ends of the first active region and the second active region in the first direction, and a fourth active region connecting the first active region and the second active region, where a two-dimensional electron gas is formed. The fourth active region includes a third nitride semiconductor layer having p-type impurities that extend in the second direction in a plan view with respect to the substrate. Within the first active region, the second active region, and the fourth active region, the second p-type nitride semiconductor layer and the fourth p-type nitride semiconductor layer are connected via the third nitride semiconductor layer. The first nitride semiconductor layer and the second nitride semiconductor layer further have, in a plan view with respect to the substrate, a fifth active region extending in the second direction at both ends of the second active region and the third active region in the first direction, connecting the second active region and the third active region, and where a two-dimensional electron gas is formed. The fifth active region includes a fourth nitride semiconductor layer having P-type impurities that extend in the second direction in a plan view with respect to the substrate. Within the second, third, and fifth active regions, the third p-type nitride semiconductor layer and the fifth p-type nitride semiconductor layer are connected via the fourth nitride semiconductor layer. In a plan view of the substrate, the first inactive region is formed as part of the inactive region between the first active region and the second active region. In a plan view of the substrate, the first inactive region is surrounded by the first active region, the second active region, and the fourth active region. In a plan view of the substrate, the second inactive region is formed as part of the inactive region between the second active region and the third active region. In a plan view of the substrate, the second inert region is surrounded by the second active region, the third active region, and the fifth active region. Semiconductor equipment.

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