Method for generating a semiconductor structure having an interface region containing aggregates

Abstract

The present invention relates to a method for producing a semiconductor structure, comprising: a) providing a processing layer made of a semiconductor material; b) providing a carrier substrate made of a semiconductor material; c) depositing a film made of a semiconductor material different from the semiconductor materials of the processing layer and the carrier substrate and having a thickness of less than 50 nm on the free surface to be bonded of the processing layer and / or on the free surface to be bonded of the carrier substrate; d) forming an intermediate structure, the forming step comprising directly bonding the free surfaces to be bonded of the processing layer and the carrier substrate, respectively, along a bonding interface extending along a main surface, the intermediate structure comprising an encapsulated film resulting from one or more films deposited in c); e) annealing the intermediate structure at a temperature equal to or greater than a critical temperature, resulting in segmentation of the encapsulated film, to form a semiconductor structure with an interface region between the processing layer and the carrier substrate, the interface region comprising an area of ​​direct contact between the processing layer and the carrier substrate and aggregates comprising the semiconductor material of the film and having a thickness of less than 250 nm along an axis perpendicular to the main surface, the area of ​​direct contact and the aggregates being adjacent in the main surface.

Description

[Technical Field]

[0001] The present invention relates to the field of semiconductor materials for microelectronic components. In particular, the present invention relates to a method for producing a structure including a processed semiconductor layer and a semiconductor carrier substrate joined at an interface region, wherein at the interface region, a region of direct contact between the layer and the carrier substrate and an aggregate containing semiconductor materials other than the semiconductor materials of the layer and the carrier substrate coexist side by side. [Background technology]

[0002] It is common practice to form semiconductor structures by transferring a thin, high-crystal-quality processed semiconductor layer onto a semiconductor carrier substrate with lower crystal-quality. A well-known thin-layer transfer solution is the Smart Cut® method, which is based on the implantation of light ions and assembly by direct bonding at the bonding interface. In addition to the economic advantages associated with the rationalization of high-quality material in the processed layer, the semiconductor structure can also offer advantageous properties, for example, due to the thermal conductivity or electrical conductivity or mechanical compatibility of the carrier substrate.

[0003] For example, in the field of power electronics, it can be advantageous to establish electrical conductivity between the processed layer and the carrier substrate in order to form vertical components. For instance, in a structure containing a processed layer made of single-crystal silicon carbide and a carrier substrate made of lower-quality silicon carbide (single-crystal or polycrystalline), the bonding interface must have the lowest possible resistivity, preferably 1 mΩ·cm. 2 Less than 0.1 mΩ·cm 2 It is less than.

[0004] In other fields, even when high vertical conductivity is not required, direct contact between the processed layer and the carrier substrate is necessary to ensure electrical and / or thermal continuity and / or very strong cohesive or mechanical strength.

[0005] Prior art solutions propose semiconductor-semiconductor bonding through molecular adsorption between the processed layer and the carrier substrate. However, it is then necessary to control the native oxide layer at the bonding interface, as this layer prevents direct contact between the processed layer and the carrier substrate. In particular, while it is possible to generate hydrophobic bonds, achieving good interface quality from this remains challenging.

[0006] F. Mu et al. (ECS Transactions, 86(5)3-21, 2018) have performed direct bonding after activation of the bonding surface by argon impact (SAB stands for "Surface Activation Bonding"). Such pre-bonding treatment generates a very high-density dangling bond, which promotes the formation of covalent bonds at the assembly interface and therefore high bonding energy. Nevertheless, this method has the disadvantage of generating an amorphous layer on the bonded surface, which particularly negatively affects perpendicular electrical conductivity between the thin layer and the carrier substrate. To overcome this problem, high-concentration doping of the surface has been proposed, particularly in European Patent No. 3168862.

[0007] (Purpose of the invention) The present invention relates to an alternative solution to a prior art solution and aims to improve all or part of the aforementioned shortcomings. In particular, the present invention relates to a method for producing a structure comprising a processed semiconductor layer and a semiconductor carrier substrate bonded at an interface region including a region of direct contact between the layer and the carrier substrate, and an aggregate comprising a semiconductor material different from the semiconductor material of the layer and the support substrate.

[0008] (Brief description of the invention) The present invention relates to a method for generating a semiconductor structure, and the method is a) To provide a processed layer made of a semiconductor material having a free surface to be bonded, a) To provide a carrier substrate made of a semiconductor material having a free surface to be bonded, c) A film composed of a semiconductor material different from the semiconductor material of the processed layer and the carrier substrate, having a thickness of less than 50 nm, is formed on the free surface to which the processed layer is bonded and / or on the free surface to which the carrier substrate is bonded. d) forming an intermediate structure, which includes directly joining the free surfaces to be joined of the processed layer and the carrier substrate along a bonding interface extending along the main surface, wherein the intermediate structure includes an embedded film resulting from one or more films formed in step c), e) Annealing the intermediate structure at a temperature above the critical temperature to bring about segmentation of the encapsulated film and form a semiconductor structure having an interface region between the processed layer and the carrier substrate, wherein the interface region is - The area of ​​direct contact between the processed layer and the carrier substrate, - An aggregate comprising a film semiconductor material and having a thickness of 250 nm or less along an axis perpendicular to the main surface, Including, The regions in direct contact and the aggregates are adjacent within the main plane.

[0009] According to other advantageous non-limiting features of the present invention, either alone or in any technically feasible combination, In step a), the free surface to which the processed layer is joined contains native oxide, and / or in step b), the free surface to which the carrier substrate is joined contains native oxide. In step e), the aggregates in the interface region take in oxygen generated from native oxides, Step a) includes injecting a light seed into the donor substrate to form an embedded brittle surface that demarcates the processed layer together with the front surface of the donor substrate. Step a) includes the formation of a donor substrate by epitaxy of a donor layer on an initial substrate, followed by injection within the donor layer. Step d) involves separation at an embedded fragile surface to form an intermediate structure on the one hand, including a processed layer, an encapsulated film, and a carrier substrate, after direct bonding which results in a bonded assembly including a donor substrate and a carrier substrate, and on the other hand, to form the rest of the donor substrate. The thickness of the film deposited in step c) is 10 nm or less, or 5 nm or less, or 3 nm or less, or 2 nm or less. • In step c), the thickness of the film deposited is less than 10 nm, and the aggregate has a thickness of 50 nm or less along the axis perpendicular to the main surface. The critical temperature is 500°C to 1800°C, depending on the properties of the semiconductor material of the film, as well as the properties of the semiconductor materials of the processed layer and carrier substrate. The semiconductor material of the processed layer is silicon carbide, and has a single-crystal structure, a polycrystalline structure, or an amorphous structure. The semiconductor material of the carrier substrate is silicon carbide, and has a single-crystal structure, a polycrystalline structure, or an amorphous structure. The semiconductor material of the film is selected from silicon or germanium. • The aggregates have a thickness of 40 nm or less, or even less than 30 nm. The aggregate is in the form of a cavity lined with a first precipitate containing the semiconductor material of the membrane, a second precipitate containing the semiconductor material of the membrane and oxygen, and / or a compound containing the semiconductor material of the membrane and oxygen. The second precipitate has a substantially triangular shape in a cross-section perpendicular to the main surface. The aggregate has a transverse dimension of 5 nm to 500 nm on its main surface.

[0010] The present invention also relates to electronic components that are generated on and / or within the processed layer of a semiconductor structure obtained by the aforementioned generation method. The semiconductor structure is -A processed layer made of semiconductor material and extending across the main surface, - Carrier substrate made of semiconductor material, - An interface region between a processed layer and a carrier substrate extending parallel to the main surface, the interface region comprising a region of direct contact between the processed layer and the carrier substrate, and an aggregate comprising a semiconductor material different from the semiconductor materials of the processed layer and the carrier substrate, having a thickness of 250 nm or less along an axis perpendicular to the main surface, wherein the region of direct contact and the aggregate are adjacent on the main surface.

[0011] According to a specific modification example, for power applications, the component includes at least one electrical contact on and / or within the carrier substrate on the back surface of the semiconductor structure.

Brief Description of the Drawings

[0012] Other features and advantages of the present invention will become apparent from the following detailed description of the present invention with reference to the accompanying drawings.

[0013] [Figure 1] It is a diagram showing a carrier substrate according to the present invention. [Figure 2a] It is a diagram showing steps of a generation method according to the present invention. [Figure 2b] It is a diagram showing steps of a generation method according to the present invention. [Figure 2c] It is a diagram showing steps of a generation method according to the present invention. [Figure 2d] It is a diagram showing steps of a generation method according to the present invention. [Figure 2e] It is a diagram showing steps of a generation method according to the present invention. [Figure 3a] It is a diagram showing a modification example of steps of a generation method according to the present invention. [Figure 3b] It is a diagram showing a modification example of steps of a generation method according to the present invention. [Figure 3c] It is a diagram showing a modification example of steps of a generation method according to the present invention. [Figure 3d] It is a diagram showing a modification example of steps of a generation method according to the present invention. [Figure 4a] Graph I(V) (current as a function of voltage) comparing the electrical characteristics of the interface region of the semiconductor structure according to the present invention with the electrical characteristics of the solid substrate for different-sized electrode patterns, respectively, and a diagram showing the arrangement of electrodes on the structure for performing such measurements. [Figure 4b]The figures show a graph I(V) (current as a function of voltage) comparing the electrical properties of the interface region of the semiconductor structure according to the present invention with those of the solid substrate for electrode patterns of different sizes, and the arrangement of electrodes on the structure for performing such measurements.

[0014] The same symbols in the diagram may be used for elements of the same type. The diagram is a schematic and is not to scale for readability. In particular, the layer thickness along the z-axis is not to scale with respect to the lateral dimensions along the x and y axes, and the relative thickness of the layers is not reflected in the diagram. [Modes for carrying out the invention]

[0015] The present invention relates to a method for generating a semiconductor structure 100 comprising a processed layer 10 made of a single-crystal semiconductor material, a carrier substrate 30 made of a semiconductor material, and an interface region 20 between the processed layer 10 and the carrier substrate 30 (Figure 1). Similar to the processed layer 10, the interface region 20 extends parallel to the main plane (x,y).

[0016] Advantageously, as is typical in the field of microelectronics, the semiconductor structure 100 is in the form of a circular wafer with a diameter of 100 mm to 450 mm and an overall thickness typically of 300 microns to 1000 microns. In this case, it is understood that the carrier substrate 30 and the processed layer 10 also have such a circular shape. The front surface 100a and back surface 100b of the wafer extend parallel to the main plane (x,y).

[0017] Many types of semiconductor structures 100 that enable vertical electrical conduction or direct contact between the processed layer 10 and the carrier substrate 30 may be of interest for microelectronics applications. Therefore, the properties of the materials constituting the processed layer 10 and the carrier substrate 30 can be very diverse.

[0018] For example, the semiconductor material of the processed layer 10 may be selected from silicon carbide, silicon, gallium nitride, gallium arsenide, indium phosphide, and silicon-germanium alloys. In general, the production of components on the processed layer 10 requires high crystal quality of the layer 10. Therefore, it is preferentially selected to be a single crystal with a quality grade, type, and doping level suitable for the intended application. Alternatively, the processed layer 10 may, of course, have a polycrystalline or amorphous structure.

[0019] Again, as an example, the semiconductor material of the carrier substrate 30 can be selected from silicon carbide, silicon, gallium nitride, gallium arsenide, indium phosphide, and silicon-germanium alloys. It is preferred, for essentially economic reasons, to have lower levels of quality and single-crystal, polycrystalline, or amorphous structures. Its type and doping level are selected according to the intended application.

[0020] The production method first includes step a) providing a processed layer 10 made of a semiconductor material, preferably a single crystal (Figure 2a). In step a), the processed layer 10 has a free surface 10a, also called a front surface 10a, which is intended to be bonded during subsequent steps of the method, and it also has a back surface 10b on the opposite side of its front surface 10a.

[0021] According to an advantageous embodiment, the processed layer 10 is obtained by transferring the surface layer of the donor substrate 1, particularly by layer transfer based on the Smart Cut® method.

[0022] Therefore, step a) may include injecting a light species, such as hydrogen, helium, or a combination of these two species, into the donor substrate 1 to form an embedded fragile surface 11 that demarcates the processed layer 10 together with the front surface 10a of the donor substrate 1 (Figure 3a).

[0023] According to a variation of this embodiment, step a) includes forming a donor substrate 1 by epitaxy of a donor layer onto an initial substrate before injecting a light seed (Figure 3b). This variation makes it possible to form a donor layer having the structural and electrical properties required for the intended application. In particular, excellent crystal quality can be obtained by epitaxy, and precise control of in-situ doping of the donor layer is possible. Injection of a light seed is then carried out in the donor layer 1' to form an embedded brittle surface 11.

[0024] Alternatively, the processed layer 10 provided in step a) may, of course, be formed from other known thin-film transfer techniques.

[0025] Next, the production method according to the present invention includes step b) providing a carrier substrate 30 made of a semiconductor material (Figure 2b). The carrier substrate 30 has a free surface 30a, also called the front surface 30a, which is intended to be bonded during the subsequent steps of the method, and it also has a back surface 30b.

[0026] The processed layer 10 and the carrier substrate 30 may be formed from one or more materials selected from the materials described above.

[0027] Next, the production method includes step c) forming a film 2 made of a semiconductor material (referred to as the second material) on the free surface 10a of the processed layer 10 to be bonded, or on the free surface 30a of the carrier substrate 30 to be bonded, or even on both the free surfaces 10a and 30a to be bonded, as shown in Figure 2c. The second material is different from the semiconductor materials of the processed layer 10 and the carrier substrate 30.

[0028] Preferably, the second material is selected due to its special affinity for oxygen, and furthermore, it must produce solid and non-gaseous compounds by reacting with oxygen, rather than being a compound of some elements.

[0029] The second material must be able to be deposited in an extremely thin layer and must be suitable for a microelectronic component manufacturing line ("front-end of line"). It can be selected from silicon, germanium, etc., in particular, depending on the properties of the processed layer 10 and the carrier substrate 30.

[0030] Film 2 has a thickness of less than 50 nm, preferably 10 nm or less, 8 nm or less, 5 nm or less, and furthermore 3 nm or less, and even furthermore 2 nm or less. For example, the deposited film 2 may have a thickness of approximately 0.5 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 15 nm, 20 nm, 30 nm, or 40 nm.

[0031] When film 2 is deposited on two free surfaces 10a and 30a, it should be noted that the total film thickness, i.e., the sum of the thicknesses of film 2 deposited on one and the other free surfaces 10a and 30a, is preferably less than 50 nm, preferably 10 nm or less, 8 nm or less, and even 5 nm or less. The total thickness of the deposited film 2 is always kept low so that in subsequent steps of this method, the film can be segmented into aggregates 21.

[0032] Film 2 is deposited under a controlled atmosphere. Depending on the properties of the deposited film 2, step c) may be carried out at low temperatures or even at ambient temperature, advantageously by existing chemical vapor deposition techniques (plasma-induced: PECVD, reduced pressure: LPCVD), or by spray techniques using neutral elements or elements where the presence of residues in the deposited film is not a problem (Ar, Si, N, etc.) to impact the target.

[0033] Next, the production method includes step d) forming an intermediate structure 150, which includes joining the free surfaces 10a and 30a of the processed layer 10 and the carrier substrate 30 at a bonding interface 15 extending along the main surface (x,y) (Figure 2d).

[0034] This direct assembly is preferentially carried out by bonding by molecular adsorption, which involves bringing the surfaces to be joined 10a and 30a into contact without adding an intermediate adsorbent material. This may be a direct bond between the processed layer 10 and the film 2 if the film 2 is deposited only on the carrier substrate 30, or a direct bond between the carrier substrate 30 and the film 2 if the film 2 is deposited only on the processed layer 10, or further, a direct bond between the two films 2 if two films 2 are deposited on the processed layer 10 and the carrier substrate 30. Direct assembly is carried out in an ambient atmosphere or under a controlled atmosphere, particularly 10 -6 This can be carried out under high vacuum conditions of Pa or less.

[0035] Optionally, the film deposition in step c) and the direct assembly in step d) can be linked in situ or in a multi-chamber apparatus without breaking the vacuum. An example is the Canon Atomic Diffusion Bonding BV7000, which allows for continuous direct deposition and bonding while maintaining a controlled atmosphere.

[0036] Referring to the advantageous embodiments shown in Figures 3a to 3d, step d) involves direct bonding of the free surface 10a of the processed layer 10 to the free surface 30a of the carrier substrate 30 to be bonded, resulting in a bonded assembly 200 including the donor substrate 1, the carrier substrate 30, and the bonding interface 15 (Figure 3c). Step d) further includes separation at the embedded weak surface 11 to form an intermediate structure 150 including the processed layer 10, the film 2, and the carrier substrate 30 on the one hand, and the remainder of the donor substrate 1' on the other hand (Figure 3d). Such separation can be carried out during a heat treatment in which lenticular cavities ("platelets") and microcracks can be grown at the embedded weak surface 11 under pressure caused by the injected seed. Separation can also be carried out by applying mechanical stress, as is well known with reference to the Smart Cut® method, or by a combination of thermal and mechanical stress.

[0037] A sequence for cleaning, smoothing, polishing, or etching the separation surface 10b of the processed layer 10 and / or the separation surface 1''a of the remaining 1'' of the donor substrate can be operated to restore good surface quality, particularly with respect to roughness, defects, and other contamination.

[0038] Regardless of the embodiment of this method, at the end of step d), the intermediate structure 150 has a front surface 10b on the processed layer 10 side, a back surface 30b on the carrier substrate 30 side, and an enclosed film 2' between the processed layer 10 and the carrier substrate 30. Note that the enclosed film 2' corresponds to the film 2 when the film 2 is deposited on only one of the free surfaces 10a, 30a, or to two films 2 deposited on the processed layer 10 and the carrier substrate 30, respectively.

[0039] Next, the production method according to the present invention includes step e) annealing the intermediate structure 150 at a temperature above the critical temperature to result in segmentation of the encapsulated film 2' in the form of aggregates 21 and to form an interface region 20 (Figure 2e), wherein the interface region 20 is - The region 22 of direct contact between the processed layer 10 and the carrier substrate 30, in other words, the region where direct bonding exists between the semiconductor material of the processed layer 10 and the semiconductor material of the carrier substrate 30, -Includes a film 2 semiconductor material (second material) and aggregates 21 having a low or very low thickness along an axis z perpendicular to the main surface (x,y), i.e., 250 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or even 10 nm or less.

[0040] The aggregates 21 distributed in the interface region 20 are either unglued or unglued, and the unglued aggregates 21 are separated from each other by the direct contact region 22. The direct contact region 22 and the aggregates 21 are adjacent on the main surface (x,y).

[0041] As a result of step e), the semiconductor structure 100 is formed.

[0042] The term “critical temperature” is used to mean the energetically more favorable temperature at which the second material forms aggregates 21 rather than remaining in the form of a very fine encapsulated film 2'. On the other hand, the annealing temperature in step e) must be sufficient to allow bonding of the regions 22 of direct contact between the aggregates 21. The critical temperature is typically between 500°C and 1800°C, depending on the properties of the second material as well as the semiconductor materials of the processed layer 10 and the carrier substrate 30.

[0043] Therefore, the annealing step e) is always carried out at a temperature above this critical temperature and in a neutral atmosphere, particularly under argon, argon / hydrogen, or nitrogen.

[0044] When the critical temperature is exceeded, the system, which includes the encapsulated film 2' and the semiconductor surfaces of the processed layer 10 and carrier substrate 30 in contact with the film 2', optimizes its surface energy by segmenting the encapsulated film 2' into aggregates 21 and by creating regions 22 of direct contact between the respective semiconductor surfaces of the processed layer 10 and carrier substrate 30.

[0045] Furthermore, because the encapsulated film 2' is extremely thin, semiconductor materials known to be stable only at low or medium temperatures can be used as a second material in the semiconductor structure 100 according to the present invention, which can be subjected to processing at high temperatures (900°C to 1100°C) or even very high temperatures (1200°C to 1900°C). In fact, their precipitation in the form of aggregates 21 of small dimensions and very small thickness does not cause any degradation of the structure 100, particularly the processed layer 10. For example, consider silicon-containing aggregates 21 in a structure 100, which includes a processed layer 10 made of SiC and a carrier substrate 30, and is intended to undergo epitaxy at a temperature of 1600°C to 1800°C. Note that in this example, complete segmentation of the film 2' into aggregates 21 is observed at approximately 1700°C.

[0046] In step a), the free surface 10a to be bonded to the processed layer 10 typically contains native oxides, and / or, in step b), the free surface 30a to be bonded to the carrier substrate 30 typically contains such oxides. The fact that there is no need to control these native oxides often simplifies the manufacturing steps.

[0047] Therefore, in step e) of the process according to the present invention, the aggregates 21 in the interface region 20 can take in oxygen obtained from native oxides, and thus any oxides at the interface between the processed layer 10 and the carrier substrate 30 can be removed in the direct contact region 22.

[0048] Furthermore, steps c) and / or d) of this method can be carried out in an oxygen-containing atmosphere, which can relieve manufacturing constraints, and the oxygen is then present at the bonding interface 15 within the intermediate structure 150.

[0049] In this case as well, in step e), the aggregates 21 in the interface region 20 take in oxygen from the bonding interface 15, thereby avoiding the presence of oxygen in the direct contact region 22.

[0050] Therefore, the described production method makes it possible to obtain a semiconductor structure 100 that provides perpendicular electrical conductivity and / or effective direct contact between the processed layer 10 and the carrier substrate 30 via the interface region 20, thanks to the region 22 of direct contact free of oxygen and / or native oxides. The very fine aggregates 21 consist of the second material and, optionally, oxygen incorporated mainly in the form of oxides.

[0051] Generally, the aggregate 21 has the following form: - A first precipitate containing the semiconductor material (second material) of film 2, and / or - A second precipitate containing the second material and oxygen (mainly in the form of an oxide of the second material), and / or - A cavity whose inner wall is lined with a compound containing a second material and oxygen (primarily in the form of an oxide of the second material).

[0052] The interface region 20 with the aggregate 21 adjacent to the direct contact region 22 ensures the mechanical strength, and more generally the reliability, of the components generated in the processed layer 10 and / or on or within the processed layer 10.

[0053] The semiconductor structure 100 according to the present invention ensures good conductivity and / or effective direct contact between the processed layer 10 and the carrier substrate 30 via its interface region 20. In particular, aggregates 21 distributed in the interface region 20 on the central plane P substantially parallel to the main plane (x,y) can effectively incorporate oxygen that may be present in the encapsulated film 2' or the bonding interface 15, and the direct contact region 22 between the processed layer 10 and the carrier substrate 30, which is free of native oxide residues, enables effective and good quality electrical conductivity and / or vertical semiconductor / semiconductor contact.

[0054] Furthermore, the aggregates 21 and the direct contact region 22 ensure the mechanical continuity of the interface region 20 and provide excellent mechanical strength between the processed layer 10 and the carrier substrate 30. Therefore, it should be noted that the quality of the processed layer 10 is not affected by any holes or interface defects, and the aforementioned cavities, if present, have dimensions and density that do not adversely affect the quality and resistance of the processed layer 10.

[0055] On the central plane P of the interface region 20, the coverage of the aggregates 21 is typically 1% to 50%, preferably 10% to 40%. The lateral dimension of the aggregates 21 (on the central plane P) is limited, typically around 5 nm to 500 nm. In particular, when the thickness of the film 2 deposited in step c) is less than 10 nm, the lateral dimension of the aggregates 21 is approximately 5 nm to 150 nm, and the thickness of the aggregates 21 is 50 nm or less.

[0056] In the aggregate 21, in a cross-section perpendicular to the main surface (x,y), the first precipitate and cavity may have a lenticular or polygonal shape, and the second precipitate may have a substantially triangular shape.

[0057] (Example embodiment) Donor substrate 1 is a high-quality single-crystal 4H-SiC with a diameter of 150 mm. Donor substrate 1 is n-doped and has a resistivity of approximately 20 mΩ·cm. It has a 5-type "C" surface on its front. E 16 / cm 2 The implantation is carried out using hydrogen ions with a dose and energy of 95 keV. In this way, the embedded vulnerable surface 11 is defined around the implantation depth, and together with the front surface 10a of the donor substrate 1, it defines the processed layer 10.

[0058] The carrier substrate 30 is made of a lower-quality single-crystal 4H-SiC with the same diameter as the donor substrate 1. It is n-doped with a resistivity of approximately 20 mΩ·cm.

[0059] Both substrates 1 and 30 undergo a cleaning sequence to remove particles and other surface contaminants. Both substrates may contain native oxides on their surfaces.

[0060] Substrates 1 and 30 are introduced into a first deposition chamber integrated into a direct coupling device. A silicon film 2 having a thickness of 1 nm is deposited under secondary vacuum for 10 -6 At Pa and ambient temperature, the film is formed by spraying onto the front surfaces 10a and 30a (free surfaces to be bonded) of substrates 1 and 30, respectively.

[0061] Substrates 1 and 30 are introduced into a second bonding chamber and bonded at their front surfaces 10a and 30a by direct contact with the films 2 deposited on the donor substrate 1 and carrier substrate 30, respectively. The atmosphere in the bonding chamber is the same as the atmosphere in the film deposition chamber, but can be optionally different; for example, the substrates may be removed from the first chamber, returned to the ambient atmosphere, and then introduced into a bonding apparatus separate from the film deposition chamber. In fact, the method according to the present invention greatly relaxes the constraints related to the presence of oxygen in or on the films to be bonded, for example, in the form of native oxides.

[0062] After assembly, the bonded assembly 200 includes a donor substrate 1 bonded to a carrier substrate 30 via a bonding interface 15, and an encapsulated film 2' formed from two films 2 deposited and embedded between the two substrates 1 and 30. The encapsulated film 2' has a thickness of approximately 2 nm.

[0063] The bonded assembly 200 is heat-treated at a temperature of approximately 900°C for 30 minutes to induce separation at the embedded weak surface 11. An intermediate structure 150 is then obtained, which includes a processed layer 10 having a thickness of 500 nm, and is placed on an embedded film 2' which itself is placed on a carrier substrate 30. A cleaning and polishing sequence is applied to restore an appropriate level of defects and roughness to the surface 10b of the processed layer 10.

[0064] Finally, annealing at 1900°C for 30 minutes is applied to the intermediate structure 150, which has a protective layer pre-applied on its front surface 10b (which is also the free surface 10b of the processed layer 10 in the intermediate structure 150). At the end of this annealing, the structure 100 according to the present invention is obtained, and the interface region 20 is formed of aggregates 21 containing silicon and oxygen (mainly in the form of SiOx) and separated by the region 20 of direct contact between the processed layer 10 and the carrier substrate 30. Such an interface region 20 gives the structure 100 good perpendicular conductivity, close to the perpendicular conductivity of a solid SiC substrate having a resistivity of 20 mΩ·cm.

[0065] The interface region 20 is 0.1 mΩ·cm 2 It has the following resistivity. This is evident in the graph of Figure 4a, which shows the current curve I(V) as a function of voltage for a simple component including two metal contact electrodes 41 and 42 of different sizes (diameter 50 microns to 230 microns), and these electrode sizes (patterns) are plotted in the graph of Figure 4a. In the case of structure 100 according to the present invention, the measurement of I(V) is performed at the two electrodes 41 and 42, and the current path between them passes through the interface region 20 due to the presence of a trench 40 passing through the interface region 20 between the electrodes 41 and 42 (Figure 4b). Approximately 0.0076 mΩ·cm 2The resistivity of the interface region 20 was extracted. For comparison and reference, electrodes 51, 52 are also formed on the carrier substrate 30. The associated curve I(V) is marked "bulk" on the graph of FIG. 4a.

[0066] In this structure 100, the aggregates 21 have a thickness of 5 nm to 15 nm and an average diameter of approximately the same size. The coverage rate of the aggregates 21 on the central plane P of the interface region 20 is approximately 20%.

[0067] It should be noted that annealing temperatures other than 1900 °C (step e), for example 1370 °C, were also applied to the intermediate structure 150 described in the above example. Approximately 0.032 mΩ·cm 2 The resistivity of the interface region 20 of was extracted, that is, clearly less than 0.1 mΩ·cm 2 is.

[0068] Of course, this example is not limiting, and a number of other semiconductor structures 100 according to the present invention can be generated based on different combinations of materials for the processing layer 10, the film 2, and the carrier substrate 30 while observing the conditions set above for the formation of the interface region 20.

[0069] Electronic components can be formed on and / or within the processing layer 10 of the semiconductor structure 100 according to the present invention. These components can, in particular, address power applications, photovoltaic applications, or light-emitting diodes.

[0070] The components can include at least one electrical contact on and / or within the carrier substrate 30 at the back surface 100b of the semiconductor structure 100, particularly for power applications. As non-limiting examples, these power components can include transistors, diodes, thyristors, or passive components (capacitors, inductors, etc.), etc.

[0071] Of course, the present invention is not limited to the described embodiments and examples, and alternative embodiments can be provided thereto without departing from the scope of the present invention defined by the claims.

Claims

1. A method for producing a semiconductor structure (100), a) To provide a processed layer (10) made of a semiconductor material having a free surface (10a) to be bonded, b) To provide a carrier substrate (30) made of a semiconductor material having a free surface (30a) to be bonded, c) A film (2) having a thickness of less than 50 nm, composed of a semiconductor material different from the semiconductor material of the processed layer (10) and the carrier substrate (30), is formed on the free surface (10a) of the processed layer (10) to be bonded and / or on the free surface (30a) of the carrier substrate (30) to be bonded. d) forming an intermediate structure (150), wherein the formation includes directly joining the free surfaces to be joined of the processed layer (10) and the carrier substrate (30) along a bonding interface (15) extending along the main surface (x, y), wherein the intermediate structure (150) includes an enclosed film (2') resulting from one or more of the films (2) formed in step c), e) Annealing the intermediate structure (150) at a temperature above the critical temperature to bring about segmentation of the encapsulated film (2'), thereby forming the semiconductor structure (100) having an interface region (20) between the processed layer (10) and the carrier substrate (30), wherein the interface region (20) - The region (22) of direct contact between the processed layer (10) and the carrier substrate (30), - The film (2) comprises the semiconductor material and an aggregate (21) having a thickness of 250 nm or less along an axis (z) perpendicular to the main surface (x, y), Including, A method for generating a material, wherein the direct contact region (22) and the aggregate (21) are adjacent to each other on the main surface (x, y).

2. - In step a), the free surface (10a) to which the processed layer (10) is joined contains native oxide, and / or, in step b), the free surface (30a) to which the carrier substrate (30) is joined contains native oxide, - e) The method of production according to claim 1, wherein the aggregate (21) of the interface region (20) takes in oxygen generated from the native oxide.

3. a) The production method according to claim 1 or 2, wherein step a) includes injecting a light seed into the donor substrate (1) to form an embedded fragile surface (11) that demarcates the processed layer (10) together with the front surface (10a) of the donor substrate (1).

4. a) comprising the formation of the donor substrate (1) by epitaxy of the donor layer (1') on an initial substrate, and subsequently the injection being carried out within the donor layer (1'), according to claim 3.

5. d) The generating method according to claim 3 or 4, wherein after a direct assembly that gives rise to a bonded assembly (200) comprising the donor substrate (1) and the carrier substrate (30), the method comprises, on the one hand, forming the intermediate structure (150) comprising the processed layer (10), the encapsulated film (2'), and the carrier substrate (30), and on the other hand, separating at the embedded fragile surface (11) to form the remaining portion (1") of the donor substrate.

6. The production method according to any one of claims 1 to 5, wherein the thickness of the film (2) formed in c) is 10 nm or less.

7. The method for producing according to claim 6, wherein the thickness of the film (2) formed in c) is less than 10 nm, and the aggregate (21) has a thickness of 50 nm or less along an axis (z) perpendicular to the main surface (x, y).

8. The production method according to any one of claims 1 to 7, wherein the critical temperature is 500°C to 1,800°C, depending on the properties of the semiconductor material of the film (2) and the semiconductor material of the processed layer (10) and the carrier substrate (30).

9. The method for producing the processed layer (10) according to any one of claims 1 to 8, wherein the semiconductor material of the processed layer (10) is silicon carbide and has a single-crystal structure, a polycrystalline structure or an amorphous structure.

10. The method for producing according to any one of claims 1 to 9, wherein the semiconductor material of the carrier substrate (30) is silicon carbide and has a single crystal structure, a polycrystalline structure or an amorphous structure.

11. The method for producing the film (2) according to any one of claims 1 to 10, wherein the semiconductor material of the film (2) is selected from silicon or germanium.

12. The method for producing the aggregate (21) according to any one of claims 1 to 11, wherein the aggregate has a thickness of 40 nm or less.

13. The aggregate (21) - The first precipitate of the film (2) containing the semiconductor material, - The second precipitate of the film (2) containing the semiconductor material and oxygen, and / or - The cavity of the film (2) lined with the semiconductor material and an oxygen-containing compound, A method for generating according to any one of claims 1 to 12, which is a form of the method described.

14. The method for producing according to claim 13, wherein the second precipitate has a substantially triangular shape in a cross-section perpendicular to the main surface (x, y).

15. An electronic component produced on and / or within a processed layer (10) of a semiconductor structure (100) obtained as a result of the production method described in any one of claims 1 to 14, wherein the semiconductor structure (100) is - The processed layer (10) is made of a semiconductor material and extends along the main surface (x, y), - A carrier substrate (30) made of semiconductor material, - An interface region (20) between the processed layer (10) and the carrier substrate (30) that extends parallel to the main surface (x, y), wherein the interface region (20) includes a direct contact region (22) between the processed layer (10) and the carrier substrate (30), and an aggregate (21) having a thickness of 250 nm or less along an axis (z) perpendicular to the main surface (x, y), wherein the direct contact region (22) and the aggregate (21) are adjacent on the main surface (x, y).

16. The electronic component according to claim 15, wherein the semiconductor structure (100) has at least one electrical contact on and / or within the carrier substrate (30) on its back surface for power applications.

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