Method for manufacturing semiconductor photodetectors for optical communications

Abstract

The present disclosure provides a method for manufacturing a semiconductor photodetector for optical communications, wherein the semiconductor photodetector for optical communications (100) comprises a semiconductor substrate (1), an n-type semiconductor layer (2) formed on the semiconductor substrate (1), a digital alloy structure multiplier layer (3) formed on the n-type semiconductor layer (2), a p-type field relaxation layer (4) formed on the digital alloy structure multiplier layer (3), a light absorption layer (5) formed on the p-type field relaxation layer (4), and a p-type semiconductor layer (7) formed on the light absorption layer (5), and the method comprises at least the step of applying a reverse voltage to the semiconductor photodetector for optical communications (100) having at least a digital alloy structure multiplier layer (3) for a period of 0.2 hours to 100 hours.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor light-receiving element for optical communication.

Background Art

[0002] With the progress of digital transformation that utilizes digital information, the development of communication networks that communicate digital information with each other and data centers that perform data storage and processing has been remarkable. Optical communication is used for communication networks and in-data center communication. In recent years, optical communication has made remarkable progress in terms of high speed and large capacity. Among the progress of optical communication, as a receiver for optical communication, a photodiode (PD) and an avalanche photodiode (APD) that can obtain high reception sensitivity are required.

[0003] In the access network that connects to subscribers of optical communication, a passive optical network (PON) is mainly adopted. In the PON system, it starts from the G(E)-PON system that transmits signals of 1 to 2 Gbps, and in the future, it is expected that the 10G-EPON system and the XG-PON system that transmit signals of 10 Gbps will increase.

[0004] Furthermore, in ITU-T (International Telecommunication Union Telecommunication Standardization Sector), a 50G-PON system, which is a next-generation high-speed PON system, is being studied, and it is expected that transmission at the 50 Gbps level will be put into practical use in the access network in the future.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Non-Patent Document

[0006]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0007] In an APD, electrons and holes are accelerated and ionized, that is, multiplied, in a multiplication layer where a high electric field is applied. When both electrons and holes are ionized, the multiplication noise increases. On the other hand, when only electrons are ionized, the noise is low. The value obtained by dividing the ionization rate β of holes by the ionization rate α of electrons, β / α, is called the ionization rate ratio k. The closer the ionization rate ratio k approaches zero, the smaller the noise becomes.

[0008] Numerous attempts have been reported to bring the ionization ratio k closer to zero. In recent years, as described in Non-Patent Document 1, for example, it has been reported that applying a Digital Alloy structure, in which InAs and AlAs layers are stacked in a period of several atomic layers, to the multiplication layer of an APD suppresses hole ionization, bringing the ionization ratio k closer to zero, resulting in a lower noise APD.

[0009] The lattice constants of InAs and AlAs differ by +3% and -3%, respectively, from the lattice constant of InP used in the substrate. In other words, the InAs layer and AlAs layer experience crystal strains of +3% and -3%, respectively, relative to the InP substrate. Normally, a crystal strain of ±3% relative to the substrate would cause dislocations. However, in a digital alloy structure in which InAs and AlAs layers are stacked with a periodicity of several atomic layers, the magnitudes of the strains in InAs and AlAs are almost the same, and they cancel each other out, so no dislocations occur.

[0010] In a digital alloy structure, ideally, two layers of different compositions are grown regularly with uniform strain at the same atomic layer count. However, in reality, even when InAs and AlAs layers are stacked periodically in pairs of two atomic layers, local strain distributions occur in the digital alloy structure due to the influence of the wafer distribution of crystal growth temperature, the strain distribution of the underlying layer, and disturbances such as atomic layer-level irregularities and dislocations. This local strain distribution affects the band structure and the effective mass of electrons and holes, changing the ionization rates of electrons and holes. Originally, the distance between each atom forming the crystal lattice is uniform within the crystal plane. Here, local strain distribution refers to the localized increase or decrease in the distance between each atom compared to the average value. Locally, this range is from 0.5 nm (roughly the size of a single lattice) to several μm.

[0011] Furthermore, the ionization rates and ionization ratio k of electrons and holes are affected by the strain distribution. When a strain distribution on the scale of atomic layers occurs, the ionization ratio k becomes larger compared to the case of an ideal digital alloy multiplier layer, thus worsening the multiplication noise. An increase in multiplication noise leads to a decrease in the signal-to-noise ratio, resulting in a problem where the receiving sensitivity of the APD deteriorates.

[0012] Furthermore, APDs also have problems such as non-uniformity and instability of the electric field in the multiplier layer. Non-uniformity and instability of the electric field in the multiplier layer are caused by the distribution of dopants and the activation of dopants that are normally inactive, respectively. In particular, in APDs that use a digital alloy structure as the multiplier layer, the non-uniformity and instability of the electric field in the multiplier layer become factors that worsen the noise, as the noise is inherently very low.

[0013] Noise generated in semiconductor photodetectors used for optical communication, i.e., deterioration of reception sensitivity, has a significant impact on the system. In next-generation 50G-PON systems, the reception sensitivity of semiconductor photodetectors used for optical communication tends to be insufficient. For this reason, it is being considered to install a digital bandwidth compensation circuit using a digital signal processor (DSP) after the APD in the Optical Network Unit (ONU), i.e., the subscriber-side receiving device.

[0014] Furthermore, in optical line terminals (OLTs), that is, the receiving equipment on the central office side, a semiconductor optical amplifier (SOA) is required to compensate for the insufficient receiving sensitivity of the semiconductor photodetectors for optical communication. Alternatively, an SOA may be integrated into the electro-absorption modulated laser diode (EML) on the transmitting side of the ONU to increase the optical output.

[0015] However, DSPs and SOA consume very high power, which increases costs, raising concerns that the replacement of existing PON systems with 50G-PON systems will not progress.

[0016] In existing PON systems other than next-generation high-speed PON systems, increasing the number of branches of the optical signal output from the OLT is being considered to reduce costs. However, in this case as well, it is necessary to integrate the SOA into the EML on the transmitting side of the OLT and ONU to increase the optical output, which leads to problems such as increased power consumption of the transmitter and increased costs.

[0017] As described above, in order to compensate for the limitations of the receiving sensitivity of semiconductor photodetectors for optical communications, transceivers have been designed by incorporating expensive and power-hungry DSPs and SOAs into ONUs and OLTs. However, this results in increased power consumption and increased costs. For this reason, APDs with a digital alloy structure as the multiplier layer are expected to dramatically improve the receiving sensitivity of semiconductor photodetectors for optical communications.

[0018] In APDs using a digital alloy structure as the multiplier layer, the challenge is to reduce and stabilize the multiplier noise by improving the distortion distribution, electric field non-uniformity, and instability of the digital alloy structure multiplier layer, which are factors that worsen reception sensitivity.

[0019] This disclosure was made to resolve the above-mentioned problems and aims to provide a manufacturing method that enables the stable fabrication of semiconductor photodetectors for optical communications that have low amplification noise, i.e., high receiving sensitivity. [Means for solving the problem]

[0020] The method for manufacturing a semiconductor photodetector for optical communications relating to this disclosure is: The optical communication semiconductor photodetector having at least a digital alloy structure multiplier layer At a heat treatment temperature of 120°C to 200°C, The process includes at least the step of applying a reverse voltage for a period of 0.2 hours or more and 100 hours or less. [Effects of the Invention]

[0021] The method for manufacturing a semiconductor photodetector for optical communication according to this disclosure provides the effect that, in a semiconductor photodetector for optical communication having a digital alloy structure multiplier layer, by performing an energizing process, the deterioration of the ionization ratio caused by the strain distribution and non-uniformity and instability of the electric field within the digital alloy structure multiplier layer can be reduced, thereby reducing multiplication noise and enabling the easy manufacture of a semiconductor photodetector for optical communication with high receiving sensitivity. [Brief explanation of the drawing]

[0022] [Figure 1] This is a cross-sectional view showing the device structure of a surface-incident APD (Analytic Photodetector) having a multiplier layer made of a digital alloy structure, which is an example of a semiconductor photodetector for optical communications. [Figure 2] This is a cross-sectional view showing the device structure of a surface-incident APD (Analytic Photodetector) having a multiplier layer made of a digital alloy structure, which is another example of a semiconductor photodetector for optical communications. [Figure 3] This figure shows the measurement results of local strain in an InAlAs random alloy structure layer. [Figure 4] This figure shows the measurement results of local strain in the InAs / AlAs digital alloy structural layer. [Figure 5] This diagram schematically represents the localized strains discretely present within the multiplier layer of the InAs / AlAs digital alloy structure in a surface-incident APD. [Figure 6] This figure shows the field field dependence of electron dead space in InAlAs random alloy structure multiplier layers and InAs / AlAs digital alloy structure multiplier layers. [Figure 7] This is a schematic diagram illustrating a high-temperature energizing method for reducing noise in an APD having a digital alloy structure multiplier layer, in a manufacturing method for a semiconductor photodetector for optical communication according to Embodiment 1. [Figure 8]This figure illustrates the effect of improving the ionization ratio k of the APD by a high-temperature energization process in the manufacturing method of a semiconductor photodetector for optical communication according to Embodiment 1. [Figure 9] This figure shows an example of the reverse voltage dependence of the magnification factor M in the manufacturing method of a semiconductor photodetector for optical communication according to Embodiment 1. [Figure 10] This figure shows an example of the reverse voltage dependence of 1 / increasing factor M in the manufacturing method of a semiconductor photodetector for optical communication according to Embodiment 1. [Figure 11] This is a schematic diagram illustrating a method of arranging APDs in parallel within the voltage application method of the high-temperature energizing process in the manufacturing method of a semiconductor photodetector for optical communication according to Embodiment 1. [Figure 12] This is a schematic diagram illustrating a method of applying voltage during the high-temperature energizing process in a manufacturing method for a semiconductor photodetector for optical communication according to Embodiment 1, in which APDs are arranged in series. [Figure 13] This figure shows a current supply circuit used in the light injection current supply process in the manufacturing method of a semiconductor photodetector for optical communication according to Embodiment 3. [Figure 14] This figure shows the reverse voltage dependence of the photocurrent and dark current of the APD in the manufacturing method of a semiconductor photodetector for optical communication according to Embodiment 3. [Figure 15] This figure shows the forward current dependence of the temperature rise near the multiplication layer of the APD. [Figure 16] This diagram shows the manufacturing flow for the manufacturing method of a semiconductor photodetector for optical communication according to Embodiments 1 to 4. [Figure 17] This is a schematic diagram illustrating probe current application in the method for manufacturing a semiconductor photodetector for optical communication according to Embodiments 1 to 4. [Modes for carrying out the invention]

[0023] Embodiment 1. In describing the manufacturing method of the semiconductor photodetector for optical communication according to Embodiment 1, the semiconductor photodetector for optical communication, which is the subject of the manufacturing method, will be described below.

[0024] FIG. 1 is a cross-sectional view showing the element structure of a surface incident type APD 100 having a multiplication layer with a digital alloy structure, which is an example of a semiconductor light receiving element for optical communication.

[0025] The surface incident type APD 100 includes an n-type InP substrate 1, and an n-type InAlAs buffer layer 2 having a carrier concentration of 1×10 -3 , -3 cm -3 or more and 5×10 18 cm -3 or less and a layer thickness of 0.01 μm or more and 1.0 μm or less, an i-type AlAs layer (for example, a layer thickness of 2 atomic layers, about 0.6 nm), and an i-type InAs layer (for example, a layer thickness of 2 atomic layers, about 0.6 nm) are alternately laminated a plurality of times to form a multiplication layer 3 having an i-type InAs / AlAs digital alloy structure (hereinafter, referred to as an i-type InAs / AlAs digital alloy structure multiplication layer 3), a p-type InP electric field relaxation layer 4 having a carrier concentration of 1×10 16 cm -3 or more and 5×10 18 cm -3 or less and a layer thickness of 10 nm or more and 70 nm or less, an i-type InGaAs light absorption layer 5 having a layer thickness of 0.1 μm or more and 2.0 μm or less, an i-type InAlGaAs / InAlAs graded layer 6, a p-type InP window layer 7 having a layer thickness of 0.1 μm or more and 3.0 μm or less, a p-type InGaAs contact layer 8, an n-type electrode 31 formed on the back side of the n-type InP substrate 1, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8. Here, the n-type InAlAs buffer layer 2 may also be referred to as an n-type semiconductor layer. Instead of the n-type InAlAs buffer layer 2, an n-type InP buffer layer may be used. Here, the i-type means a semiconductor having a carrier concentration of 5×10 17 cm -3 or less. ​​The n-type InAlAs buffer layer 2 can have either a random alloy structure or a digital alloy structure. Silicon (Si), which is difficult to diffuse, is optimal as the n-type dopant for the n-type InAlAs buffer layer 2. This is to prevent n-type impurities from diffusing from the n-type InAlAs buffer layer 2 to the i-type InAs / AlAs digital alloy structure multiplication layer 3, which would cause the digital alloy structure to become disordered. Here, disordering refers to the phenomenon where the compositions of each layer in the digital alloy structure mix together, resulting in a random alloy structure with an average composition.

[0027] As described above, the i-type InAs / AlAs digital alloy structure multiplier layer 3 is composed of semiconductor layers stacked alternately in the order of AlAs layers (layer thickness of 2 atomic layers, approximately 0.6 nm) and InAs layers (layer thickness of 2 atomic layers, approximately 0.6 nm). However, the layer thickness of the AlAs layer and the InAs layer can be in the range of 2 to 6 atomic layers, respectively. The reason for limiting the layer thickness to 6 atomic layers or less is that it is desirable that the stacked structure of the AlAs layer and the InAs layer does not function as a quantum well structure.

[0028] Furthermore, the number of atomic layers in each layer of the i-type InAs / AlAs digital alloy structure multiplication layer 3 is preferably between 2 and 4 atomic layers, with 2 atomic layers being optimal. This is because the thinner the atomic layer thickness of each layer, the greater the effect of reducing the ionization ratio k by the digital alloy structure.

[0029] Considering the affinity with the InAlAs constituting the n-type InAlAs buffer layer 2, it is preferable to increase the thickness of only the first AlAs layer of the i-type InAs / AlAs digital alloy structure multiplier layer 3 to 3 atomic layers or more. Alternatively, the i-type InAs / AlAs digital alloy structure multiplier layer 3 may be laminated by alternately forming InAs layers and AlAs layers in that order.

[0030] The conductivity type of the i-type InAs / AlAs digital alloy structure multiplier layer 3 is i-type, and the carrier concentration is 1 × 10⁻⁶ 17 cm -3The following is one example. However, as a conductive type of the InAs / AlAs digital alloy structure multiplier layer, the carrier concentration is 5 × 10 18 cm -3 It may be of type p or type n as follows:

[0031] To increase the dead space effect in the i-type InAs / AlAs digital alloy structure multiplier layer 3, the layer thickness of the i-type InAs / AlAs digital alloy structure multiplier layer 3 is preferably in the range of 40 nm to 170 nm. However, considering the typical variation of 20% in layer thickness during the fabrication of semiconductor photodetectors for optical communication, the layer thickness of the i-type InAs / AlAs digital alloy structure multiplier layer 3 is preferably in the range of 50 nm to 140 nm.

[0032] Here, we will explain the dead space effect. The distance that electrons or holes can travel without ionizing within a multiplier layer to which a high electric field is applied is called the dead space. Normally, since the effective mass of holes is larger than that of electrons, holes are less likely to ionize, and therefore the dead space for holes is larger. If the thickness of the multiplier layer is made thinner than the dead space for holes, only electrons can ionize, so the ionization ratio k becomes smaller, resulting in lower noise. This phenomenon is called the dead space effect. Note that if the multiplier layer becomes too thin, the tunnel current increases and the noise worsens, so there is a lower limit to the optimal thickness of the multiplier layer.

[0033] In addition to the multiplier layer composed of an InAs / AlAs digital alloy structure, an InAlGaAs digital alloy structure, in which InAlyGa(1-y)As (layer thickness of 2 to 6 atomic layers, Al composition ratio: Y) and InAlzGa(1-z)As (layer thickness of 2 to 6 atomic layers, Al composition ratio: Z) are alternately stacked, can also be applied as a multiplier layer according to this disclosure. Furthermore, a digital alloy structure made of InAlAsSb, a material system to which antimony (Sb) has been added, can also be applied as a multiplier layer according to this disclosure.

[0034] As mentioned above, the p-type InP field relaxation layer 4 has a carrier concentration of 1 × 10⁻⁶16 cm -3 The above 5 x 10 18 cm -3 The following conditions apply, and the layer thickness is preferably in the range of 10 nm to 70 nm. Examples of p-type dopants for the p-type InP field relaxation layer 4 include beryllium (Be), zinc (Zn), and carbon (C).

[0035] Furthermore, the field relaxation layer does not necessarily have to be composed of p-type InP. In other words, the field relaxation layer can be a p-type InAs / AlAs digital alloy structure or a p-type InAlAs random alloy structure. However, if the dopant contained in the p-type InP field relaxation layer 4 diffuses into the adjacent i-type InAs / AlAs digital alloy structure multiplication layer 3, there is a risk that the digital alloy structure will become disordered and transform into a random InAlAs alloy structure.

[0036] As mentioned above, the i-type InAs / AlAs digital alloy structure multiplication layer 3 is thin, with a thickness of approximately 100 nm, and is therefore highly susceptible to disorder caused by dopant diffusion. For this reason, in the case of the p-type InP field relaxation layer 4, it is optimal to use Be, which is less prone to diffusion, as the p-type dopant. On the other hand, when using p-type InAlAs as the constituent material of the field relaxation layer, Zn is the optimal choice for the p-type dopant.

[0037] By providing a layer with a thickness of 0.1 μm or less, made of InAlGaAs or InGaAsP having an intermediate bandgap value between the two, between the p-type InP field relaxation layer 4 and the i-type InGaAs light absorption layer 5, it is possible to prevent the accumulation of electrons and holes at the heterojunction interface. The conductivity type of the InGaAs light absorption layer may be n-type or p-type.

[0038] Furthermore, for a similar purpose, a layer made of InAlGaAs or InGaAsP having an intermediate bandgap value between the two, with a thickness of 0.1 μm or less, may be provided between the i-type InGaAs light absorption layer 5 and the p-type InAlAs layer. The p-type InGaAs contact layer 8 has an outer periphery that is smaller in area than the multiplication layer.

[0039] In the example of the device structure of the semiconductor photodetector for optical communication shown in Figure 1, an i-type InAlGaAs / InAlAs graded layer 6 is formed by alternately stacking two types of i-type InAlGaAs layers with different compositions multiple times on an i-type InGaAs light absorption layer 5. The conductivity type of the i-type InAlGaAs / InAlAs graded layer 6 may be p-type or n-type instead of i-type. Also, a p-type InAlAs window layer may be used instead of the p-type InP window layer 7.

[0040] In the surface-incident APD100 having a digital alloy structure multiplier layer shown in Figure 1, the n-type InP substrate 1 side is n-type, but it is also possible to reverse the vertical positions of the p-type semiconductor layer and the n-type semiconductor layer. Figure 2 is a cross-sectional view showing the device structure of a surface-incident APD110 having a digital alloy structure multiplier layer, which is another example of a semiconductor photodetector for optical communication.

[0041] The surface-incident APD110, having a multiplier layer consisting of a digital alloy structure, is sequentially formed on an Fe-doped semi-insulating InP substrate 1a, with a carrier concentration of 1 × 10⁻¹⁶ 16 cm -3 The above 5 x 10 18 cm -3 A p-type InAlAs or p-type InP buffer layer 7a having a thickness of 0.1 μm to 1.0 μm, an i-type InAlGaAs / InAlAs graded layer 6a, an i-type InGaAs light absorption layer 5a having a thickness of 0.1 μm to 2.0 μm, and a carrier concentration of 1 × 10 16 cm -3 The above 5 x 10 18 cm -3The following components may be configured in order: a p-type InP field relaxation layer 4a with a thickness of 10 nm to 70 nm, an i-type InAs / AlAs digital alloy structure multiplication layer 3a, an n-type InP window layer 2a with a thickness of 0.1 μm to 3.0 μm, an n-type InGaAs contact layer 8a, a p-type electrode 32a formed on a p-type InAlAs or p-type InP buffer layer 7a, and an n-type electrode 31a formed on an n-type InGaAs contact layer 8a. The p-type InAlAs or p-type InP buffer layer 7a is also called a p-type semiconductor layer.

[0042] <Method for manufacturing APD having a digital alloy structure multiplier layer> An example of a semiconductor photodetector for optical communication according to Embodiment 1, the surface-incident APD100 having a digital alloy structure multiplier layer, can be realized on an n-type InP substrate 1 using metal-organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE). The manufacturing method of the surface-incident APD100 having a digital alloy structure multiplier layer according to Embodiment 1 is described below.

[0043] Using the MOVPE or MBE method, a layer with a carrier concentration of 1 × 10⁻¹ is created on an n-type InP substrate 1 with a thickness of 0.01 μm to 1 μm. 18 cm -3 The above 5 x 10 18 cm -3 The following n-type InAlAs buffer layer 2 is grown as a crystal.

[0044] An i-type InAs / AlAs digital alloy structure multiplier layer 3 is grown on an n-type InAlAs buffer layer 2. In other words, the i-type InAs / AlAs digital alloy structure multiplier layer 3 is formed by alternately growing AlAs layers (layer thickness of 2 atomic layers, approximately 0.6 nm) and InAs layers (layer thickness of 2 atomic layers, approximately 0.6 nm) on the n-type InAlAs buffer layer 2.

[0045] On the i-type InAs / AlAs digital alloy structure, layer 3 has a layer thickness of 10 nm to 70 nm and a carrier concentration of 1 × 10⁻¹⁶ 16 cm -3 The above 5 x 10 18 cm -3 The following p-type InP field relaxation layer 4 is grown as a crystal.

[0046] On a p-type InP field relaxation layer 4, an i-type InGaAs light absorption layer 5 with a thickness of 0.1 μm to 2 μm, an i-type InAlGaAs / InAlAs graded layer 6, a p-type InP window layer 7 with a thickness of 0.1 μm to 3 μm, and a p-type InGaAs contact layer 8 are sequentially grown as crystals. The InAlGaAs / InAlAs graded layer may be n-type or p-type. Also, a p-type InAlAs window layer may be used instead of the p-type InP window layer 7.

[0047] After the crystal growth is complete, a p-type electrode 32 is formed on the surface of the p-type InGaAs contact layer 8, and an n-type electrode 31 is formed on the back surface of the n-type InP substrate 1.

[0048] In the case of the surface-incident APD100 shown in Figure 1, an anti-reflective coating film 40 is applied to the incident surface of the APD on the chip surface. Light is incident on the i-type InGaAs light absorption layer 5 from a direction perpendicular to the anti-reflective coating film 40. The diameter of the APD's light-receiving area when it is circular, or the size of the longest side when the APD's light-receiving area is rectangular, is in the range of 5 μm to 1 mm.

[0049] <Noise reduction and noise stabilization of APD using a digital alloy structure as the multiplier layer> In the manufacturing method of a semiconductor photodetector for optical communication according to Embodiment 1, the manufacturing process for reducing and stabilizing the multiplication noise of an APD having a characteristic digital alloy structure multiplication layer is described below.

[0050] <Local strain distribution in the digital alloy structure multiplier layer> First, we will explain the local strain distribution within the multiplication layer. Figures 3 and 4 show the amount of strain in the stacking direction (perpendicular to the wafer surface) for the InAlAs random alloy structure layer and the InAs / AlAs digital alloy structure layer, respectively. Figures 3 and 4 are measurement results using the GPA (Geometrical Phase Analysis) method with a TEM (Transmission Electron Microscope).

[0051] The local strain distribution ΔSr in the InAlAs random alloy structure layer shown in Figure 3 is 0.02. Here, the local strain distribution is the deviation from the average value of the distance between each atom. Specifically, if Sa is the average value of the distance between atoms in the crystal layer, and Sx is the distance between atoms at a certain location (locally), then ΔSr = (Sx - Sa) / Sa. In the case of the InAs / AlAs digital alloy structure layer, the average value Sa of the distance S1 between adjacent In atoms and As atoms and the distance S2 between adjacent Al atoms is given by Sa = (S1 + S2) / 2.

[0052] On the other hand, in the case of the InAs / AlAs digital alloy structure layer shown in Figure 4, the lattice constants (distance between adjacent atoms, or size of a single lattice) differ by ±3% between the InAs layer and the AlAs layer, so the amount of strain fluctuates periodically. What is noteworthy here is that even when comparing AlAs layers to each other, the local strain distribution ΔSr is large, at about 0.04.

[0053] Thus, in InAs / AlAs digital alloy structural layers, if the amount of local strain distribution is large, the original band structure of the digital alloy structural layer is not formed, resulting in a large ionization ratio k and worsening of multiplication noise. Furthermore, an increase in local strain distribution also causes a local distribution of the multiplication factor.

[0054] Figure 5 schematically represents the discrete local strain distribution within the i-type InAs / AlAs digital alloy structure multiplication layer 3 of the surface-incident APD100. As shown by the local strain distribution schematically represented by x in Figure 5, discrete local strains exist within the InAs / AlAs digital alloy structure multiplication layer.

[0055] In APD, the amplification noise is M (2+x) It is approximately proportional to , where M is the multiplication factor and x is the excess noise figure. The excess noise figure x is a value in the range of 0.2 to 0.5. If the excess noise figure x is 0.2, the multiplication noise is M 2.2 It is proportional to the ratio. When the electric field distribution within the light-receiving surface of the APD is uniform, if the amplification factor M is 8, the amplification noise is 97 times (=8) higher than the amplification noise when the amplification factor M is 1. 2.2 )

[0056] On the other hand, if a uniform electric field is not applied within the plane of the multiplier layer, and if a distribution of the multiplier is generated due to local distortion distributions, the multiplier noise of the APD increases. For example, an electric field distribution and a multiplier distribution are generated within the light-receiving surface of the APD due to dopants or local distortion distributions. If the multiplier M is 10 in half the area of ​​the multiplier layer and 6 in the remaining half of the area of ​​the multiplier layer, the averaged multiplier M will be 8.

[0057] Therefore, the multiplication noise is 10 2.2 and 6 2.2 This averages out to 105 times the amplification noise when the amplification factor M is 1. In other words, if the electric field distribution is non-uniform within the amplification layer, even if the averaged amplification factor M is 8, the amplification noise increases by approximately 8%, from 97 times to 105 times, compared to when the amplification factor M is 1.

[0058] <Methods for reducing noise> To ensure uniform and stable multiplication by stabilizing the local strain distribution unique to the multiplication layer of the digital alloy structure, it is effective to pass an electric current (electrons and holes) in the reverse direction of the pn junction of the APD at high temperature. This is because when electrons and holes collide with atoms, i.e., the lattice, the unstable and localized lattice strain is stabilized, and the amount of strain in each atomic layer becomes uniform. The kinetic energy (m·v) of electrons and holes colliding with the lattice 2 The higher the ( / 2) value, the greater the effect of stabilizing local lattice strain. Here, m represents the effective mass of electrons or holes, and v represents the trajectory velocity of electrons or holes.

[0059] In the dead space within the multiplier layer, the energy of the moving carriers is not consumed by ionization, so the carrier velocity increases. For example, Non-Patent Literature 2 shows that the effective carrier velocity in a multiplier layer with a thickness of 200 nm increases by as much as 169%.

[0060] Figure 6 shows the electric field dependence of the electron dead space in the InAlAs multiplier layer. As shown in Figure 6, the dead space becomes longer in the digital alloy structure multiplier layer, which increases the kinetic energy of electrons and holes, resulting in a unique effect in eliminating strain instability. Furthermore, it is thought that this effect can be achieved in a short time by increasing the heat treatment temperature when applying current. In other words, by performing a high-temperature current application process on the APD, it is possible to reduce the noise of the APD, that is, to reduce the ionization ratio k.

[0061] <Function of the high-temperature energization process> The inventors verified the effect of reducing the ionization ratio k by applying a reverse voltage to an APD having an InAs / AlAs digital alloy structure multiplier layer and passing a current through it at a high heat treatment temperature. The InAs / AlAs digital alloy structure multiplier layer of the wafer from which the test sample APD was fabricated was known in advance through TEM analysis to have a relatively large amount of disorder in the interatomic distances of InAs and AlAs, meaning that an APD with a local strain distribution was thought to be occurring.

[0062] As shown in Figure 7, the inside of the energizing cell 50 was kept under a nitrogen atmosphere, and the temperature inside the energizing cell 50 was controlled by T (°C). A voltage Vapd (V) was applied to the APD from a voltage source, and a current Iapd flowed in the reverse direction across the pn junction of the APD. A resistor R was connected in series between the APD and the voltage source to minimize the change in current Iapd even when the IV characteristics of the APD changed.

[0063] For APDs that underwent a high-temperature energization process, the ionization ratio k was calculated from the measured multiplication noise. The relationship between the ionization ratio k and the multiplication noise is expressed by the following equation (1). The multiplication noise is defined as the mean square of the current amplitude of the shot noise. Noise multiplication = 2qIBM 2 F (1)

[0064] In equation (1), q represents the elementary charge, I represents the average current flowing through the multiplier layer, B represents the frequency band, M represents the multiplier, and F represents the excess noise coefficient. The relationship between the excess noise figure x and the excess noise coefficient F is expressed by the following equation (2). F=M x (2)

[0065] In the case of electron injection, the excess noise coefficient F is correlated with the ionization ratio k and the multiplication factor M, as shown in equation (3) below. F = M[1 - (1 - k) ((M - 1) / M] 2 (3) The ionization ratio k of APD was calculated using equations (1) and (2) above.

[0066] Figure 8 shows the effect of the high-temperature energization process on improving the ionization ratio k of APDs. Without the high-temperature energization process, the ionization ratio k is 0.20 (sample size: n=7). On the other hand, with the high-temperature energization process, the ionization ratio k improves to 0.12 (sample size: n=11). Note that the ionization ratio k is the value when the multiplication factor M is 5. The effect of the high-temperature energization process was verified with multiple APDs. As shown in Figure 8, the variance value σ of the ionization ratio k is sufficiently small, and the difference in the ionization ratio k between the presence and absence of the high-temperature energization process is statistically significant.

[0067] In the case of APDs using an InAlAs random alloy structure as the multiplier layer, the ionization ratio k is 0.20 regardless of whether or not a high-temperature energizing process is performed. Therefore, the improvement in the ionization ratio k due to the high-temperature energizing process can be said to be a unique effect that only appears with APDs using an InAs / AlAs digital alloy structure as the multiplier layer.

[0068] <Temperature conditions for the high-temperature energization process> For the heat treatment temperature in the high-temperature energizing process, a range of 85°C to 280°C is preferable. 85°C is the maximum temperature during actual use, and 280°C is the upper limit temperature to keep it below the melting point of the solder used during mounting. A range of 120°C to 200°C is even more preferable for the heat treatment temperature. 120°C is the temperature at which a 10-fold acceleration is obtained compared to 85°C, when the activation energy is 0.8 eV, allowing for a reduction in energizing time. 200°C is the upper limit temperature at which electrode deterioration does not occur.

[0069] <Voltage conditions for the high-temperature energization process> Figure 9 shows an example of the reverse voltage dependence of the multiplier M in the manufacturing method of a semiconductor photodetector for optical communication according to Embodiment 1. Figure 10 also shows an example of the reverse voltage dependence of 1 / (multiplier M) in the manufacturing method of a semiconductor photodetector for optical communication according to Embodiment 1.

[0070] As optimal voltage conditions during the high-temperature energization process, the reverse voltage of the APD must be greater than or equal to the reach-through voltage in order for electrons to be efficiently injected into the multiplier layer. Furthermore, the reverse voltage of the APD must be less than or equal to 1.1 times the breakdown voltage to prevent excessive current flow and burnout of the APD.

[0071] Figure 10 shows the range of suitable applied voltages, i.e., energizing voltages, during the high-temperature energizing process. An applied voltage of 0.9 to 1.1 times the breakdown voltage at the energizing temperature is even more preferable. This is because energizing can be completed in a short time and degradation due to overcurrent can be prevented. Here, reach-through voltage is the voltage at which the multiplier M is approximately 1.1 times or more. Breakdown voltage is the voltage at which the dark current increases rapidly. Specifically, breakdown voltage is defined as the voltage at which the multiplier is 8 times or 1.1 to 1.2 times the voltage at which the multiplier is 8 times, or the voltage at which the multiplier M is 20 times, or the voltage at which the dark current is 100 μA or more.

[0072] <Voltage application method in high-temperature energization process> To apply a voltage between 0.9 and 1.1 times the breakdown voltage, a constant current power supply (voltage source and resistor, or constant current source) is used to control the current density (A / m). 2 ) to 3.2 × 10 2 A / m 2 From 3.2 × 10 6 A / m 2 The current may be set to a value within the specified range and power may be supplied. Furthermore, pulsed voltage application is also acceptable instead of continuous voltage application. Note: 3.2 × 10 2 A / m 2 This refers to the current density equivalent to 1 mA at the light-receiving diameter of 1 mmΦ on the light-receiving surface of the APD, which is 3.2 × 10⁻⁶. 6 A / m 2 This refers to a current density equivalent to 1 mA at the light-receiving surface of the APD with a light-receiving diameter of 10 μmΦ.

[0073] Figure 11 is a schematic diagram showing a method of applying voltage in the high-temperature energizing process in the manufacturing method of a semiconductor photodetector for optical communication according to Embodiment 1, in which APDs are arranged in parallel. Figure 12 is a schematic diagram showing a method of applying voltage in the high-temperature energizing process, in which APDs are arranged in series.

[0074] As a voltage application circuit for the high-temperature energization process, a preferred method is to connect the APDs in parallel with respect to the power supply, as shown in Figure 11, and insert a resistor R between the power supply and each APD. By using a constant voltage source and setting the resistor R to a high value within the range of 1kΩ to 1MΩ, it is possible to supply almost the same current to each APD, even if the breakdown voltages of each APD are different. In other words, by connecting a high-resistance resistor R in series with each APD, it is the same as connecting a separate constant current source to each APD. On the other hand, as shown in Figure 12, it is also possible to supply the same current value to all APDs by connecting multiple APDs in series with respect to the power supply.

[0075] <Specific conditions for the energizing time in the high-temperature energizing process> In the high-temperature energizing process, the energizing time is preferably the time required for the breakdown voltage or dark current fluctuations of the APD to stabilize. The stabilization time may be set by performing the same energizing time twice, such that the fluctuations in the breakdown voltage or dark current before and after the first energizing are smaller than the fluctuations before and after the second energizing.

[0076] The high-temperature energizing process is preferably within the range of 0.2 hours to 100 hours, which is sufficient to stabilize the rapid fluctuations in the dark current of the APD. It is even more preferable to set the energizing time within the range of 0.5 hours to 48 hours. The 0.5 hours is the time required to stabilize the temperature of the energizing chamber, and the 48 hours is a constraint time considering productivity. Furthermore, the energizing time can be shortened by applying voltage during the heating and cooling of the energizing chamber 50.

[0077] <Method for confirming the effectiveness of the high-temperature energization process> When applying a high-temperature energization process to APD manufacturing, it is necessary to appropriately monitor the effects of the high-temperature energization process to exclude APDs that are thought to have high noise levels. Since individually measuring the amplification noise of APDs is inefficient, an alternative method is needed. This alternative method is described below.

[0078] One example of such a method is to determine that an APD is defective if the breakdown voltage Vbr and dark current Id change several times larger than the average value before and after the high-temperature energizing process, or if the change in breakdown voltage Vbr and dark current Id does not decrease even after repeated high-temperature energizing. This may indicate the presence of a fatal defect in the digital alloy structure multiplier layer.

[0079] The specific method for determining this is to monitor ΔVbr, which represents the change in breakdown voltage Vbr, or ΔId, which represents the change in dark current Id. Vbr and ΔId are calculated using the following equations (4) and (5), respectively. ΔVbr=Vbr after energization / Vbr before energization (4) ΔId=Id after energization / Id before energization (5)

[0080] As an example of criteria for determining whether APD is good or bad, the following criteria (6) and (7) can be used. A<ΔVbr C<ΔId <D (7)

[0081] The criteria for acceptance are set considering the variance σ of ΔVbr and ΔId. For example, for ΔVbr, A = ΔVbr - 2σ, B = ΔVbr + 2σ, etc., where σ represents the variance of ΔVbr. For ΔId, C = ΔId - 2σ, D = ΔId + 2σ, etc., where σ represents the variance of ΔId. Another example of an acceptance criterion is to examine the correlation between the results of long-term reliability tests and ΔVbr and ΔId and set the criteria accordingly. ​

[0082] <Effects of Embodiment 1> As described above, the method for manufacturing a semiconductor photodetector for optical communication according to Embodiment 1 reduces the deterioration of the ionization ratio k caused by local strain distribution and non-uniformity and instability of the electric field in a semiconductor photodetector for optical communication having a digital alloy structure multiplier layer, by performing a high-temperature energization process. This reduces multiplication noise and makes it possible to easily manufacture a semiconductor photodetector for optical communication with high receiving sensitivity.

[0083] Embodiment 2. <Effect of noise reduction through low-temperature energization process> In the depletion layer of an APD, increasing the electric field increases the velocity of electrons and holes. However, at electric fields above several hundred kV / cm, the velocity reaches a point where it no longer increases further. This velocity is called the saturation velocity. When a reverse voltage is applied to the pn junction of an APD, an electric field of 500 kV / cm to 1000 kV / cm is applied to the multiplier layer, causing electrons and holes to move within the multiplier layer at the saturation velocity. The kinetic energy of electrons and holes (m·v) 2 The higher the ( / 2) value, the greater the effect of mitigating and stabilizing the local distortion distribution due to current application. Therefore, applying current while increasing the saturation speed can result in noise reduction.

[0084] According to R. Quay et al. “A temperature dependent model for the saturation velocity in semiconductor” Materials Science in Semiconductor Processing 3 pp.149-155 (2000), the saturation velocity Vs(T) of electrons and holes at lattice temperature T is expressed by the following equation (8).

[0085] Vs(T)=Vs(300K) / [(1-A)+A·(T / 300)] (8) In equation (8), T represents the lattice temperature (K), Vs(T) represents the saturation rate at lattice temperature T, and A represents the temperature coefficient.

[0086] As is clear from equation (8), by reducing the lattice temperature T, the saturation rate can be increased, and furthermore, the kinetic energy of electrons and holes can be increased, thereby enabling relaxation and stabilization of the local strain distribution of the multiplier layer in an APD having a digital alloy structure multiplier layer.

[0087] APDs are composed of multiple compound semiconductor materials with different compositions. Since each material has a different coefficient of thermal expansion, the local strain distribution of the multiplier layer differs between low and high temperatures. Therefore, there are areas where the amount of strain increases locally at low temperatures. In other words, the areas where relaxation and stabilization of the local strain distribution can be achieved by applying current at low temperatures are different from those where it can be achieved by applying current at high temperatures. Furthermore, by applying current at low temperatures in addition to high temperatures, relaxation and stabilization of the local strain distribution can be expected.

[0088] <Low temperature energization process> The temperature range for the low-temperature energization process is preferably from -196°C, which is the stable liquid nitrogen temperature, to room temperature (25±10°C).

[0089] For a suitable current-taking voltage range, the reverse voltage of the APD must be above the reach-through voltage in order for electrons to be efficiently injected into the multiplier layer, while it must be 1.1 times or less of the breakdown voltage in order to prevent excessive current flow and burnout. Here, the reach-through voltage is the voltage at which the multiplier M is approximately 1.1 times or more, and the breakdown voltage is the voltage at which the multiplier M is 8 times or 1.1 to 1.2 times the voltage at which the multiplier M is 8 times, or the voltage at which the multiplier M is 20 times, or the voltage at which the dark current is 100 μA or more. A range of 80% to 100% of the breakdown voltage at the current-taking temperature is even more preferable in that current-taking can be completed in a short time and degradation due to overcurrent can be prevented.

[0090] The optimal energizing time is between 0.2 hours and 100 hours, which is the range during which rapid changes in dark current subside. A more preferable energizing time is between 0.5 hours and 48 hours. Note that 0.5 hours is the time required for the temperature of the energizing chamber to stabilize, and 48 hours is a constraint time considering productivity.

[0091] <Effects of Embodiment 2> As described above, according to the manufacturing method of a semiconductor photodetector for optical communication according to Embodiment 2, by performing a low-temperature energization process in a semiconductor photodetector for optical communication having a digital alloy structure multiplier layer, the deterioration of the ionization ratio k caused by the local strain distribution within the digital alloy structure multiplier layer and the non-uniformity and instability of the electric field can be reduced. This reduces multiplication noise and makes it possible to easily manufacture a semiconductor photodetector for optical communication with high receiving sensitivity.

[0092] Embodiment 3. <Noise reduction through light injection and current application process> By applying current to an APD while light is incident on it, a large number of electrons and holes can be generated. When a large number of electrons and holes collide with atoms and the lattice, the unstable local lattice strain distribution becomes uniform and stable. Therefore, relaxation and stabilization of the local strain distribution in the multiplier layer of an APD having a digital alloy structure multiplier layer can be achieved.

[0093] Figure 13 is a diagram showing the energizing circuit used in the light injection energizing step in the manufacturing method of a semiconductor photodetector for optical communication according to Embodiment 3. Figure 14 is a diagram showing the reverse voltage dependence of the photocurrent and dark current of the APD in the manufacturing method of a semiconductor photodetector for optical communication according to Embodiment 3. In the light injection energizing step, light is incident on the pn junction of the APD while applying a reverse voltage using the energizing circuit shown in Figure 13. As shown in Figure 14, a photocurrent, i.e., electrons and holes, that is more than an order of magnitude larger than the dark current, flows. The wavelength of the incident light is preferably within the range of 1.2 μm to 1.6 μm, which is absorbed by the InGaAs light absorption layer.

[0094] A suitable amount of photocurrent for the APD in the photo-injection current-encouraging process is the photocurrent density (A / m). 2 ) is 3.2 × 10 2 A / m 2 From 3.2 × 10 6 A / m 2 The amount of incident light and the applied voltage may be set and power supplied so that the current value falls within the range. 2 A / m 2 This refers to the current density equivalent to 1 mA at the light-receiving diameter of 1 mmΦ on the light-receiving surface of the APD, which is 3.2 × 10⁻⁶. 6 A / m 2 This refers to a current density equivalent to 1 mA at the light-receiving surface of the APD with a light-receiving diameter of 10 μmΦ.

[0095] The amount of light incident on the APD during the light injection energization process is preferably 1 μW or more so that the photocurrent is greater than the dark current, and 100 mW or less so that the APD is not damaged by over-input. A range of 100 μW to 1 mW is even more preferable for stable operation of the APD.

[0096] For the photo-induced energization process, a temperature range from -196°C, which is the stable temperature of liquid nitrogen, to 200°C, which is a high temperature, is preferable. A temperature range from room temperature (25±5°C) to the maximum operating temperature (85°C or lower) is even more preferable.

[0097] In the photo-induced energization process, a suitable energizing voltage range is required for the APD's reverse voltage to be above the reach-through voltage for efficient electron injection into the multiplier layer, while it must be below 1.1 times the breakdown voltage to prevent excessive current flow and burnout. Here, the reach-through voltage is the voltage at which the multiplier M is approximately 1.1 times or more, and the breakdown voltage is the voltage at which the multiplier M is 8 times or 1.1 to 1.2 times the voltage at which the multiplier M is 8 times, or the voltage at which the multiplier M is 20 times, or the voltage at which the dark current is 100 μA or more. A range of 80% to 100% of the breakdown voltage at the energizing temperature is even more preferable because it allows for quick energization and prevents degradation due to overcurrent.

[0098] In the light-induced energizing process, the energizing time is preferably within the range of 0.2 hours to 100 hours, which is when the rapid change in dark current subsides. More preferably, the energizing time is within the range of 0.5 hours to 48 hours. Note that 0.5 hours is the time required for the energizing chamber temperature to stabilize, and 48 hours is a constraint time considering productivity.

[0099] <Effects of Embodiment 3> As described above, according to the manufacturing method of a semiconductor photodetector for optical communication according to Embodiment 3, by performing a light injection current application process in a semiconductor photodetector for optical communication having a digital alloy structure multiplier layer, the deterioration of the ionization ratio k caused by the local strain distribution within the digital alloy structure multiplier layer and the non-uniformity and instability of the electric field can be reduced. This reduces multiplication noise and makes it possible to easily manufacture a semiconductor photodetector for optical communication with high receiving sensitivity.

[0100] Embodiment 4. <Noise reduction by forward voltage energization process in manufacturing method of semiconductor photodetectors for optical communications> Embodiments 1 to 3 relate to energization processes utilizing reverse voltage energization. Embodiment 4, on the other hand, relates to a forward voltage energization process of an APD having a digital alloy structure multiplier layer.

[0101] By applying a forward voltage to the APD, it becomes possible to flow more than 100 times more electrons and holes than by applying a reverse voltage to the APD. When a large number of electrons and holes collide with atoms, i.e., the lattice, the lattice temperature rises even if the velocity of electrons and holes is slow, and the distribution of unstable local lattice strain becomes uniform and stable. Therefore, relaxation and stabilization of the local strain distribution within the multiplier layer of an APD having a digital alloy structure multiplier layer can be achieved.

[0102] Figure 15 shows the forward current dependence of the temperature rise near the multiplier layer of an APD. The APD's built-in voltage is 0.75V, the element resistance is 20Ω, and the thermal resistance is 300KW. As shown in Figure 15, when a forward current is applied to the APD, the temperature near the multiplier layer rises. As can be seen from Figure 15, a forward current of 110mA raises the temperature near the multiplier layer by approximately 100°C. In other words, when energized at room temperature, the temperature near the multiplier layer becomes 125°C.

[0103] Forward current density (A / m 2 ) is 3.2 × 10 4 A / m 2 The above 3.2 × 10 8 A / m 2 The current value should be set as follows. For high-speed APDs, the light-receiving diameter is about 10 μmΦ, so 100 mA ± 50 mA is considered optimal. Note 3.2 × 10 4 A / m 2 This refers to a current density equivalent to 100mA at a light-receiving diameter of 1mmΦ on the light-receiving surface of the APD, which is 3.2 × 10⁻⁶. 8 A / m 2 This refers to a current density equivalent to 100 mA at the light-receiving surface of the APD with a light-receiving diameter of 10 μmΦ.

[0104] For the forward voltage energization process, considering that applying a current of several tens of mA at temperatures above 200°C may cause the electrode ohmic portion to burn out, a temperature range above room temperature, i.e., between 25°C and 200°C, is preferable. A temperature range of 85°C to 180°C is even more preferable. Note that 85°C is the maximum temperature during actual use, and 180°C is a temperature with a 10% margin over 200°C.

[0105] In the forward voltage energizing process, the energizing time is preferably within the range of 0.2 hours to 100 hours, which is when the rapid change in dark current subsides. More preferably, the energizing time is within the range of 0.5 hours to 48 hours. Note that 0.5 hours is the time required for the energizing chamber temperature to stabilize, and 48 hours is a constraint time considering productivity.

[0106] <Effects of Embodiment 4> As described above, according to the manufacturing method of a semiconductor photodetector for optical communication according to Embodiment 4, by performing a forward voltage energization process in a semiconductor photodetector for optical communication having a digital alloy structure multiplier layer, the deterioration of the ionization ratio k caused by local strain distribution and non-uniformity and instability of the electric field can be reduced. As a result, multiplication noise is reduced, and a semiconductor photodetector for optical communication with high receiving sensitivity can be easily manufactured.

[0107] <Regarding each step in the manufacturing method of a semiconductor photodetector for optical communication according to Embodiments 1 to 4> Based on the manufacturing flow diagram in Figure 16, we will explain the timing of the power-on process in the APD manufacturing flow.

[0108] The APD manufacturing flow has optimal processes for each stage, from substrate loading to the completion of inspection. The process of forming the APD, i.e., from substrate loading to back electrode formation, is a known manufacturing method, so we will omit the explanation.

[0109] After the back electrode formation process ST001, which completes the configuration as an APD, the surface-incident APD 100 is completed through the following processes: wafer inspection process ST002, which inspects the device characteristics in the wafer state; chip separation process ST003, which separates the chips individually from the wafer; assembly and mounting process ST004, which assembles and mounts the separated individual chips; and inspection process ST005, which inspects the assembled and mounted APD.

[0110] The energizing step in the manufacturing method of a semiconductor photodetector for optical communication according to Embodiments 1 to 4 may be performed at any of the following timings in the APD manufacturing flow described above: timing P1 after the back electrode formation step ST001, timing P2 after the wafer inspection step ST002, timing P3 after the chip separation step ST003 for separating chips individually from the wafer, timing P4 after the assembly and mounting step ST004 for assembling and mounting the separated individual chips, and timing P5 after the inspection step ST005 for inspecting the assembled and mounted APD.

[0111] As an example of how to perform the energizing process at timing P1 after the back electrode formation process ST001 and at timing P2 after the wafer inspection process ST002, energizing using a prober 60 as shown in Figure 17 can be mentioned. In energizing using a prober 60, the prober 60 is brought into contact with the APD chip 62 formed on the wafer 61 to apply energy. Therefore, energizing using a prober 60 is efficient because the energizing process can be performed with a simple equipment configuration.

[0112] The reason for performing the energizing process after the back electrode formation process ST001 is to relieve the stress during back electrode formation by performing the energizing process after the back electrode formation. Furthermore, performing the energizing process at timing P4 after the assembly and mounting process ST004, or at timing P5 after the inspection process ST005, is even more preferable because it also relieves the stress on the solder when mounting the APD.

[0113] Embodiment 5. <Noise reduction by applying high-temperature annealing in the manufacturing method of semiconductor photodetectors for optical communications> High-temperature annealing after crystal growth is also effective in stabilizing the local strain distribution of the digital alloy structure multiplier layer. However, annealing, or heat treatment, of the digital alloy structure at high temperatures can cause disorder, potentially resulting in a random alloy structure. Therefore, it is necessary to alleviate the local strain distribution using the minimum necessary processing temperature and processing time.

[0114] Since order is likely to occur when dopants in a semiconductor layer undergo thermal diffusion, a heat treatment temperature lower than the temperature at which dopants begin to diffuse is preferable. For example, if the dopant is Be, a heat treatment temperature of 650°C or lower is preferable, and if the dopant is Zn, a heat treatment temperature of 500°C or lower is preferable.

[0115] On the other hand, to obtain the effect of high-temperature annealing, a heat treatment temperature of 300°C or higher is preferable, as this allows for the movement of vacancies and other elements within the semiconductor layer. A heat treatment time of 0.5 hours or more, corresponding to the temperature stabilization time after inserting the wafer into the annealing furnace, is also preferable.

[0116] Furthermore, even at temperatures lower than the temperature at which dopants begin thermal diffusion, prolonged heat treatment can lead to the separation of phosphorus and arsenic, which are constituent elements of the semiconductor layer, and the diffusion of dopant within the semiconductor layer. To prevent the separation of phosphorus and arsenic, a heat treatment time of 10 hours or less, preferably 3 hours or less, is preferable, as this limits dopant diffusion to a small amount.

[0117] Therefore, in the APD manufacturing flow shown in Figure 16, annealing, or heat treatment, at relatively high temperatures is possible from after crystal growth until before the surface electrode formation process. Heat treatment within the range of 300°C to 650°C is preferred when the dopant is Be, and heat treatment within the range of 300°C to 500°C is preferred when the dopant is Zn. Furthermore, in order to prevent oxidation of the semiconductor layer, an arsenic atmosphere, a phosphorus atmosphere, a nitrogen atmosphere, a hydrogen atmosphere, or a vacuum is preferred as the atmosphere inside the energizing cell 50.

[0118] From the back electrode formation process ST001 onward, although the effect of high-temperature heat treatment is reduced, the electrodes sink into the semiconductor layer, so the heat treatment temperature needs to be lowered. Therefore, when an energizing process is performed after the back electrode formation process ST001, the heat treatment temperature is preferably in the range of 300°C to 400°C. After mounting the APD, that is, from the assembly mounting process ST004 onward, the heat treatment temperature is preferably in the range of 100°C to 250°C to prevent melting of mounting materials such as solder. In addition, to prevent oxidation of the semiconductor layer, a nitrogen atmosphere, a hydrogen atmosphere, or a vacuum is desirable as the atmosphere inside the energizing chamber 50.

[0119] <Effects of Embodiment 5> As described above, according to the manufacturing method of a semiconductor photodetector for optical communication according to Embodiment 5, by performing a high-temperature heat treatment process in a semiconductor photodetector for optical communication having a digital alloy structure multiplier layer, the deterioration of the ionization ratio k caused by the local strain distribution within the digital alloy structure multiplier layer and the non-uniformity and instability of the electric field can be reduced. This reduces multiplication noise and makes it possible to easily manufacture a semiconductor photodetector for optical communication with high receiving sensitivity.

[0120] Embodiment 6. <Noise reduction by applying temperature cycling in the manufacturing method of semiconductor photodetectors for optical communications> As a method to alleviate local strain distributions, temperature cycling may be applied to the APD. Temperature cycling is a method of alleviating local strain distributions by repeatedly raising and lowering the temperature, for example, by repeating a temperature cycle of 30°C, 400°C, 30°C, 400°C.

[0121] In the APD manufacturing flow shown in Figure 16, if performed before the back electrode formation process ST001, the high-temperature side of the temperature cycle is preferably between 300°C and 500°C, and the low-temperature side is preferably between room temperature and 100°C. If performed after the back electrode formation process ST001 or the assembly and mounting process ST004, the high-temperature side of the temperature cycle is preferably between 85°C and 250°C, and the low-temperature side is preferably between -45°C and 30°C. The number of temperature cycles is preferably between 10 and 300 cycles.

[0122] <Effects of Embodiment 6> As described above, according to the manufacturing method of a semiconductor photodetector for optical communication according to Embodiment 6, by performing a temperature cycling process in a semiconductor photodetector for optical communication having a digital alloy structure multiplier layer, the deterioration of the ionization ratio k caused by local strain distribution within the digital alloy structure multiplier layer and non-uniformity and instability of the electric field can be reduced. This has the effect of reducing multiplication noise and easily manufacturing a semiconductor photodetector for optical communication with high receiving sensitivity.

[0123] While this disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but are applicable individually or in various combinations to the embodiments.

[0124] Accordingly, countless variations not illustrated are conceivable within the scope of the art of this disclosure. These include, for example, modifying, adding or omitting at least one component, or even extracting at least one component and combining it with components of other embodiments. [Explanation of Symbols]

[0125] 1 n-type InP substrate, 1a Fe-doped semi-insulating InP substrate, 2 n-type InAlAs buffer layer, 2a n-type InP window layer, 3, 3a i-type InAs / AlAs digital alloy structure multiplication layer, 4, 4a p-type InP field relaxation layer, 5, 5a i-type InGaAs light absorption layer, 6, 6a i-type InAlGaAs / InAlAs graded layer, 7 p-type InP window layer, 7a p-type InP buffer layer, 8 p-type InGaAs contact layer, 8a n-type InGaAs contact layer, 31, 31a n-type electrode, 32, 32a p-type electrode, 50 energizing cell, 60 prober, 61 wafer, 62 APD chip, 100, 110 surface-incident APD

Claims

1. A method for manufacturing a semiconductor photodetector for optical communication, A step of applying a reverse voltage to the optical communication semiconductor photodetector having at least a digital alloy structure multiplier layer at a heat treatment temperature of 120°C to 200°C for a period of 0.2 hours to 100 hours, A method for manufacturing a semiconductor photodetector that comprises at least the following.

2. A method for manufacturing a semiconductor photodetector for optical communication, A step of applying a reverse voltage to the optical communication semiconductor photodetector having at least a digital alloy structure multiplier layer at a heat treatment temperature of -196°C to 35°C for a period of 0.2 hours to 100 hours, A method for manufacturing a semiconductor photodetector that comprises at least the following.

3. The method for manufacturing an optical communication semiconductor photodetector according to claim 1 or 2, characterized in that the reverse voltage is applied by connecting a plurality of optical communication semiconductor photodetectors, each having a resistor connected in series, in parallel with a constant voltage source, and the resistance value of the resistors is 1 kΩ or more and 1 MΩ or less.

4. The method for manufacturing a semiconductor photodetector for optical communication according to claim 1 or 2, characterized in that the reverse voltage is greater than or equal to the reach-through voltage of the semiconductor photodetector for optical communication and less than or equal to 1.1 times the breakdown voltage.

5. A method for manufacturing an optical communication semiconductor photodetector according to claim 1 or 2, characterized in that when the reverse voltage is applied, light with a light intensity of 1 μW or more and 100 mW or less is incident on the optical communication semiconductor photodetector.

6. The method for manufacturing a semiconductor photodetector according to claim 1 or 2, wherein the semiconductor photodetector for optical communication comprises a semiconductor substrate, an n-type semiconductor layer formed on the semiconductor substrate, a digital alloy structure multiplier layer formed on the n-type semiconductor layer, a p-type field relaxation layer formed on the digital alloy structure multiplier layer, a light absorption layer formed on the p-type field relaxation layer, and a p-type semiconductor layer formed on the light absorption layer.

7. The method for manufacturing a semiconductor photodetector according to claim 1 or 2, characterized in that the semiconductor photodetector for optical communication comprises a semiconductor substrate, a p-type semiconductor layer formed on the semiconductor substrate, a light-absorbing layer formed on the p-type semiconductor layer, an n-type field relaxation layer formed on the light-absorbing layer, a digital alloy structure multiplier layer formed on the n-type field relaxation layer, and an n-type semiconductor layer formed on the digital alloy structure multiplier layer.

8. A method for manufacturing a semiconductor photodetector for optical communication, A step of applying a forward current to the optical communication semiconductor photodetector having at least a digital alloy structure multiplier layer at a heat treatment temperature of 25°C to 200°C for a period of 0.2 hours to 100 hours, A method for manufacturing a semiconductor photodetector for optical communications, comprising at least the following:

9. The current density of the forward current is 3.2 × 10⁻⁶. 4 A / m 2 The above 3.2 x 10 8 A / m 2 The method for manufacturing a semiconductor photodetector for optical communications according to claim 8, characterized in that it is as follows.

10. The method for manufacturing an optical communication semiconductor photodetector according to claim 8 or 9, characterized in that the forward voltage is applied by connecting a plurality of optical communication semiconductor photodetectors, each having a resistor connected in series, in parallel to a constant voltage source, and the resistance value of the resistors is 1 kΩ or more and 1 MΩ or less.

11. The method for manufacturing a semiconductor photodetector according to 8 or 9, wherein the semiconductor photodetector for optical communication comprises a semiconductor substrate, an n-type semiconductor layer formed on the semiconductor substrate, a digital alloy structure multiplier layer formed on the n-type semiconductor layer, a p-type field relaxation layer formed on the digital alloy structure multiplier layer, a light absorption layer formed on the p-type field relaxation layer, and a p-type semiconductor layer formed on the light absorption layer.

12. The method for manufacturing a semiconductor photodetector according to 8 or 9, characterized in that the semiconductor photodetector for optical communication comprises a semiconductor substrate, a p-type semiconductor layer formed on the semiconductor substrate, a light-absorbing layer formed on the p-type semiconductor layer, an n-type field relaxation layer formed on the light-absorbing layer, a digital alloy structure multiplier layer formed on the n-type field relaxation layer, and an n-type semiconductor layer formed on the digital alloy structure multiplier layer.

13. A method for manufacturing a semiconductor photodetector for optical communication, A step of heat-treating the optical communication semiconductor photodetector having at least a digital alloy structure multiplier layer at a temperature of 300°C to 650°C for a period of 0.5 hours to 10 hours, After heat treatment, a step of forming electrodes on the semiconductor photodetector for optical communication, A method for manufacturing a semiconductor photodetector for optical communications, comprising at least the following:

14. The method for manufacturing a semiconductor photodetector according to claim 13, wherein the semiconductor photodetector for optical communication comprises a semiconductor substrate, an n-type semiconductor layer formed on the semiconductor substrate, a digital alloy structure multiplier layer formed on the n-type semiconductor layer, a p-type field relaxation layer formed on the digital alloy structure multiplier layer, a light absorption layer formed on the p-type field relaxation layer, and a p-type semiconductor layer formed on the light absorption layer.

15. The method for manufacturing a semiconductor photodetector according to claim 13, wherein the semiconductor photodetector for optical communication comprises a semiconductor substrate, a p-type semiconductor layer formed on the semiconductor substrate, a light-absorbing layer formed on the p-type semiconductor layer, an n-type field relaxation layer formed on the light-absorbing layer, a digital alloy structure multiplier layer formed on the n-type field relaxation layer, and an n-type semiconductor layer formed on the digital alloy structure multiplier layer.

16. A method for manufacturing a semiconductor photodetector for optical communication, The process of forming electrodes on the optical communication semiconductor photodetector having at least a digital alloy structure multiplier layer, The process involves subjecting the semiconductor photodetector for optical communication, after electrode formation, to a temperature cycle of 85°C to 250°C on the high-temperature side and -45°C to 30°C on the low-temperature side, within a range of 10 to 300 cycles. A method for manufacturing a semiconductor photodetector for optical communications, comprising at least the following:

17. The method for manufacturing a semiconductor photodetector according to claim 16, wherein the semiconductor photodetector for optical communication comprises a semiconductor substrate, an n-type semiconductor layer formed on the semiconductor substrate, a digital alloy structure multiplier layer formed on the n-type semiconductor layer, a p-type field relaxation layer formed on the digital alloy structure multiplier layer, a light absorption layer formed on the p-type field relaxation layer, and a p-type semiconductor layer formed on the light absorption layer.

18. The method for manufacturing a semiconductor photodetector according to claim 16, characterized in that the semiconductor photodetector for optical communication comprises a semiconductor substrate, a p-type semiconductor layer formed on the semiconductor substrate, a light-absorbing layer formed on the p-type semiconductor layer, an n-type field relaxation layer formed on the light-absorbing layer, a digital alloy structure multiplier layer formed on the n-type field relaxation layer, and an n-type semiconductor layer formed on the digital alloy structure multiplier layer.

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