Semiconductor equipment

Abstract

To provide a semiconductor device using an oxide semiconductor that achieves miniaturization while maintaining good characteristics.SOLUTION: In a semiconductor device, a transistor 160 includes an oxide semiconductor layer 144, a source electrode in contact with the oxide semiconductor layer and including a stack of a first conductive layer 142a and a second conductive layer 145a having a region extending in the channel length direction from an end of the first conductive layer, and a drain electrode having a stack of a first conductive layer 142b and a second conductive layer 145b having a region extending in the channel length direction from an end of the first conductive layer, a gate electrode 148 overlapping with the oxide semiconductor layer, and a gate insulating layer 146 provided between the oxide semiconductor layer and the gate electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technical field of this invention relates to semiconductor devices. Here, a semiconductor device is a device that utilizes semiconductor properties. This refers to all elements and devices that function by doing so. [Background technology]

[0002] Metal oxides exist in diverse forms and are used in a variety of applications. Indium oxide is well known. It is a material that has been developed and is used as a material for transparent electrodes required for liquid crystal display devices and the like. ru.

[0003] Some metal oxides exhibit semiconductor properties. For example, there are tungsten oxide, tin oxide, indium oxide, zinc oxide, and so on. Thin-film transistors using metal oxides in the channel formation region are already known (for example) , Patent Documents 1 to 4, Non-Patent Document 1, etc.).

[0004] By the way, metal oxides include not only monocrystalline oxides but also multicrystalline oxides. For example... InGaO3(ZnO) has a homologous phase. m (m: natural number) is In, Ga and It is known as a multi-component oxide semiconductor containing Zn (for example, Non-Patent Documents 2 to Non-Patent Documents 2 to 2). (See Reference 4, etc.).

[0005] Furthermore, oxide semiconductors composed of In-Ga-Zn oxides as described above are also thin-film transistors. It has been confirmed that it is applicable to the channel formation region of an inverter (for example, patent document). 5. See Non-Patent Documents 5 and 6, etc. [Prior art documents] [Patent Documents]

[0006] [License 1] Special Announcement No. 60-198861 [License 2] Special Announcement No. 8-264794 [License 3] Special Notice No. 11-505377 [License 4] Special Announcement No. 2000-150900 [Patent Document 5] Special Announcement No. 2004-103957 [Non-licensed literature]

[0007] [Non-licensed Document 1] MW Prins, KO Grosse-Holz, G. Muller, JFM Cillessen, JB Giesbers, RP Weening, and RM Wolf, "A ferroelectric transparent thin-film transistor", Appl. Phys. Lett., 17 June 1996, Vol.68 p.3650-3652 [Non-licensed Document 2] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315 [Non-licensed Document 3] N. Kimizuka, M. Isobe, and M. Nakamura, “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m(m=3,4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m(m=7,8,9, and 16) in the In2O3-ZnGa2O4-ZnO System”, J. Solid State Chem., 1995, Vol.116, p.170-178 [Non-Patent Document 4] Masaki Nakamura, Noboru Kimizuka, Naohiko Mohri, and Mitsumasa Isobe, "Synthesis and Crystal Structure of Homologous Phase, InFeO3(ZnO)m (m: natural number) and its Isomorphic Compounds," Solid State Physics, 1993, Vol.28, No.5, pp.317-327. [Non-Patent Document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, "Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor", SCIENCE, 2003, Vol.300, p.1269-1272 [Non-Patent Document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors", NATURE, 2004, Vol.432 p.488-492 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] By the way, increasing the operating speed of transistors, reducing the power consumption of transistors, and lowering their cost, etc. To achieve this, miniaturization of transistors is essential.

[0009] When miniaturizing transistors, defects that occur during the manufacturing process become a major problem. For example, the source electrode and drain electrode are electrically connected to the channel formation region. Due to miniaturization and the resulting decrease in coating quality, disconnections and connection problems may occur.

[0010] Furthermore, when miniaturizing transistors, the problem of short-channel effects arises. The effect refers to the electrical characteristics that become apparent as transistors are miniaturized (reduced channel length (L)). This is a degradation of quality. The short-channel effect occurs when the effect of the electric field at the drain electrode extends to the source electrode. This is caused by the following. Specific examples of short-channel effects include a decrease in threshold voltage. These include an increase in the S value and an increase in leakage current. In particular, transistors using oxide semiconductors, It is known that at room temperature, the off-current is smaller compared to silicon transistors. This is because there are few carriers generated by thermal excitation, meaning the carrier density is low. It is conceivable. In transistors using materials with such low carrier density, the threshold Short-channel effects, such as voltage drops, tend to be more likely to occur.

[0011] Therefore, one aspect of the disclosed invention is the provision of a semiconductor device that achieves miniaturization while suppressing defects. One of the objectives is to provide a semiconductor device that achieves miniaturization while maintaining good characteristics. This is one of its objectives. [Means for solving the problem]

[0012] One aspect of the disclosed invention comprises an oxide semiconductor layer, a source electrode in contact with the oxide semiconductor layer, and a The rain electrode, the gate electrode overlapping the oxide semiconductor layer, and the relationship between the oxide semiconductor layer and the gate electrode A gate insulating layer is provided between them, and the source electrode or drain electrode is a first conductive A layer and a second conductive layer having a region extending in the channel length direction from the edge of the first conductive layer, This is a semiconductor device that includes [a specific component / feature].

[0013] In the semiconductor device described above, it is preferable that the first conductive layer and the second conductive layer have a tapered shape. It seems so.

[0014] Furthermore, in the semiconductor device described above, a sidewall insulating layer is provided on the region of the second conductive layer. It is preferable to do so.

[0015] Another aspect of the disclosed invention is an oxide semiconductor layer and a source in contact with the oxide semiconductor layer. The electrode and drain electrode, the gate electrode overlapping the oxide semiconductor layer, and the gate electrode overlapping the oxide semiconductor layer. The source electrode and drain electrode have a gate insulating layer provided between them, and the source electrode and drain electrode are The device includes a conductive layer and a second conductive layer having higher resistance than the first conductive layer, wherein the second conductive layer In this context, it is a semiconductor device that is in contact with an oxide semiconductor layer.

[0016] Another aspect of the disclosed invention is an oxide semiconductor layer and a source in contact with the oxide semiconductor layer. The electrode and drain electrode, the gate electrode overlapping the oxide semiconductor layer, and the gate electrode overlapping the oxide semiconductor layer. The source electrode and drain electrode have a gate insulating layer provided between them, and the source electrode and drain electrode are The device includes a conductive layer and a second conductive layer having higher resistance than the first conductive layer, wherein the second conductive layer The semiconductor device is in contact with the oxide semiconductor layer in the first conductive layer.

[0017] Furthermore, in the semiconductor device described above, the second conductive layer is preferably a metal nitride.

[0018] Furthermore, in the semiconductor device described above, the thickness of the second conductive layer is 5 nm to 15 nm. preferable.

[0019] Another aspect of the disclosed invention is an oxide semiconductor layer including a channel-forming region, and a channel The source electrode and drain electrode are in contact with the channel formation region, and the gate electrode overlaps with the channel formation region. It has an electrode and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, and a source In the electrode and drain electrode, the region in contact with the channel formation region of the oxide semiconductor layer is This is a semiconductor device that has higher resistance than other regions.

[0020] Furthermore, in the above semiconductor device, the source electrode or drain electrode has an end In contact with the oxide semiconductor layer, and between the source electrode or drain electrode and the oxide semiconductor layer It is preferable that it has an insulating layer.

[0021] Here, "semiconductor device" refers to any device that can function by utilizing semiconductor properties. For example Display devices, memory devices, and integrated circuits can be included in semiconductor devices.

[0022] Furthermore, in this specification, the terms "above" and "below" refer to the positional relationship of the constituent elements, meaning "directly above" or This does not necessarily mean "directly below". For example, "gate electrode on the gate insulating layer". If the expression is ", then exclude those that include other components between the gate insulating layer and the gate electrode. No. Also, the terms "upper" and "lower" are merely expressions used for the sake of explanation and do not require any special mention. This also includes the inverted versions, unless otherwise specified.

[0023] Furthermore, in this specification, the terms "electrode" and "wiring" do not limit the functionality of these components. It is not fixed. For example, "electrode" can be used as part of "wiring". The reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and "wiring". This also includes cases where the "lines" are formed as a single unit.

[0024] Furthermore, the functions of the "source electrode" and "drain electrode" are achieved by using transistors with different polarities. The positions may be reversed in cases such as when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source electrode" and "drain electrode" are interchangeable. It may be used in this way.

[0025] Furthermore, in this specification, "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via ". Here, "something that has some electrical effect" The term "connection" is not particularly limited as long as it enables the exchange of electrical signals between connected objects. For example, "things that have some kind of electrical effect" include electrodes and wiring, as well as transistors. These include switching elements, resistive elements, inductors, capacitors, and various other functional elements. This includes elements such as [specific components]. [Effects of the Invention]

[0026] One aspect of the disclosed invention can achieve one or both of the following effects: be.

[0027] Firstly, the source electrode and drain electrode are configured as a laminated structure of a first conductive layer and a second conductive layer. By providing a region in the second conductive layer that extends in the channel length direction from the edge of the first conductive layer, Therefore, the coverage when forming a semiconductor layer on the source electrode and drain electrode is improved. This suppresses the occurrence of connection problems and other issues.

[0028] Secondly, in the source electrode or drain electrode, the vicinity of the region in contact with the channel formation region. By creating a high-resistance region, the electric field between the source electrode and the drain electrode can be relaxed. Therefore, short-channel effects such as threshold voltage reduction can be suppressed.

[0029] These effects eliminate the problems associated with miniaturization, and as a result, It becomes possible to make the transistor size sufficiently small. By making it smaller, the area occupied by the semiconductor device using transistors is reduced, and the substrate area The number of semiconductor devices per unit increases. As a result, the manufacturing cost per semiconductor device is reduced. It will be controlled. Also, because semiconductor devices will be miniaturized, it will be possible to further enhance functionality while maintaining the same size. This enables the realization of advanced semiconductor devices. Furthermore, the reduction in channel length allows for faster operation. Furthermore, effects such as reduced power consumption can be obtained. In other words, according to one aspect of the disclosed invention, acid The miniaturization of transistors using synthetic semiconductors will lead to various associated effects. It is possible to obtain results.

[0030] Thus, according to one aspect of the disclosed invention, defects can be suppressed, or good characteristics can be achieved. This allows us to provide semiconductor devices that achieve miniaturization while maintaining existing features. [Brief explanation of the drawing]

[0031] [Figure 1] Cross-sectional view of a semiconductor device. [Figure 2] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 3] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 4] Cross-sectional view of a semiconductor device. [Figure 5] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 6] An example of a semiconductor device circuit diagram. [Figure 7] An example of a semiconductor device circuit diagram. [Figure 8] An example of a semiconductor device circuit diagram. [Figure 9] Examples of electronic devices. [Figure 10] A cross-sectional view showing the transistor model used in the calculations. [Figure 11] This figure shows the relationship between channel length L (nm) and threshold voltage shift amount ΔVth (V). [Figure 12] This figure shows the relationship between channel length L (nm) and threshold voltage shift amount ΔVth (V). [Figure 13] This figure shows the relationship between channel length L (nm) and threshold voltage shift amount ΔVth (V). [Modes for carrying out the invention]

[0032] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is as follows The description is not limited to the present invention, and the form and details may not depart from the spirit and scope of the present invention. Those skilled in the art will readily understand that the parameters can be modified in various ways. Accordingly, the present invention is described below. This should not be interpreted as being limited to the contents described in the embodiment.

[0033] Note that the position, size, and scope of each component shown in the drawings, etc., are for ease of understanding. The position, size, and range of the edges may not be shown. Therefore, the disclosed invention is not necessarily However, this is not limited to the location, size, and scope disclosed in drawings, etc.

[0034] Furthermore, the ordinal numbers such as "1st," "2nd," and "3rd" used in this specification, etc., are intended to avoid confusion of constituent elements. This is added to avoid any misunderstandings and does not mean that the number is limited.

[0035] (Embodiment 1) This embodiment provides an example of the configuration of a semiconductor device and its manufacturing process according to one aspect of the disclosed invention. This will be explained with reference to Figures 1 to 3.

[0036] <Example of semiconductor device configuration> Figures 1(A) to 1(D) show the cross-sectional structure of a transistor as an example of a semiconductor device. Figures 1(A) to 1(D) show a transistor according to one aspect of the disclosed invention, This shows a buoyant gate-type transistor.

[0037] The transistor 160 shown in Figure 1(A) has a first conductive layer 142a and on the substrate 100. A source electrode in which two conductive layers 145a are sequentially stacked, and the first conductive layer 142b and the second conductive layer A drain electrode in which layers 145b are sequentially stacked, and an insulating layer 143 provided on the source electrode. a, an insulating layer 143b provided on the drain electrode, insulating layer 143a and insulating layer 143 an oxide semiconductor layer 144 provided on b, and a gate provided on the oxide semiconductor layer 144 It has an insulating layer 146 and a gate electrode 148 provided on the gate insulating layer 146. .

[0038] In the transistor 160 shown in Figure 1(A), the second conductive layer 145a is the first conductive layer It has a region that extends from the end of 142a in the channel length direction (direction of carrier flow). Furthermore, the second conductive layer 145a and at least the channel formation region of the oxide semiconductor layer 144 are in contact. Furthermore, the second conductive layer 145b has a channel length greater than the edge of the first conductive layer 142b. It has a region that is extended in the direction, and the second conductive layer 145b and the oxide semiconductor layer 144 are less However, it is in contact with the channel-forming region.

[0039] More specifically, the second conductive layer 145a has a channel length greater than the edge of the first conductive layer 142a. It has a region that extends toward the drain electrode in the direction (the direction in which the carrier flows). Furthermore, the second conductive layer 145b is sourced from the edge of the first conductive layer 142b in the channel length direction. It has a region that extends toward the electrode.

[0040] The difference between transistor 170 shown in Figure 1(B) and transistor 160 shown in Figure 1(A). One difference is the presence or absence of insulating layers 143a and 143b. Transistor 170 shown in Figure 1(B) Acid is used to contact the upper surface and edges of the second conductive layer 145a and the second conductive layer 145b. A synthetic semiconductor layer 144 is provided.

[0041] In transistor 170 shown in Figure 1(B), similar to transistor 160, the second The conductive layer 145a has a region that extends in the channel length direction from the edge of the first conductive layer 142a. The second conductive layer 145b extends in the channel length direction from the edge of the first conductive layer 142b. It has an extended region.

[0042] The difference between transistor 180 shown in Figure 1(C) and transistor 160 shown in Figure 1(A). One of the stacking order of the first conductive layer 142a and the second conductive layer 145a, and the first conductive layer 1 This is the stacking order of 42b and the second conductive layer 145b. Transistor 180 shown in Figure 1(C) This includes a source electrode in which a second conductive layer 145a and a first conductive layer 142a are sequentially laminated, and The drain electrode comprises a second conductive layer 145b and a first conductive layer 142b, which are stacked in order. It is.

[0043] Furthermore, in the transistor 180 shown in Figure 1(C), the second conductive layer 145a is the first The conductive layer 142a has a region that extends in the channel length direction from its edge, and the second conductive layer 1 45b has a region that extends in the channel length direction from the edge of the first conductive layer 142b. Therefore, the insulating layer 143a is in the second conductive layer 145a, and the first conductive layer 142a A region extending in the channel length direction from the end, and the first conductive layer 142a, are provided in contact with each other. Furthermore, the insulating layer 143b is in the second conductive layer 145b, and the first conductive layer 142 A region extending in the channel length direction from the end of b is provided in contact with the first conductive layer 142b. It is being done.

[0044] The difference between transistor 190 shown in Figure 1(D) and transistor 180 shown in Figure 1(C). One difference is the presence or absence of insulating layers 143a and 143b. Transistor 190 shown in Figure 1(D) Now, regarding the first conductive layer 142a, the first conductive layer 142b, and the second conductive layer 145a... a region extending in the channel length direction from the edge of the first conductive layer 142a, and the second conductive layer 14 In 5b, a region extending in the channel length direction from the edge of the first conductive layer 142b is in contact with, An oxide semiconductor layer 144 is provided.

[0045] In the transistor 190 shown in Figure 1(D), the second conductive layer 145a is the first conductive layer It has a region that extends in the channel length direction from the end of 142a, and the second conductive layer 145a It is in contact with at least the channel formation region of the oxide semiconductor layer 144. Also, the second guide The conductive layer 145b has a region that extends in the channel length direction from the end of the first conductive layer 142b. The second conductive layer 145b and at least the channel formation region of the oxide semiconductor layer 144 They are in contact.

[0046] <Example of the transistor manufacturing process> The following describes an example of the transistor fabrication process shown in Figure 1, using Figures 2 and 3. .

[0047] <Manufacturing process for transistor 160 or transistor 170> First, using Figures 2(A) to 2(F), we fabricate the transistor 160 shown in Figure 1(A). An example of the process will be explained. Note that the transistor 170 shown in Figure 1(B) has an insulating layer 1 Except for not providing 43a and 143b, refer to the manufacturing process of transistor 160. Since this is possible, detailed descriptions will be omitted.

[0048] A first conductive film is formed on a substrate 100 having an insulating surface, and the conductive film is selectively etched. Then, the first conductive layers 142a and 142b are formed (see Figure 2(A)). The film thickness is, for example, 50 nm to 500 nm.

[0049] There are no major restrictions on the type of substrate that can be used for substrate 100, however, at least the following It is necessary to have heat resistance sufficient to withstand heat treatment. For example, glass substrates, Ceramic substrates, quartz substrates, sapphire substrates, etc. can be used as substrates. If it has a surface, it can be a single-crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate It is also possible to apply plates, compound semiconductor substrates such as silicon germanium, and SOI substrates. It is possible, and semiconductor elements may be provided on these substrates. Also, on the substrate 100 A base layer may be provided.

[0050] The first conductive film is produced using PVD methods such as sputtering, or CVD methods such as plasma CVD. It can be formed using the method. Furthermore, as the material for the first conductive film, aluminum, Elements selected from chromium, copper, tantalum, titanium, molybdenum, and tungsten, and this Nitrides, alloys containing the above-mentioned elements, etc., can be used. Manganese, Magnesium Materials consisting of one or more of the following: cyum, zirconium, beryllium, or a combination of these. It may also be used. In addition, titanium, tantalum, tungsten, molybdenum, Elements selected from chromium, neodymium, and scandium, or combinations of these elements. You may use a fertilizer.

[0051] The first conductive film may be a single-layer structure or a laminated structure of two or more layers. , a single-layer structure of titanium film, a single-layer structure of silicon-containing aluminum film, on an aluminum film A two-layer structure with stacked titanium films, and a three-layer structure with stacked titanium films, aluminum films, and titanium films. Examples include layered structures. Furthermore, if the first conductive film is a single-layer structure, a tapered shape is used. It has the advantage of being easy to process into source and drain electrodes.

[0052] Furthermore, the first conductive film may be formed using a conductive metal oxide. The materials are indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (ZnO). Indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO) indium zinc oxide alloy (In2O3-ZnO), or these metal oxide materials A material containing silicon or silicon oxide can be used.

[0053] Etching of the first conductive film results in the formation of the first conductive layer 142a and the first conductive layer 142 It is preferable that the end of b be tapered. Here, the taper angle α1 and β1 is the edge of the first conductive layer 142a and the first conductive layer 142b with respect to the substrate surface, respectively. This is the angle formed by the side surfaces of the part, and it is preferable that it is, for example, 30° or more and 60° or less (Figure 2(A )reference).

[0054] Next, a second conductive film 1 is applied so as to cover the first conductive layers 142a, 142b and the substrate 100. Form 45. The thickness of the second conductive film 145 is 3 nm to 30 nm, preferably 5 nm. The nm range is 15 nm or less.

[0055] The second conductive film 145 can be formed using the same material and the same film formation method as the first conductive film. Yes. In other words, the materials for the second conductive film include aluminum, chromium, copper, tantalum, and thi. Elements selected from tan, molybdenum, and tungsten, as well as their nitrides, and the elements mentioned above. Alloys containing the following components can be used: manganese, magnesium, zirconium, bellflower. Any of the lylium materials, or combinations thereof, may be used. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, sulfite Materials may be made from elements selected from zinc, or from combinations of several of these elements. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), in Dium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), tin oxide Zinc oxide alloy (In2O3-ZnO), or silicon alloys of these metal oxide materials A conductive metal oxide containing silicon dioxide or silicon oxide may also be used.

[0056] Furthermore, the material for the second conductive film 145 has higher resistance than the first conductive layers 142a and 142b. It is preferable to use such materials. Source electrode and drain of the fabricated transistor 160 In the electrode, the region in contact with the channel formation region of the oxide semiconductor layer is larger than the other regions. This high resistance also relaxes the electric field between the source and drain electrodes, resulting in a short-channel effect. This is because it can suppress [the following]. Examples of conductive materials used for the second conductive film 145 include For example, metallic nitrides such as titanium nitride, tungsten nitride, tantalum nitride, or molybdenum nitride. A compound can preferably be used. Also, the second conductive film 145 is the source electrode or Dray Since it becomes part of the in electrode and comes into contact with the oxide semiconductor layer, the second conductive film 145 has an oxide semiconductor layer It is desirable to use a material that does not chemically react upon contact with the conductive layer. The metal nitrides mentioned above are This is also preferable.

[0057] Next, an insulating film 143 is applied to the second conductive film 145 to a thickness of 50 nm to 300 nm, preferably. The layer is formed at a wavelength of 100 nm to 200 nm (see Figure 2(A)). In this embodiment, The insulating film 143 is to form a silicon oxide film. Note that in Figure 1(B) As shown with transistor 170, the insulating film 143 does not necessarily have to be formed. However, if an insulating film 143 is provided, the source electrode or drain electrode that is formed later will be required. This makes it easier to control the contact area (contact area, etc.) with the oxide semiconductor layer. This facilitates control of the resistance of the electrode or drain electrode, effectively suppressing short-channel effects. This can be achieved. Furthermore, by providing the insulating film 143, the gate electrode that is formed later can be connected to it. This makes it possible to reduce parasitic capacitance between the source electrode and the drain electrode.

[0058] Next, a mask is formed on the insulating film 143, and the insulating film 143 is etched using the mask. This forms insulating layers 143a and 143b (see Figure 2(B)). Insulating film 14 For etching step 3, either wet etching or dry etching can be used. Wet etching and dry etching may be used in combination. The insulating film can be shaped as desired. To enable etching in a specific pattern, etching conditions (etching gas and etching) are adjusted according to the material. The etching solution, etching time, temperature, etc. should be set appropriately. However, the transistor chip To precisely machine the channel length (L), it is preferable to use dry etching. Examples of etching gases used in lye etching include sulfur hexafluoride (SF6), and 3. Fluorine-containing gases such as nitrogen fluoride (NF3) and trifluoromethane (CHF3), or A mixed gas of carbon tetrafluoride (CF4) and hydrogen can be used, as can a noble gas (helium ( Add He), argon (Ar), xenon (Xe), carbon monoxide, or carbon dioxide, etc. You can.

[0059] Next, the second conductive film 145 is etched using the mask used to etch the insulating film 143. By chipping, second conductive layers 145a and 145b are formed (see Figure 2(C)). Furthermore, before etching the second conductive film 145, remove the mask and the insulating layer 143a and The second conductive film 145 may be etched using the insulating layer 143b as a mask. As shown in transistor 170 in Figure 1(B), if an insulating layer is not provided, the second conductor Alternatively, the second conductive film can be etched by directly forming a mask on the conductive film 145. Etching of the conductive film 145 is performed on the edges of the second conductive layer 145a and the second conductive layer 145b. It is preferable to make it tapered. If an insulating film 143 is provided, the insulating layer It is preferable that the ends of 143a and the insulating layer 143b also be tapered. Here, the taper angles α2 and β2 are, respectively, relative to the substrate surface of the second conductive layer 145a , at the corner formed by the second conductive layer 145b, the insulating layer 143a, and the side surface of the end of the insulating layer 143b Yes, and preferably it is between 30° and 60°.

[0060] For etching the second conductive film 145, either wet etching or dry etching is used. It is possible to use a combination of wet etching and dry etching. To etch the material into the desired shape, etching conditions (etching gas and The etching solution, etching time, temperature, etc. should be set appropriately. However, transient To precisely machine the channel length (L) of the sta, dry etching is preferred. For example, chlorine is used as the etching gas for etching the second conductive film 145. (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrafluoride ( CF4) Sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), etc. can be used. A mixed gas can be used, with multiple gases selected from among them. Also, a noble gas (helium (He) Argon (Ar) or oxygen may be added. Also, the second conductive film 145 The etching can also be performed continuously using the same gas as the etching of insulating film 143.

[0061] This etching process results in the lamination of the first conductive layer 142a and the second conductive layer 145a. A source electrode and a drain electrode with a first conductive layer 142b and a second conductive layer 145b laminated together. An electrode is formed. By appropriately adjusting the mask used for etching, the first conductive layer 14 A second conductive layer 145a having a region extending in the channel length direction from the end of 2a, or A second conductive layer 1 having a region extending in the channel length direction from the edge of the first conductive layer 142b 45b can be formed.

[0062] The channel length (L) of transistor 160 is the distance between the lower end of the second conductive layer 145a and the second The channel length (L) is determined by the distance from the lower end of the conductive layer 145b. The wavelength varies depending on the application of Sta 160, but for example, 10 nm to 1000 nm, preferably 20 The wavelength can be between nm and 400 nm.

[0063] Furthermore, when forming a transistor with a channel length (L) of less than 25 nm, the insulating film 143 and When performing exposure for mask formation used in etching the second conductive film 145, several nm to several It uses extremely short wavelengths of 10 nm (extreme ultraviolet). This is desirable. Exposure with ultra-ultraviolet light provides high resolution and a large depth of field. Therefore, later formation The channel length (L) of the transistor can be made sufficiently small, and the circuit It is possible to increase the operating speed. Also, miniaturization reduces the power consumption of semiconductor devices. It was also possible to reduce it.

[0064] Furthermore, in the second conductive layer, the region extending in the channel length direction from the edge of the first conductive layer is This provides the effect of improving coverage in the subsequent oxide semiconductor layer and gate insulating layer formation process. In the second conductive layer 145a, from the edge of the first conductive layer 142a in the channel length direction. The length in the channel length direction of the extended region (L S ) and in the second conductive layer 145b, The length in the channel length direction of the region extending in the channel length direction from the edge of conductive layer 142b ( L D ) and are not necessarily the same. However, for example, if transistor 160 is on the same board When multiple transistors are provided, the L in each transistor S and L D The sum of these two values ​​will be approximately constant.

[0065] Next, the oxide semiconductor layer 144 is spat onto the insulating layers 143a, 143b, and the substrate 100. It is formed by the T method (see Figure 2(D)). The thickness of the oxide semiconductor layer 144 is, for example, 3 The nm to 30 nm, preferably 5 nm to 15 nm. The formed oxide semiconductor layer 1 44 is a second conductive layer 145a and a second conductive layer 145b and at least a channel forming region They are in contact at that point.

[0066] Here, the second conductive layers 145a and 145b are located at the edges of the first conductive layers 142a and 142b. Furthermore, by having a region that extends in the direction of the channel length, the ends of the source electrode and drain electrode The step in this can be made gentler. Therefore, the oxide semiconductor layer 144 This improves coverage and prevents uneven tearing.

[0067] The source and drain electrodes of the fabricated transistor 160 are connected to the second conductive layer 1. Only at the edges of 45a and the second conductive layer 145b are in contact with the oxide semiconductor layer 144. This allows the oxide semiconductor layer to be in contact with the upper surfaces of the source electrode and drain electrode. Compared to the case where the contact area is significantly reduced, the source electrode can be reduced in this way. Furthermore, by reducing the contact area between the drain electrode and the oxide semiconductor layer 144, the contact interface This can increase the contact resistance and the electric field between the source electrode and the drain electrode. It can be mitigated. The technical concept of the disclosed invention is the source electrode and the drain electrode. Since the objective is to form a high-resistance region, the source electrode and drain electrode are strictly second Only at the edges of the conductive layer 145a and the second conductive layer 145b, the oxide semiconductor layer 144 and Contact is not required. For example, the second conductive layer 145a and the second conductive layer 145b are on the upper surface In some parts, it may be in contact with the oxide semiconductor layer 144.

[0068] The oxide semiconductor layer 144 is made of a quaternary metal oxide such as In-Sn-Ga-Zn-O, or a three-component metal oxide. The original metal oxide systems are In-Ga-Zn-O, In-Sn-Zn-O, and In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O Systems such as the In-Zn-O system, Sn-Zn-O system, and Al-Zn-O system, which are binary metal oxides. , Zn-Mg-O system, Sn-Mg-O system, In-Mg-O system, and monocrystalline metal oxides It can be formed using In-O, Sn-O, Zn-O, and other similar materials.

[0069] In particular, In-Ga-Zn-O oxide semiconductor materials have sufficiently high resistance in the absence of an electric field. Because the current can be made sufficiently small, and the field effect mobility is also high, semiconductors It is suitable as a semiconductor material for use in the device.

[0070] A typical example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m There are some that are written as (m>0, m: non-natural number). Also, M is used instead of Ga, and I nMO3(ZnO) m Oxide semiconductor materials that are expressed as (m>0, m: non-natural number) Yes, there is. Here, M is gallium (Ga), aluminum (Al), iron (Fe), nickel. One or multiple metallic elements selected from (Ni), manganese (Mn), cobalt (Co), etc. It shows a number of metallic elements. For example, as M, there are Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and Mn, Ga and Co, etc. can be used. Note that the above compositions are It should be noted that this is derived from the crystal structure and is merely one example.

[0071] For fabricating the oxide semiconductor layer 144 by sputtering, the target is In:Ga: We use a material represented by the empirical formula Zn=1:x:y (where x is greater than or equal to 0, and y is between 0.5 and 5). It is preferable to do so. For example, In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] A metal oxide target having the composition ratio of ] can be used. Also, In2O3 Metal oxide target having a composition ratio of :Ga2O3:ZnO=1:1:1 [molar ratio] Gold with a composition ratio of In2O3:Ga2O3:ZnO=1:1:4 [molar ratio] For group oxide targets, or In2O3:Ga2O3:ZnO=1:0:2 [molar ratio] Metal oxide targets with specific compositional ratios can also be used.

[0072] In this embodiment, the amorphous oxide semiconductor layer 144 is made of an In-Ga-Zn-O gold The material will be formed by sputtering using an oxide target.

[0073] The relative density of metal oxides in the metal oxide target is 80% or more, preferably 95% or more. More preferably, it is 99.9% or higher. A metal oxide target with a high relative density is used. This makes it possible to form an oxide semiconductor layer 144 with a dense structure.

[0074] The formation atmosphere for the oxide semiconductor layer 144 is a noble gas (typically argon) atmosphere, an oxygen atmosphere. A gaseous atmosphere, or a mixed atmosphere of a noble gas (typically argon) and oxygen, is preferable. Specifically, for example, impurities such as hydrogen, water, hydroxyl groups, and hydrides must be present at a concentration of 1 ppm or less. It is preferable to use a high-purity gas atmosphere in which the gas has been removed to a concentration of 10 ppb or less (preferably). That is the case.

[0075] During the formation of the oxide semiconductor layer 144, for example, the workpiece is placed in a processing chamber maintained under reduced pressure. The object (in this case, a structure including the substrate 100) is held, and the temperature of the object to be processed is 100°C or higher 55°C Heat the object to be treated to a temperature below 0°C, preferably between 200°C and 400°C. The temperature of the workpiece during the formation of the oxide semiconductor layer 144 may be room temperature. While removing moisture from the laboratory, sputtered gas from which hydrogen and water have been removed is introduced, and the above-mentioned ter A GET is used to form an oxide semiconductor layer 144. The oxide semiconductor layer is formed while heating the workpiece. By forming 144, the impurities contained in the oxide semiconductor layer 144 can be reduced. Yes, it is possible. Furthermore, it can reduce damage caused by spatter. It also removes moisture from the processing chamber. For this purpose, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, ion A turbo pump, titanium sublimation pump, etc. can be used. A system with a cold trap added to the pump may also be used. Exhaust can be performed using a cryopump or similar device. By doing so, hydrogen and water can be removed from the processing chamber, thus the oxide semiconductor layer 144 The concentration of impurities inside can be reduced.

[0076] The conditions for forming the oxide semiconductor layer 144 include, for example, the distance between the workpiece and the target. The diameter is 170 mm, the pressure is 0.4 Pa, the DC power is 0.5 kW, and the atmosphere is oxygen (oxygen 100% argon atmosphere, or argon (100% argon) atmosphere, or oxygen and argon Conditions such as a mixed atmosphere can be applied. Furthermore, a pulsed DC power supply can be used. When used, it can reduce the amount of powdery material (also called particles or dust) generated during film formation, and the film thickness The uniform distribution is also preferable. The thickness of the oxide semiconductor layer 144 is, for example, 3 nm to 3 The thickness is 0 nm, preferably 5 nm to 15 nm. Oxide semiconductor layer 144 of this thickness. By using this method, it is possible to suppress the short-channel effect associated with miniaturization. However, The appropriate thickness varies depending on the oxide semiconductor material used and the application of the semiconductor device. The thickness can be selected according to the materials used and the intended application.

[0077] Furthermore, before forming the oxide semiconductor layer 144 by sputtering, argon gas was introduced. Reverse sputtering is performed to generate plasma, and the formed surface (e.g., insulating layer 143a, 143b) It is preferable to remove deposits from the surface. Here, reverse sputtering is a type of conventional sputtering. In this process, instead of ions colliding with the sputtering target, ions are instead collided with the surface of the treated area. This refers to a method of modifying a surface by impacting it with ions. One method of collision involves applying a high-frequency voltage to the surface being treated under an argon atmosphere. Methods include generating plasma near the physical object. Note that nitrogen or helium can be used instead of an argon atmosphere. An atmosphere containing alium, oxygen, etc., may also be applied.

[0078] Subsequently, it is desirable to perform a heat treatment (first heat treatment) on the oxide semiconductor layer 144. This first heat treatment removes excess hydrogen (water and hydroxyl groups) from the oxide semiconductor layer 144. This removes the defects, improves the structure of the oxide semiconductor layer, and reduces the defect levels in the energy gap. This is possible. The temperature of the first heat treatment is, for example, 300°C or more and less than 550°C, or 40°C. The temperature should be between 0°C and 500°C.

[0079] Heat treatment involves, for example, introducing the workpiece into an electric furnace using a resistance heating element, and performing the treatment under a nitrogen atmosphere. This can be carried out under conditions of 450°C for 1 hour. During this time, the oxide semiconductor layer 144 is not exposed to the atmosphere. Prevent leakage and ensure that no water or hydrogen is introduced.

[0080] Heat treatment equipment is not limited to electric furnaces; it also utilizes heat conduction or thermal radiation from a heated medium such as gas. A device that heats the object to be processed may be used. For example, LRTA (Lamp Ra PID Thermal Anneal) device, GRTA (Gas Rapid The RTA (Rapid Thermal Annealing) for devices such as thermal annealing equipment. ) The device can be used. The LRTA device uses halogen lamps and metal halide lamps. xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps This device heats the object to be processed by radiating light (electromagnetic waves) emitted from lamps such as fountains. A GRTA apparatus is a device that performs heat treatment using high-temperature gas. The gas used is argon. Noble gases such as nitrogen, or inert gases that do not react with the material being treated by heat treatment. It is used.

[0081] For example, as a first heat treatment, the object to be treated is placed in a heated inert gas atmosphere for several minutes. After interheating, a GRTA treatment may be performed in which the workpiece is removed from the inert gas atmosphere. Using GRTA treatment enables high-temperature heat treatment in a short time. Furthermore, the heat resistance temperature of the workpiece... It can be applied even under temperature conditions exceeding [a certain degree]. Furthermore, during the process, an inert gas is used, along with oxygen. You may switch to a gas containing [the specified substance]. Perform the first heat treatment in an oxygen-containing atmosphere. This is because it can reduce defect levels in the energy gap caused by oxygen deficiency. .

[0082] The inert gas atmosphere can be nitrogen or a noble gas (helium, neon, argon, etc.). It is desirable to apply an atmosphere whose main component is ( ) and which does not contain water, hydrogen, etc. For example, nitrogen, helium, neon, argon, and other noble gases introduced into heat treatment equipment. The purity should be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher. That is, the impurity concentration should be 1 ppm or less, preferably 0.1 ppm or less.

[0083] In any case, the first heat treatment reduces impurities, resulting in a type i (intrinsic semiconductor) or type i By forming an oxide semiconductor layer 144 that is extremely close to the original, an extremely excellent transient is achieved. It is possible to achieve this.

[0084] By the way, the heat treatment described above (the first heat treatment) has the effect of removing hydrogen, water, etc. This heat treatment can also be called a dehydration treatment or a dehydrogenation treatment. Dehydrogenation treatment is performed after the formation of the oxide semiconductor layer or the gate insulating layer, and after the formation of the gate electrode. It can also be done at later times, such as afterwards. Hydrogenation treatment can be performed multiple times, not just once.

[0085] Next, a gate insulating layer 146 is formed in contact with the oxide semiconductor layer 144 (see Figure 2(E)). Here, the second conductive layers 145a and 145b are located at the edges of the first conductive layers 142a and 142b. Having a region that extends further in the channel length direction than the source electrode and drain electrode ends The step in the section can be made gentler. Therefore, the gate insulating layer 146 This improves coverage and prevents uneven tearing.

[0086] The gate insulating layer 146 can be formed using methods such as CVD or sputtering. The gate insulating layer 146 is made of silicon oxide, silicon nitride, silicon oxide nitride, and aluminum oxide. Hfnium, tantalum oxide, hafnium oxide, yttrium oxide, hafnium silicate (Hf SixOy (x>0, y>0), nitrogen-added hafnium silicate (HfSix OyNz(x>0, y>0, z>0), nitrogen-doped hafnium aluminate (H It is preferable to form it such that it includes fAlxOyNz(x>0, y>0, z>0), etc. Yes. The gate insulating layer 146 may be a single-layer structure or a multi-layer structure. Also, The thickness is not particularly limited, but when miniaturizing semiconductor devices, the operation of the transistor To ensure this, it is desirable to make it thin. The wavelength can be between m and 100 nm, preferably between 10 nm and 50 nm.

[0087] As mentioned above, thinning the gate insulation layer can lead to gate leakage caused by the tunnel effect, etc. This poses a problem. To resolve the gate leakage problem, the gate insulating layer 146 contains hafny oxide. Mu, tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy(x>0) , y>0)), nitrogen-added hafnium silicate (HfSixOyNz(x>0, y>0, z>0), nitrogen-added hafnium aluminate (HfAlxOyNz( It is preferable to use high-dielectric constant (high-k) materials such as x>0, y>0, z>0). By using igh-k material for the gate insulating layer 146, electrical characteristics are ensured while the gate It becomes possible to increase the film thickness to suppress leakage. A film containing silicon oxide, silicon nitride, silicon oxide nitride, silicon oxide, and a It may also be a laminated structure with a film containing luminium or any other material.

[0088] After the formation of the gate insulating layer 146, a second heat treatment is performed under an inert gas atmosphere or an oxygen atmosphere. It is desirable to perform the treatment. The heat treatment temperature should be between 200°C and 450°C, preferably 25°C. It is 350°C or lower and 0°C or higher. For example, heat treatment may be performed at 250°C for 1 hour in a nitrogen atmosphere. By performing the second heat treatment, variations in the electrical characteristics of the transistor can be reduced. In addition, when the gate insulating layer 146 contains oxygen, oxygen is supplied to the oxide semiconductor layer 144 to fill the oxygen deficiency in the oxide semiconductor layer 144, and an oxide semiconductor layer of type i (intrinsic semiconductor) or an oxide semiconductor layer that is extremely close to type i can also be formed.

[0089] Note that in this embodiment, the second heat treatment is performed after the formation of the gate insulating layer 146, but the timing of the second heat treatment is not particularly limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. Further, the second heat treatment may be performed following the first heat treatment, or the second heat treatment may be combined with the first heat treatment, or the first heat treatment may be combined with the second heat treatment.

[0090] As described above, by applying at least one of the first heat treatment and the second heat treatment, the oxide semiconductor layer 144 can be purified to a high purity so that it contains as few impurities other than its main component as possible. As a result, the hydrogen concentration in the oxide semiconductor layer 144 can be made 5×10 atoms / 19 cm 3 or less, desirably 5×10 18 atoms / cm 3 or less, more desirably 5×10 17 atoms / cm 3 or less. Further, the carrier density of the oxide semiconductor layer 144 can be made sufficiently smaller than the carrier density (about 1×10 / cm 14 3 ) in a general silicon wafer (for example, 1×10 12 / cm 3Less than, more preferably, 1 .45×10 10 / cm 3 It can be set to less than ). And this allows the off-current to It becomes sufficiently small. For example, the off-current of transistor 160 at room temperature (here, the unit is ch The value per channel width (1 μm) is 100 zA / μm (1 zA (zeptoampere) is 1 ×10 -21 A) Preferably, the level should be 10 zA / μm or less.

[0091] Next, the gate insulating layer 146 is superimposed with the channel formation region of the oxide semiconductor layer 144. A gate electrode 148 is formed in the region (see Figure 2(F)). The gate electrode 148 is a gate After forming a conductive film on the insulating layer 146, selective etching of the conductive film is performed. It can be formed in this way. The conductive film that will become the gate electrode 148 can be formed by sputtering, among other methods. It can be formed using PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition) methods such as plasma CVD. For details, see below. This is similar to the case of source electrodes or drain electrodes, and these descriptions can be taken into consideration. However, the work function of the gate electrode material 148 is approximately the same as the electron affinity of the oxide semiconductor layer 144. If the threshold voltage is minus 1 degree or less, when the transistor is miniaturized, the threshold voltage will be minus 1 degree It may shift to eggplant. Therefore, the gate electrode 148 has an oxide semiconductor layer 144 It is preferable to use a material that has a work function greater than its electron affinity. Examples include tungsten, platinum, gold, and silicon with p-type conductivity.

[0092] With the above steps, the transistor 160 using the oxide semiconductor layer 144 is completed.

[0093] <Manufacturing process for transistor 180 or transistor 190> Next, using Figures 3(A) to (F), the fabrication process for transistor 180 shown in Figure 1(C) is described. Let's explain an example of this. Note that the transistor 190 shown in Figure 1(D) has an insulating layer 14 Except for the absence of 3a and 143b, the manufacturing process of transistor 180 can be considered. Therefore, detailed descriptions are omitted.

[0094] A second conductive film 145 is deposited on the substrate 100. The thickness of the second conductive film 145 is 3 nm. The thickness is to 30 nm, preferably 5 nm to 15 nm. Next, on the second conductive film 145 A first conductive film is formed, and the first conductive film is selectively etched to form a first conductive layer 142 a and 142b are formed. Then, the first conductive layer 142a, 142b and the second conductive film are formed. An insulating film 143 is formed on 145 (see Figure 3(A)).

[0095] Furthermore, when the first conductive film is deposited on the second conductive film, the second conductive film and the first conductive film The materials selected shall be those that allow for an appropriate etching selectivity ratio. Furthermore, the second conductive It is preferable to use a material with higher resistance than the first conductive film for the film. This forms a titanium nitride film as the second conductive film 145, and a tungsten film as the first conductive film. It forms a film or molybdenum film, and carbon tetrafluoride (CF4), chlorine (Cl2), and oxygen (O2) A mixed gas of ) and a mixed gas of carbon tetrafluoride (CF4) and oxygen (O2), sulfur hexafluoride (S A mixed gas of F6, chlorine (Cl2), and oxygen (O2), or sulfur hexafluoride (SF6) By etching the first conductive film using a mixed gas of and oxygen (O2), the first conductive Layers 142a and 142b are formed.

[0096] Furthermore, as shown in Figure 1(D) with transistor 190, the insulating film 143 is not necessarily Although it is not necessary to form it, by providing the insulating film 143, the gate electrode that will be formed later will be This makes it possible to reduce parasitic capacitance between the source electrode and the drain electrode.

[0097] Next, a mask is formed on the insulating film 143, similar to the process shown in Figure 2(B), and the mask By etching the insulating film 143 using this method, insulating layers 143a and 143b are formed. (See Figure 3(B)).

[0098] Next, the insulating layer 143a and insulating layer 143b are etched in the same manner as shown in Figure 2(C). By etching the second conductive film 145 using the mask used for etching, the second conductive film Form the electrode layers 145a and 145b (see Figure 3(C)). Note that the second conductive film 145 is Remove the mask before cutting, and use insulating layer 143a and insulating layer 143b as the mask. The second conductive film 145 may be etched. Examples of etching gases include chlorine (Cl2), boron trichloride (BCl3), and tetrachloride. Silicon chloride (SiCl4), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), trifluoride Nitrogen (NF3), etc., can be used, and a mixed gas can be used by selecting several of these. It is also possible to add noble gases (helium (He), argon (Ar)). Furthermore, as shown in transistor 190 in Figure 1(D), if an insulating layer is not provided, the second The second conductive film can be etched by directly forming a mask on the conductive film 145.

[0099] Next, similar to the process shown in Figure 2(D), insulating layers 143a, 143b, and substrate 100 An oxide semiconductor layer 144 is formed on top by sputtering (see Figure 3(D)). The oxide semiconductor layer 144 is less than the second conductive layer 145a and the second conductive layer 145b. They are in contact in the channel formation region. Also, heat It is desirable to perform the treatment (first heat treatment).

[0100] Next, similar to the process shown in Figure 2(E), the gate insulating layer in contact with the oxide semiconductor layer 144 is formed. Form 146 (see Figure 3(E)). After the formation of the gate insulating layer 146, heat treatment (second It is desirable to perform heat treatment.

[0101] Next, similar to the process shown in Figure 2(F), an oxide semiconductor is formed on the gate insulating layer 146. A gate electrode 148 is formed in the region overlapping with the channel formation region of layer 144 (Figure 3(F)). reference).

[0102] With the above steps, the transistor 180 using the oxide semiconductor layer 144 is completed.

[0103] In the transistors 160, 170, 180, and 190 shown in this embodiment, the first guide The device includes a source electrode and a drain electrode, each having a voltage layer and a second conductive layer laminated together, the second conductive layer 1 45a and 145b extend in the channel length direction beyond the edges of the first conductive layers 142a and 142b. It has an elongated region. This eliminates the step difference at the ends of the source electrode and drain electrode. Because it can be made gradual, the oxide semiconductor layer 144 and the gate insulating layer 146 This improves the coverage and suppresses the occurrence of connection failures.

[0104] Furthermore, in the transistors 160, 170, 180, and 190 shown in this embodiment, In the source electrode or the drain electrode, by making the vicinity of the region in contact with the channel formation region a high-resistance region, the electric field between the source electrode and the drain electrode can be relaxed, and the short-channel effect associated with the reduction in transistor size can be suppressed. Thus, in one aspect of the disclosed invention, problems associated with miniaturization can be solved, and as a result, the transistor size can be made sufficiently small. By making the transistor size sufficiently small, the area occupied by the semiconductor device using the transistor becomes small, so the number of semiconductor devices per substrate increases. As a result, the manufacturing cost of the semiconductor device or the like is suppressed. Also, since the semiconductor device is miniaturized, a semiconductor device with enhanced functions can be realized with the same size. Further, effects such as high-speed operation and low power consumption due to the reduction of the channel length can also be obtained. That is, by achieving the miniaturization of the transistor using the oxide semiconductor according to one aspect of the disclosed invention, various effects associated with this can be obtained. As described above, in one aspect of the disclosed invention, problems associated with miniaturization can be solved, and as a result, the transistor size can be made sufficiently small. By making the transistor size sufficiently small, the area occupied by the semiconductor device using the transistor becomes small, so the number of semiconductor devices per substrate increases. As a result, the manufacturing cost of the semiconductor device or the like is suppressed. Also, since the semiconductor device is miniaturized, a semiconductor device with enhanced functions can be realized with the same size. Further, effects such as high-speed operation and low power consumption due to the reduction of the channel length can also be obtained. That is, by achieving the miniaturization of the transistor using the oxide semiconductor according to one aspect of the disclosed invention, various effects associated with this can be obtained.

[0105] As described above, in one aspect of the disclosed invention, problems associated with miniaturization can be solved, and as a result, the transistor size can be made sufficiently small. By making the transistor size sufficiently small, the area occupied by the semiconductor device using the transistor becomes small, so the number of semiconductor devices per substrate increases. As a result, the manufacturing cost of the semiconductor device or the like is suppressed. Also, since the semiconductor device is miniaturized, a semiconductor device with enhanced functions can be realized with the same size. Further, effects such as high-speed operation and low power consumption due to the reduction of the channel length can also be obtained. That is, by achieving the miniaturization of the transistor using the oxide semiconductor according to one aspect of the disclosed invention, various effects associated with this can be obtained. As described above, in one aspect of the disclosed invention, problems associated with miniaturization can be solved, and as a result, the transistor size can be made sufficiently small. By making the transistor size sufficiently small, the area occupied by the semiconductor device using the transistor becomes small, so the number of semiconductor devices per substrate increases. As a result, the manufacturing cost of the semiconductor device or the like is suppressed. Also, since the semiconductor device is miniaturized, a semiconductor device with enhanced functions can be realized with the same size. Further, effects such as high-speed operation and low power consumption due to the reduction of the channel length can also be obtained. That is, by achieving the miniaturization of the transistor using the oxide semiconductor according to one aspect of the disclosed invention, various effects associated with this can be obtained. As described above, in one aspect of the disclosed invention, problems associated with miniaturization can be solved, and as a result, the transistor size can be made sufficiently small. By making the transistor size sufficiently small, the area occupied by the semiconductor device using the transistor becomes small, so the number of semiconductor devices per substrate increases. As a result, the manufacturing cost of the semiconductor device or the like is suppressed. Also, since the semiconductor device is miniaturized, a semiconductor device with enhanced functions can be realized with the same size. Further, effects such as high-speed operation and low power consumption due to the reduction of the channel length can also be obtained. That is, by achieving the miniaturization of the transistor using the oxide semiconductor according to one aspect of the disclosed invention, various effects associated with this can be obtained. As described above, in one aspect of the disclosed invention, problems associated with miniaturization can be solved, and as a result, the transistor size can be made sufficiently small. By making the transistor size sufficiently small, the area occupied by the semiconductor device using the transistor becomes small, so the number of semiconductor devices per substrate increases. As a result, the manufacturing cost of the semiconductor device or the like is suppressed. Also, since the semiconductor device is miniaturized, a semiconductor device with enhanced functions can be realized with the same size. Further, effects such as high-speed operation and low power consumption due to the reduction of the channel length can also be obtained. That is, by achieving the miniaturization of the transistor using the oxide semiconductor according to one aspect of the disclosed invention, various effects associated with this can be obtained. As described above, in one aspect of the disclosed invention, problems associated with miniaturization can be solved, and as a result, the transistor size can be made sufficiently small. By making the transistor size sufficiently small, the area occupied by the semiconductor device using the transistor becomes small, so the number of semiconductor devices per substrate increases. As a result, the manufacturing cost of the semiconductor device or the like is suppressed. Also, since the semiconductor device is miniaturized, a semiconductor device with enhanced functions can be realized with the same size. Further, effects such as high-speed operation and low power consumption due to the reduction of the channel length can also be obtained. That is, by achieving the miniaturization of the transistor using the oxide semiconductor according to one aspect of the disclosed invention, various effects associated with this can be obtained. As described above, in one aspect of the disclosed invention, problems associated with miniaturization can be solved, and as a result, the transistor size can be made sufficiently small. By making the transistor size sufficiently small, the area occupied by the semiconductor device using the transistor becomes small, so the number of semiconductor devices per substrate increases. As a result, the manufacturing cost of the semiconductor device or the like is suppressed. Also, since the semiconductor device is miniaturized, a semiconductor device with enhanced functions can be realized with the same size. Further, effects such as high-speed operation and low power consumption due to the reduction of the channel length can also be obtained. That is, by achieving the miniaturization of the transistor using the oxide semiconductor according to one aspect of the disclosed invention, various effects associated with this can be obtained. As described above, in one aspect of the disclosed invention, problems associated with miniaturization can be solved, and as a result, the transistor size can be made sufficiently small. By making the transistor size sufficiently small, the area occupied by the semiconductor device using the transistor becomes small, so the number of semiconductor devices per substrate increases. As a result, the manufacturing cost of the semiconductor device or the like is suppressed. Also, since the semiconductor device is miniaturized, a semiconductor device with enhanced functions can be realized with the same size. Further, effects such as high-speed operation and low power consumption due to the reduction of the channel length can also be obtained. That is, by achieving the miniaturization of the transistor using the oxide semiconductor according to one aspect of the disclosed invention, various effects associated with this can be obtained.​​​​​​​​​​​​​​​​​​​​​​​​​, the stacking order corresponds to the transistor 180 shown in FIG. 1(C). The difference between the transistor 280 and the transistor 180 is that a sidewall insulating layer 252a is provided on a region extending in the channel length direction from the end of the first conductive layer 242a of the second conductive layer 245a, and the second a sidewall insulating layer 252b is provided on a region extending in the channel length direction from the end of the first conductive layer 242b of the conductive layer 245b. is that a sidewall insulating layer 252b is provided on a region extending in the channel length direction from the end of the first conductive layer 242b of the second conductive layer 245b. is that a sidewall insulating layer 252b is provided on a region extending in the channel length direction from the end of the first conductive layer 242b of the second conductive layer 245b.

[0109] The transistor 280 shown in FIG. 4 includes a source electrode in which a second conductive layer 245a and a first conductive layer 242a are sequentially stacked on a substrate 200, a drain electrode in which a second conductive layer 245b and a first conductive layer 2 42b are sequentially stacked, an insulating layer 243a provided on the source electrode, an insulating layer 243b provided on the drain electrode, an oxide semiconductor layer 244 provided on the insulating layer 243a and the insulating layer 243b, a gate insulating layer 246 provided on the oxide semiconductor layer 244, and a gate electrode 248 provided on the gate insulating layer 246. has.

[0110] In the transistor 280 shown in FIG. 4, the second conductive layer 245a has a region extending in the channel length direction from the end of the first conductive layer 242 a, and the second conductive layer 245a is in contact with at least the channel formation region of the oxide semiconductor layer 244. Also, the second conductive layer 2 45b has a region extending in the channel length direction from the end of the first conductive layer 242b, and the second conductive layer 245b is in contact with at least the channel formation region of the oxide semiconductor layer 244. is in contact with at least the channel formation region of the oxide semiconductor layer 244. is in contact with at least the channel formation region of the oxide semiconductor layer 244.

[0111] More specifically, the second conductive layer 245a has a channel length longer than the end of the first conductive layer 242a. It has a region that extends toward the drain electrode in the direction (the direction in which the carrier flows). Furthermore, the second conductive layer 245b is sourced from the edge of the first conductive layer 242b in the channel length direction. It has a region that extends toward the electrode.

[0112] Furthermore, the transistor 280 shown in Figure 4 has a second conductive layer 245a, and the first conductive layer A sidewall insulating layer 252 is placed on a region extending in the channel length direction from the edge of layer 242a. a is present, and in the second conductive layer 245b, the channel length extends from the end of the first conductive layer 242b A sidewall insulating layer 252b is provided on the region that extends in the direction. The insulating layer 252a is at least the channel formation region of the oxide semiconductor layer 244, the second conductive It is provided in contact with layer 245a, the first conductive layer 242a, and the insulating layer 243a. In the sidewall insulating layer 252a, the region in contact with the oxide semiconductor layer 244 is small. Both also have a curved shape in part. The sidewall insulating layer 252b is made of oxide semiconductor layer 2 44 at least channel-forming regions, second conductive layer 245b, first conductive layer 242b, and It is provided in contact with the insulating layer 243b. Also, the sidewall insulating layer 252b Furthermore, at least a portion of the region in contact with the oxide semiconductor layer 244 has a curved shape.

[0113] <Example of the manufacturing process for transistor 280> Next, an example of the manufacturing process for the transistor 280 is shown in Figures 5(A) to (F). I will explain.

[0114] First, a second conductive film 245 is formed on the substrate 200. Next, on the second conductive film 245 , a first conductive film 242 is formed, and an insulating film 243 is formed on the first conductive film 242 (Figure (Refer to 5(A).)

[0115] Here, the substrate 200 can be made of the same material as the substrate 100 shown in Embodiment 1. Also, the second conductive film 245 can be formed using the same material and film formation method as the second conductive film 145 shown in Embodiment 1. Further, the first conductive film 242 can be formed using the same material and film formation method as the first conductive film shown in Embodiment 1. For the details above, the description of Embodiment 1 can be referred to. However, materials with an etching selectivity ratio ensured are used for the first conductive film 242 and the second conductive film 245. In this embodiment, a titanium nitride film is formed as the second conductive film 245, and a tungsten film or a molybdenum film is formed as the first conductive film 242.

[0116]

[0117] Next, a mask is formed on the insulating film 243, and the insulating film 243 is etched using the mask to form insulating layers 243a and 243b. For the etching of the insulating film 243, wet etching or dry etching can be used, or a combination of wet etching and dry etching may be used. The etching conditions (etching gas, etching solution, etching time, temperature, etc.) are appropriately set according to the material so that the insulating film can be etched into a desired shape. However, for finely processing the channel length (L) of the transistor, dry etching is preferably used. As the etching gas used for dry etching, for example, sulfur hexafluoride (SF6), nitrogen trifluoride (NF3) ​​​​​​​​​​​​​), fluorine-containing gases such as trifluoromethane (CHF3), or carbon tetrafluoride (C A mixed gas of F4 and hydrogen can be used, as can noble gases (helium (He), argon ( Ar (Ar), xenon (Xe), carbon monoxide, or carbon dioxide may be added.

[0118] Next, the first conductive film 242 is etched using the mask used for etching the insulating film 243. By chipping, the first conductive layers 242a and 242b are formed (see Figure 5(B)). Furthermore, when etching the first conductive film 242, etching with the second conductive film 245 is performed. An etching material is used that ensures a selectivity ratio for the first conductive film 242. Before proceeding, remove the mask and use insulating layer 243a and insulating layer 243b as a mask. The conductive film 242 of 1 may be etched.

[0119] In this embodiment, an etching gas for etching the first conductive film 242 and A mixed gas of carbon tetrafluoride (CF4), chlorine (Cl2), and oxygen (O2), carbon tetrafluoride A mixed gas of element (CF4) and oxygen (O2), sulfur hexafluoride (SF6), chlorine (Cl2), and acid A gas mixture with element (O2), or a gas mixture of sulfur hexafluoride (SF6) and oxygen (O2). This shall be used.

[0120] By providing insulating layers 243a and 243b, the source electrode and drain that are formed later can be safely controlled. This makes it easier to control the contact area (contact region, etc.) between the electrode and the oxide semiconductor layer. This facilitates the control of the resistance of the source and drain electrodes, effectively suppressing short-channel effects. This can be done. In addition, by providing insulating layers 243a and 243b, later To reduce the parasitic capacitance between the formed gate electrode and the source and drain electrodes. This is possible.

[0121] Next, insulating layers 243a, 243b and the exposed second conductive film 245 are covered with insulating material. A film 252 is formed (see Figure 5(C)). The insulating film 252 is formed by CVD or sputtering. It can be formed using [materials]. In addition, the insulating film 252 can be silicon oxide, silicon nitride, It is preferable to form it to contain silicon oxide nitride, aluminum oxide, etc. The insulating film 252 may be a single-layer structure or a multilayer structure.

[0122] Next, the exposed region of the second conductive film 245 (the first conductive layer 242a and the first conductive layer 242 Sidewall insulating layers 252a and 252b are formed on the region between b (Figure 5(D)). (See reference). The sidewall insulating layers 252a and 252b have a highly anisotropic ester in the insulating film 252. By performing a ching process, it can be formed in a self-aligned manner. Here, highly anisotropic e Dry etching is preferred for etching, for example, as the etching gas, Fluorine-containing gases such as fluoromethane (CHF3) can be used, and helium (H e) Noble gases such as argon (Ar) may be added. Furthermore, dry etching is performed. Therefore, the reactive ion etching (RIE) method, which involves applying a high-frequency voltage to the substrate, is used. preferable.

[0123] Next, the second conductive film 245 is selected using the sidewall insulating layers 252a and 252b as a mask. Selective etching is performed to form the second conductive layers 245a and 245b (see Figure 5(E)). This etching process results in the lamination of the second conductive layer 245a and the first conductive layer 242a. A source electrode and a drain electrode formed by laminating a second conductive layer 245b and a first conductive layer 242b. An electrode is formed. Note that etching of the second conductive film 245 is performed on the sidewall insulating layer 2 Except for using 52a and 252b as masks, the same method as in Embodiment 1 is used in Figure 2(C). This can be done using a method similar to the one shown.

[0124] The channel length (L) of transistor 280 is the length between the lower end of the second conductive layer 245a and the second conductive layer The channel length (L) is determined by the distance from the bottom edge of layer 245b. 80 It varies depending on the application, but for example, 10 nm to 1000 nm, preferably 20 nm It can be reduced to 400 nm.

[0125] In the transistor fabrication process shown in this embodiment, the sidewall insulating layer 252a Alternatively, the second conductive film 245 is etched using 252b. In the conductive layer 245a, a region extending in the channel length direction from the edge of the first conductive layer 242a. The length in the channel direction (L S ) and the bottom surface of the sidewall insulating layer 252a The lengths in the longitudinal direction of the flannel are approximately the same. Similarly, in the second conductive layer 245b, the first conductive The length (L) of the region extending in the channel length direction from the end of the electrode layer 242b D ) The length of the channel in the channel direction at the bottom surface of the sidewall insulating layer 252b is approximately the same. The sidewall insulating layers 252a and 252b are formed by etching the insulating film 252. Because it is formed in a self-consistent manner, the above (L S ) or (L D ) is the thickness of the insulating film 252 Therefore, it is determined. In other words, by controlling the film thickness of the insulating film 252, the transistor 280 The channel length (L) of transistor 280 can be finely adjusted. The flannel length (L) can also be adjusted to be finer than the minimum processing dimension of the exposure device for mask formation. It is possible. For this reason, the desired channel length (L) of transistor 280 and the first conductive layer 2 The thickness of the insulating film 252 is determined according to the resolution of the exposure equipment used for processing 42a and 242b. Just set it.

[0126] Next, the insulating layers 243a, 243b and the sidewall insulating layers 252a, 252b are covered, and Furthermore, an oxide semiconductor layer 24 is placed in contact with the second conductive layer 245a and the second conductive layer 245b. Form 4 and form a gate insulating layer 246 on the oxide semiconductor layer 244. Then, the gate On the insulating layer 246, the region that will become the channel formation region of the transistor 280 overlaps with the region that will become the channel formation region of the transistor 280. A gate electrode 248 is formed in the region (see Figure 5(F)).

[0127] The oxide semiconductor layer 244 is made of the same material and method as the oxide semiconductor layer 144 shown in Embodiment 1. It can be formed by the method. In addition, the oxide semiconductor layer 244 can be subjected to heat treatment (1 It is desirable to perform the heat treatment described below. For details, please refer to the description in Embodiment 1. It is possible.

[0128] The gate insulating layer 246 is made of the same material and is prepared using the same method as the gate insulating layer 146 shown in Embodiment 1. It can be formed more effectively. Also, after the formation of the gate insulating layer 246, an inert gas atmosphere It is preferable to perform the heat treatment (second heat treatment) under a low temperature or oxygen atmosphere. For details, see below. The description of Embodiment 1 can be given due consideration.

[0129] The gate electrode 248 has a conductive film formed on the gate insulating layer 246, and then the conductive film is selected It can be formed by etching. The gate electrode 248 is in the form of an implemented shape. It can be formed using the same materials and methods as the gate electrode 148 shown in state 1.

[0130] Furthermore, the source electrode of transistor 280 is in the second conductive layer 245a, the first conductive At the edge of the region that extends in the channel length direction beyond the edge of layer 242a, oxide semiconductor layer 244 It is in contact with the first conductive layer 2 in the second conductive layer 245b. At the edge of the region that extends in the channel length direction beyond the edge of 42b, it is in contact with the oxide semiconductor layer 244. In this way, the second conductive layer has a smaller film thickness than the first conductive layers 242a and 242b. The oxide semiconductor layer 244 is in contact with the edges of layers 245a and 245b, thus forming the source electrode. Furthermore, the contact area between the drain electrode and the oxide semiconductor layer 244 can be reduced, The contact resistance at the contact interface can be increased. Therefore, transistor 2 Even if the channel length (L) of 80 is shortened, the electric field between the source electrode and the drain electrode is relaxed. Short-channel effects can be suppressed. In addition, the second conductive layer is made higher than the first conductive layer. Using resistant materials in the fabrication process allows for a more effective increase in contact resistance. , preferable. Furthermore, the technical concept of the disclosed invention is to use high resistance in the source electrode and drain electrode. Since the purpose is to form a region, the source electrode and drain electrode are strictly in the second conductive layer 2 It is necessary for 45a and the second conductive layer 245b to be in contact with the oxide semiconductor layer 244 only at their edges. There isn't one.

[0131] As described above, a transistor 280 using the oxide semiconductor layer 244 can be fabricated. .

[0132] The channel length (L) of the transistor 280 shown in this embodiment is determined by the sidewall insulating layer 2 The thickness of the insulating film 252 used to form 52a and 252b can be precisely controlled. Therefore, by appropriately setting the film thickness of the insulating film 252, the transistor 280 By reducing the channel length (L), it is possible to easily miniaturize semiconductor devices.

[0133] In this embodiment, the transistor 280 has a second conductive layer 245a, and the first conductive layer In the region extending in the channel length direction from the edge of layer 242a, and in the second conductive layer 245b Furthermore, in the region extending in the channel length direction from the edge of the first conductive layer 242b, sidewall A main insulating layer 252a and a sidewall insulating layer 252b are provided, respectively. This improves the coverage of the oxide semiconductor layer 244 and the gate insulating layer 246, thereby reducing the occurrence of connection failures. It can be suppressed.

[0134] Furthermore, the transistor 280 shown in this embodiment has a second conductive layer 245a with a first conductive layer A region is provided extending in the channel length direction from the edge of layer 242a, and a second conductive layer 245 A region is provided in b that extends in the channel length direction from the edge of the first conductive layer 242b, and the oxide semiconductor The region near the channel-forming region of the conductor layer 244 is designated as a high-resistance region. This makes it possible to Relaxing the electric field between the source and drain electrodes reduces short-channel effects such as threshold voltage reduction. The effect can be suppressed.

[0135] Thus, in one aspect of the disclosed invention, the problems associated with miniaturization can be resolved. As a result, it becomes possible to significantly reduce the size of the transistor. By making the size of the transistors sufficiently small, the area occupied by semiconductor devices using transistors is reduced. As a result, the number of semiconductor devices per substrate increases. The manufacturing cost per unit will be reduced. Also, because semiconductor devices will be miniaturized, they will be able to maintain the same size. This makes it possible to realize semiconductor devices with even greater functionality. In addition, channel length reduction This can also result in benefits such as faster operation and lower power consumption. By miniaturizing a transistor using an oxide semiconductor according to one aspect of the invention, It is possible to obtain various associated effects.

[0136] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0137] (Embodiment 3) In this embodiment, an example of an application of a semiconductor device according to one aspect of the disclosed invention is shown in Figure 6. Let's explain this in reference. Here, we will explain an example of a memory device. Note that in the circuit diagram... In addition, the sign OS is added to indicate that it is a transistor using an oxide semiconductor. There are cases where this is the case.

[0138] In the semiconductor device shown in Figure 6(A-1), the first line and the transient The source electrode of the ST300 is electrically connected to the second wiring (2nd Line) and The drain electrode of the transistor 300 is electrically connected. Also, the third wiring (3 The rd Line) and either the source electrode or the drain electrode of transistor 310 are connected. It is electrically connected to the fourth line and the gate electrode of transistor 310. They are electrically connected. And the gate electrode of transistor 300 and the transistor The source electrode or the other of the drain electrode of the sta 310 is connected to one of the electrodes of the capacitive element 320. They are electrically connected, and the fifth line and the other electrode of the capacitive element 320 are electrically connected. They are connected by energy.

[0139] Here, the transistor 310 uses the oxide semiconductor of Embodiment 1 and Embodiment 2. Transistors are applied. Transistors using oxide semiconductors have extremely low off-currents. It has the characteristic of being small. Therefore, by turning off transistor 310 This makes it possible to maintain the potential of the gate electrode of transistor 300 for an extremely long period of time. And, by having a capacitive element 320, the gate electrode of the transistor 300 This makes it easier to retain the charge applied to the device, and also makes it easier to read out the retained information.

[0140] Note that the transistor 300 is not particularly limited. From this perspective, for example, transistors using single-crystal silicon, switching It is preferable to use high-speed transistors.

[0141] Furthermore, as shown in Figure 6(B), it is also possible to omit the capacitive element 320. .

[0142] In the semiconductor device shown in Figure 6(A-1), the potential of the gate electrode of transistor 300 can be maintained. By utilizing its unique characteristics, it is possible to write, store, and read information in the following ways: ru.

[0143] First, we will explain how to write and retain information. First, the potential of the fourth wire is... The potential is set to the point where transistor 310 is ON, thereby turning on transistor 310. As a result, the potential of the third wiring is such that the gate electrode of transistor 300 and the capacitive element 320 A predetermined charge is given to the gate electrode of transistor 300. (Write). Here, we have two charges that give different potentials (hereinafter referred to as charges that give a low potential). Charge Q L Charge Q, which gives a high potential H One of the following will be given: Furthermore, applying charges that provide three or more different potentials can improve memory capacity. You may do so. After that, set the potential of the fourth wire to the potential at which transistor 310 is in the off state. By turning off transistor 310, the gate electrode of transistor 300 The charge applied to it is retained (held).

[0144] Because the off-current of transistor 310 is extremely small, the gate electrode of transistor 300 The electric charge is retained for a long period of time.

[0145] Next, we will explain how to read the information. When a predetermined potential (constant potential) is applied to the first wiring... In this state, when the appropriate potential (readout potential) is applied to the fifth wiring, the gate of transistor 300 Depending on the amount of charge held in the electrode, the second wiring takes on a different potential. Generally, If transistor 300 is an n-channel type, then Q is the gate electrode of transistor 300. H Given Apparent threshold V in this case th_H Q is connected to the gate electrode of transistor 300. L but Apparent threshold V when giventh_L This is because it will be lower. Here, The threshold voltage is the fifth voltage required to turn transistor 300 into the "on state". This refers to the potential of the wiring. Therefore, the potential of the fifth wiring is V th_H and V th_L By setting the potential V0 to the intermediate potential, the charge applied to the gate electrode of transistor 300 It is possible to determine Q. For example, in writing, H If given, the fifth wiring The potential is V0 (>V th_H ) In that case, transistor 300 will be in the "on state". Q L If given, the potential of the fifth wire is V0( <V th_L Even if that happens, The transistor 300 remains in the "off state". Therefore, we can observe the potential of the second wiring. Then, the stored information can be read.

[0146] Furthermore, when memory cells are arranged in an array, only the information of the desired memory cell is used. It is necessary to be able to read the information. In this way, the information of a predetermined memory cell is read, and To prevent reading information from external memory cells, transistor 3 is used between each memory cell. If the 00s are connected in parallel, the first of the memory cells that are not to be read out For wiring 5, regardless of the gate electrode state, transistor 300 is in the "off state". A potential such that, that is, V th_H A smaller potential should be applied. Also, each memory cell If transistors 300 are connected in series between them, the target of reading is For the fifth wiring of the memory cell, regardless of the state of the gate electrode, transistor 3 The potential at which 00 is in the "on state," that is, V th_LA higher potential in the fifth wiring Give it to them.

[0147] Next, we will explain how to rewrite information. Rewriting information involves writing and saving the above information. This is done in the same way as before. In other words, the potential of the fourth wire is set when transistor 310 is in the ON state. The potential is set to this value, and transistor 310 is turned on. This sets the potential of the third wiring ( A potential related to new information is applied to the gate electrode of transistor 300 and the capacitive element 320. Then, the potential of the fourth wire is set to the potential at which transistor 310 is in the off state. By turning off transistor 310, the gate electrode of transistor 300 is This results in a state where an electric charge related to new information is assigned to the device.

[0148] Thus, the semiconductor device relating to the disclosed invention directly generates information through subsequent writing. It is possible to rewrite the information. Therefore, it is necessary in flash memory and other applications. It eliminates the need to extract charge from the floating gate using high voltage, and the erase operation This can suppress the decrease in operating speed caused by this. In other words, high-speed operation of semiconductor devices is possible. It will be revealed.

[0149] Note that the source or drain electrode of transistor 310 is connected to the source electrode of transistor 300. By being electrically connected to the electrode, it is used as a non-volatile memory element. It performs the same function as the floating gate of a ting-gate transistor. In the diagram, the source electrode or drain electrode of transistor 310 and the gate of transistor 300. The part where the electrode is electrically connected is sometimes called the floating gate section (FG). When the transistor 310 is off, the floating gate section FG is embedded in the insulator. It can be seen that charge is held in the floating gate portion FG. Oxide semiconductor The off-current of transistor 310 using is due to the transistor formed by silicon semiconductors, etc. Because it is less than 1 / 100,000th of the original, the floating due to leakage in transistor 310 The dissipation of charge accumulated in the gate portion FG can be ignored. In other words, oxide semiconductors The transistor 310, which uses a body, allows for the retention of information even without a power supply. It is possible to create a sex memory device.

[0150] For example, the off-current of transistor 310 at room temperature is 10 zA (1 zA (zeptampere)). is 1 x 10 -21 A) When the capacitance value of the capacitive element 320 is approximately 10 fF at least 10 4 Data can be retained for more than a second. Needless to say, this will vary depending on the DISTA characteristics and capacitance values.

[0151] Furthermore, in this case, the gate issue that has been pointed out in conventional floating-gate transistors The problem of degradation of the tunnel insulating film (tunnel insulating film) does not exist. In other words, the conventional problem is The problem of degradation of the gate insulating film when injecting electrons into the floating gate was solved. It can be erased. This means that, in principle, there is no limit to the number of write cycles. Furthermore, in conventional floating-gate transistors, writing and erasing The high voltage required in that process is no longer necessary.

[0152] The semiconductor device shown in Figure 6(A-1) consists of elements such as transistors that make up the semiconductor device. It is possible to consider this as including resistance and capacitance, as shown in Figure 6(A-2). In Figure 6(A-2), transistor 300 and capacitive element 320 are resistors, respectively. And it is assumed that it is composed including capacity. R1 and C1 are capacity, respectively. The resistance and capacitance values ​​of element 320 are shown, where the resistance value R1 is the insulating layer that constitutes the capacitance element 320. This corresponds to the resistance value of the transistor 300. Also, R2 and C2 are the resistance values ​​of transistor 300, respectively. These are the capacitance and capacitance values, and the resistance value R2 is the gate insulating layer when transistor 300 is ON. This corresponds to the resistance value, and the capacitance value C2 is the so-called gate capacitance (between the gate electrode and the source electrode). This is the capacitance formed between the drain electrode and the gate electrode and the channel formation region. This corresponds to the capacity value of the volume that is formed.

[0153] The resistance between the source and drain electrodes when transistor 310 is in the off state (actual) If ROS (also called effective resistance) is defined as the gate leakage of transistor 310, then the gate leakage of transistor 310 is sufficiently small. In the given conditions, R1 and R2 are R1 ≥ ROS (R1 is greater than or equal to ROS), R2 ≥ ROS (R If the condition (2 is ROS or higher) is met, then the charge retention period (which can also be called the information retention period) is determined. This will be primarily determined by the off-current of transistor 310.

[0154] Conversely, if the above conditions are not met, the off-current of transistor 310 will be sufficiently small. However, it becomes difficult to ensure a sufficient retention period. Other than the off-current of transistor 310. The leakage current (for example, the leakage current that occurs between the source electrode and the gate electrode) is large. Therefore, the semiconductor device disclosed in this embodiment has the above-mentioned relationship It is desirable that the conditions be met.

[0155] On the other hand, it is desirable that C1 and C2 satisfy the relationship C1 ≥ C2 (C1 is greater than or equal to C2). By increasing C1, the potential of the floating gate section FG is controlled by the fifth wiring. When performing such operations (for example, during reading), the potential fluctuation of the fifth wiring can be kept low. That is the reason.

[0156] By satisfying the above-mentioned relationship, it is possible to realize a more suitable semiconductor device. R1 and R2 are insulated by the gate insulating layer of transistor 300 and the insulating layer of capacitive element 320. It is controlled. The same applies to C1 and C2. Therefore, the material and thickness of the gate insulating layer are controlled. It is desirable to set these appropriately so that the above relationship is satisfied.

[0157] In the semiconductor device shown in this embodiment, the floating gate portion FG is a flash It functions similarly to the floating gate of a floating-gate transistor in memory, etc. However, the floating gate portion FG of this embodiment is a flash memory, etc. It has characteristics that are fundamentally different from control gates. In flash memory, control gates Because the voltage applied to the cell is high, the potential of that cell affects the floating gate of the adjacent cell. To prevent this from extending to the tide, it becomes necessary to maintain a certain amount of spacing between cells. This is one of the factors that hinders the high integration of semiconductor devices. And this factor is high-voltage This stems from the fundamental principle of flash memory, which involves generating tunnel current by applying a boundary. It is.

[0158] Furthermore, due to the above principle of flash memory, the insulating film deteriorates, limiting the number of write cycles. Kai (10 4 ~10 5 Another problem arises (approximately a few times).

[0159] The semiconductor device according to the disclosed invention is a transistor switching device using an oxide semiconductor. Therefore, it operates without using the principle of charge injection by tunnel current as described above. That is, Unlike flash memory, it does not require a high electric field for charge injection. Because it is not necessary to consider the effect of the high electric field from the control gate on the tangent cell, Integration becomes easier.

[0160] Furthermore, because it does not use charge injection via tunnel current, there is a cause for memory cell degradation. No. In other words, it has higher durability and reliability compared to flash memory.

[0161] Furthermore, the fact that a high electric field is not required and large peripheral circuits (such as boost converters) are not needed is also a plus. This is an advantage over Shumemori.

[0162] Furthermore, the relative permittivity εr1 of the insulating layer constituting the capacitive element 320 and the transistor 300 If the relative permittivity εr2 of the insulating layer constituting the gate capacitance is to be different, then the capacitive element 32 The area S1 of the insulating layer that constitutes 0, and the insulating layer that constitutes the gate capacitance in transistor 300. The area of ​​the margin layer S2 is such that 2·S2 ≥ S1 (where 2·S2 is greater than or equal to S1) (preferably S2 ≥ S1). It is easy to achieve C1 ≥ C2 (where C1 is greater than or equal to C2) while satisfying S2 being greater than or equal to S1. Therefore, it is easy to make S1 small while making C1 equal to or greater than C2. For example, in the insulating layer constituting the capacitive element 320, a material such as hafnium oxide is used. A film made of a high-k material, or a film made of a high-k material such as hafnium oxide and oxidation A laminated structure with a film made of a monosemiconductor is adopted, and εr1 is set to 10 or more, preferably 15 or more. In transistor 300, silicon oxide is used in the insulating layer that constitutes the gate capacitance. Using this, we can set εr² = 3 to 4.

[0163] By using such a configuration in combination, the semiconductor device according to the disclosed invention can be made even more advanced. Integration is possible.

[0164] Note that the above explanation refers to an n-type transistor (n-channel transistor) that uses electrons as the majority carrier. This concerns the case where a st(s) is used, but instead of an n-type transistor, a large number of holes are used. It goes without saying that a p-type transistor can be used as the carrier.

[0165] As described above, a semiconductor device according to one aspect of the disclosed invention has a source electrode and a dotted electrode in the off state. A writing transistor with low leakage current (off-current) between rain electrodes, said writing Readout transistors and capacitive elements using semiconductor materials different from transistors. It has volatile memory cells.

[0166] The off-current of the writing transistor is 100 Hz at the operating temperature (e.g., 25°C). 1 x 10 -19 A) Preferably 10 zA (1 × 10 -20 A) The following are even more preferable Ku is, 1zA(1×10 -21 A) The following applies to ordinary silicon semiconductors: Although it is difficult to obtain a low off-current, it can be obtained by processing oxide semiconductors under appropriate conditions. This can be achieved in transistors. For this reason, as a writing transistor, It is preferable to use a transistor that includes a solid semiconductor.

[0167] Furthermore, transistors using oxide semiconductors have a small subthreshold swing value (S value). Therefore, it is possible to achieve a sufficiently high switching speed even with relatively low mobility. Therefore, by using the transistor as a writing transistor, floating The rising edge of the write pulse applied to the gate section FG can be made extremely steep. Furthermore, because the off-current is small, the amount of charge held in the floating gate section FG is small. It is possible to eliminate it. In other words, a transistor using an oxide semiconductor is used for writing. By using it as a transistor, information can be rewritten at high speed.

[0168] There are no restrictions on the off-current for the readout transistor, but the readout speed... To increase performance, it is desirable to use high-speed transistors. For example, readout It is preferable to use transistors with a switching speed of 1 nanosecond or less as the transistors used. It's nice.

[0169] Information is written to the memory cell by turning on the writing transistor. , one of the source or drain electrodes of the writing transistor and the electrode of the capacitive element One side is electrically connected to the gate electrode of the readout transistor. By supplying potential to the FG in the lute section, and then turning off the writing transistor, This is done by holding a predetermined amount of charge in the floating gate section FG. Because the off-current of the transistor used for charging is extremely small, it is supplied to the floating gate section FG. The charged charge is retained for a long time. If the off-current is, for example, substantially zero, conventionally The refresh operation required for the DRAM will become unnecessary, or the refresh operation will be eliminated. This makes it possible to reduce the frequency of this to an extremely low level (for example, once a month or once a year), and semiconductor The power consumption of the device can be significantly reduced.

[0170] Furthermore, it is possible to directly rewrite information by rewriting it to the memory cell. It is capable of this. Therefore, the erase operation required in flash memory and the like is unnecessary. This can suppress the decrease in operating speed caused by the erase operation. In other words, it can suppress the high speed of semiconductor devices. The operation is realized. In addition, writing and erasing can be done with conventional floating-gate transistors. Because it does not require the high voltage needed in the previous process, it further reduces the power consumption of semiconductor devices. This is possible. The voltage applied to the memory cell according to this embodiment (each terminal of the memory cell) The maximum value of the difference between the maximum and minimum potentials applied simultaneously is in two stages (1 bit). When writing information to a single memory cell, the voltage should be 5V or less, preferably 3V or less. be.

[0171] The memory cell arranged in the semiconductor device according to the disclosed invention includes a writing transistor and It is sufficient to include at least a readout transistor and a capacitive element, and the capacitive element Even with a small area, it can still function. Therefore, the area per memory cell can be, for example, Compared to SRAM, which requires six transistors per memory cell, it is sufficiently small. This makes it possible to arrange memory cells at high density in a semiconductor device. .

[0172] Furthermore, in conventional floating-gate transistors, the gate insulating film (T) is used during writing. As charges move through the tunnel insulating film, the gate insulating film (tunnel insulating film) deteriorates. It was unavoidable. However, in a memory cell according to one aspect of the present invention, writing Since information is written by the switching operation of the transistor, the gate insulating film There is no degradation problem. This is because, in principle, there is no limit to the number of write cycles, and the rewrite endurance is This means extremely high. For example, a memory cell according to one aspect of the present invention is 1 ×10 9 Even after more than 1 billion write cycles, no degradation in current-voltage characteristics is observed. stomach.

[0173] Furthermore, an oxide semiconductor transistor is used as the writing transistor for the memory cell. When using this, oxide semiconductors generally have a large energy gap (for example, In-Ga -In the case of Zn-O systems, the thermal excitation carriers are extremely few (3.0~3.5eV), for example For example, no degradation is observed in the current-voltage characteristics of the memory cell even in high-temperature environments of 150°C.

[0174] As a result of diligent research, the inventors have found that a transistor using an oxide semiconductor can withstand high temperatures of 150°C. Even so, it does not cause degradation of characteristics, and the off-current at 150°C is extremely low at 100 Hz or less. It was found to have the excellent characteristic of being small. In this embodiment, such excellent characteristics By applying a transistor with properties as a writing transistor for memory cells, the conventional approach is achieved. This invention provides a semiconductor device with the following characteristics.

[0175] According to one aspect of the disclosed invention, defects are suppressed in a transistor using an oxide semiconductor. Miniaturization can be achieved while doing so or while maintaining good characteristics. By using such transistors, the above-mentioned excellent memory devices can be highly integrated. It is possible.

[0176] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0177] (Embodiment 4) In this embodiment, an application example of a semiconductor device according to one aspect of the disclosed invention is shown in Figure 7 and This will be explained using Figure 8.

[0178] Figures 7(A) and 7(B) show the semiconductor device shown in Figure 6(A-1) (hereinafter referred to as memory cell 40 This is a circuit diagram of a semiconductor device formed using multiple (also written as 0) elements. Figure 7(A) shows the Me This is a circuit diagram of a so-called NAND-type semiconductor device in which Morisel 400 transistors are connected in series. Figure 7(B) shows a so-called NOR-type semiconductor device in which memory cells 400 are connected in parallel. This is a circuit diagram.

[0179] The semiconductor device shown in Figure 7(A) has a source line SL, a bit line BL, a first signal line S1, and m lines. The second signal line S2, m word lines WL, and multiple memory cells 400(1,1)~400( m, 1) are arranged in a vertical row of m units × horizontal column of 1 unit. Note that in Figure 7(A), The configuration includes one line SL and one bit line BL, but is not limited to this. By having n source lines SL and n bit lines BL, a memo with m rows x n columns can be created. A configuration including a recell array may also be used.

[0180] In each memory cell 400, the gate electrode of transistor 300 and transistor 310 One of the source or drain electrodes of the capacitor and one of the electrodes of the capacitive element 320 are electrically connected. They are connected. Also, the first signal line S1 and the source electrode or drain of transistor 310 are connected. The other electrode is electrically connected to the second signal line S2 and the gate of transistor 310. The electrodes are electrically connected. And the word line WL and the electrode of the capacitive element 320 The other is electrically connected.

[0181] Furthermore, the source electrode of the transistor 300 in the memory cell 400 is adjacent to the memory cell The memory cell 400 is electrically connected to the drain electrode of transistor 300. The drain electrode of transistor 300 is connected to the transistor of the adjacent memory cell 400. It is electrically connected to 300 source electrodes. However, it is connected in series to multiple memory cells. Of these, the drain of the transistor 300 located at one end of the memory cell 400 The electrodes are electrically connected to the bit lines. Also, multiple memory cells connected in series... The source electrode of the transistor 300 of the memory cell 400 located at the other end is It is electrically connected to the source wire.

[0182] The semiconductor device shown in Figure 7(A) performs line-by-line writing and reading operations. The writing operation is performed as follows: Transistor 3 is connected to the second signal line S2 of the row to be written. Apply a potential that turns on transistor 10, turning on transistor 310 of the row to be written. This connects the gate electrode of transistor 300 in the specified row to the first signal line S1. A potential is applied, and a predetermined charge is given to the gate electrode of the transistor 300. In this way, data can be written to the memory cell of the specified row.

[0183] Furthermore, the reading operation is performed as follows: First, the word lines WL other than the line to be read. Regardless of the charge applied to the gate electrode of transistor 300, transistor 300 By applying a potential that turns it on, the transistors 300 other than those in the row being read are turned on. Then, the gate of transistor 300 is connected to the word line WL of the row to be read. The on or off state of transistor 300 is selected based on the charge present in the electrodes. A certain potential (readout potential) is applied. Then, a constant potential is applied to the source line SL, and the bit line The readout circuit (not shown) connected to BL is set to the operating state. Here, the source line Multiple transistors 300 between SL and bit line BL are turned ON except for the row being read. Because of this state, the conductance between the source line SL and the bit line BL is read out. This is determined by the state (on or off) of transistor 300 in the "U" row. The charge on the gate electrode of transistor 300 in the row that is performing the discharge is due to the charge on the transistor Since the conductances are different, the potential of the bit line BL will take on different values ​​accordingly. This is achieved by reading the potential of the bit line using a reading circuit. Information can be extracted from the code.

[0184] The semiconductor device shown in Figure 7(B) has n source lines SL, bit lines BL, and a first signal line S1 And, m second signal lines S2 and word line WL, and multiple memory cells 400(1,1)~4 Memory cells are arranged in a matrix of m rows and n columns, with each cell containing 00(m, n) arranged vertically. It has an array 410. The gate electrode of each transistor 300 and the socket of transistor 310 One of the electrode or drain electrode and one of the electrodes of the capacitive element 320 are electrically connected. It is also electrically connected to the source wire SL and the source electrode of transistor 300. Therefore, the bit line BL and the drain electrode of transistor 300 are electrically connected. Also, the first signal line S1 and the other of the source electrode or drain electrode of transistor 310 The second signal line S2 and the gate electrode of transistor 310 are electrically connected. They are connected precisely. And the word line WL and the other electrode of the capacitive element 320 are electrically connected. It is connected.

[0185] The semiconductor device shown in Figure 7(B) performs line-by-line writing and reading operations. The loading operation is performed in the same manner as the semiconductor device shown in Figure 7(A) above. Readout operation This is done as follows: First, on the word lines WL other than the row to be read, transistor 3 Regardless of the charge applied to the gate electrode of 00, transistor 300 will be in the off state. A potential is applied, and the transistors 300 other than those in the row being read are turned off. The charge on the gate electrode of transistor 300 is applied to the word line WL of the row being read. Therefore, the potential (readout) such that the ON or OFF state of transistor 300 is selected A constant potential is applied to the source line SL, which is connected to the bit line BL. The readout circuit (not shown) is set to the operating state. Here, source line SL - bit line BL The conductance between them is determined by the state of transistor 300 in the row being read (on state or Determined by the (off state). In other words, the gauge of transistor 300 of the row being read. The potential of the bit line BL will take on different values ​​depending on the charge of the bit electrode. By reading the potential of the line using a reading circuit, information can be read from the memory cell of the specified row. It is possible to break out of it.

[0186] In the above, the amount of information to be held in each memory cell 400 was set to 1 bit, however The configuration of the memory device shown in the embodiment is not limited thereto. The gate electrode of transistor 300 It is also possible to increase the amount of information held by each memory cell 400 by providing a potential of 3 or more. For example, if we want to apply four different potentials to the gate electrode of transistor 300, Each memory cell can hold 2 bits of information.

[0187] Next, Figure 8 shows an example of a readout circuit that can be used in semiconductor devices such as those shown in Figure 7. We will explain using this method.

[0188] Figure 8(A) shows a schematic of the readout circuit. This readout circuit consists of a transistor and a sensor. It has a amp circuit.

[0189] During read operation, terminal A is connected to the bit line to which the memory cell to be read is connected. Furthermore, a bias potential Vbias is applied to the gate electrode of the transistor, and the voltage at terminal A The position is controlled.

[0190] The memory cell 400 exhibits different resistance values ​​depending on the data stored. Specifically, If the selected memory cell 400's transistor 300 is in the ON state, it will be in a low-resistance state. If transistor 300 of the selected memory cell 400 is in the off state, it will be in a high-resistance state. .

[0191] When the memory cell is in the high-resistance state, the potential of terminal A becomes higher than the reference potential Vref, and the sense amplifier outputs a potential corresponding to the potential of terminal A. On the other hand, when the memory cell is in the low-resistance state , the potential of terminal A becomes lower than the reference potential Vref, and the sense amplifier circuit outputs a potential corresponding to the potential of terminal A.

[0192] In this way, by using the read circuit, data can be read from the memory cell . Note that the read circuit of this embodiment is an example. Other circuits may be used. Also, the read circuit may have a precharge circuit. Instead of the reference potential Vref, a reference bit line may be connected.

[0193] Fig. 8(B) shows a differential sense amplifier, which is an example of a sense amplifier circuit. The differential sense amplifier has input terminals Vin(+) and Vin(-) and an output terminal Vout, and amplifies the difference between Vin(+ ) and Vin(-). If Vin(+) > Vin(-), Vout is generally a High output, and if Vin(+) < Vin(-), Vout is generally a Low output . When the differential sense amplifier is used in the read circuit, one of Vin(+) and Vin(-) is connected to input terminal A, and the reference potential Vref is applied to the other of Vin(+) and Vin(-).

[0194] Fig. 8(C) shows a latch-type sense amplifier, which is an example of a sense amplifier circuit. The latch-type sense amplifier has input / output terminals V1 and V2 and input terminals for control signals Sp and Sn. First, set signal Sp to High and signal Sn to Low to cut off the power supply potential (Vdd). Then, apply the potentials for comparison to V1 and V2. After that, set signal Sp to Low and signal Sn to When a power supply potential (Vdd) is supplied as High, potentials V1in and V2in for comparison are provided. If V1in > V2in, the output of V1 is High and the output of V2 is Low. If V1in < V2in, the output of V1 is Low and the output of V2 is High. By utilizing such a relationship, the difference between V1in and V2in can be amplified. When using this latch - type sense amplifier in a read - out circuit, one of V1 and V2 is connected to terminal A and an output terminal via a switch, and a reference potential Vref is applied to the other of V1 and V2.

[0195] The configurations, methods, etc. shown in this embodiment can be appropriately combined with those shown in other embodiments and used.

[0196] (Embodiment 5) In this embodiment, the case of applying the semiconductor device described in Embodiments 1 to 4 to an electronic device will be described using FIG. 9. In this embodiment, the case of applying the semiconductor device described in Embodiments 1 to 4 to electronic devices such as a computer, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable information terminal (including a portable game machine, an audio reproduction device, etc.), a digital camera, a digital video camera, an electronic paper, a television device (also referred to as a TV or a television receiver), etc. will be described. FIG. 9(A) is a notebook - type personal computer, which is composed of a housing 601, a housing 602, a display unit 603, a keyboard 604, etc. The miniaturized semiconductor device shown in the previous embodiments is provided inside the housing 601 and the housing 602. Therefore, it is small - sized.

[0197] ​​Notebook-type personal computers with features such as high-speed operation and low power consumption are now available. It will be revealed.

[0198] Figure 9(B) shows a personal digital assistant (PDA), and the main unit 611 has a display unit 613 and an external An interface 615 and operation buttons 614, etc., are provided. It is equipped with a stylus 612 for operation. The main body 611 contains the same as shown in the previous embodiment. Miniaturized semiconductor devices are provided. Therefore, they are small, operate at high speed, and consume low power. A portable information terminal with these features will be realized.

[0199] Figure 9(C) shows an e-reader 620 with electronic paper implemented, consisting of a casing 621 and a casing 623. It consists of two enclosures. Enclosure 621 and enclosure 623 each contain a display unit 625 A display unit 627 is also provided. Housing 621 and housing 623 are connected by a shaft 637. The shaft portion 637 is configured to allow opening and closing operations. The housing 621 is It is equipped with a power supply 631, operation keys 633, speaker 635, etc. Enclosure 621, enclosure At least one of 623 is provided with the miniaturized semiconductor device shown in the previous embodiment. Therefore, ebooks with features such as small size, high-speed operation, and low power consumption have been realized. It can be done.

[0200] Figure 9(D) shows a mobile phone, which is composed of two casings, casing 640 and casing 641. Furthermore, casings 640 and 641 slide apart and unfold as shown in Figure 9(D). It can be transformed from one state to an overlapping state, and miniaturization suitable for portability is possible. The enclosure 641 includes a display panel 642, a speaker 643, a microphone 644, and control keys. 645, pointing device 646, camera lens 647, external connection terminal 648 It is equipped with, etc. Also, the housing 640 has a solar cell 649 for charging the mobile phone, and It is equipped with a memory slot 650, etc. The antenna is built into the housing 641. There is a miniaturized version of housing 640 and housing 641 as shown in the previous embodiment. A semiconductor device is installed. Therefore, it has features such as being small, operating at high speed, and having low power consumption. A mobile phone equipped with these features will be realized.

[0201] Figure 9(E) shows a digital camera, consisting of the main body 661, display unit 667, eyepiece 663, and operation unit. It consists of a switch 664, a display unit 665, a battery 666, etc. Main unit 6 The miniaturized semiconductor device shown in the previous embodiment is provided inside 61. This will result in digital cameras with features such as small size, high-speed operation, and low power consumption.

[0202] Figure 9(F) shows a television device 670, consisting of a housing 671, a display unit 673, and a stand 6 It consists of 75, etc. The television device 670 is operated by the switches provided in the housing 671. This can be done via the switch or by the remote control unit 680. (Enclosure 671 and remote control unit) The 680 is equipped with the miniaturized semiconductor device shown in the previous embodiment. This will enable the realization of television equipment with features such as high-speed operation and low power consumption.

[0203] As described above, the electronic device shown in this embodiment is equipped with the semiconductor device according to the previous embodiment. It is included. Therefore, electronic devices with features such as small size, high-speed operation, and low power consumption. This will be realized. [Examples]

[0204] In this embodiment, the characteristics of a semiconductor device according to one aspect of the invention were verified using a computer. The results will be explained using Figures 10 to 13. Specifically, with different channel lengths L The characteristics of the transistors were compared. Note that device simulation was used for the calculations. We used the software Atlas (manufactured by Silvaco Data Systems).

[0205] The structure of the transistor used in the calculations is shown in Figure 10. Figure 10(A) relates to one aspect of the present invention. This is a structure in which a part of the source electrode or drain electrode is extended, as shown in Figure 10(B). This is a structure for comparison (a structure in which part of the source electrode or drain electrode is not extended). That is the case.

[0206] The details of the transistors used in the calculations will be explained. The transistors shown in Figure 10(A) are , a first conductive layer 742a (material: titanium, thickness: 100 nm) and a second conductive layer 745a A source electrode in which layers (material: titanium nitride, thickness: arbitrary) are stacked in order, and a first conductive layer 742 b (material: titanium, thickness: 100 nm) and the second conductive layer 745b (material: titanium nitride, A drain electrode with a thickness of any size (arbitrary) stacked in order, and an insulating layer 743 provided on the source electrode. a (material: silicon oxide, thickness: 100 nm) and an insulating layer 7 provided on the drain electrode 43b (Material: Silicon oxide, Thickness: 100 nm), and insulating layer 743a and insulating layer 743 b is provided with an oxide semiconductor layer 744 (material: In-Ga-Zn-O based oxide semiconductor). (Thickness: 10 nm) and a gate insulating layer 746 (Material) provided on the oxide semiconductor layer 744 (Hafnium oxide, thickness: 10 nm) and gate electrode provided on gate insulating layer 746 It has 748 (material: tungsten).

[0207] In the transistor shown in Figure 10(A), the second conductive layer 745a is the first conductive layer 74 It has a region that extends in the channel length direction from the end of 2a (i.e., the second conductive layer 74 The end of 5a is closer to the channel formation region than the end of the first conductive layer 742a), the second conductive layer The edge of layer 745a is in contact with the channel formation region of oxide semiconductor layer 744. Similarly, The second conductive layer 745b extends in the channel length direction from the edge of the first conductive layer 742b. It has a region (that is, the end of the second conductive layer 745b is the end of the first conductive layer 742b) The edge of the second conductive layer 745b (closer to the channel formation region) is the oxide semiconductor layer 744 It is in contact with the channel-forming region.

[0208] The transistor shown in Figure 10(B) has a source electrode made of conductive layer 752a (material: titanium nitride). The drain electrode (material: titanium nitride, thickness: 100 nm) consists of a conductive layer 752b. (100 nm) and an oxide semiconductor layer 744 provided on the source electrode and drain electrode. (Material: In-Ga-Zn-O based oxide semiconductor, thickness: 10 nm) and oxide semiconductor layer A gate insulating layer 746 (material: hafnium oxide, thickness: 10 nm) is provided on 744 and , having a gate electrode 748 (material: tungsten) provided on the gate insulating layer 746 .

[0209] The difference between Figure 10(A) and Figure 10(B) is that in the second conductive layer 745a described above, the first conductive In the region extending in the channel length direction from the end of the conductive layer 742a, and in the second conductive layer 745b The presence or absence of a region extending in the channel length direction from the edge of the first conductive layer 742b, source The presence or absence of an insulating layer on the electrode and on the drain electrode.

[0210] In Figure 10(A), the edge of the first conductive layer 742a in the second conductive layer 745a The region that extends in the direction of the channel length (the region consisting of the second conductive layer) is the same as the other region (the first conductive layer) The electrode thickness is small compared to the region consisting of a layer and a second conductive layer stacked together. In other words, the flow of charge The area of ​​the cross-section perpendicular to it is small. Since resistance is inversely proportional to the cross-sectional area, the second conductivity In layer 745a, the region extending in the channel length direction from the edge of the first conductive layer 742a is Therefore, it can be said that it has higher resistance compared to other regions. The second conductive layer 745b is also The same can be said. In this embodiment, the second conductive layer 745a, the first A region extending in the channel length direction from the edge of the conductive layer 742a, and the second conductive layer 745b In this region, the area extending in the channel length direction from the edge of the first conductive layer 742b is defined as the high-resistance region. (HRR: High-Resistance Region) is abbreviated as such.

[0211] Furthermore, in Figure 10(A), the upper part of the source electrode is covered with an insulating layer 743a, The upper part of the in electrode is covered with an insulating layer 743b, so the source electrode and drain electrode are separated from the acid The contact area of ​​the ionized semiconductor layer 744 is very small (here, the edge of the second conductive layer) (Only the portion in contact). In other words, the source electrode and drain electrode are in contact with the channel formation region. In the vicinity of that region, the resistance is higher than in other regions.

[0212] In the above configuration (Figures 10(A) and 10(B)), by changing the channel length L, We investigated the behavior of the threshold voltage Vth of the transistor. The channel length L and The six conditions are 20nm, 30nm, 50nm, 100nm, 200nm, and 400nm. We adopted it.

[0213] Furthermore, the behavior of the threshold voltage Vth was investigated by changing the thickness of the second conductive layer. Four different layer thicknesses were used: 3nm, 10nm, 50nm, and 100nm.

[0214] The voltage Vds between the source electrode and the drain electrode was set to 1V. Also, the channel in the high-resistance region The length in the longitudinal direction was set to 0.3 μm.

[0215] The parameters used in the calculation are as follows: 1. In-Ga-Zn-O based oxide semiconductors (materials for oxide semiconductor layers) Band gap Eg: 3.15 eV, electron affinity χ: 4.3 eV, relative permittivity: 15, electron Mobility: 10cm 2 / Vs, Effective density of states in the conduction band: 5 × 10 18 cm -3 2. Titanium nitride (material for source and drain electrodes) Work function φ M :3.9eV, resistivity ρ:2.2×10 -4 Ω·cm 3. Hafnium oxide (material for gate insulation layer) Relative permittivity: 15 4. Tungsten (gate electrode material) Work function φ M :4.9eV

[0216] The calculation results are shown in Figures 11 to 13. In Figures 11 to 13, the horizontal axis represents the channel length L( The vertical axis shows the threshold voltage shift amount ΔVth(V), with the vertical axis representing the value in nm. ΔVth was calculated based on the threshold voltage at a channel length L=400nm.

[0217] Figures 11(A), 11(B), 12(A), and 12(B) show the structure shown in Figure 10(A). The calculation results are as follows: Figure 11(A) shows the second conductive layer thickness as 100 nm, and Figure 11(B) shows the result as Figure 12(A) shows a second conductive layer with a thickness of 50 nm, and a second conductive layer with a thickness of 10 nm. Figure 12(B) shows the case where the thickness of the second conductive layer is 3 nm. Figure 3 shows the calculation results for the structure shown in Figure 10(B).

[0218] A comparison of Figures 11(A), 11(B), 12(A), and 12(B) reveals the second conductive material. It can be seen that the thinner the layer, the more the negative shift of the threshold voltage is suppressed. Also, Figure 1 A comparison of 1(A) and Figure 13 shows that when an insulating layer is provided to cover the source electrode and drain electrode... This shows that the negative shift of Vth is suppressed. In all of these cases, the source electrode and By reducing the contact area between the drain electrode and the oxide semiconductor layer and increasing the resistance, short-circuit This suggests that the channel effect can be suppressed.

[0219] Furthermore, the above results indicate that in the vicinity of the region in contact with the semiconductor layer, the source electrode and drain electrode If the resistance of the poles is high, it means that the effect of suppressing short-channel effects can be obtained. It's also possible.

[0220] Therefore, the region near the channel formation area of ​​the source electrode and drain electrode is made to have high resistance. (Specifically, for example, reducing the cross-sectional area of ​​part of the source electrode and drain electrode, An insulating layer is formed to cover the upper part of the source electrode and drain electrode, and the contact area with the oxide semiconductor layer is formed. It is understood that reducing the threshold voltage suppresses the negative shift. This is due to the relaxation of the electric field strength between the source electrode and the drain electrode. Thus, according to one aspect of the disclosed invention, short-channel effects such as threshold voltage reduction can be reduced. It was shown that the fruit can be suppressed. [Explanation of symbols]

[0221] 100 circuit boards 142a First conductive layer 142b First conductive layer 143 Insulating film 143a Insulating layer 143b Insulating layer 144 Oxide semiconductor layer 145 Conductive film 145a Second conductive layer 145b Second conductive layer 146 Gate Insulation Layer 148 Guard gate 160 transistors 170 transistors 180 transistors 190 transistors 200 circuit boards 242 Conductive film 242a First conductive layer 242b First conductive layer 243 Insulating film 243a Insulating layer 243b Insulating layer 244 oxide semiconductor layer 245 Conductive film 245a Second conductive layer 245b Second conductive layer 246 Gate Insulation Layer 248 Grid gate 252 Insulating film 252a Sidewall insulation layer 252b Sidewall insulation layer 280 transistors 300 transistors 310 transistors 320 Capacitive elements 400 memory cells 410 memory cell array 601 cabinet 602 cabinet 603 Display section 604 Keyboard 611 Main Unit 612 Stylus 613 Display section 614 Operation Buttons 615 External Interface 620 eBooks 621 cabinet 623 cabinets 625 Display section 627 Display section 631 Power supply 633 Operation Keys 635 Speakers 637 Shaft 640 cabinets 641 cabinets 642 Display Panel 643 speakers 644 Microphone 645 Operation Keys 646 Pointing Devices 647 Camera Lenses 648 External connection terminals 649 solar cells 650 external memory slots 661 Main Unit 663 Eyepiece 664 Operation Switch 665 Display section 666 Battery 667 Display section 670 Television equipment 671 cabinets 673 Display section 675 Stand 680 Remote Control Unit 742a First conductive layer 742b First conductive layer 743a Insulating layer 743b Insulating layer 744 oxide semiconductor layer 745a Second conductive layer 745b Second conductive layer 746 Gate Insulation Layer 748 Guard gate 752a conductive layer 752b Conductive layer

Claims

1. A first transistor having an oxide semiconductor in the channel formation region, A second transistor having silicon in the channel formation region, A semiconductor device in which one of the source and drain of the first transistor is electrically connected to the gate of the second transistor, The first transistor comprises a gate electrode, an oxide semiconductor layer overlapping the gate electrode, a source electrode electrically connected to the oxide semiconductor layer, and a drain electrode electrically connected to the oxide semiconductor layer. The source electrode has a laminated structure including a first conductive layer having a region in contact with the oxide semiconductor layer and a second conductive layer not in contact with the oxide semiconductor layer. The drain electrode has a laminated structure including a third conductive layer having a region in contact with the oxide semiconductor layer, and a fourth conductive layer that does not contact the oxide semiconductor layer. The thickness of the first conductive layer is smaller than the thickness of the second conductive layer. The thickness of the third conductive layer is smaller than the thickness of the fourth conductive layer. In a cross-sectional view of the first transistor in the channel length direction, each of the first to fourth conductive layers has a tapered shape. In the cross-sectional view, the first conductive layer has a first portion that overlaps with the second conductive layer and a second portion that does not overlap with the second conductive layer. In the cross-sectional view, the first portion overlaps with the tapered portion of the second conductive layer. In the cross-sectional view, the second portion extends from the lower end of the second conductive layer in the direction of the channel length and is not in contact with the upper end of the second conductive layer. In the cross-sectional view, the upper and side surfaces of the second portion overlap with the gate electrode without the second conductive layer in between. In the cross-sectional view, the third conductive layer has a third portion that overlaps with the fourth conductive layer and a fourth portion that does not overlap with the fourth conductive layer. In the cross-sectional view, the third portion overlaps with the tapered portion of the fourth conductive layer. In the cross-sectional view, the fourth portion extends from the lower end of the fourth conductive layer in the direction of the channel length and is not in contact with the upper end of the fourth conductive layer. In the cross-sectional view, the upper and side surfaces of the fourth portion overlap with the gate electrode without the fourth conductive layer in between. In the cross-sectional view, the gate electrode overlaps with each of the tapered portions of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer, respectively, in the semiconductor device.

2. A first transistor having an oxide semiconductor in the channel formation region, A second transistor having silicon in the channel formation region, A semiconductor device in which one of the source and drain of the first transistor is electrically connected to the gate of the second transistor, The first transistor comprises a gate electrode, an oxide semiconductor layer overlapping the gate electrode, a source electrode electrically connected to the oxide semiconductor layer, and a drain electrode electrically connected to the oxide semiconductor layer. The source electrode has a laminated structure including a first conductive layer having a region in contact with the oxide semiconductor layer and a second conductive layer not in contact with the oxide semiconductor layer. The drain electrode has a laminated structure including a third conductive layer having a region in contact with the oxide semiconductor layer, and a fourth conductive layer that does not contact the oxide semiconductor layer. The thickness of the first conductive layer is smaller than the thickness of the second conductive layer. The thickness of the third conductive layer is smaller than the thickness of the fourth conductive layer. In a cross-sectional view of the first transistor in the channel length direction, each of the first to fourth conductive layers has a tapered shape. In the cross-sectional view, the first conductive layer has a first portion that overlaps with the second conductive layer and a second portion that does not overlap with the second conductive layer. In the cross-sectional view, the first portion overlaps with the tapered portion of the second conductive layer. In the cross-sectional view, the second portion extends from the lower end of the second conductive layer in the direction of the channel length and is not in contact with the upper end of the second conductive layer. In the cross-sectional view, the upper and side surfaces of the second portion overlap with the gate electrode without the second conductive layer in between. In the cross-sectional view, the third conductive layer has a third portion that overlaps with the fourth conductive layer and a fourth portion that does not overlap with the fourth conductive layer. In the cross-sectional view, the third portion overlaps with the tapered portion of the fourth conductive layer. In the cross-sectional view, the fourth portion extends from the lower end of the fourth conductive layer in the direction of the channel length and is not in contact with the upper end of the fourth conductive layer. In the cross-sectional view, the upper and side surfaces of the fourth portion overlap with the gate electrode without the fourth conductive layer in between. In the cross-sectional view, the gate electrode overlaps with each of the tapered portions of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer. The first conductive layer has a material with higher resistance than the second conductive layer. A semiconductor device wherein the third conductive layer is made of a material with higher resistance than the fourth conductive layer.

3. A first transistor having an oxide semiconductor in the channel formation region, A second transistor having silicon in the channel formation region, A semiconductor device in which one of the source and drain of the first transistor is electrically connected to the gate of the second transistor, The first transistor comprises a gate electrode, an oxide semiconductor layer overlapping the gate electrode, a source electrode electrically connected to the oxide semiconductor layer, and a drain electrode electrically connected to the oxide semiconductor layer. The source electrode has a laminated structure including a first conductive layer having a region in contact with the oxide semiconductor layer and a second conductive layer not in contact with the oxide semiconductor layer. The drain electrode has a laminated structure including a third conductive layer having a region in contact with the oxide semiconductor layer, and a fourth conductive layer that does not contact the oxide semiconductor layer. The thickness of the first conductive layer is smaller than the thickness of the second conductive layer. The thickness of the third conductive layer is smaller than the thickness of the fourth conductive layer. In a cross-sectional view of the first transistor in the channel length direction, each of the first to fourth conductive layers has a tapered shape. In the cross-sectional view, the first conductive layer has a first portion that overlaps with the second conductive layer and a second portion that does not overlap with the second conductive layer. In the cross-sectional view, the first portion overlaps with the tapered portion of the second conductive layer. In the cross-sectional view, the second portion extends from the lower end of the second conductive layer in the direction of the channel length and is not in contact with the upper end of the second conductive layer. In the cross-sectional view, the upper and side surfaces of the second portion overlap with the gate electrode without the second conductive layer in between. In the cross-sectional view, the third conductive layer has a third portion that overlaps with the fourth conductive layer and a fourth portion that does not overlap with the fourth conductive layer. In the cross-sectional view, the third portion overlaps with the tapered portion of the fourth conductive layer. In the cross-sectional view, the fourth portion extends from the lower end of the fourth conductive layer in the direction of the channel length and is not in contact with the upper end of the fourth conductive layer. In the cross-sectional view, the upper and side surfaces of the fourth portion overlap with the gate electrode without the fourth conductive layer in between. In the cross-sectional view, the gate electrode overlaps with each of the tapered portions of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer. The first conductive layer has a material with higher resistance than the second conductive layer. The third conductive layer has a material with higher resistance than the fourth conductive layer. A semiconductor device wherein each of the first conductive layer and the third conductive layer is made of tantalum, titanium, molybdenum, or tungsten.

4. In any one of claims 1 to 3, The oxide semiconductor layer comprises In, Ga, and Zn, and is a semiconductor device.

5. In any one of Claims 1 to 4, In the cross-sectional view, the gate electrode has a tapered shape. The first tapered portion of the gate electrode does not overlap with the tapered portion of the first conductive layer and the tapered portion of the second conductive layer. A semiconductor device wherein the second tapered portion of the gate electrode does not overlap with the tapered portion of the third conductive layer and the tapered portion of the fourth conductive layer.

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