Semiconductor device and method for manufacturing a semiconductor device

Abstract

To attain improvement in reliability of a semiconductor device.SOLUTION: A semiconductor device 10 comprises: a radiation plate 41; an insulation resin layer 42 formed in the radiation plate 41; a metal plate 33 of which a bottom face 33B is contacted to a first region R1 which is a part of a surface of the insulation resin layer 42; a power semiconductor chip 12A bonded to a top face 33A of the metal plate 33; a first lead terminal 31 connected to the metal plate 33; a first mold resin 51 covering a part of the metal plate 33 and a part of the first lead terminal 31; and a second mold resin 52 formed from a resin material, of which the characteristics are different from the first mold resin 51, and covering a part of the metal plate 33, the power semiconductor chip 12 and a part of the first lead terminal 31. The first mold resin 51 is spread over an outer peripheral edge of the metal plate 33 and a line of an outer peripheral edge of the insulation resin layer 42 or the outside in a planar view, and a bottom face 51B thereof is in contact with a second region R2 different from the first region R1 in the surface of the insulation resin layer 42.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] Conventionally, improvements have been made to the heat dissipation characteristics and insulation characteristics of semiconductor devices applied to power conversion devices such as motor drive inverters and DC-DC converters. For example, Patent Document 1 below discloses a method for manufacturing a semiconductor device in which a chip is resin-molded. The method for manufacturing a semiconductor device described in Patent Document 1 includes the steps of: preparing a frame having a front surface and a back surface and a die pad; preparing an insulating resin sheet having a first surface and a second surface; preparing a resin sealing mold equipped with retaining pins; placing the resin sheet in the resin sealing mold such that the second surface of the resin sheet is in contact with the inner bottom surface of the resin sealing mold; placing a power chip on the surface of the die pad; arranging the frame on the first surface of the resin sheet such that the back surface of the die pad is in contact with the first surface of the resin sheet; pressing the die pad toward the resin sheet with retaining pins to fix the die pad; filling the resin sealing mold with sealing resin and curing it; and removing the semiconductor device from the resin sealing mold. In this way, by contacting and fixing a highly thermally conductive insulating resin sheet to the back surface of the frame on which the power chip is mounted, the resin sheet and the frame can be firmly fixed together, resulting in a semiconductor device with high heat dissipation characteristics and excellent insulating properties. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2005-123495 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] In the conventional technology described above, a frame having a die pad is placed on the first surface of a resin sheet, and heating and pressurizing are performed while the die pad and frame are pressed toward the resin sheet with retaining pins, thereby curing the sealing resin. At this time, the resin sheet is in a semi-cured state, and there is a possibility that the resin sheet may deform due to the pressure of the frame. Specifically, the portion of the resin sheet located directly below the outer edge of the frame may be pushed outward relative to the frame, potentially causing a bulge of resin on the side of the frame and the formation of voids in the portion of the resin sheet located directly below the outer edge of the frame. The outer edge of the frame is a point where the electric field is concentrated when the semiconductor device is operating, and if there is a defect in the nearby insulating resin layer, it may lead to dielectric breakdown of the insulating resin layer, potentially reducing the reliability of the semiconductor device. Considering these circumstances, one aspect of the present invention aims to improve the reliability of a semiconductor device. [Means for solving the problem]

[0005] To solve the above problems, the semiconductor device of the present disclosure comprises a heat sink, an insulating resin layer formed on the heat sink, a metal plate including a first surface and a second surface opposite to the first surface, the first surface contacting a first region which is a part of the surface of the insulating resin layer, a first semiconductor chip bonded to the second surface, a first lead terminal connected to the metal plate, a first molded resin covering a part of the metal plate and a part of the first lead terminal, and a second molded resin formed of a resin material with different properties from the first molded resin, covering a part of the metal plate, the first semiconductor chip, and a part of the first lead terminal, wherein the first molded resin includes a third surface located in the same plane as the first surface, extending in a plan view from the outer edge of the metal plate to or outside the line of the outer edge of the insulating resin layer, and the third surface contacts a second region on the surface of the insulating resin layer that is different from the first region.

[0006] Also, the method for manufacturing a semiconductor device according to the present disclosure is the method for manufacturing the semiconductor device, including a step of covering a part of the metal plate and a part of the lead terminal with a first mold resin, a step of forming the insulating resin layer by bringing the first surface of the metal plate into contact with the third surface of the first mold resin and curing the resin sheet, and a step of covering the metal plate, the first semiconductor chip, and a part of the lead terminal with a second mold resin.

Brief Description of the Drawings

[0007] [Figure 1] It is a circuit diagram including the semiconductor device 10 according to the embodiment and its peripheral configuration. [Figure 2A] It is a top view of the appearance of the semiconductor device 10. [Figure 2B] It is a side view of the appearance of the semiconductor device 10. [Figure 3] It is a cross-sectional view taken along the A-A line of the semiconductor device 10. [Figure 4A] It is a view in which a part of the second mold resin 52 is removed from the cross-sectional view of FIG. 3. [Figure 4B] It is a view in which the first lead terminal 31 disposed inside the first mold resin 51 of FIG. 4A is made transparent. [Figure 5] It is a cross-sectional view of the semiconductor device 10 along the Y direction. [Figure 6] It is a flowchart showing the method for manufacturing the semiconductor device 10. [Figure 7] It is a view showing the manufacturing process of the semiconductor device 10. [Figure 8] It is a view showing the manufacturing process of the semiconductor device 10. [Figure 9] It is a view showing the manufacturing process of the semiconductor device 10. [Figure 10] It is a view showing the manufacturing process of the semiconductor device 10. [Figure 11] It is a view showing the manufacturing process of the semiconductor device 10. [Figure 12] It is a view showing the manufacturing process of the semiconductor device 10. [Figure 13] It is a cross-sectional view showing a modified example of the semiconductor device 10. [Figure 14A] This is a cross-sectional view of the semiconductor device 10A in the X direction, according to a modified example. [Figure 14B] This is a cross-sectional view of the semiconductor device 10B according to a modified example, along the X direction. [Figure 15] This figure shows the configuration of semiconductor device 100 in the comparative example. [Modes for carrying out the invention]

[0008] Embodiments relating to this disclosure will be described below with reference to the drawings. Note that the dimensions and scale of parts in the drawings may differ from those of the actual parts as appropriate. Furthermore, the embodiments described below are preferred examples of this disclosure. For this reason, the following embodiments are subject to various technically preferred limitations. However, the scope of this disclosure is not limited to these forms unless otherwise stated in the following description to specifically limit this disclosure.

[0009] [First Embodiment] [A. Circuit configuration of semiconductor device 10] Figure 1 is a circuit diagram including a semiconductor device 10 and its peripheral configuration according to an embodiment. The semiconductor device 10 is a motor drive semiconductor device that drives a three-phase motor M. The semiconductor device 10 comprises a power semiconductor chip 12 and a control semiconductor chip 14 (HVIC14α, LVIC14β, BSD14γ). The power semiconductor chip 12 is an example of a first semiconductor chip, and the control semiconductor chip 14 is an example of a second semiconductor chip.

[0010] In this embodiment, the semiconductor device 10 comprises six power semiconductor chips 12α to 12ζ. The power semiconductor chips 12 are insulated gate bipolar transistors (IGBTs) having a high-voltage electrode (collector), a low-voltage electrode (emitter), and a control electrode (gate), and reverse conducting IGBTs (RC-IGBTs) having a rectifier element (diode) having an anode electrode and a cathode electrode. In each power semiconductor chip 12, the high-voltage electrode of the switching element is connected to the cathode electrode of the rectifier element, and the low-voltage electrode of the switching element is connected to the anode electrode of the rectifier element.

[0011] Of the six power semiconductor chips 12α to 12ζ, power semiconductor chips 12α to 12γ constitute the upper arm, and power semiconductor chips 12δ to 12ζ constitute the lower arm. Hereinafter, power semiconductor chips 12α to 12γ may be referred to as "upper arm semiconductor elements 12α to 12γ," and power semiconductor chips 12δ to 12ζ may be referred to as "lower arm semiconductor elements 12δ to 12ζ." The low-voltage electrodes of the upper arm semiconductor elements 12α to 12γ and the high-voltage electrodes of the lower arm semiconductor elements 12δ to 12ζ are connected by connecting wires, forming a series circuit. This series circuit has output terminals U, V, and W connected to the connecting line between the upper arm semiconductor elements 12α to 12γ and the lower arm semiconductor elements 12δ to 12ζ, a positive DC terminal P connected to the high-voltage electrodes of the upper arm semiconductor elements 12α to 12γ, and negative DC terminals N(U), N(V), and N(W) connected to the low-voltage electrodes of the lower arm semiconductor elements 12δ to 12ζ, thus forming a half-bridge circuit.

[0012] The semiconductor device 10 is equipped with three half-bridge circuits (U-phase, V-phase, and W-phase). The positive DC terminals P of each half-bridge circuit are connected in common inside the semiconductor device 10, and the DC power supply V is provided outside the semiconductor device 10. DC It is connected to the positive voltage electrode. The negative DC terminals N(U), N(V), and N(W) of each half-bridge circuit are commonly joined outside the semiconductor device 10, and a DC power supply V is connected via a current sensing resistor Rdet provided outside the semiconductor device 10.DC is connected to the negative voltage electrode. The semiconductor device 10 receives DC power from the DC power supply V through the positive DC terminal P and the negative DC terminals N(U), N(V), and N(W). DC The output terminals U, V, and W are connected to the phase input terminals U, V, and W of the three-phase motor M, and the semiconductor device 10 supplies the power necessary for driving the three-phase motor M through the output terminals U, V, and W.

[0013] The semiconductor device 10 includes a high-side control IC (HVIC: High Voltage Integrated Circuit) 14α that controls the driving states of the switching elements of the upper-arm semiconductor elements 12α to 12γ. The gate output terminals U OUT , V OUT , W OUT of the HVIC 14α are connected to the control electrodes (gate electrodes) of the switching elements of the upper-arm semiconductor elements 1 to 12γ. Also, the first reference potential terminals V S1U of the HVIC 14α, V S1V , V S1W are connected to the low-voltage electrodes (emitters) of the switching elements of the upper-arm semiconductor elements 12α to 12γ. The HVIC 14α turns on or off the switching elements of the upper-arm semiconductor elements 12α to 12γ by changing the voltage between the gate output terminals U OUT , V[[ID=ID=22]] OUT , W OUT and the first reference potential terminals V S1U , V S1V , V S1W .

[0014] Further, the gate power supply terminals V BU , V BV , V BW of the HVIC 14α are connected to one terminal of the power supply capacitors CB(U), CB(V), and CB(W) provided outside the semiconductor device 10. The second reference potential terminals V S2U , V S2V , V S2WThis is connected to the other terminal of the power supply capacitors CB(U), CB(V), and CB(W). HVIC14α uses the power supply capacitors CB(U), CB(V), and CB(W) as gate drive power supplies for the switching elements of the upper arm semiconductor elements 12α to 12γ.

[0015] Also, the signal input terminal U of the HVIC14α INH ,V INH ,W INH This is connected to the signal output terminal of the integrated computing unit (MPU: Micro Processing unit) 90 located outside the semiconductor device 10. The signal power terminal V of HVIC14α CCH The HVIC14α is connected to the positive terminal of the signal power supply Vcc located outside the semiconductor device 10, and the ground terminal (GND) of the HVIC14α is connected to the negative terminal of the signal power supply Vcc. As a result, the HVIC14α receives the PWM signal output from the signal output terminal of the MPU90 at the signal input terminal U INH ,V INH ,W INH Received at gate output terminal U OUT ,V OUT ,W OUT It transmits a signal.

[0016] The semiconductor device 10 further comprises bootstrap diodes (BSDs) 14γ. In this embodiment, the semiconductor device 10 comprises three BSDs 14γ. The anode side of the BSD 14γ is connected to the signal power terminal (V) of the HVIC 14α. CCH ) is connected. The cathode side of BSD14γ is connected to one terminal of the power supply capacitors CB(U), CB(V), and CB(W). As a result, BSD14γ is connected to the signal power supply V CC The power supply capacitors CB(U), CB(V), and CB(W) are charged using [this method].

[0017] The semiconductor device 10 includes a low-side control IC (LVIC: Low Voltage Integrated Circuit) 14β that controls the driving state of the switching elements of the lower arm semiconductor elements 12δ to 12ζ. The gate output terminal U of the LVIC 14β OUT ,VOUT ,W OUT This is connected to the control electrode (gate electrode) of the switching element of the lower arm semiconductor element 12δ~12ζ. The ground terminal GND of LVIC14β is connected to the negative DC terminals N(U), N(V), and N(W) via the current sensing resistor Rdet, and the gate output terminal U OUT ,V OUT ,W OUT By changing the voltage between the terminal and the ground terminal GND, the switching elements of the lower arm semiconductor elements 12δ~12ζ are turned on or off.

[0018] Also, the signal input terminal U of the LVIC14β INL ,V INL ,W INL This connects to the signal output terminal of the MPU90. It connects to the signal power terminal V of the LVIC14β. CCL This is connected to the positive terminal of the signal power supply Vcc. The ground terminal GND of the LVIC14β is also connected to the negative terminal of the signal power supply Vcc. As a result, the LVIC14β receives the PWM signal output from the signal output terminal of the MPU90 and connects it to the signal input terminal U of the LVIC14β. INL ,V INL ,W INL Received at gate output terminal U OUT ,V OUT ,W OUT It transmits a signal.

[0019] The semiconductor device 10 has a function to protect itself from damage in the event of an overcurrent by detecting the current flowing through each phase of the half-bridge circuit using a current-sensing resistor Rdet. The current level signal detected by the current-sensing resistor Rdet is transmitted to the LVIC 14β via the current-sensing terminal IS. The LVIC 14β performs an overcurrent determination based on a reference value of the current, and if an overcurrent occurs, it interrupts the current of the switching elements of the lower arm semiconductor elements 12δ to 12ζ. On the other hand, the protection of the switching elements of the upper arm semiconductor elements 12α to 12γ is performed by the MPU 90. The current level signal detected by the current-sensing resistor Rdet is also transmitted to the MPU 90. The MPU 90 performs an overcurrent determination based on a reference value, and if an overcurrent occurs, it interrupts the current of the switching elements of the upper arm semiconductor elements 12α to 12γ, thereby protecting the semiconductor device 10.

[0020] [B. Configuration of semiconductor device 10] Figure 2A is a top view of the semiconductor device 10, and Figure 2B is a side view of the semiconductor device 10. The semiconductor device 10 comprises a main body 20 and a plurality of lead terminals (first lead terminal 31 and second lead terminal 32). The plurality of lead terminals are exposed from the main body 20. The main body 20 has a top surface 20A, a bottom surface 20B, a pair of side surfaces 20C and a pair of side surfaces 20D. The top surface 20A and the bottom surface 20B are roughly rectangular in shape. The long side of the top surface 20A and the long side of the bottom surface 20B are the same length, but the short side of the top surface 20A and the short side of the bottom surface 20B are of different lengths, with the short side of the bottom surface 20B being shorter. Side surface 20C connects the long side of the top surface 20A and the long side of the bottom surface 20B. As described above, the short side of the upper surface 20A and the short side of the lower surface 20B are of different lengths, so the side surface 20C has a step. The side surface 20D connects the short side of the upper surface 20A and the short side of the lower surface 20B.

[0021] In the following, we assume that the space in which the semiconductor device 10 is located has XYZ coordinates. The longer sides of the upper surface 20A and the lower surface 20B extend along the X direction. The shorter sides of the upper surface 20A and the lower surface 20B extend along the Y direction. The upper surface 20A and the lower surface 20B are separated along the Z direction. That is, the Z direction is the height direction of the semiconductor device 10.

[0022] Of the surfaces of the main body 20, the top surface 20A, side surface 20C, and side surface 20D are entirely made of the second molded resin 52, which will be described later. The bottom surface 20B has a central part which is made of the bottom surface 41B of the heat sink 41 (see Figure 5), which will be described later, and the area around the central part is made of the second molded resin 52.

[0023] Multiple first lead terminals 31 and multiple second lead terminals 32 are exposed to the outside of the main body 20 from the side surface 20C. Each first lead terminal 31 has an outer lead portion 311 extending along the Y direction from the side surface 20C, and a tip portion 312 rising upward from the tip of the outer lead portion 311. Each second lead terminal 32 has an outer lead portion 321 extending along the Y direction from the side surface 20C, and a tip portion 322 rising upward from the tip of the outer lead portion 321.

[0024] Figure 3 is an AA cross-sectional view of the semiconductor device 10. Figure 4A is a view obtained by removing a part of the second molded resin 52 (the second molded resin 522 in the opening 510, which will be described later) from the cross-sectional view of Figure 3. Figure 4B is a view obtained by seeing through the first lead terminal 31 located inside the first molded resin 51 of Figure 4A. In Figure 4A, the wire 38 is shown, while in Figure 4B, the wire 38 is omitted for the sake of visibility. The names of each lead terminal (first lead terminal 31 and second lead terminal 32) shown in Figure 4A correspond to the names of the terminals shown in Figure 1. Figure 5 is a cross-sectional view of the semiconductor device 10 along the Y direction. Figure 5 schematically shows the arrangement of the components constituting the semiconductor device 10 along the Y direction. In Figures 3 to 5, the tip 312 of the first lead terminal 31 and the tip 322 of the second lead terminal 32 are omitted from the illustration.

[0025] As shown in Figure 5, the semiconductor device 10 comprises a heat sink 41, an insulating resin layer 42, a metal plate 33, a first lead terminal 31, a second lead terminal 32, wires 38, a power semiconductor chip 12, a control semiconductor chip 14, a first molded resin 51, and a second molded resin 52.

[0026] The heat sink 41 is a rectangular flat plate (metal plate) made of metal, and has an upper surface 41A, a lower surface 41B, and a side surface 41C. The lower surface 41B is the surface opposite to the upper surface 41A. The side surface 41C connects the upper surface 41A and the lower surface 41B. The side surface 41C of the heat sink 41 is an example of the outer circumferential surface of the heat sink 41. The heat sink 41 protects the insulating resin layer 42 and releases the heat generated by the driving of the power semiconductor chip 12 to the outside of the semiconductor device 10. As described above, the lower surface 41B of the heat sink 41 constitutes the lower surface 20B of the semiconductor device 10. In this embodiment, on the lower surface 20B of the semiconductor device 10, the lower surface 41B of the heat sink 41 and the second molded resin 52 are located in the same plane.

[0027] In this embodiment, "within the same plane" includes not only cases where the surfaces are located in exactly the same plane, but also cases where they are located in substantially the same plane. "Surface a and surface b are located in substantially the same plane" means, for example, that the step difference between surface a and surface b is within the range of manufacturing tolerance. Specifically, if there is a step difference between surface a and surface b due to a dimensional error within the range of ±10% (more preferably ±5%), then surface a and surface b are interpreted as "continuous without a step." A configuration in which surface a and surface b are continuous without a step has the advantage of suppressing damage caused by stress concentration or insufficient rigidity at the step portion. In other words, as long as the effect of suppressing damage as exemplified above is achieved, even if there is actually a step difference between surface a and surface b, they can be interpreted as "within the same plane."

[0028] The insulating resin layer 42 is made of insulating resin and insulates the metal plate 33, which is part of the internal circuit of the semiconductor device 10, from the heat sink 41, which is exposed to the outside of the semiconductor device 10. The insulating resin layer 42 has an upper surface 42A, a lower surface 42B, and a side surface 42C. The lower surface 42B is the surface opposite to the upper surface 42A. The side surface 42C connects the upper surface 42A and the lower surface 42B. The upper surface 42A of the insulating resin layer 42 is an example of the surface of the insulating resin layer 42. The side surface 42C of the insulating resin layer 42 is an example of the outer peripheral surface of the insulating resin layer 42. The lower surface 42B of the insulating resin layer 42 is formed on the upper surface 41A of the heat sink 41. In a plan view, the outer peripheral edges of the insulating resin layer 42 and the heat sink 41 overlap. That is, the side surface 42C of the insulating resin layer 42 and the side surface 41C of the heat sink 41 are located in the same plane. In this embodiment, "planar view" refers to viewing the semiconductor device 10, which is placed on the XY plane, from the Z direction. Furthermore, "planar shape" refers to the shape when viewed from a planar perspective.

[0029] The metal plate 33 is a plate made of metal and has an upper surface 33A, a lower surface 33B, and a side surface 33C. The lower surface 33B is the surface opposite to the upper surface 33A. The side surface 33C connects the upper surface 33A and the lower surface 33B. ru. The upper surface 33A of the metal plate 33 is an example of a second surface, and the lower surface 33B of the metal plate 33 is an example of a first surface. The side surface 33C of the metal plate 33 is an example of an outer peripheral surface of the metal plate 33. The lower surface 33B of the metal plate 33 is positioned on the upper surface 42A of the insulating resin layer 42. The lower surface 33B of the metal plate 33 is in contact with a portion of the upper surface 42A of the insulating resin layer 42.

[0030] The region of the upper surface 42A of the insulating resin layer 42 that is in contact with the lower surface 33B of the metal plate 33 is defined as the first region R1. The region of the upper surface 42A of the insulating resin layer 42 other than the first region R1 is defined as the second region R2. The surface along the upper surface 33A of the metal plate 33 is defined as the reference plane S. The reference plane S is an example of a plane that includes the upper surface 33A of the metal plate 33.

[0031] The first lead terminal 31 and the second lead terminal 32 supply power or signals from an external source to the power semiconductor chip 12 and the control semiconductor chip 14 inside the semiconductor device 10. The first lead terminal 31 is formed integrally with the metal plate 33 to which the power semiconductor chip 12 is bonded inside the semiconductor device 10. On the other hand, the second lead terminal 32 is provided separately from the metal plate 33.

[0032] The first lead terminal 31 includes the outer lead portion 311 and tip portion 312 (see Figure 2A, etc.) described above, as well as an inner lead portion 313 connected to the end of the outer lead portion 311 opposite to the tip portion 312. The outer lead portion 311 is an example of the first part, and the inner lead portion 313 is an example of the second part. A part of the outer lead portion 311 is exposed from the main body portion 20 (second molded resin 52) of the semiconductor device 10 and connects to the tip portion 312. The inner lead portion 313 connects the outer lead portion 311 to the metal plate 33. In other words, the first lead terminal 31 is connected to the metal plate 33.

[0033] The outer lead portion 311 is located approximately in the center of the main body portion 20 in the Z direction, and the metal plate 33 is located below the semiconductor device 10 in the Z direction. In other words, the outer lead portion 311 and the metal plate 33 are spaced apart in the Z direction. Furthermore, the position of the end of the outer lead portion 311 on the inner lead portion 313 side and the position of the end of the metal plate 33 on the inner lead portion 313 side are offset in the Y direction in a plan view. Therefore, the inner lead portion 313 extends in the Z direction while being inclined with respect to the XY plane.

[0034] The outer lead portion 311 has an upper surface 311A ​​and a lower surface 311B opposite to the upper surface 311A. The cutting line AA shown in Figure 2B follows the upper surface 311A ​​of the outer lead portion 311. The inner lead portion 313 has an upper surface 313A and a lower surface 313B opposite to the upper surface 313A.

[0035] As described above, the second lead terminal 32 comprises an outer lead portion 321 and a tip portion 322. A portion of the outer lead portion 321 is exposed from the main body portion 20 (second molded resin 52) of the semiconductor device 10 and connects to the tip portion 322. As shown in Figure 5, the outer lead portion 321 is located approximately in the center of the main body portion 20 in the Z direction and is provided at a distance from the metal plate 33 in the Z direction. The second lead terminal 32 is also formed from a thin metal plate of the same type as the metal plate 33. The outer lead portion 321 has an upper surface 321A and a lower surface 321B opposite to the upper surface 321A. The position of the upper surface 311A ​​of the outer lead portion 311 in the Z direction and the height of the upper surface 321A of the outer lead portion 321 are the same.

[0036] The power semiconductor chip 12 has an upper surface 12A, a lower surface 12B, and a side surface 12C. The lower surface 12B is located on the opposite side from the upper surface 12A. The side surface 12C connects the upper surface 12A and the lower surface 12B. The lower surface 12B of the power semiconductor chip 12 is bonded to the upper surface 33A of the metal plate 33 via a bonding agent 34 such as solder. The low-voltage electrode (emitter) and control electrode (gate) of the switching element and the anode electrode of the rectifier element are arranged on the upper surface 12A of the power semiconductor chip 12. The high-voltage electrode (collector) of the switching element and the cathode electrode of the rectifier element are arranged on the lower surface 12B. Power wires 38A and inter-element wires 38C are connected to the upper surface 12A of the power semiconductor chip 12.

[0037] The control semiconductor chip 14 has an upper surface 14A, a lower surface 14B, and a side surface 14C. The lower surface 14B is located on the opposite side from the upper surface 14A. The side surface 14C connects the upper surface 14A and the lower surface 14B. The lower surface 14B of the control semiconductor chip 14 is bonded to the upper surface 321A of the outer lead portion 321 via a bonding agent 35 such as a conductive or insulating adhesive. Control wires 38B and inter-element wires 38C are connected to the upper surface 14A of the control semiconductor chip 14.

[0038] Wire 38 connects the first lead terminal 31, the second lead terminal 32, the power semiconductor chip 12, and the control semiconductor chip 14. The wire connecting the first lead terminal 31 and the power semiconductor chip 12 is designated as the power wire 38A, the wire connecting the second lead terminal 32 and the control semiconductor chip 14 is designated as the control wire 38B, and the wire connecting the power semiconductor chip 12 and the control semiconductor chip 14 is designated as the inter-element wire 38C.

[0039] The first mold resin 51 has an upper surface 51A, a lower surface 51B, a side surface 51C, and a side surface 51D, as shown in Figures 4B and 5. The lower surface 51B is located on the opposite side from the upper surface 51A. Side surfaces 51C and 51D connect the upper surface 51A and the lower surface 51B, respectively. Side surface 51C is the surface located on the side of the first lead terminal 31, and side surface 51D is the surface located on the side of the second lead terminal 32. The upper surface 51A is an example of a fourth surface, the lower surface 51B is an example of a third surface, and side surfaces 51C and 51D are examples of a fifth surface.

[0040] The upper surface 51A of the first mold resin 51 is located in the same plane as the upper surface 311A ​​of the outer lead portion 311 of the first lead terminal 31 and the upper surface 321A of the outer lead portion 321 of the second lead terminal 32.

[0041] Furthermore, the lower surface 51B of the first molded resin 51 is located in the same plane as the lower surface 33B of the metal plate 33. Also, the outer edges of the first molded resin 51, i.e., the positions of the side surfaces 51C and 51D in a plan view, coincide with the positions of the outer edges of the heat sink 41 and the insulating resin layer 42 (the positions of the side surfaces 41C and 42C in a plan view). Note that the position of the outer edges of the first molded resin 51 may be outside the positions of the outer edges of the heat sink 41 and the insulating resin layer 42. Even in that case, it is preferable that the side surfaces 51C and 51D of the first molded resin 51 are covered with the second molded resin 52.

[0042] As shown in Figure 4B, an opening 510 is formed in the center of the first molded resin 51 in a plan view, extending from the upper surface 51A to the lower surface 51B. On the lower surface 51B side of the opening 510, at least the portion of the upper surface 33A of the metal plate 33 on which the power semiconductor chip 12 is placed is exposed. ru. Multiple metal plates 33 are exposed within the opening 510, and a power semiconductor chip 12 is placed on each metal plate 33. As a result of the formation of the opening 510, the planar shape of the first mold resin 51 is a rectangular frame.

[0043] The opening 510 is a space surrounded by the inner circumferential surface of the first molded resin 51. The inner circumferential surface of the first molded resin 51 includes wall surfaces 51F and 51G. Wall surfaces 51F and 51G are planes connecting the upper surface 51A and the lower surface 51B. Wall surface 51F is the surface located on the side of the first lead terminal 31, and wall surface 51G is the surface located on the side of the second lead terminal 32.

[0044] The wall surface 51F covers the upper surface 313A of the inner lead portion 313 and is inclined with respect to the XY plane at approximately the same angle as the inner lead portion 313. The wall surface 51G is inclined with respect to the XY plane at approximately the same angle as the wall surface 51F. The inclination direction of the wall surface 51F and the inclination direction of the wall surface 51G are opposite, and the cross-sectional area of ​​the opening 510 in the XY plane increases as you approach the upper surface 51A from the lower surface 51B.

[0045] The second molded resin 52 forms the main body 20 of the semiconductor device 10. The second molded resin 52 forms the upper surface 20A, lower surface 20B, and side surfaces 20C, 20D shown in Figures 2A, 2B, and 5.

[0046] The first mold resin 51 and the second mold resin 52 are formed from resin materials with different properties. Different properties include not only cases where the types of resin materials are different, but also cases where the materials are the same but the formulation (e.g., amount of filler) is different. In this embodiment, the thermal conductivity of the first mold resin 51 is higher than that of the second mold resin 52. Specifically, for example, a high thermal conductivity mold resin with a thermal conductivity of 2 [W / K·m] or more is used as the first mold resin 51, and a general mold resin with a thermal conductivity of less than 1 [W / K·m] is used as the second mold resin 52.

[0047] Furthermore, the thermal conductivity of the first mold resin 51 is higher than that of the second mold resin 52. 51 The thermal expansion coefficient of the first mold and the thermal expansion coefficient of the second mold resin 52 may be the same. In this embodiment, "the same" thermal expansion coefficient means that it is substantially the same, including within the range of manufacturing tolerances. Specifically, it is interpreted as being the same if it is within a range of ±10% (more preferably ±5%).

[0048] The first molding resin 51 and the second molding resin 52 may, for example, use a thermosetting resin such as epoxy resin as the main material, and add silica, alumina, boron nitride, etc. as fillers. For example, the first molding resin 51 and the second molding resin 52 may be the same epoxy resin but with different fillers. By using the same epoxy resin, the adhesion between the first molding resin 51 and the second molding resin 52 is improved, and damage to the semiconductor device 10 due to peeling or the like can be prevented. In this case, the proportion of filler contained in the first molding resin 51 may be greater than the proportion of filler contained in the second molding resin 52. By doing so, the thermal conductivity of the first molding resin 51 can be easily made higher than that of the second molding resin 52. Also, the proportion of boron nitride filler contained in the first molding resin 51 may be greater than the proportion of boron nitride filler contained in the second molding resin 52. The first mold resin 51 does not need to contain boron nitride filler, while the second mold resin 52 does not need to contain boron nitride filler. This makes it easy to make the thermal conductivity of the first mold resin 51 higher than that of the second mold resin 52, while the first mold resin 51 The thermal expansion coefficient of the first mold and the thermal expansion coefficient of the second mold resin 52 can be made the same.

[0049] [C. Method for manufacturing semiconductor device 10] Next, the manufacturing method of the semiconductor device 10 will be described with reference to Figures 6 to 12. Figure 6 is a flowchart showing the manufacturing method of the semiconductor device 10. First, as shown in Figure 7, a lead frame F is prepared in which a metal plate 33, a first lead terminal 31, and a second lead terminal 32 are integrated. A workpiece W1 is created by bonding a power semiconductor chip 12 to the upper surface 33A of the metal plate 33 via an adhesive 34 (Step S1: die attach process).

[0050] Next, as shown in Figure 8, workpiece W2 is formed by forming a first mold resin 51 on workpiece W1 (Step S2: First mold resin sealing step). Specifically, first, workpiece W1 is placed in a mold cavity 81 for the first mold resin 51. The mold cavity 81 is composed of an upper mold 81A and a lower mold 81B. Next, liquid resin material 512, which will become the first mold resin 51, is filled into the mold cavity 81. By curing the resin material 512, the first mold resin 51 is formed and workpiece W2 is completed.

[0051] Next, as shown in Figure 9, the workpiece W2 is removed from the mold cavity 81, and the control semiconductor chip 14 is bonded to the upper surface 321A of the outer lead portion 311 of the second lead terminal 32 via a bonding agent 35 (insulating or conductive adhesive) to create workpiece W3 (Step S3: Control semiconductor mounting process). The order of steps S1 to S3 may be changed.

[0052] Next, as shown in Figure 10, a plate-shaped member 83 is prepared by laminating a resin sheet 420 onto the upper surface 41A of the heat sink 41. The resin sheet 420 is in a semi-cured state (stage B). Then, the workpiece W3 is placed on the resin sheet 420 side of the plate-shaped member 83 (the surface corresponding to the upper surface 42A of the insulating resin layer 42) so that the lower surface 33B of the metal plate 33 and the lower surface 51B of the first molded resin 51 are in contact, and pressure and temperature are applied and held for a certain period of time. As a result, the resin sheet 420 hardens to become an insulating resin layer 42, and a workpiece W4 is created in which the workpiece W3, the insulating resin layer 42, and the heat sink 41 are fixed together (step S4: resin sheet curing process).

[0053] Next, as shown in Figure 11, the power semiconductor chip 12, control semiconductor chip 14, first lead terminal 31, and second lead terminal 32 of workpiece W4 are interconnected with wires 38 (38A, 38B, 38C) to create workpiece W5 (Step S5: Wire bonding process).

[0054] Next, as shown in Figure 12, workpiece W6 is formed by forming a second mold resin 52 on workpiece W5 (Step S6: Second mold resin sealing step). Specifically, first, workpiece W5 is placed in a mold cavity 82 for the second mold resin 52. The mold cavity 82 is composed of an upper mold 82A and a lower mold 82B. Next, liquid resin material 521, which will become the second mold resin 52, is filled into the mold cavity 82. By curing the resin material 521, the second mold resin 52 is formed and workpiece W6 is completed.

[0055] Finally, the workpiece W6 is removed from the mold cavity 82, and the tie bars of the first lead terminal 31 and the second lead terminal 32, which are integrated in the lead frame F, are cut to separate the first lead terminal 31 and the second lead terminal 32 (Step S7: Lead processing step). After these steps, the semiconductor device 10 is completed.

[0056] [D. Comparative example] Figure 15 shows the configuration of a semiconductor device 100 according to a comparative example. Components of the semiconductor device 100 that are the same as those in the semiconductor device 10 according to the embodiment are denoted by the same reference numerals, and detailed explanations are omitted.

[0057] In semiconductor device 100, the first mold resin 51 is not provided, and in the part where the first mold resin 51 was provided in semiconductor device 10, Second mold resin 52 Therefore, in the resin sheet curing process shown in step S4 of Figure 6, only the lower surface 33B of the metal plate 33 is in contact with the resin sheet constituting the insulating resin layer 42.

[0058] In this state, when the metal plate 33 is pressed against the resin sheet, the pressing force is concentrated at the part of the resin sheet that is in contact with the outer peripheral edge 33E of the lower surface 33B of the metal plate 33, and this part may deform. Specifically, the part of the resin sheet located directly below the outer peripheral edge 33E is pushed outward relative to the metal plate 33, which may cause a bulge in the resin on the side of the metal plate 33 and the formation of a void in the part of the resin sheet located directly below the outer peripheral edge 33E. The outer peripheral edge 33E of the metal plate 33 is a semiconductor device. 100 This is a point where the electric field is concentrated when the device is operating, and if there is a defect in the nearby insulating resin layer 42, it will cause dielectric breakdown of the insulating resin layer 42, resulting in a semiconductor device. 100 The reliability of this may decrease.

[0059] [E. Characteristics of the first mold resin 51] The semiconductor device 10 according to the embodiment is shown in Figure 15 Compared to the semiconductor device 100 in the comparative example shown, the semiconductor device 10 is characterized by having a first mold resin 51 that has different properties from the second mold resin 52 that covers the outer surface of the semiconductor device 10. The following describes in more detail the positional relationship between the first mold resin 51 and the other components.

[0060] [Feature 1] The lower surface 51B of the first mold resin 51 and the lower surface 33B of the metal plate 33 are located in the same plane. As shown in Figure 5, the first molded resin 51 is mainly positioned around the metal plate 33, covering a portion of the metal plate 33 and a portion of the first lead terminal 31. The lower surface 51B of the first molded resin 51 and the lower surface 33B of the metal plate 33 are located in the same plane. Furthermore, since the outer edge of the first molded resin 51 coincides with the outer edge of the insulating resin layer 42, the upper surface 42A of the insulating resin layer 42 is entirely covered by the lower surface 51B of the first molded resin 51 or the lower surface 33B of the metal plate 33.

[0061] In other words, the first molded resin 51 covers a portion of the metal plate 33 and a portion of the first lead terminal 31. The first molded resin 51 includes a lower surface 51B that, in a plan view, extends along or outside the line of the outer edge of the metal plate 33 and the outer edge of the insulating resin layer 42, and is located in the same plane as the lower surface 33B of the metal plate 33. The lower surface 51B is in contact with a second region R2 on the surface of the insulating resin layer 42, which is different from the first region R1.

[0062] According to Feature 1, a portion of the metal plate 33 is covered with the first molded resin 51, and the lower surface 33B of the metal plate 33 and the lower surface 51B of the first molded resin 51 are located in the same plane. Therefore, when the metal plate 33 is brought into contact with the insulating resin layer 42, the lower surface 51B of the first molded resin 51, in addition to the lower surface 33B of the metal plate 33, comes into contact with the upper surface 42A of the insulating resin layer 42. Thus, compared to the case where only the metal plate 33 is brought into contact with the insulating resin layer 42, as in the comparative example, the contact area between the insulating resin layer 42 and the other components (metal plate 33 and first molded resin 51) is increased. As shown in step S4 (resin sheet curing process) in Figure 6, when curing the resin sheet 420 to form the insulating resin layer 42, the workpiece W3 is placed on the resin sheet 420 so that the lower surface 33B of the metal plate 33 and the lower surface 51B of the first molded resin 51 are in contact with the resin sheet 420, and pressure and temperature are applied and held for a certain period of time (see Figure 10). By increasing the contact area between the resin sheet 420 and the workpiece W3, the pressing force exerted by the workpiece W3 on the resin sheet 420 is distributed, suppressing localized stress concentration. This makes it possible to suppress localized deformation of the resin sheet 420.

[0063] In particular, as in the comparative example, if the edge of the metal plate 33 comes into contact with the resin sheet 420, the pressing force will be concentrated at the point of contact with the edge of the resin sheet 420, potentially causing deformation at that point. In the semiconductor device 10, the lower surface 51B of the first molded resin 51, which is located in the same plane as the lower surface 33B of the metal plate 33, extends to a position that coincides with the outer edge line of the insulating resin layer 42 (resin sheet 420). Therefore, the edge of the metal plate 33 does not come into contact with the resin sheet 420, preventing deformation when the resin sheet 420 is cured.

[0064] The outer edge of the metal plate 33 is a point where the electric field is concentrated when the semiconductor device 10 is operating. If there is a defect in the insulating resin layer 42 near this point, it can lead to dielectric breakdown of the insulating resin layer 42, potentially reducing the reliability of the semiconductor device. Feature 1 makes it possible to suppress defects in the insulating resin layer 42 near the outer edge of the metal plate 33, thereby improving the reliability of the semiconductor device 10.

[0065] [Feature 2] The upper surface 51A of the first mold resin 51 is parallel to the lower surface 51B. As shown in Figure 5, the first molded resin 51 includes an upper surface 51A opposite to the lower surface 51B, and the upper surface 51A is parallel to the lower surface 51B. In the example in Figure 5, the upper surface 51A of the first molded resin 51 is in the same plane as the upper surface 311A ​​of the outer lead portion 311, but in feature 2, for example, the upper surface 51A may be at a lower position than the lower surface 311B of the outer lead portion 311. Also, for example, the upper surface 51A may be at the upper surface of the outer lead portion 311 311A It may be located at a higher position, and the outer lead portion 311 may be covered with the first mold resin 51.

[0066] According to Feature 2, the first mold resin 51 has an upper surface 51A parallel to the lower surface 51B of the first mold resin 51 that is in contact with the insulating resin layer 42. Therefore, in the resin sheet curing process (step S4 in Figure 6), when a pressing force is applied from the upper surface 51A of the first mold resin 51, the pressing force is uniformly transmitted to the resin sheet 420, and localized stress concentration is suppressed. This makes it possible to suppress deformation of the resin sheet 420.

[0067] [Feature 3] The upper surface 51A of the first molded resin 51 is in the same plane as the upper surface 311A ​​of the outer lead portion 311 of the first lead terminal 31. As shown in Figure 5, the upper surface 51A of the first molded resin 51 is on the same plane as the upper surface 311A ​​of the outer lead portion 311 of the first lead terminal 31. That is, the first lead terminal 31 includes an outer lead portion 311 that extends parallel to the reference plane S, at a position spaced apart from the insulating resin layer 42 with respect to the reference plane S which includes the upper surface 33A of the metal plate 33, and an inner lead portion 313 that connects the outer lead portion 311 and the metal plate 33. The upper surface 51A of the first molded resin 51 is on the same plane as the upper surface 311A ​​of the outer lead portion 311, which is located on the opposite side of the reference plane S.

[0068] According to Feature 3, the upper surface 51A of the first mold resin 51 is located on the same plane as the upper surface 311A ​​of the outer lead portion 311. This allows for a wider and more flexible setting of the pressurized area during the resin sheet curing process (step S4 in Figure 6), enabling the application of a more stable pressing force.

[0069] [Feature 4] The entire surface of the inner lead portion 313 is covered with the first molded resin 51. As shown in Figures 4A and 5, the inner lead portion 313 of the first lead terminal 31 is entirely covered with the first molded resin 51. The entire surface of the inner lead portion 313 refers to the entire inner lead portion 313, including the upper surface 313A, the lower surface 313B, and the side surfaces connecting the upper surface 313A and the lower surface 313B.

[0070] According to Feature 4, since the entire surface of the inner lead portion 313 of the first lead terminal 31 is covered with the first molded resin 51, it is possible to suppress the peeling of the first molded resin 51 from the first lead terminal 31.

[0071] [Feature 5] The side surface 51C of the first mold resin 51 is covered with the second mold resin 52. As shown in Figure 5, the first molded resin 51 has a side surface 51C that connects the lower surface 51B and the upper surface 51A, and at least a portion of the side surface 51C is covered with the second molded resin 52. In the example in Figure 5, the entire surface of the side surface 51C is covered with the second molded resin 52. Also in the example in Figure 5, the side surface 51D on the second lead terminal 32 side is also covered with the second molded resin 52.

[0072] According to Feature 5, the side of the first mold resin 51 51C Compared to a configuration where the entire surface is exposed, this configuration can suppress the reduction in strength of the side surface 51C. Also, generally, molding resins with high thermal conductivity have lower shielding performance compared to molding resins with low thermal conductivity. If a molding resin with low shielding performance constitutes the outer surface of the semiconductor device 10, dust and water vapor may enter the interior of the semiconductor device 10, potentially causing corrosion or failure of internally sealed components (such as the parts of the first lead terminals 31 and second lead terminals 32 located inside the semiconductor device 10, the power semiconductor chip 12, and the control semiconductor chip 14). If the thermal conductivity of the first molding resin 51 is higher than that of the second molding resin 52, the durability of the semiconductor device 10 may decrease if the first molding resin 51 is exposed on the outer surface of the semiconductor device 10. As shown in Feature 5, by covering the side surfaces 51C and 51D of the first molding resin 51 with the second molding resin 52, which has relatively high shielding performance, the durability of the semiconductor device 10 can be improved.

[0073] [Feature 6] In addition to the first lead terminal 31 side, the first molded resin 51 is also placed on the second lead terminal 32 side. As shown in Figures 4A and 5, the first mold resin 51 is arranged not only on the side of the first lead terminal 31 as viewed from the metal plate 33, but also on the side of the second lead terminal 32 as viewed from the metal plate 33. That is, the semiconductor device 10 comprises the outer lead portion 321 of the second lead terminal 32 and a control semiconductor chip 14. teethThe first mold resin 51 is spaced apart from the reference plane S on the opposite side of the insulating resin layer 42, and extends parallel to the reference plane S at a position opposite to the outer lead portion 311 of the first lead terminal 31, with the metal plate 33 in between. The control semiconductor chip 14 is bonded to the upper surface 321A of the outer lead portion 321, which is located on the opposite side of the reference plane S. The upper surface 51A of the first mold resin 51 is in the same plane as the upper surface 321A of the outer lead portion 321 of the second lead terminal 32 to which the control semiconductor chip 14 is bonded.

[0074] According to Feature 6, the upper surface 51A of the first mold resin 51 is on the same plane as the upper surface 321A of the outer lead portion 321 of the second lead terminal 32 to which the control semiconductor chip 14 is bonded. This makes it possible to apply pressing force from both sides of the metal plate 33 during the resin sheet curing process (step S4 in Figure 6), allowing for a more stable pressing force to be applied.

[0075] [Feature 7] A power semiconductor chip 12 is placed inside the opening 510 of the first mold resin 51. As shown in Figure 4B, the first mold resin 51 has an opening 510 extending from the upper surface 51A to the lower surface 51B. The upper surface 33A of the metal plate 33 is exposed on the lower surface 51B side of the opening 510, and the power semiconductor chip 12 is bonded to the portion of the upper surface 33A of the metal plate 33 that is exposed within the opening 510.

[0076] The opening 510 is formed in the first mold resin encapsulation step S2 in Figure 6 by using a mold cavity 81 having a shape corresponding to the opening 510. Therefore, according to feature 7, the placement location for the power semiconductor chip 12 can be secured in a simple process. In addition, because the opening 510 is provided, a space is formed around the power semiconductor chip 12, making it easy to connect the wires 38 to the power semiconductor chip 12 (the wire bonding step S5 in Figure 6).

[0077] [Feature 8] The opening 510 widens towards the top. As shown in Figure 5, the area of ​​the opening 510 on the upper surface 51A of the first mold resin 51 is larger than the area of ​​the opening 510 on the lower surface 51B.

[0078] According to Feature 8, the wall surfaces 51F and 51G between the upper surface 51A and the lower surface 51B of the first mold resin 51 become inclined surfaces that widen toward the upper surface 51A. Therefore, while ensuring the contact area between the first mold resin 51 and the insulating resin layer 42, a wide working area can be secured when connecting the wires 38 to the power semiconductor chip 12, thereby improving workability. In this case, the working area refers to, for example, the space in which the device for forming the wires 38 can move without interfering with the first mold resin 51. In addition, when molding the first mold resin 51, the mold cavity 81 can be smoothly demolded.

[0079] [Feature 9] The planar shapes of the first mold resin 51, the heat sink 41, and the insulating resin layer 42 are identical. As shown in Figure 5, the outer edge of the first mold resin 51 (position on the XY plane of the side surface 51C), the outer edge of the heat sink 41 (position on the XY plane of the side surface 41C), and the outer edge of the insulating resin layer 42 (position on the XY plane of the side surface 42C) overlap in a plan view.

[0080] According to Feature 9, when laminating the first mold resin 51, the heat sink 41, and the insulating resin layer 42, components with the same planar shape are stacked together, thereby improving the moldability of the semiconductor device 10.

[0081] [Feature 10] The side surface 33C of the metal plate 33 is covered with the first mold resin 51. As shown in Figure 4B, the side surface 33C of the metal plate 33 is covered with the first mold resin 51.

[0082] According to feature 10, since there is no step between the metal plate 33 and the first molded resin 51, stress concentration caused by the second molded resin 52 can be reduced.

[0083] [Feature 11] At least a portion of the outer edge of the upper surface 33A of the metal plate 33 is covered with the first mold resin 51. As shown in Figure 5, at least a portion of the outer peripheral edge on the side of the first lead terminal 31, and at least a portion of the outer peripheral edge on the opposite side of the outer peripheral edge on the side of the first lead terminal 31, are covered with the first molded resin 51.

[0084] According to feature 11, it is possible to prevent the metal plate 33 from peeling off (lifting) from the insulating resin layer 42.

[0085] In Figure 5, the metal plate 33 is arranged along the X direction, and the outer edge of the upper surface 33A of the metal plate 33 along the X direction is covered with the first molded resin 51. When the metal plate 33 is arranged along the X direction, it is preferable that the outer edge of the upper surface 33A of the metal plate 33 along the Y direction is not covered with the first molded resin 51. This is to secure a larger mounting area for the power semiconductor chip 12 on the upper surface 33A of the metal plate 33.

[0086] Furthermore, in Figure 5, the entire outer edge of the upper surface 33A of the metal plate 33 along the X direction is covered with the first molded resin 51. However, as shown in Figure 13, for example, only a part of the outer edge may be covered with the first molded resin 51. In the example of Figure 13, only the four corners of the upper surface 33A of the metal plate 33 that are exposed in a rectangular shape in the opening 510 are covered with the first molded resin 51 (protrusions 513). By covering only a part of the outer edge of the metal plate 33 with the first molded resin 51 in this way, a larger mounting area for the power semiconductor chip 12 on the upper surface 33A of the metal plate 33 can be secured.

[0087] [Feature 12] The side surface 41C of the heat sink 41 is surrounded by the second molded resin 52. As shown in Figure 5, the side surface 41C of the heat sink 41 is covered with the second molded resin 52.

[0088] According to feature 12, since the side surface 41C of the heat sink 41 is covered with the second molded resin 52, a decrease in the strength of the heat sink 41 can be suppressed.

[0089] [Feature 13] The side surface 42C of the insulating resin layer 42 is surrounded by the second mold resin 52. As shown in Figure 5, the side surface 42C of the insulating resin layer 42 is covered with the second mold resin 52.

[0090] According to feature 13, since the side surface 42C of the insulating resin layer 42 is covered with the second mold resin 52, a decrease in the strength of the insulating resin layer 42 can be suppressed.

[0091] [Feature 14] The semiconductor device 10 has a plurality of power semiconductor chips 12 (metal plates 33). As shown in Figure 4B, multiple metal plates 33 are in contact with the upper surface 42A of the insulating resin layer 42, and multiple first lead terminals 31 and multiple second lead terminals 32 are provided corresponding to each of the multiple metal plates 33, and the first molded resin 51 is integrally formed across the multiple metal plates 33.

[0092] According to Feature 14, in a semiconductor device 10 having multiple metal plates 33, the first mold resin 51 is molded integrally, which simplifies the molding process compared to molding the first mold resin 51 individually onto the multiple metal plates 33.

[0093] [Feature 15] The thermal conductivity of the first mold resin 51 is higher than that of the second mold resin 52. As described above, the thermal conductivity of the first mold resin 51 is higher than that of the second mold resin 52.

[0094] According to Feature 15, as heat generated in the power semiconductor chip 12 is transferred through the metal plate 33 and the first lead terminal 31 (the inner lead portion 313 and the outer lead portion 311 connected to the inner lead portion 313), heat is also more easily transferred to the first molded resin 51 that seals the metal plate 33 and the first lead terminal 31. This prevents heat generated in the power semiconductor chip 12 from being transferred through the first lead terminal 31 to other components to which the first lead terminal 31 is connected. In particular, since the first molded resin 51 is positioned in contact with the insulating resin layer 42 that is joined to the heat sink 41, the amount of heat transferred to the heat sink 41 is greater compared to covering the area with the second molded resin 52, thereby enhancing the cooling effect of the power semiconductor chip 12.

[0095] Generally, molding resins with high thermal conductivity are more expensive than ordinary molding resins (with typical thermal conductivity). In the semiconductor device 10, the first molding resin 51 is used in the part close to the power semiconductor chip 12, and the second molding resin 52 is used in the other parts. This makes it possible to improve the cooling effect of the power semiconductor chip 12 while keeping the manufacturing cost of the semiconductor device 10 down.

[0096] [Feature 16] The entire structure is sealed with the second mold resin 52. As shown in Figure 5, the semiconductor device 10 is covered with a second molded resin 52, with the exception of a portion of the heat sink 41 and a portion of the first lead terminal 31 (a portion of the outer lead portion 311 and the tip portion 312).

[0097] According to Feature 16, since the components other than a part of the heat sink 41 and a part of the first lead terminal 31 are covered with the second molded resin 52, the main body 20 of the semiconductor device 10 can be formed by the second molded resin 52. Furthermore, since the surface of the semiconductor device 10 is formed of a single molded resin, the durability of the semiconductor device 10 can be improved compared to the case where multiple types of molded resins are exposed on the outer surface. Specifically, for example, in a configuration where the boundary between multiple types of molded resins with different properties is exposed on the surface of the main body 20, delamination may occur between them from that boundary. In contrast, since no boundary surface is created in a surface continuously formed with a single molded resin, the durability of the semiconductor device 10 can be improved.

[0098] In particular, molding resins with high thermal conductivity have lower shielding performance compared to (ordinary) molding resins with low thermal conductivity, and their strength may decrease if exposed to the outer periphery. Therefore, by sealing the entire semiconductor device 10 with the second molding resin 52 without exposing the first molding resin 51, the strength of the semiconductor device 10 can be increased.

[0099] [Feature 17] The lower surface 41B of the heat sink 41 is exposed on the surface of the semiconductor device 10. As shown in Figure 5, the surface of the heat sink 41 opposite to the insulating resin layer 42, i.e., the lower surface 41B, is exposed to the surface of the semiconductor device 10. As described above, the lower surface 41B of the heat sink 41, together with the second molded resin 52, constitutes the lower surface 20B of the main body 20.

[0100] According to Feature 17, since the lower surface 41B of the heat sink 41 is fully exposed to the outside of the semiconductor device 10, the heat generated by the power semiconductor chip 12 can be easily released to the outside through the heat sink 41, thereby improving the cooling performance of the semiconductor device 10.

[0101] [Feature 18] The lower surface 41B of the heat sink 41 and the second molded resin 52 are in the same plane. As shown in Figure 5, the second mold resin 52 has a surface that is in the same plane as the lower surface 41B of the heat sink 41 that is exposed to the outside of the semiconductor device 10.

[0102] According to Feature 18, the second mold resin 52 has a surface that is in the same plane as the lower surface 41B of the heat sink 41 (the surface opposite to the insulating resin layer 42). Therefore, when the semiconductor device 10 is placed with this surface facing downwards, its orientation is stabilized, and the side surface 41C of the heat sink 41 is protected.

[0103] [Feature 19] As shown in Figure 6, the method for manufacturing the semiconductor device 10 includes: a first molded resin sealing step of covering a part of the metal plate 33 and a part of the first lead terminal 31 with a first molded resin 51; a resin sheet curing step of bringing the lower surface 33B of the metal plate 33 and the lower surface 51B of the first molded resin 51 into contact with a resin sheet 420 and curing the resin sheet 420 to form an insulating resin layer 42; and a second molded resin sealing step of covering the metal plate 33, the power semiconductor chip 12 and a part of the first lead terminal 31 with a second molded resin 52.

[0104] According to Feature 19, the first molded resin 51 covers a portion of the metal plate 33 and a portion of the first lead terminal 31, and then the lower surface 33B of the metal plate 33 and the lower surface 51B of the first molded resin 51 are brought into contact with the resin sheet 420, and the resin sheet 420 is cured to form an insulating resin layer 42. Since the lower surface 33B of the metal plate 33 and the lower surface 51B of the first molded resin 51 are located in the same plane, when the metal plate 33 is brought into contact with the resin sheet 420, the lower surface 51B of the first molded resin 51 comes into contact with the surface of the resin sheet 420 in addition to the lower surface 33B of the metal plate 33. Therefore, compared to the case where only the metal plate 33 is brought into contact with the resin sheet 420, the contact area between the resin sheet 420 and the other components (metal plate 33 and first molded resin 51) is increased, and the pressing force at contact can be distributed.

[0105] In particular, as explained in step S4 of Figure 6, the insulating resin layer 42 is formed by curing the semi-cured resin sheet 420 by applying pressure and heat. At this time, if the edge of the metal plate 33 comes into contact with the resin sheet 420, the pressing force will be concentrated at the point of contact with the edge of the resin sheet 420, and this point may deform. According to the manufacturing method of Feature 19, the lower surface 51B of the first molded resin 51, which is located in the same plane as the lower surface 33B of the metal plate 33, extends to a position that overlaps with the line of the outer edge of the insulating resin layer 42 (resin sheet 420). Therefore, the edge of the metal plate 33 does not come into contact with the resin sheet 420, and deformation when curing the resin sheet 420 can be prevented. As described above, the outer edge of the metal plate 33 is a point where the electric field is concentrated in the actual operating state, but defects in the nearby insulating resin layer 42 can be suppressed, and the reliability of the semiconductor device 10 can be improved.

[0106] [Differentiation] Figure 14A is a cross-sectional view of a modified semiconductor device 10A along the X direction, and Figure 14B is a cross-sectional view of a modified semiconductor device 10B along the X direction. Components of semiconductor devices 10A and 10B that are the same as those in the semiconductor device 10 of the embodiment are denoted by the same reference numerals, and detailed descriptions are omitted.

[0107] In the semiconductor device 10A shown in Figure 14A, similar to the semiconductor device 10, a plurality of metal plates 33 are arranged on an insulating resin layer 42 placed on a heat sink 41. A first molded resin 51 is arranged in the region between adjacent metal plates 33, more specifically, in the region R3 sandwiched between the side surfaces 33C of adjacent metal plates 33. In the semiconductor device 10 according to the embodiment, the upper surface 51A of the first molded resin 51 arranged in the region between adjacent metal plates 33 was coplanar with the upper surface 33A of the metal plates 33. In contrast, in the semiconductor device 10A, the upper surface 51A of the first molded resin 51 arranged in the region between adjacent metal plates 33 is convex with respect to the upper surface 33A of the metal plates 33. Also, the semiconductor device 10 shown in Figure 14B BTherefore, the upper surface 51A of the first mold resin 51, which is positioned in the region between adjacent metal plates 33, is concave relative to the upper surface 33A of the metal plate 33.

[0108] In other words, in the modified semiconductor devices 10A and 10B, the region sandwiched between the side surfaces 33C of adjacent metal plates 33 is covered with the first molded resin 51. The surface of the first molded resin 51 in the region sandwiched between the side surfaces 33C is concave or convex with respect to the upper surface 33A of the metal plate 33.

[0109] Semiconductor device for modification 10A and 10B According to this, compared to the case where the upper surface 51A of the first mold resin 51 between the metal plates 33 is a flat surface, the creepage distance between the metal plates 33 becomes longer, and the insulation performance can be improved. [Explanation of Symbols]

[0110] 10...Semiconductor device, 12 (12α~12ζ)...Power semiconductor chip, 14 (14α~14γ)...Control semiconductor chip, 20...Main body, 31...First lead terminal, 32...Second lead terminal, 33...Metal plate, 34...Bonding agent, 35...Bonding agent, 38 (38A~38C)...Wire, 41...Heat sink, 42...Insulating resin layer, 51...First molded resin, 510...Opening, 52...Second molded resin, 81,82...Molded cavity, 83...Plate-shaped member, 311,321...Outer lead part, 312,322...Tip part, 313...Inner lead part, 420...Resin sheet to.

Claims

1. Heat sink and An insulating resin layer formed on the heat sink, A metal plate comprising a first surface and a second surface opposite to the first surface, wherein the first surface contacts a first region which is part of the surface of the insulating resin layer, The first semiconductor chip bonded to the second surface, The first lead terminal connected to the metal plate, A first molded resin covering a portion of the metal plate and a portion of the first lead terminal, It comprises a second mold resin formed from a resin material with different properties from the first mold resin, which covers a part of the metal plate, the first semiconductor chip, and a part of the first lead terminal, The first mold resin is In a plan view, the third surface extends along the line between the outer edge of the metal plate and the outer edge of the insulating resin layer, or to the outside of it, and is located in the same plane as the first surface, The third side is, It contacts a second region of the surface of the insulating resin layer that is different from the first region, At least one of the outer circumferential surface of the heat sink and the outer circumferential surface of the insulating resin layer is covered with the second molded resin. Semiconductor equipment.

2. The first mold resin is Including the fourth surface opposite to the third surface, The fourth surface is parallel to the third surface. The semiconductor device according to claim 1.

3. The first lead terminal is, A first portion extending parallel to the plane, at a position spaced apart from the insulating resin layer with respect to the plane including the second surface, It includes a second part that connects the first part and the metal plate, The fourth surface of the first mold resin is located in the same plane as the surface located on the opposite side of the plane in the first portion. The semiconductor device according to claim 2.

4. The second portion is entirely covered with the first mold resin. The semiconductor device according to claim 3.

5. The first mold resin is It has a fifth surface that connects the third surface and the fourth surface, At least a portion of the fifth surface is covered with the second mold resin. A semiconductor device according to any one of claims 3 to 4.

6. A second lead terminal is spaced apart from the insulating resin layer with respect to the plane including the second surface, and extends parallel to the plane at a position opposite to the first portion with respect to the metal plate, The present invention further comprises a second semiconductor chip bonded to the surface of the second lead terminal located opposite to the aforementioned plane, The fourth surface of the first mold resin is located in the same plane as the surface of the second lead terminal to which the second semiconductor chip is bonded. The semiconductor device according to any one of claims 3 to 5.

7. The first mold resin is Having an opening from the fourth surface to the third surface, The second surface of the metal plate is exposed on the third surface side of the opening. The first semiconductor chip is bonded to the portion of the second surface of the metal plate that is exposed within the opening. The semiconductor device according to claim 6.

8. The area of ​​the opening on the fourth surface is larger than the area of ​​the opening on the third surface. The semiconductor device according to claim 7.

9. The outer edge of the first mold resin, the outer edge of the heat sink, and the outer edge of the insulating resin layer overlap in a plan view. A semiconductor device according to any one of claims 1 to 8.

10. The outer surface of the metal plate is covered with the first mold resin. A semiconductor device according to any one of claims 1 to 9.

11. At least a portion of the outer peripheral edge of the second surface of the metal plate on the side of the first lead terminal, and at least a portion of the outer peripheral edge on the side opposite to the outer peripheral edge on the side of the first lead terminal, are covered with the first molded resin. A semiconductor device according to any one of claims 1 to 10.

12. Multiple metal plates are in contact with the surface of the insulating resin layer. Multiple first lead terminals are provided corresponding to each of the multiple metal plates. The first mold resin is integrally formed across the plurality of metal plates. A semiconductor device according to any one of claims 1 to 11.

13. The region sandwiched between the outer surfaces of the adjacent metal plates is covered with the first mold resin. The surface of the first mold resin in the region sandwiched between the outer peripheral surfaces is concave or convex with respect to the second surface of the metal plate. The semiconductor device according to claim 12.

14. The thermal conductivity of the first mold resin is higher than that of the second mold resin. A semiconductor device according to any one of claims 1 to 13.

15. The second molded resin covers all components except for a portion of the heat sink and a portion of the first lead terminal. A semiconductor device according to any one of claims 1 to 14.

16. The surface of the heat sink opposite to the insulating resin layer is exposed to the surface of the semiconductor device. A semiconductor device according to any one of claims 1 to 15.

17. The second mold resin has a surface that is located in the same plane as the surface of the heat sink that is exposed to the outside of the semiconductor device. The semiconductor device according to claim 16.

18. A method for manufacturing a semiconductor device according to any one of claims 1 to 17, A step of covering a part of the metal plate and a part of the first lead terminal with the first mold resin, The process of forming the insulating resin layer by bringing the first surface of the metal plate and the third surface of the first molded resin into contact with a resin sheet and curing the resin sheet, A step of covering the metal plate, the first semiconductor chip, and a part of the first lead terminal with the second mold resin, A method for manufacturing a semiconductor device containing [a specific component].

Images