Semiconductor equipment

Abstract

To inhibit occurrence and expansion of damage in a joint member.SOLUTION: A joint member 3 of a semiconductor device 1 is formed in a manner that a second thickness T2 at the other side 4b2 is larger than a first thickness T1 at one side 4b1. A thick portion at the other side 4b2 side of the joint member 3 has elasticity. Thus, stress caused between a wiring board 2a and a semiconductor chip 4 in the joint member 3 by heat is buffered. Therefore, occurrence of cracks is reduced in the joint member 3. Further, even if a crack occurs, expansion of the crack is inhibited. As a result, deterioration of reliability of the semiconductor device 1 is prevented.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] A semiconductor device includes a semiconductor chip having a switching function and a diode function, and is used as a power conversion device. The semiconductor chip includes, for example, an IGBT (Insulated Gate Bipolar Transistor) and a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as switching elements. Further, a control electrode is provided on one side of the front surface of such a semiconductor chip, an output electrode is provided on the other side, and an input electrode is provided on the back surface. The semiconductor chip includes, for example, a FWD (Free Wheeling Diode) and a SBD (Schottky Barrier Diode) as diode elements (see, for example, Patent Document 1). The semiconductor device has the semiconductor chip joined onto a wiring board of an insulating circuit board by a joining member (for example, solder).

[0003] Further, the semiconductor chip is formed of a wide bandgap semiconductor having a larger bandgap than silicon. Thereby, the semiconductor chip achieves a higher breakdown voltage than when silicon is used. Such a wide bandgap semiconductor includes, for example, silicon carbide.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] When semiconductor devices undergo power cycling tests, cracks can form in the bonding material due to the difference in thermal expansion coefficients between the circuit board and the semiconductor chip. In particular, semiconductor chips generate more heat on the output electrode side than on the control electrode side. Therefore, crack formation and propagation are greater on the output electrode side of the bonding material. Furthermore, if the semiconductor chip is made of silicon carbide, its Young's modulus is higher than that of silicon. In such semiconductor chips, cracks tend to propagate more easily from the edge of the semiconductor chip on the output electrode side of the bonding material towards the center of the semiconductor chip. As a result, there is a higher risk of a decrease in the long-term reliability of the semiconductor device.

[0006] The present invention has been made in view of these points, and aims to provide a semiconductor device in which the occurrence and extension of damage in the joining members are suppressed. [Means for solving the problem]

[0007] According to one aspect of the present invention, a semiconductor chip formed of a wide bandgap semiconductor is provided, having a rectangular shape in plan view and including a control electrode and a main electrode on its front surface, wherein the control electrode is provided in a first region including one side of the front surface, and the main electrode is provided in a second region including the other side opposite to the first side of the front surface, and the back surface of the semiconductor chip is joined via a bonding member, and the bonding member In The second thickness on the other side is equal to the first thickness on the one side. It is between 1.2 and 2.0 times. Semiconductor devices are provided. [Effects of the Invention]

[0008] According to the disclosed technology, the occurrence and spread of damage to the bonding members can be suppressed, thereby preventing a decrease in the reliability of the semiconductor device. [Brief explanation of the drawing]

[0009] [Figure 1] This is a diagram illustrating a semiconductor device of the first embodiment. [Figure 2] This is a cross-sectional view of a reference semiconductor device. [Figure 3] This is a diagram illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 4] This is a plan view of the semiconductor device according to the second embodiment. [Figure 5] This is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 6] This is an equivalent circuit diagram of the semiconductor device according to the second embodiment. [Figure 7] This is a flowchart showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 8] This is a plan view of the arm portion included in the semiconductor device of the second embodiment. [Figure 9] This is a cross-sectional view (part 1) of the arm portion included in the semiconductor device of the second embodiment. [Figure 10] This is a cross-sectional view (part 2) of the arm portion included in the semiconductor device of the second embodiment. [Figure 11] This is a plan view of the arm portion included in the semiconductor device of Modification 2-1 of the second embodiment. [Figure 12] This is a cross-sectional view of an arm portion included in a semiconductor device of Modification 2-1 of the second embodiment. [Figure 13] This is a flowchart showing a method for manufacturing a semiconductor device according to a modified example 2-2 of the second embodiment. [Figure 14] This is a plan view of the semiconductor device according to the third embodiment. [Figure 15] This is a plan view of a semiconductor unit containing a semiconductor device according to a third embodiment. [Figure 16] This is a cross-sectional view (part 1) of the semiconductor device according to the third embodiment. [Figure 17] This is a cross-sectional view (part 2) of the semiconductor device according to the third embodiment. [Figure 18] This is a diagram of a lead frame included in a semiconductor device of Modification 3-1 of the third embodiment. [Figure 19] This is a cross-sectional view of a semiconductor device according to a modified example 3-1 of the third embodiment.

Best Mode for Carrying Out the Invention

[0010] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the "front surface" and the "upper surface" represent the surfaces facing the +Z direction in the semiconductor devices 1, 10, and 10a of FIGS. 1, 4, and 14. Similarly, "up" represents the direction of the +Z direction in the semiconductor devices 1, 10, and 10a of FIGS. 1, 4, and 14. The "back surface" and the "lower surface" represent the surfaces facing the -Z direction in the semiconductor devices 1, 10, and 10a of FIGS. 1, 4, and 14. Similarly, "down" represents the direction of the -Z direction in the semiconductor devices 1, 10, and 10a of FIGS. 1, 4, and 14. The "side surface" represents the surface connecting the "front surface" or the "upper surface" and the "back surface" and the "lower surface" in the semiconductor devices 1, 10, and 10a of FIGS. 1, 4, and 14. For example, the "side surface" represents the surfaces facing the ±X direction and the ±Y direction in the semiconductor devices 1, 10, and 10a of FIGS. 1, 4, and 14. Such a directionality is meant in all the drawings. The "front surface", the "upper surface", "up", the "back surface", the "lower surface", "down", and the "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical idea of the present invention. For example, "up" and "down" do not necessarily mean the vertical direction with respect to the ground. That is, the directions of "up" and "down" are not limited to the gravitational direction. In the following description, the "main component" represents the case where it contains 80 vol% or more. In the following description, the substantially parallel and the substantially horizontal directions mean that the angle formed by two objects is in the range of 170° or more and 190° or less. The substantially right angle and the substantially vertical directions mean that the angle formed by two objects is in the range of 85° or more and 95° or less.

[0011] [First Embodiment] The semiconductor device of the first embodiment will be described with reference to FIG. 1. FIG. 1 is a diagram for explaining the semiconductor device of the first embodiment. FIG. 1(A) is a plan view of the semiconductor device 1, FIG. 1(B) is a cross-sectional view taken along the dash-dotted line X-X in FIG. 1(A), and FIG. 1(C) is a cross-sectional view taken along the dash-dotted line Y-Y in FIG. 1(A).

[0012] The semiconductor device 1 includes at least a semiconductor chip 4 and a wiring board 2a to which the back surface of the semiconductor chip 4 is joined via a bonding member 3. The semiconductor chip 4 is rectangular in shape when viewed from above and is surrounded on all four sides by one side 4b1, the other side 4b2 opposite to the first side 4b1, and side edges 4b3 and 4b4 connecting the first side 4b1 and the other side 4b2. The semiconductor chip 4 includes a control electrode 4c1 and a main electrode 4c2 on its front surface 4a. The semiconductor chip 4 also includes a main electrode on its back surface, although this is not shown in the illustration.

[0013] The control electrode 4c1 is provided in a first region 4a1, which is the outer edge along one side 4b1 of the front surface 4a. The control electrode 4c1 only needs to be provided in the first region 4a1; for example, it may be provided in the center of one side 4b1. The main electrode 4c2 is provided in a second region 4a2, which includes at least the outer edge along the other side 4b2 of the front surface 4a. The second region 4a2 is adjacent to the first region 4a1 on the front surface 4a. Also, in Figure 1, the main electrode 4c2 on the front surface 4a is included in the region extending from one side 4b1 to the other side 4b2. That is, the main electrode 4c2 on the front surface 4a is formed from the second region 4a2 to the first region 4a1 and is included in the entire front surface 4a excluding the control electrode 4c1. The main electrode on the back surface is included in the region extending from one side 4b1 to the other side 4b2 of the semiconductor chip 4. In other words, the main electrodes on the back surface are contained within the entire back surface of the semiconductor chip 4.

[0014] Furthermore, the semiconductor chip 4 is formed from a wide-bandgap semiconductor. The wide-bandgap semiconductor is, for example, silicon carbide. The Young's modulus of the silicon carbide semiconductor chip 4 is 400 GPa or more and 500 GPa or less. The semiconductor chip 4 may include a switching element consisting of a MOSFET made of silicon carbide. Such a semiconductor chip 4 has a gate electrode as a control electrode 4c1 and a source electrode (output electrode) as a main electrode 4c2 on its front surface 4a. The semiconductor chip 4 also has a drain electrode (input electrode) as a main electrode on its back surface. Furthermore, the control electrode 4c1 is located in the center of the side of the front surface 4a, and the main electrode 4c2 is located in the center of the front surface 4a. The input electrode on the back surface is not shown in the diagram.

[0015] The wiring board 2a is mainly composed of a metal with excellent conductivity. Such a metal is, for example, copper, nickel, or an alloy containing at least one of these. In Figure 1, the wiring board 2a is shown as being rectangular in plan view. The wiring board 2a is not limited to being rectangular in plan view, and may be any shape necessary to construct a given circuit. For example, it may be U-shaped, L-shaped, or hook-shaped. The wiring board 2a may also be, for example, a circuit pattern or a lead frame.

[0016] The joining member 3 is, for example, solder. The solder is made of lead-free solder mainly composed of a predetermined alloy. The predetermined alloy is, for example, at least one of the following alloys: a tin-silver alloy, a tin-zinc alloy, or a tin-antimony alloy. The solder may also contain additives such as copper, bismuth, indium, nickel, germanium, cobalt, or silicon. Alternatively, the joining member 3 may be a sintered metal. The sintered metal is made of a metal mainly composed of silver.

[0017] In a side view, as shown in Figure 1(B), such a joint member 3 is configured such that the second thickness T2 on the other side 4b2 is thicker than the first thickness T1 on the one side 4b1. The second thickness T2 should be 1.2 times or more and 2.0 times or less than the first thickness T1. More preferably, it is 1.5 times or more and 1.8 times or less.

[0018] Furthermore, in a plan view, the joining member 3 protrudes in directions perpendicular to the other side 4b2 and the one side 4b1 (±X direction). In this case, the second protrusion width W2 outward in the direction perpendicular to the other side 4b2 (-X direction) is longer than the first protrusion width W1 outward in the direction perpendicular to the one side 4b1 (+X direction). Note that the second protrusion width W2 and the first protrusion width W1 vary, as shown in Figure 1(A). The second protrusion width W2 and the first protrusion width W1 here are the average values ​​of the joining member 3 that protrude from the other side 4b2 and the one side 4b1. The second protrusion width W2 and the first protrusion width W1 are also the same as the second thickness T2 and the first thickness T1. That is, the second protrusion width W2 should be between 1.2 and 2.0 times the first protrusion width W1. More preferably, it is 1.5 times or more and 1.8 times or less.

[0019] Furthermore, in a plan view, the joining member 3 also protrudes outward in directions perpendicular to the sides 4b3 and 4b4 (±Y directions). The widths W3 and W4 of these outward protrusions in directions perpendicular to the sides 4b3 and 4b4 are approximately the same. Also, the thicknesses T3 and T4 of the sides 4b3 and 4b4 of the joining member 3 are also approximately the same. These identical values ​​are within the range of 0.9 times or more and 1.1 times or less.

[0020] Here, we will explain the reference semiconductor device using Figure 2. Figure 2 is a cross-sectional view of the reference semiconductor device. The cross-sectional view of semiconductor device 1a shown in Figure 2 corresponds to the cross-sectional view in Figure 1(B).

[0021] The components included in semiconductor device 1a are the same as those in semiconductor device 1. However, the joining member 3 of semiconductor device 1a has approximately the same first thickness T1 on one side 4b1 and the same second thickness T2 on the other side 4b2. Also, the first overhang width W1 and the second overhang width W2 are approximately the same. Although not shown in the illustration, the overhang widths of the side sides 4b3 and 4b4 are also approximately the same as the first overhang width W1 and the second overhang width W2. In this case, the same values ​​are within the range of 0.9 times or more and 1.1 times or less.

[0022] In such a semiconductor device 1a, a control voltage is applied to the control electrode of the first region 4a1 while a current is applied to the main electrode (input electrode) on the back surface of the semiconductor chip 4. This causes an output current to be output from the output electrode of the second region 4a2. The second region 4a2 is heated according to the output current. At this time, the thermal expansion coefficients of the semiconductor chip 4 and the bonding member 3 are different. Furthermore, the Young's modulus of the semiconductor chip 4 is between 400 GPa and 500 GPa. This is more than four times the Young's modulus of, for example, a semiconductor chip made of silicon. The Young's modulus of a semiconductor chip made of silicon is between 100 GPa and 124 GPa. Therefore, the thermal expansion rates of the semiconductor chip 4 and the wiring board 2a are different, and furthermore, the semiconductor chip 4, with its relatively large Young's modulus, has difficulty keeping up with the expansion of the wiring board 2a. In particular, the difference in expansion between the semiconductor chip 4 and the wiring board 2a becomes large on the second region 4a2 (the other side 4b2) of the bonding member 3, where the thermal changes are significant. As a result, a large stress is generated in the joining member 3 that joins the semiconductor chip 4 and the wiring board 2a in this region, and a crack C extends laterally (+X direction) inward from the end on the second region 4a2 side of the joining member 3.

[0023] On the other hand, the bonding member 3 of the semiconductor device 1 is configured such that the second thickness T2 on the other side 4b2 is thicker than the first thickness T1 on the one side 4b1. The thicker portion of the bonding member 3 on the other side 4b2 is elastic. Therefore, the stress generated in the bonding member 3 between the wiring board 2a and the semiconductor chip 4 due to heat is relieved. Consequently, the occurrence of cracks C in the bonding member 3 is reduced, and even if cracks do occur, their propagation is suppressed. As a result, the bonding of the semiconductor chip 4 to the wiring board 2a by the bonding member 3 is properly maintained, and a decrease in the reliability of the semiconductor device 1 is prevented.

[0024] Next, the method for manufacturing the semiconductor device 1 will be explained using Figure 3. Figure 3 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment. Note that Figure 3 corresponds to the cross-sectional view in Figure 1(B). Figure 3(A) shows the case where the wiring board 2a and the main current conductor 2b are located on the same plane. Figure 3(B) shows the case where the main current conductor 2b is located above the wiring board 2a. Figure 3(C) shows the case where the connection density of the wires 5 is greater on one side 4b1 than on the other side 4b2.

[0025] In manufacturing the semiconductor device 1, first, a semiconductor chip 4 is bonded to a wiring board 2a via a bonding member 3. The wiring board 2a may be, for example, a circuit pattern formed on a ceramic plate to constitute an insulating circuit board.

[0026] Next, wires are connected to the semiconductor chip 4. At this time, a wire (not shown) is connected to the control electrode 4c1 of the first region 4a1 of the semiconductor chip 4. Also, the second region 4a2 of the semiconductor chip 4 and the main current conductor 2b are connected by a wire 5. At this time, the second connection point 5a2 of the other end of the wire 5 to the second region 4a2 is on the other side 4b2. One end of the wire 5 is connected to the main current conductor 2b at a reference connection point 5b. The main current conductor 2b receives the output current output from the output electrode, which is the main electrode 4c2 of the semiconductor chip 4. Examples of such a main current conductor 2b include a circuit pattern and an external connection terminal (e.g., a lead frame).

[0027] The second height h2 from the second connection point 5a2 of the wire 5 connected in this manner to the reference plane B horizontal to the wiring board 2a passing through the vertex P of the wire 5 is lower than the reference height hb from the reference connection point 5b to the reference plane B. Note that the second height h2 may be the same as the reference height hb.

[0028] Next, an insulating circuit board including a wiring board 2a to which such semiconductor chips 4 are bonded is joined to a metal base plate, for example, via solder. At this time, the insulating circuit board is heated while placed on the metal base plate via solder. As the solder melts, the joining member 3 also remelts. Furthermore, the wire 5 expands due to the heat, generating a restoring force that tries to return it to a straight state. At this time, since the second height h2 is lower than the reference height hb, the second connection point 5a2 of the wire 5 moves upward. As a result, as shown in Figure 3(A), the second region 4a2 of the semiconductor chip 4 is pulled upward (+Z direction) at the second connection point 5a2, and the semiconductor chip 4 tilts so that the other side 4b2 is higher than the one side 4b1 relative to the wiring board 2a. In this state, when the joining member 3 solidifies, as shown in Figure 1(B), the joining member 3 of the semiconductor device 1 is configured such that the second thickness T2 on the other side 4b2 is thicker than the first thickness T1 on the one side 4b1.

[0029] Furthermore, if the main current conductor 2b is located above the wiring board 2a, the semiconductor chip 4 can be tilted by connecting the wire 5 to the semiconductor chip 4 as follows. First, the other end of the wire 5 is connected to one side 4b1 of the second region 4a2. That is, the first connection point 5a1 to which the other end of the wire 5 is connected is located on one side 4b1 (see Figure 3(B)).

[0030] Next, similar to the above, an insulating circuit board including a wiring board 2a to which such semiconductor chips 4 are bonded is placed on a metal base plate via solder and heated. In this case as well, the wire 5 expands due to the heat, generating a restoring force that tries to return it to a straight state. In this case, since the first height h1 is higher than the reference height hb, the first connection point 5a1 of the wire 5 moves downward. The first height h1 is the height from the first connection point 5a1 of the wire 5 connected to the second region 4a2 to the reference plane B which is horizontal to the wiring board 2a passing through the vertex P of the wire 5. As a result, as shown in Figure 3(B), the first connection point 5a1 of the second region 4a2 of the semiconductor chip 4 is pushed downward (in the -Z direction), and the semiconductor chip 4 tilts so that the other side 4b2 is higher than the other side 4b1 relative to the wiring board 2a. In this state, once the joining member 3 solidifies, as shown in Figure 1(B), the joining member 3 of the semiconductor device 1 is configured such that the second thickness T2 on the other side 4b2 is thicker than the first thickness T1 on the one side 4b1.

[0031] Furthermore, based on the above, in Figure 3(A), when multiple wires 5 (including wires connected to the control electrode 4c1 (not shown)) are connected to the front surface 4a of the semiconductor chip 4, the connection density of the multiple wires 5 should be greater on the other side 4b2 than on the other side 4b1. Note that connection density represents the number of wires connected per unit area. In other words, the center of gravity of the connection points of the multiple wires 5 (including wires connected to the control electrode 4c1 (not shown)) to the front surface 4a of the semiconductor chip 4 may be closer to the other side 4b2 than to the other side 4b1. As a result, the semiconductor chip 4 is pulled up towards the second region 4a2, and the semiconductor chip 4 tilts so that the other side 4b2 is higher than the one side 4b1 relative to the wiring board 2a (Figure 3(A)).

[0032] Furthermore, in Figure 3(B), when multiple wires 5 (including wires connected to the control electrode 4c1 (not shown)) are connected to the front surface 4a of the semiconductor chip 4, the connection density of the multiple wires 5 should be greater on one side 4b1 than on the other side 4b2. For example, as shown in Figure 3(C), the main current conductors 2b1 and 2b2 are located above the wiring board 2a. Wire 6 connects the main current conductor 2b1 to the control electrode 4c1. Multiple wires 5 connect the main current conductor 2b2 to one side 4b1 of the second region 4a2. In this case, wires 5 and 6 act to push down on their respective connection points.

[0033] In this case, the connection density of wires 5 and 6 to the front surface 4a of the semiconductor chip 4 is greater on one side 4b1 than on the other side 4b2. That is, the center of gravity of the connection points of wires 5 and 6 to the front surface 4a of the semiconductor chip 4 is closer to one side 4b1 than to the other side 4b2. As a result, the first region 4a1 side of the semiconductor chip 4 is pushed down, and the semiconductor chip 4 tilts so that the other side 4b2 is higher than the one side 4b1 relative to the wiring board 2a (see Figure 3(B)).

[0034] As shown in Figures 3(A) and 3(B) above, the second thickness T2 on the other side 4b2 of the bonding member 3 of the semiconductor device 1 shown in Figure 1 is configured to be thicker than the first thickness T1 on the other side 4b1.

[0035] [Second Embodiment] In the second embodiment, a specific semiconductor device will be described using Figures 4 and 5. Figure 4 is a plan view of the semiconductor device of the second embodiment, and Figure 5 is a cross-sectional view of the semiconductor device of the second embodiment. In Figure 4, the connection points of the external connection terminals 43, 44, and 45 on the wiring boards 23a, 23b, and 33a are represented by rectangles, and the illustration of the external connection terminals 43, 44, and 45 is omitted. Figure 5 is a cross-sectional view along the dashed line YY in Figure 4.

[0036] The semiconductor device 10 has a first arm portion 20 and a second arm portion 30, which together form an upper and lower arm portion. The first arm portion 20 and the second arm portion 30 are electrically connected by a wire 28. The semiconductor device 10 also has a metal base plate 46 on which the first arm portion 20 and the second arm portion 30 are arranged via a connecting member 27, and a housing 40 which is arranged on the metal base plate 46 and surrounds the first arm portion 20 and the second arm portion 30. External connection terminals 43, 44, and 45 are joined to insulating circuit boards 21 and 31 via a connecting member (Figure 5 shows the external connection terminals 43 and 44 being joined by the connecting member 27). The inside of the housing 40 is sealed by a sealing member 47. The external connection terminals 43 and 44 connected to the first arm portion 20 and the second arm portion 30 are exposed on the housing 40.

[0037] The first arm portion 20 includes an insulating circuit board 21, a semiconductor chip 26 provided on the front surface of the insulating circuit board 21, and external connection terminals 44 and 45. The first arm portion 20 is formed by placing such an insulating circuit board 21 on a metal base plate 46 via a joining member 27.

[0038] The semiconductor chips 25 and 26 may be MOSFETs made of silicon carbide. The semiconductor chips 25 and 26 have control electrodes 25a and 26a in the center of the side of the front surface, and output electrodes 25b and 26b in the center. The input electrodes on the back surface are not shown in the diagram. The semiconductor device 10 uses a switching element made of a MOSFET equipped with a body diode, so there is no need to connect a diode element in parallel. For this reason, the switching element made of a MOSFET is suitable for placement on the concave circuit patterns 23a and 33a described later.

[0039] The insulated circuit board 21 has an insulating plate 22 and a metal plate 24 formed on the back surface of the insulating plate 22. Furthermore, the insulated circuit board 21 has wiring boards 23a to 23d formed on the front surface of the insulating plate 22. The insulating plate 22 is made of a highly thermally conductive ceramic with excellent thermal conductivity. Examples of ceramics include aluminum oxide, aluminum nitride, and silicon nitride. The metal plate 24 is made of a metal with excellent thermal conductivity, such as aluminum, iron, silver, copper, or an alloy containing at least one of these. The circuit patterns 23a to 23d are made of a metal with excellent conductivity. Examples of metals include copper or copper alloys. In addition, plating may be applied to improve corrosion resistance. Examples of plating materials include nickel, nickel-phosphorus alloy, and nickel-boron alloy. The thickness of the wiring boards 23a to 23d is, for example, 0.1 mm or more and 1 mm or less. As an insulating circuit board 21 having such a configuration, for example, a DCB (Direct Copper Bonding) board or an AMB (Active Metal Brazed) board can be used. The insulating circuit board 21 can conduct the heat generated by the semiconductor chips 25 and 26 to the metal base plate 46 side via the circuit pattern 23a, insulating plate 22, and metal plate 24.

[0040] The wiring board 23a constitutes the drain pattern of the first arm portion 20 (see Figure 8(A)). Input electrodes formed on the back surfaces of semiconductor chips 25 and 26 are joined to the wiring board 23a via a bonding member 27. External connection terminals 44 are also joined to the wiring board 23a via a bonding member 27. Such a wiring board 23a has a concave shape in plan view. Inside the wiring board 23a is a concave recess, which has a first wiring region 23a1 shown by the dashed line in Figure 4. The wiring board 23a may have a U-shape in plan view. On the wiring board 23a, semiconductor chips 25 and 26 are separated by the first wiring region 23a1 and arranged in one row along the first wiring region 23a1. The semiconductor chips 25 and 26 are arranged so that their control electrodes 25a and 26a form a single row. Furthermore, the control electrodes 25a face each other, and the control electrodes 26a face each other.

[0041] The wiring board 23b constitutes the source pattern of the first arm section 20 (see Figure 8(A)). Wires 28a (main current wires) connected to the output electrodes 25b and 26b of the semiconductor chips 25 and 26 are connected to the wiring board 23b in the first wiring region 23a1. The wiring board 23a is also joined to the external connection terminals 45 via a joining member 27. Such a wiring board 23b forms an L shape in the plan view of Figure 4. Details of the connection between the output electrodes 25b and 26b of the semiconductor chips 25 and 26 of the first arm section 20 and the wiring board 23b by wires 28a will be described later.

[0042] The wiring boards 23c and 23d constitute the sense source pattern and gate pattern of the first arm portion 20, respectively. The wiring boards 23c and 23d are arranged adjacent to the wiring board 23a, sandwiching it together with the first wiring region 23a1. That is, in a plan view, the wiring boards 23c and 23d are arranged adjacent to the wiring board 23a, parallel to the edges perpendicular to the concave opening of the wiring board 23a. They are also arranged adjacent to the wiring board 23a, parallel to two opposing edges of the first wiring region 23a1. Furthermore, the wiring boards 23c and 23d are constructed by extending them in a long, narrow shape along the edges of the insulating board 22 to save space. Wire 28a (control wire) connected to the output electrode 25b of the semiconductor chip 25 is connected to wiring board 23c. Wire 29a (control wire) connected to the control electrodes 25a and 26a of the semiconductor chips 25 and 26 is connected to wiring board 23d, respectively.

[0043] The second arm portion 30 includes an insulating circuit board 31, semiconductor chips 35 and 36 provided on the front surface of the insulating circuit board 31, and an external connection terminal 43. The insulating circuit board 31 is also arranged on a metal base plate 46 via a bonding member 27. The components of the second arm portion 30 are arranged in a way that is approximately point-symmetric with respect to the components of the first arm portion 20 in a plan view, with respect to the center point of the semiconductor device 10.

[0044] Like semiconductor chips 25 and 26, semiconductor chips 35 and 36 include a switching element made of a MOSFET composed of silicon carbide. Therefore, semiconductor chips 35 and 36 have a drain electrode on their back surface as the main input electrode, and gate electrodes 35a and 36a as control electrodes and source electrodes 35b and 36b as the main output electrodes on their front surface. Furthermore, the control electrodes 35a and 36a are located in the center of the sides of the front surface of semiconductor chips 35 and 36, and the output electrodes 35b and 36b are located in the center. The input electrodes on the back surface are not shown in the diagram.

[0045] The insulated circuit board 31 has an insulating plate 32 and a metal plate 34 formed on the back surface of the insulating plate 32. Furthermore, the insulated circuit board 31 has wiring boards 33a to 33d formed on the front surface of the insulating plate 32. The insulated circuit board 31 may be made of the same material as the insulated circuit board 21.

[0046] The wiring board 33a constitutes the drain pattern of the second arm portion 30 (see Figure 8(B)). Input electrodes formed on the back surfaces of semiconductor chips 35 and 36 are joined to the wiring board 33a via a bonding member 27. External connection terminals 43 are also joined to the wiring board 33a via the bonding member 27. Such a wiring board 33a has a concave shape in plan view. Inside the wiring board 33a, there is a second wiring region 33a1, which consists of a concave recess and is shown by the dashed line in Figure 4. Furthermore, the wiring board 33a is adjacent to the wiring board 23a with the first wiring region 23a1 side and the second wiring region 33a1 side facing each other. That is, the wiring board 23a of the first arm portion 20 and the wiring board 33a of the second arm portion 30 are adjacent with their respective recesses facing each other. On the wiring board 33a, semiconductor chips 35 and 36 are arranged in separate rows, with the second wiring region 33a1 in between. The semiconductor chips 35 and 36 are arranged so that their control electrodes 35a and 36a form a single row. Furthermore, the control electrodes 35a face each other, and the control electrodes 36a face each other.

[0047] The wiring board 33b constitutes the source pattern of the second arm portion 30 (see Figure 8(B)). Wires 28b (main current wires) connected to the output electrodes 35b and 36b of the semiconductor chips 35 and 36 are connected to the wiring board 33b in the second wiring region 33a1. In the plan view of Figure 4, such a wiring board 33b is L-shaped and includes a region that covers the entire second wiring region 33a1 and a region perpendicular to the upper side in Figure 2. The wiring board 33b is electrically connected to the wiring board 23a by wires 28b. In the plan view of Figure 4, such a wiring board 33b is L-shaped. In the plan view of Figure 4, the wiring board 33b is T-shaped. Details of the connection between the output electrodes 35b and 36b of the semiconductor chips 35 and 36 of the second arm portion 30 and the wiring board 33b by wires 28b will be described later.

[0048] The wiring boards 33c and 33d constitute the sense source pattern and gate pattern of the second arm portion 30, respectively. The wiring boards 33c and 33d, together with the second wiring region 33a1, sandwich the wiring board 33a, are adjacent to the wiring board 33a, and are positioned in a point-symmetric position with respect to the wiring boards 23c and 23d, with reference to the center point of the semiconductor device 10. In this case, the wiring boards 33c and 33d are positioned above the wiring board 33a in Figure 4, but depending on the position of the wiring boards 23c and 23d, they may also be positioned below the wiring board 33a in Figure 4. Furthermore, the wiring boards 33c and 33d are constructed by extending them in a long, narrow shape along the edge of the insulating board 32 to save space. Wire 28b (control wire) connected to the output electrode 36b of the semiconductor chip 36 is connected to the wiring board 33c. Wires 29b (control wires) connected to the control electrodes 35a and 36a of semiconductor chips 35 and 36 are connected to the wiring board 33d.

[0049] As previously described, the housing 40 is positioned on a metal base plate 46 and includes an outer frame 41 that forms a rectangular shape in plan view. The outer frame 41 of this housing 40 is box-shaped, enclosing the four sides, and forms a storage area 42 in which the first arm portion 20 and the second arm portion 30 described above are housed. External connection terminals 43, 44, and 45 are provided at both the left and right ends of the outer frame 41 in Figure 4. External connection terminal 43 is electrically connected to the wiring board 33a of the second arm portion 30 housed in the outer frame 41. External connection terminal 44 is electrically connected to the wiring board 23a of the first arm portion 20 housed in the outer frame 41. External connection terminal 45 is electrically connected to the wiring board 23b of the first arm portion 20 housed in the outer frame 41. Therefore, a positive terminal is connected to external connection terminal 43 and a negative terminal is connected to external connection terminal 45, and an output is obtained from external connection terminal 44. Although not shown in the figures, the housing 40 is equipped with control terminals on both sides of the outer frame 41 in the longitudinal direction to which control signals are input, and these control terminals are electrically connected to the wiring boards 23c and 33c, respectively. Such a housing 40 includes, for example, external connection terminals 43, 44, and 45 and is constructed by injection molding using a thermoplastic resin. Examples of such resins include polyphenylene sulfide (PPS), polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, polyamide (PA) resin, or acrylonitrile butadiene styrene (ABS) resin.

[0050] The external connection terminals 43, 44, and 45 described above are made of a material with excellent conductivity. Such materials include, for example, copper, aluminum, nickel, or alloys containing at least one of these. The surfaces of the external connection terminals 43, 44, and 45 may be plated. Examples of materials used in this plating process include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0051] Furthermore, the joining member 27 described above is solder. The solder is the same as in the first embodiment. Also, when joining the insulating circuit boards 21, 31 and the metal base plate 46, the joining member 27 may be silver solder.

[0052] Furthermore, the wires 28, 28a, 28b, 29a, and 29b described above are mainly composed of materials with excellent conductivity. Such materials are, for example, gold, copper, aluminum, or alloys containing at least one of these. Preferably, the wires 28, 28a, 28b, 29a, and 29b may be aluminum alloys containing trace amounts of silicon. The diameter of the wires 28, 28a, and 28b (main current wires) is, for example, 200 μm or more and 500 μm or less. The diameter of the wires 29a and 29b (control wires) is, for example, 100 μm or more and 400 μm or less. The wires 28, 28a, and 28b (main current wires) and the wires 29a and 29b (control wires) may have the same diameter.

[0053] The metal base plate 46 has a rectangular shape in plan view. The front surface of the metal base plate 46 is joined to the back surfaces of the insulating circuit board 21 of the first arm portion 20 and the insulating circuit board 31 of the second arm portion 30 by a joining member 27. The housing 40 is also joined to the metal base plate 46 on all four sides of its outer periphery by adhesive members (not shown). Such a metal base plate 46 is mainly composed of a material with excellent thermal conductivity. Such a material is, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these.

[0054] The sealing member 47 comprises a thermosetting resin and a filler contained in the thermosetting resin. Examples of thermosetting resins include epoxy resin, phenolic resin, and maleimide resin. Examples of fillers include glass, silicon dioxide, aluminum oxide, boron nitride, or aluminum nitride. An example of such a sealing member 47 includes an epoxy resin and a filler. At least one of the fillers described above is used as the filler. Alternatively, the sealing member 47 may be a silicone gel.

[0055] Furthermore, a cooler (not shown) may be attached to the back surface of the metal base plate 46 of such a semiconductor device 10 via a heat conductive member to improve heat dissipation.

[0056] Next, the circuit configuration realized in such a semiconductor device 10 will be explained using Figures 4 and 6. Figure 6 is an equivalent circuit diagram of the semiconductor device of the second embodiment. The semiconductor device 10 is configured with semiconductor chips 25, 26, 35, 36, wiring boards 23a to 23d, 33a to 33d, and wires 28a, 28b, 29a, 29b to form the inverter circuit shown in Figure 6.

[0057] The inverter circuit includes a first arm section 20 and a second arm section 30. The first arm section 20 (lower arm) is composed of semiconductor chips 25, 26, wiring boards 23a to 23d, and wires 28a and 28b. The second arm section 30 (upper arm) is composed of semiconductor chips 35, 36 and wiring boards 33a to 33d.

[0058] The semiconductor device 10 is equipped with terminals D1 (corresponding to external connection terminal 43), S2 (corresponding to external connection terminal 45), and S1D2 (corresponding to external connection terminal 44). The high-potential terminal of the external power supply is connected to terminal D1, which is the input P terminal, and the low-potential terminal of the external power supply is connected to terminal S2, which is the input N terminal. A load (not shown in the figure) is connected to terminal S1D2, which is the output U terminal of the semiconductor device 10. As a result, the semiconductor device 10 functions as an inverter.

[0059] Next, the method for manufacturing a semiconductor device will be explained using Figure 7. Figure 7 is a flowchart illustrating the method for manufacturing a semiconductor device according to the second embodiment. In manufacturing the semiconductor device 10 shown in Figures 4 and 5, first, a preparation process is carried out to prepare the manufacturing components for the semiconductor device 10 (step S1). The manufacturing components prepared here include, for example, semiconductor chips 25, 26, 35, and 36, insulating circuit boards 21 and 31, and a housing 40. In addition, equipment used in the manufacturing of the semiconductor device 10 is also prepared. The equipment includes, for example, a soldering furnace, a bonding apparatus, and a dispenser apparatus. Any other necessary equipment not listed here will also be prepared.

[0060] Next, a first bonding process is performed to bond semiconductor chips 25, 26 and semiconductor chips 35, 36 to insulating circuit boards 21 and 31 (step S2). Semiconductor chips 25, 26 are placed on the wiring board 23a of insulating circuit board 21 via solder sheets. Alternatively, solder paste may be applied instead of solder sheets. The insulating circuit board 21 and semiconductor chips 25, 26 are then heated in a soldering furnace. The solder sheets melt, and the insulating circuit board 21 and semiconductor chips 25, 26 are bonded by the bonding member 27. Similarly, semiconductor chips 35, 36 are bonded to insulating circuit board 31 by the bonding member 27. The semiconductor chips 25, 26 have one side 25a1, 26a1 on the control electrode 25a, 26a side, and the other side 25b1, 26b1 on the output electrode 25b, 26b side that is opposite to the other side 25a1, 26a1. Similarly, semiconductor chips 35 and 36 also have one side 35a1, 36a1 and the other side 35b1, 36b1.

[0061] Next, a wiring process is performed in which wires are used to connect the semiconductor chips 25, 26 and the insulating circuit board 21, and the semiconductor chips 35, 36 and the insulating circuit board 31 (step S3). Here, wire bonding is performed between the output electrodes 25b, 26b of the semiconductor chips 25, 26 and the output electrodes 35b, 36b of the semiconductor chips 35, 36 and the insulating circuit board 31 using a bonding apparatus. In addition, the wiring boards 23a, 23b and the wiring board 33b are connected with wires 28. This connection will be explained using Figure 8. Figure 8 is a plan view of the arm portion included in the semiconductor device of the second embodiment. Figure 8(A) shows an enlarged plan view of the first arm portion 20, and Figure 8(B) shows an enlarged plan view of the second arm portion 30. However, in Figure 8, the wiring boards 23c, 23d, 33c, and 33d are not shown.

[0062] As shown in Figure 8(A), the first arm portion 20 includes a rectangular insulating plate 22 in plan view, wiring boards 23a and 23b formed on the insulating plate 22, and semiconductor chips 25 and 26 arranged on the wiring boards 23a. The second arm portion 30 also includes a rectangular insulating plate 22 in plan view, wiring boards 33a and 33b formed on the insulating plate 22, and semiconductor chips 35 and 36 arranged on the wiring boards 33a.

[0063] The two semiconductor chips 25 and 35 are arranged in a line on the lower (-Y direction) portion of the U-shaped wiring boards 23a and 33a in a plan view, with their control electrodes 25a and 35a facing each other. The two semiconductor chips 26 and 36 are arranged in a line on the upper (+Y direction) portion of the U-shaped wiring boards 23a and 33a in a plan view, with their control electrodes 26a and 36a facing each other. Furthermore, these rows of semiconductor chips 25 and 26 and semiconductor chips 35 and 36 are parallel and face each other. The control electrodes 25a and 26a of semiconductor chips 25 and 26 and semiconductor chips 35 and 36 are arranged in a line in the ±Y direction.

[0064] Furthermore, the wires 28a connect the output electrodes 25b and 26b of the semiconductor chips 25 and 26 to the wiring board 23b of the first wiring region 23a1 along the ±Y direction. Four wires 28a are connected to each of the output electrodes 25b and 26b of one semiconductor chip 25 or 26.

[0065] Similarly, wire 28b connects the output electrodes 35b and 36b of the semiconductor chips 35 and 36 to the wiring board 33b of the second wiring region 33a1 along the ±Y direction. Four wires 28b are connected to each of the output electrodes 35b and 36b of one semiconductor chip 35 or 36.

[0066] In the semiconductor chips 25 and 35 on the left, the four wires 28a and 28b are connected to the output electrodes 25b and 35b on the side furthest from the control electrodes 25a and 35a (the other side 25b1 and 35b1). Of the four wires 28a and 28b, the two wires 28a and 28b furthest from the control electrodes 25a and 35a are connected to the side of the output electrodes 25b and 35b of the semiconductor chips 25 and 35 on the -Y direction side (the side furthest from the opposing semiconductor chips 26 and 25). The remaining two wires 28a and 28b are connected to the side of the output electrodes 25b and 35b of the semiconductor chips 25 and 35 on the +Y direction side (the side closer to the opposing semiconductor chips 26 and 25).

[0067] In the semiconductor chips 25 and 35 on the right, the four wires 28a and 28b are connected to the output electrodes 25b and 35b on the side furthest from the control electrodes 25a and 35a (the other side 25b1 and 35b1). Furthermore, of the four wires 28a and 28b, the two wires 28a and 28b furthest from the control electrodes 25a and 35a are connected to the side of the output electrodes 25b and 35b of the semiconductor chips 25 and 35 on the -Y direction side (the side furthest from the opposing semiconductor chips 26 and 36). The remaining two wires 28a and 28b are connected to the side of the output electrodes 25b and 35b of the semiconductor chips 25 and 35 on the +Y direction side (the side closer to the opposing semiconductor chips 26 and 36).

[0068] In other words, the four wires 28a and 28b are connected to the output electrodes 25b and 35b on the other side 25b1 and 35b1. Furthermore, the four wires 28a and 28b are connected to the output electrodes 25b and 35b with a ±Y offset, half on each side of the center line (of the semiconductor chips 25 and 35 perpendicular to one side 25a1 and 35a1) that passes through the control electrodes 25a and 35a. Note that the connection points of the four wires 28a and 28b to the output electrodes 25b and 35b are just examples. It is preferable that the center of gravity of these connection points is closer to the other side 25b1 and 35b1. Any other connection point is acceptable as long as the center of gravity of such a connection point is in this position.

[0069] In the semiconductor chips 26 and 36 on the left, wires 28a and 28b are connected to the side of the output electrodes 26b and 36b that is furthest from the control electrodes 26a and 36a (the other side 26b1 of semiconductor chip 26 as shown in Figure 9). Of the four wires 28a and 28b, the two wires 28a and 28b furthest from the control electrodes 26a and 36a (the other side 26b1 and 36b1) are connected to the side of the output electrodes 26b and 36b of semiconductor chips 26 and 36 on the +Y side (the side furthest from the opposing semiconductor chips 25 and 35). The remaining two wires 28a and 28b are connected to the side of the output electrodes 26b and 36b of semiconductor chips 26 and 36 on the -Y side (the side closer to the opposing semiconductor chips 25 and 35).

[0070] In the semiconductor chips 26 and 36 on the right, wires 28a and 28b are connected to the side of the output electrodes 26b and 36b that is farther from the control electrodes 26a and 36a (the other side 26b1 and 36b1). Of the four wires 28a and 28b, the two wires 28a and 28b furthest from the control electrodes 26a and 36a are connected to the side of the output electrodes 26b and 36b of the semiconductor chips 26 and 36 on the +Y side (the side farther from the opposing semiconductor chips 25 and 35). The remaining two wires 28a and 28b are connected to the side of the output electrodes 26b and 36b of the semiconductor chips 26 and 36 on the -Y side (the side closer to the opposing semiconductor chips 25 and 35).

[0071] In other words, the four wires 28a and 28b are connected to the output electrodes 26b and 36b on the other side 26b1 and 36b1. Furthermore, the four wires 28a are connected to the output electrodes 26b and 36b with a ±Y offset, half on each side of the center line (of the semiconductor chips 26 and 36 perpendicular to one side 26a1 and 36a1) that passes through the control electrodes 26a and 36a. Note that the connection points of the four wires 28a and 28b to the output electrodes 26b and 36b are just examples. It is preferable that the center of gravity of these connection points is closer to the other side 26b1 and 36b1. Other connection points are also acceptable as long as the position of the center of gravity of such connection points is as described.

[0072] Wire 29a connects the control electrode 25a of semiconductor chip 25 and the control electrode 26a of semiconductor chip 26 in the ±Y direction, and is also connected to the wiring board 23c (see Figure 4) in the -Y direction. Wire 29b connects the control electrode 35a of semiconductor chip 35 and the control electrode 36a of semiconductor chip 36 in the ±Y direction, and is also connected to the wiring board 33d (see Figure 4) in the +Y direction. Wire 28 connects the wiring board 23a of the first arm section 20 and the wiring board 33b of the second arm section 30. Wire 28 connects the wiring board 23b of the first arm section 20 and the wiring board 33b of the second arm section 30 (see Figure 4).

[0073] As described above, wiring is performed on the insulating circuit board 21 to which the semiconductor chips 25 and 26 are bonded, thereby obtaining the first arm portion 20. Similarly, wiring is performed on the insulating circuit board 31 to which the semiconductor chips 35 and 36 are bonded, thereby obtaining the second arm portion 30.

[0074] Next, a second bonding process is performed (step S4) in which the back surfaces of the insulating circuit board 21 of the first arm portion 20 and the insulating circuit board 31 of the second arm portion 30 are bonded to the metal base plate 46. The insulating circuit board 21 of the first arm portion 20 and the insulating circuit board 31 of the second arm portion 30 are placed on the metal base plate 46 via solder. External connection terminals 43, 44, and 45 are also placed on the insulating circuit boards 21 and 31 via solder. Then, heating is performed. As each solder melts, the bonding member 27 that bonds the insulating circuit board 21 and semiconductor chips 25 and 26, and the insulating circuit board 31 and semiconductor chips 35 and 36, remelts. Furthermore, the wires 28a, 28b, 29a, and 29b included in the first arm portion 20 and the second arm portion 30 undergo thermal expansion. Here, the semiconductor chips 25 and 26 and semiconductor chips 35 and 36 after step S4 will be explained using Figures 9 and 10. Figures 9 and 10 are cross-sectional views of the arm portion included in the semiconductor device of the second embodiment. Figures 9(A) and 9(B) are cross-sectional views along the dashed lines Y1-Y1 and Y2-Y2 in Figures 8(A) and 8(B). Figures 10(A) and 10(B) are cross-sectional views along the dashed lines X1-X1 and X2-X2 in Figure 8(A).

[0075] Here, semiconductor chips 25 and 26 will be described. Note that Figure 9(A) shows semiconductor chip 26. Semiconductor chip 25 also includes one side 25b1 and one side 25a1, similar to semiconductor chip 26 (see Figure 10). As in step S3, in semiconductor chips 25 and 26, wire 28a is connected to the side of the output electrodes 25b and 26b that is farther from the control electrodes 25a and 26a (the side with the other side 25b1 and 26b1), and wire 29a is connected to the control electrodes 25a and 26a. In addition, the wiring board 23a to which semiconductor chips 25 and 26 are joined and the wiring boards 23b and 23d are located on the same plane.

[0076] The height from the connection point of the output electrodes 25b and 26b of the wire 28a connecting these to a reference plane horizontal to the wiring board 23a passing through the top of the wire 28a is lower than the height from the connection point of the wire 28a to the said reference plane. Therefore, as described in the first embodiment, the output electrode 25b and 26b side of the semiconductor chips 25 and 26 is pulled upward. Similarly, the control electrode 25a and 26a side of the wire 29a is also pulled upward.

[0077] The diameter of wire 28a is greater than the diameter of wire 29a. Furthermore, the connection density of wires 28a and 29a is greater on the other side 25b1,26b1 than on the other side 25a1,26a1. Connection density refers to the number of wire connections per unit area. As a result, the semiconductor chips 25 and 26 are pulled up by a greater force on the other side 25b1,26b1 than on the other side 25a1,26a1. Therefore, the semiconductor chips 25 and 26 are tilted so that one side 25a1,26a1 is closer to the printed circuit board 23a,23b than the other side 25b1,26b1 (Figure 9(A) shows the case of semiconductor chip 26).

[0078] Furthermore, the four wires 28a are connected in pairs to both sides of the output electrodes 25b and 26b of the semiconductor chips 25 and 26 that are parallel to the ±X directions. As a result, the semiconductor chips 25 and 26, with their other sides 25b1 and 26b1 lifted, are tilted so as to be approximately parallel to the wiring board 23a when viewed in the X direction, as shown in Figure 10.

[0079] The semiconductor chips 35 and 36, like the semiconductor chips 25 and 26, are tilted such that one side 35a1 and 36a1 is closer to the wiring board 33a and 33b than the other side 35b1 and 36b1 (Figure 9(B) shows the case of semiconductor chip 36). Furthermore, the semiconductor chips 35 and 36, whose other sides 35b1 and 36b1 are lifted, are tilted so as to be approximately parallel to the wiring board 33a when viewed in the X direction.

[0080] Furthermore, in order for the semiconductor chips 25, 26, 35, and 36 to be tilted so as to be approximately parallel to the wiring board 23a when viewed from the X direction, for example, in semiconductor chip 25, the four wires 28a may be connected in a straight line along the center line (of the semiconductor chip 25 perpendicular to one side 25a1) passing through the control electrode 25a of the output electrode 25b. Alternatively, for example, in the semiconductor chip 25 on the left, the two wires 28a furthest from the control electrodes 25a and 35a may be connected to the side of the output electrode 25b of the semiconductor chip 25 on the +Y direction side (closer to the opposing semiconductor chip 26), and the remaining two wires 28a may be connected to the side of the output electrode 25b of the semiconductor chip 25 on the -Y direction side (away from the opposing semiconductor chip 26). The same applies to semiconductor chips 26, 35, and 36.

[0081] In this tilted state, the semiconductor chips 25 and 26 are joined to the wiring board 23a by the bonding member 27. Similarly, the tilted semiconductor chips 35 and 36 are joined to the wiring board 33a by the bonding member 27.

[0082] In addition, the insulating circuit boards 21 and 31 are also joined to the metal base plate 46 by the joining member 27. Furthermore, in step S4, the external connection terminals 43, 44, and 45 are also joined to the wiring boards 23a, 23b, and 33a by the joining member 27.

[0083] Next, a storage process is performed in which the first arm portion 20 and the second arm portion 30, which are joined to the metal base plate 46, are housed in the housing 40 (step S5). An adhesive member is applied to the lower end surface of the housing 40 and attached to the outer circumference of the metal base plate 46. As a result, the first arm portion 20 and the second arm portion 30 are housed in the housing 40 on the metal base plate 46 (see Figure 5). The adhesive member is heat-cured by heating, thereby fixing the metal base plate 46 and the housing 40 together.

[0084] Next, a sealing process is performed in which the housing 40 is sealed with a sealing member 47 (step S6). The sealing member 47 is filled into the opening of the housing 40 to seal the first arm portion 20 and the second arm portion 30. At this time, the sealing member 47 is filled to a height that completely seals the wires 28, 28a, 28b, 29a, and 29b of the first arm portion 20 and the second arm portion 30. As a result, the semiconductor device 10 shown in Figures 4 and 5 is obtained.

[0085] In the semiconductor device 10 obtained in this manner, the semiconductor chips 25, 26, 35, and 36 are inclined such that one side 25a1, 26a1, 35a1, and 36a1 are closer to the wiring board 23a, and 33a than the other side 25b1, 26b1, 35b1, and 36b1, resulting in different thicknesses of the bonding members 27. Therefore, the stress generated in the bonding members 27 between the wiring board 23a, and 33a and the semiconductor chips 25, 26, 35, and 36 due to the heat generated in response to the operation of the semiconductor device 10 is buffered. Consequently, the occurrence of cracks in the bonding members 27 is reduced, and even if cracks do occur, their propagation is suppressed. As a result, a decrease in the reliability of the semiconductor device 10 is prevented.

[0086] [Modification 2-1] In Modification 2-1 of the second embodiment, the arrangement direction of the semiconductor chips 25, 26, 35, and 36 differs from that in Figures 4 and 5. This case will be explained using Figures 11 and 12. Figure 11 is a plan view of the arm portion included in the semiconductor device of Modification 2-1 of the second embodiment, and Figure 12 is a cross-sectional view of the arm portion included in the semiconductor device of Modification 2-1 of the second embodiment. Note that Figure 12 is a cross-sectional view along the dashed line XX in Figure 11. Furthermore, in Modification 2-1, the first arm portion 20a will be described, but in the second arm portion, semiconductor chips 35 and 36 are arranged in the same way as in the first arm portion 20a.

[0087] In the first arm section 20a, the semiconductor chips 25 and 26 are positioned relative to the wiring board 23a with their control electrodes 25a and 26a (one side 25a1 and 26a1) facing outwards. Specifically, the control electrode 25a of semiconductor chip 25 (one side 25a1 and 26a1) faces the -Y direction, and the control electrode 26a of semiconductor chip 26 faces the +Y direction. In addition, the output electrodes 25b and 26b (the other sides 25b1 and 26b1) of semiconductor chips 25 and 26 are positioned facing inwards.

[0088] Furthermore, wire 28a connects the output electrodes 25b and 26b of the semiconductor chips 25 and 26 to the wiring board 23b of the first wiring region 23a1 along the ±Y direction, respectively. Six wires 28a are connected to each of the output electrodes 25b and 26b of one semiconductor chip 25 or 26. In addition, wire 28b is connected to the control electrodes 25a and 26a of the semiconductor chips 25 and 26 and is routed outwards (in the ±Y direction), respectively.

[0089] In the semiconductor chip 25, wire 28a is connected to the output electrode 25b on the side furthest from the control electrode 25a (towards the other side 25b1). In particular, of the six wires 28a, the four wires 28a furthest from the control electrode 25a are connected to the region of the output electrode 25b of the semiconductor chip 25 on the +Y side (closer to the other side 25b1).

[0090] Furthermore, in the semiconductor chip 26, the wire 28a is connected to the output electrode 26b on the side furthest from the control electrode 26a (towards the other side 26b1). In particular, of the six wires 28a, the four wires 28a furthest from the control electrode 26a are connected to the region of the semiconductor chip 26 on the -Y direction side (closer to the other side 26b1) of the output electrode 26b.

[0091] In other words, the six wires 28a have a higher connection density on the other side 25b1,26b1 of the output electrodes 25b,26b of the semiconductor chips 25,26 than on the other side 25a1,26a1. As a result, the semiconductor chips 25,26 are pulled up more by the other side 25b1,26b1 than by the other side 25a1,26a1. Consequently, the semiconductor chips 25,26 tilt so that one side 25a1,26a1 is closer to the wiring board 23a than the other side 25b1,26b1 (see Figure 12).

[0092] Furthermore, the six wires 28a are connected equally to the output electrodes 25b and 26b on the semiconductor chips 25 and 26, with the center line (parallel to the ±Y direction) passing through the control electrodes 25a and 26a (of the semiconductor chips 25 and 26 perpendicular to one side 25a1 and 26a1) in between. Moreover, the six wires 28a are connected to the output electrodes 25b and 26b in a symmetrical manner with respect to the said center line. As a result, the semiconductor chips 25 and 26, with the output electrode 25b and 26b side lifted, are stably pulled up and tilted so as to be approximately parallel to the wiring board 23a when viewed in the X direction.

[0093] [Example 2-2] Modification 2-2 of the second embodiment involves performing the bonding steps S2 and S4 of the flowchart in Figure 7 simultaneously, and will be explained using Figure 13. Figure 13 is a flowchart of the method for manufacturing a semiconductor device according to Modification 2-2 of the second embodiment. In Modification 2-2, the explanation of steps similar to those in the flowchart in Figure 7 will be simplified or omitted.

[0094] First, a preparation process is carried out to prepare the manufacturing components for the semiconductor device 10, similar to step S1 in Figure 7 (step S1a). Next, a bonding process is carried out to bond the back surfaces of the insulating circuit board 21 and the insulating circuit board 31 to the metal base plate 46, and at the same time, to bond the semiconductor chips 25, 26 and 35, 36 to the insulating circuit board 21 and the insulating circuit board 31 (step S2a).

[0095] Insulated circuit boards 21 and 31 are placed on a metal base plate 46 via solder. Furthermore, semiconductor chips 25 and 26 are placed on the wiring board 23a of the insulating circuit board 21 via solder. These are heated in a soldering furnace. The solder melts, and the insulating circuit board 21 is joined to the metal base plate 46 by the joining member 27, and the semiconductor chips 25 and 26 are joined to the insulating circuit board 21 by the joining member 27. Similarly, the insulating circuit board 31 is joined to the metal base plate 46 by the joining member 27, and the semiconductor chips 35 and 36 are joined to the insulating circuit board 31 by the joining member 27. The orientation of the semiconductor chips 25 and 26 and semiconductor chips 35 and 36 at this time is the same as in Figure 4.

[0096] Next, a wiring process is performed in which wires are used to connect the semiconductor chips 25, 26 and the insulating circuit board 21, and the semiconductor chips 35, 36 and the insulating circuit board 31 (step S3a). The wiring here is done in the same manner as in step S3 of Figure 7. This completes the formation of the first arm portion 20 and the second arm portion 30.

[0097] Next, a storage process is performed in which the first arm portion 20 and the second arm portion 30, which are joined to the metal base plate 46, are housed in the housing 40 (step S5a). Here, similar to step S5 in the flowchart of Figure 7, an adhesive member is applied to the lower end surface of the housing 40 and attached to the outer periphery of the metal base plate 46. As a result, the first arm portion 20 and the second arm portion 30 are housed in the housing 40 on the metal base plate 46 (see Figure 5).

[0098] As previously described, the housing 40 is fixed to the metal base plate 46 by heat curing of the adhesive member. Due to the heating for heat curing, the semiconductor chips 25, 26 and 35, 36 tilt as explained using Figures 9 and 10 in step S4 of the flowchart in Figure 7. In step S5a, the external connection terminals 43, 44, and 45 provided on the housing 40 are also joined to the wiring boards 23a, 23b, and 33a by the joining member 27.

[0099] Next, a sealing process is performed in which the inside of the housing 40 is sealed with a sealing member 47 (step S6a). Similar to step S6 in the flowchart of Figure 7, the sealing member 47 is filled through the opening of the housing 40 to seal the first arm portion 20 and the second arm portion 30. As a result, the semiconductor device 10 shown in Figures 4 and 5 is obtained.

[0100] [Third Embodiment] A semiconductor device of the third embodiment will be described with reference to Figures 14 and 15. Figure 14 is a plan view of the semiconductor device of the third embodiment. Figure 15 is a plan view of the semiconductor unit containing the semiconductor device of the third embodiment.

[0101] The semiconductor device 10a comprises semiconductor units 50a, 50b, and 50c, and a metal base plate 70 on which the semiconductor units 50a, 50b, and 50c are arranged. Furthermore, it includes a housing 60 provided on the metal base plate 70, which houses the semiconductor units 50a, 50b, and 50c and is sealed with a sealing member 66 (see Figure 15). The sealing member 66 is the same as the sealing member 47 in the second embodiment. The semiconductor units 50a, 50b, and 50c all have the same configuration. When not distinguished, the semiconductor units 50a, 50b, and 50c will be described as semiconductor unit 50. Details of semiconductor unit 50 will be described later.

[0102] First, the enclosure 60 includes an outer frame 61, first connection terminals 62a, 62b, 62c, second connection terminals 63a, 63b, 63c, U-phase output terminal 64a, V-phase output terminal 64b, W-phase output terminal 64c, and control terminals 65a, 65b, 65c.

[0103] The outer frame 61 is roughly rectangular in plan view and is surrounded on all four sides by outer walls 61a, 61b, 61c, and 61d. The outer walls 61a and 61c are the longer sides of the outer frame 61, while the outer walls 61b and 61d are the shorter sides. The corners where the outer walls 61a, 61b, 61c, and 61d are connected do not necessarily have to be right angles and may be rounded off as shown in Figure 14. Fastening holes 61i that penetrate the outer frame 61 are formed at each corner of the front surface of the outer frame 61. In addition, fastening holes 61i that penetrate the outer frame 61 are formed on the outer wall 61a and 61c sides of the outer frame 61.

[0104] The outer frame 61 includes unit storage sections 61e, 61f, and 61g along the outer walls 61a and 61c on its front surface. The unit storage sections 61e, 61f, and 61g are rectangular in shape when viewed from above. Semiconductor units 50a, 50b, and 50c are housed in the unit storage sections 61e, 61f, and 61g, respectively.

[0105] In a plan view, the outer frame 61 is provided with first connection terminals 62a, 62b, 62c and second connection terminals 63a, 63b, 63c on the outer wall 61a side, flanking the unit storage sections 61e, 61f, 61g. Furthermore, the outer wall 61c side is provided with U-phase output terminal 64a, V-phase output terminal 64b, and W-phase output terminal 64c, respectively. In addition, nuts are housed in the lower part of the openings of the first connection terminals 62a, 62b, 62c and the second connection terminals 63a, 63b, 63c on the outer frame 61, facing the openings. Similarly, nuts are housed in the lower part of the openings of the U-phase output terminal 64a, V-phase output terminal 64b, and W-phase output terminal 64c on the outer frame 61, facing the openings. Furthermore, in a plan view, the outer frame 61 is provided with control terminals 65a, 65b, and 65c along the +X-direction sides of the unit housing sections 61e, 61f, and 61g, respectively. In this case, the control terminals 65a, 65b, and 65c are each provided in two separate units.

[0106] Such an outer frame 61 includes first connection terminals 62a, 62b, 62c, second connection terminals 63a, 63b, 63c, U-phase output terminal 64a, V-phase output terminal 64b, W-phase output terminal 64c, and control terminals 65a, 65b, 65c, and is integrally molded by injection molding using thermoplastic resin. This constitutes the housing 60. The material of the housing 60 may be the same as that of the housing 40 in the second embodiment.

[0107] Furthermore, the first connection terminals 62a, 62b, 62c, the second connection terminals 63a, 63b, 63c, the U-phase output terminal 64a, the V-phase output terminal 64b, the W-phase output terminal 64c, and the control terminals 65a, 65b, 65c are made of a metal with excellent conductivity. Such a metal may be the same as that used for the external connection terminals 43-45 in the second embodiment.

[0108] As shown in Figure 15, the semiconductor unit 50 includes an insulating circuit board 51, semiconductor chips 25, 26, and lead frames 57, 58, 59a, 59b, 59c. The insulating circuit board 51 includes an insulating plate 52, wiring boards 53a1, 53a2, 53a3, and a metal plate 54 (see Figure 16). Such an insulating circuit board 51 may be made of the same material and thickness as the insulating circuit boards 21, 31 of the second embodiment. The insulating plate 52 and the metal plate 54 are rectangular in plan view. The corners of the insulating plate 52 and the metal plate 54 may be rounded (R-chamfered) or chamfered (C-chamfered). The size of the metal plate 54 is smaller than the size of the insulating plate 52 in plan view and is formed inside the insulating plate 52.

[0109] The wiring boards 53a1, 53a2, and 53a3 are formed on the front surface of the insulating board 52. Wiring board 53a1 occupies half of the area on the +Y side of the front surface of the insulating board 52, from the -X side to the +X side. Wiring board 53a2 occupies half of the area on the -Y side of the front surface of the insulating board 52, from the +X side to just before the -X side. Wiring board 53a3 occupies the area on the front surface of the insulating board 52 enclosed by wiring boards 53a1 and 53a2. Note that wiring boards 53a1, 53a2, and 53a3 are just examples. The number, shape, size, and position of wiring boards 53a1, 53a2, and 53a3 may be appropriately selected as needed.

[0110] The metal plate 54 is formed on the back surface of the insulating plate 52. The metal plate 54 is rectangular in shape. The area of ​​the metal plate 54 in plan view is smaller than the area of ​​the insulating plate 52, but larger than the area of ​​the regions where the wiring boards 53a1, 53a2, and 53a3 are formed. The corners of the metal plate 54 may be rounded (R-chamfered) or chamfered (C-chamfered). The metal plate 54 is smaller than the size of the insulating plate 52 and is formed over the entire surface of the insulating plate 52, excluding the edges.

[0111] As the insulating circuit board 51 having such a configuration, for example, a DCB board, an AMB board, or a resin insulating board may be used. The insulating circuit board 51 may be attached to the front surface of the metal base plate 70 via a bonding member (not shown). Heat generated by the semiconductor chips 25 and 26 can be dissipated by conducting it to the metal base plate 70 via the wiring boards 53a1 and 53a2, the insulating plate 52, and the metal plate 54.

[0112] The semiconductor chips 25 and 26 include control electrodes 25a and 26a on one side 25a1 and 26a1 of their front surface and output electrodes 25b and 26b on the other side 25b1 and 26b1, as described in the second embodiment. However, the semiconductor chips 25 and 26 of the third embodiment include multiple control electrodes 25a and 26a. The back surfaces of the semiconductor chips 25 and 26 are joined to the wiring boards 53a2 and 53a3, respectively, by a bonding member 27a (see Figure 16). The bonding member 27a is solder as described in the first and second embodiments.

[0113] Lead frames 57, 58, 59a, 59b, and 59c electrically connect and wire the semiconductor chips 25 and 26 and the wiring boards 53a1, 53a2, and 53a3. The semiconductor unit 50 may be a device that constitutes a single-phase inverter circuit. Lead frame 57 directly connects the output electrode 25b of the semiconductor chip 25 to the wiring board 53a3. Lead frame 58 directly connects the output electrode 26b of the semiconductor chip 26 to the wiring board 53a2. Lead frame 59a is directly connected to the wiring board 53a3. Lead frame 59b is directly connected to the wiring board 53a2. Lead frame 59c is directly connected to the wiring board 53a1.

[0114] When such semiconductor units 50 are housed in unit housings 61e, 61f, and 61g, the other end of the lead frame 59a may be an output terminal of the semiconductor unit 50. That is, the other end of the lead frame 59a is connected to the U-phase output terminal 64a, the V-phase output terminal 64b, and the W-phase output terminal 64c, respectively.

[0115] The other end of lead frame 59b may be the positive side input terminal (P terminal). The other end of lead frame 59c may be the negative side input terminal (N terminal). That is, the other end of lead frame 59c is connected to the first connection terminals 62a, 62b, and 62c, respectively. The other end of lead frame 59b is connected to the second connection terminals 63a, 63b, and 63c, respectively. In addition, the control electrodes 25a and 26a of semiconductor chips 25 and 26 are directly connected to the control terminals 65a, 65b, and 65c by wires.

[0116] Such lead frames 57, 58, 59a, 59b, and 59c are made of a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or alloys containing at least one of these. In addition, the surfaces of the lead frames 57, 58, 59a, 59b, and 59c may be plated to improve corrosion resistance. The plating material used in this case is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy.

[0117] The lead frames 57, 58, 59a, 59b, and 59c are joined to the wiring boards 53a1, 53a2, and 53a3 by a joining member (not shown). The joining member may be solder or sintered metal as described above. Alternatively, the lead frames 57, 58, 59a, 59b, and 59c may be directly joined to the wiring boards 53a1, 53a2, and 53a3 by, for example, laser welding or ultrasonic welding. The lead frames 57 and 58 are joined to the output electrodes 25b and 26b of the semiconductor chips 25 and 26 via a joining member 27b (see Figure 16). The joining member 27b is solder, similar to the joining member 27a.

[0118] The metal base plate 70 has a rectangular shape when viewed from above. Semiconductor units 50a, 50b, and 50c are joined to the upper surface of the metal base plate 70 by joining members. Furthermore, the housing 60 is joined to the metal base plate 70, housing the semiconductor units 50a, 50b, and 50c. A cooling device (not shown) may be placed on the lower surface of the metal base plate 70. In addition, multiple fins may be formed on the lower surface of the metal base plate 70. Furthermore, a flow path for a refrigerant may be formed inside the metal base plate 70.

[0119] Next, the lead frames 57 and 58 included in the semiconductor unit 50 will be described with reference to Figures 16 and 17. Figures 16 and 17 are cross-sectional views of the semiconductor device according to the third embodiment. Note that Figures 16 and 17 are cross-sectional views along the dashed lines Y1-Y1 and Y2-Y2 in Figure 14, respectively.

[0120] The lead frame 57 includes an electrode junction 57a, a first vertical linkage 57b, a horizontal linkage 57c, a second vertical linkage 57d, and a leg portion 57e. Each part of the lead frame 57 is flat.

[0121] The electrode junction 57a ​​is joined to the output electrode 25b of the semiconductor chip 25 by a joining member 27b. The electrode junction 57a ​​is inclined with respect to the wiring board 53a2 to which the semiconductor chip 25 is joined. That is, the electrode junction 57a ​​is inclined such that one side 25a1 is closer to the semiconductor chip 25 than the other side 25b1.

[0122] The lower end of the first vertical linkage portion 57b is connected to the output electrode 25b side end of the electrode junction portion 57a ​​bonded to the semiconductor chip 25, and its upper end extends vertically upward relative to the wiring board 53a2. One end of the horizontal linkage portion 57c is connected to the upper end of the first vertical linkage portion 57b, and the other end extends in the -X direction, forming a horizontal plane with respect to the wiring board 53a2.

[0123] The upper end of the second vertical linkage section 57d is connected to the other end of the horizontal linkage section 57c, and its lower end extends vertically downward toward the wiring board 53a3. The leg section 57e is connected to the lower end of the second vertical linkage section 57d and joined to the wiring board 53a3.

[0124] Furthermore, the lead frame 58 includes an electrode junction 58a, a vertical linkage 58b, a horizontal linkage 58c, a second vertical linkage 58e, and leg portions 58e (see also Figure 15). Each part of the lead frame 58 is also flat.

[0125] The electrode junction 58a is joined to the output electrode 26b of the semiconductor chip 26 by a joining member 27b. The electrode junction 58a is inclined with respect to the wiring board 53a1 to which the semiconductor chip 26 is joined. That is, the electrode junction 58a is inclined such that one side 26a1 is closer to the semiconductor chip 26 than the other side 26b1.

[0126] The lower end of the first vertical linkage portion 58b is connected to the side of the electrode joint portion 58a bonded to the semiconductor chip 26 on the semiconductor chip 25 side, and its upper end extends vertically upward relative to the wiring board 53a1. One end of the horizontal linkage portion 58c is connected to the upper end of the first vertical linkage portion 58b, and the other end extends in the -X direction, forming a horizontal plane with respect to the wiring board 53a1.

[0127] The second vertical linkage section is hidden by the horizontal linkage section 58c in Figure 15 and hidden by the first vertical linkage section 58b in Figure 17 and is therefore not shown. The second vertical linkage section connects the horizontal linkage section 58c and the leg section 58e, similar to the second vertical linkage section 57d of the lead frame 57. The upper end of the second vertical linkage section is connected to the other end of the horizontal linkage section 58c, and its lower end extends vertically downward toward the wiring board 53a1. The leg section 57e is connected to the lower end of the second vertical linkage section 57d and joined to the wiring board 53a3.

[0128] A semiconductor device 10a including such lead frames 57, 58 can also be manufactured according to the flowchart in Figure 7. In this case as well, the preparation process and the first bonding process in steps S1 and S2 of Figure 7 are performed. Next, in the wiring process in step S3, the lead frames 57, 58, 59a, 59b, and 59c are bonded to the semiconductor chips 25, 26 and the insulating circuit board 51. In particular, the electrode bonding portions 57a and 58a of the lead frames 57 and 58 are bonded to the output electrodes 25b and 26b of the semiconductor chips 25 and 26 by bonding members 27b. The leg portions 57e and 58e of the lead frames 57 and 58 are also bonded to the wiring boards 53a3 and 53a2 by bonding members 27b.

[0129] Next, the second joining process of step S4 is performed. The insulating circuit board 21 of the first arm portion 20 and the insulating circuit board 31 of the second arm portion 30 are placed on the metal base plate 46 via solder and heated. As the solder melts, the joining member 27a that joins the insulating circuit board 21 and the semiconductor chips 25 and 26 remelts. Furthermore, the joining member 27b that joins the output electrodes 25b and 26b of the semiconductor chips 25 and 26 and the electrode joints 57a and 58a of the lead frames 57 and 58 remelts. At this time, the electrode joints 57a and 58a of the lead frames 57 and 58 are inclined such that one side 25a1 and 26a1 is closer to the semiconductor chips 25 and 26 than the other side 25b1 and 26b1. Therefore, the semiconductor chips 25 and 26 also tilt along the inclined electrode joints 57a and 58a, along with the remelted joining members 27a and 27b. In this tilted state, the semiconductor chips 25 and 26 are joined to the wiring boards 53a3 and 53a1 by the bonding member 27a, as shown in Figures 16 and 17. After this, the semiconductor device 10a is obtained through steps S5 and S6.

[0130] In the semiconductor device 10a obtained in this manner, the semiconductor chips 25 and 26 are tilted such that one side 25a1 and 26a1 is closer to the wiring board 53a3 and 53a1 than the other side 25b1 and 26b1, resulting in different thicknesses of the bonding member 27a. Therefore, the stress generated in the bonding member 27a between the wiring board 53a3 and 53a1 and the semiconductor chips 25 and 26 due to the heat generated in response to the operation of the semiconductor device 10a is buffered. Consequently, the occurrence of cracks in the bonding member 27a is reduced, and even if cracks do occur, their propagation is suppressed. As a result, a decrease in the reliability of the semiconductor device 10a is prevented.

[0131] Furthermore, the electrode joints 57a and 58a of the lead frames 57 and 58 may have different thicknesses, with only the back side being inclined and the front side being substantially parallel to the wiring boards 53a3 and 53a1, rather than being inclined overall. In other words, in order to join the semiconductor chips 25 and 26 as described above, the electrode joints 57a and 58a included in the lead frames 57 and 58 only need to be closer to the wiring boards 53a3 and 53a1 as the portion on one side 25a1 and 26a1 is closer than the portion on the other side 25b1 and 26b1. The following modified example 3-1 describes the case in which the flat electrode joints 57a and 58a included in the lead frames 57 and 58 are not inclined.

[0132] [Modification 3-1] The lead frame 57 of Modification 3-1 of the third embodiment will be described with reference to Figures 18 and 19. Figure 18 is a diagram of the lead frame included in the semiconductor device of Modification 3-1 of the third embodiment. Figure 19 is a cross-sectional view of the semiconductor device of Modification 3-1 of the third embodiment. Figure 18(A) is a side view of the lead frame 57, and Figure 18(B) is a rear view (bottom view) of the lead frame 57. Figure 19 is a cross-sectional view taken at the same position as in Figure 17.

[0133] The lead frame 57 shown in Figure 18, like the lead frame 57 shown in Figures 15 and 16, includes an electrode joint 57a, a first vertical linkage 57b, a horizontal linkage 57c, a second vertical linkage 57d, and a leg portion 57e. Each part of the lead frame 57 is flat.

[0134] The electrode junction 57a ​​of the lead frame 57 shown in Figure 18 is substantially parallel to the wiring board 53a2. Furthermore, a control-side projection 57f1 and an output-side projection 57f2 are formed on the back surface of the electrode junction 57a ​​of the lead frame 57 shown in Figure 18. The height (thickness) of the output-side projection 57f2 is greater (thicker) than the height (thickness) of the control-side projection 57f1. The control-side projection 57f1 is formed on one side 25a1, 26a1 on the back surface of the electrode junction 57a. The output-side projection 57f2 is formed on the other side 25b1, 26b1 on the back surface of the electrode junction 57a. The control-side projection 57f1 and the output-side projection 57f2 are columnar in shape. Columnar shape can be a rectangular prism, cylindrical shape, or triangular prism shape. It is not limited to a columnar shape; it may also be hemispherical. Furthermore, Figure 18 only shows the case where two control-side protrusions 57f1 and two output-side protrusions 57f2 are formed. There may be one control-side protrusion 57f1 or three or more output-side protrusions 57f2. Also, the control-side protrusions 57f1 and output-side protrusions 57f2 only need to be formed biasedly on one side 25a1,26a1 and the other side 25b1,26b1 of the back surface of the electrode junction 57a, respectively. For this reason, there may be two or more rows, not just one row as shown in Figure 18.

[0135] Although not shown in the diagram, the electrode joint portion 58a of the lead frame 58 is also substantially parallel to the wiring board 53a1. Furthermore, similar to the electrode joint portion 57a, control-side protrusions and output-side protrusions are formed on the back surface of the electrode joint portion 58a.

[0136] Even when using such a lead frame 57, when the bonding members 27a and 27b are remelted in the second bonding step S4, the semiconductor chip 25 is tilted along with the remelted bonding members 27a and 27b by the control-side projection 57f1 and output-side projection 57f2 of the electrode bonding portion 57a. In this tilted state, as shown in Figure 19, the semiconductor chip 25 is bonded to the wiring board 53a3 by the bonding member 27a. The lead frame 58 is similarly bonded to the semiconductor chip 26.

[0137] Therefore, even in the semiconductor device 10a including lead frames 57, 58, the semiconductor chips 25, 26 are tilted such that one side 25a1, 26a1 is closer to the wiring board 53a3, 53a1 than the other side 25b1, 26b1, resulting in different thicknesses of the bonding member 27a. As a result, the stress generated in the bonding member 27a between the wiring board 53a3, 53a1 and the semiconductor chips 25, 26 due to the heat generated in response to the operation of the semiconductor device 10a is buffered. Consequently, the occurrence of cracks in the bonding member 27a is reduced, and even if cracks do occur, their propagation is suppressed. As a result, a decrease in the reliability of the semiconductor device 10a is prevented. [Explanation of Symbols]

[0138] 1,10,10a Semiconductor device 2a,23a~23d,33a~33d,53a1,53a2,53a3 Wiring board 2b Main current conductor 3,27,27a,27b Joining members 4, 25, 26, 35, 36 semiconductor chips 4a Front side 4a1 Area 1 4a2 2nd area 4b1,25a1,26a1,35a1,36a1 One side 4b2, 25b1, 26b1, 35b1, 36b1 The other side 4b3,4b4 side 4c1 control electrode 4c2 Main electrode 5,6,28,28a,28b,29a,29b wire 5a1 First connection point 5a2 Second connection point 5b Reference connection point 20,20a First arm section 21, 31, 51 Insulated circuit board 22, 32, 52 Insulating board 23a1 1st wiring area 33a1 2nd wiring area 24,34,54 metal plate 25a, 26a, 35a, 36a control electrodes 25b,26b,35b,36b output electrode 30 Second Arm Section 40 cabinets 41 Outer frame 42 Storage Areas 43, 44, 45 External connection terminals 46 Metal base plate 47,66 Sealing member 50, 50a, 50b, 50c Semiconductor Unit 57, 58, 59a, 59b, 59c Lead Frames 57a,58a Electrode joint 57b, 58b First vertical linkage section 57d Second vertical linkage section 57c, 58c Horizontal linkage section 57e,58e Legs 57f1 Control side projection 57f2 Output side protrusion 60 cabinets 61 Outer frame 61a, 61b, 61c, 61d Exterior walls 61e, 61f, 61g Unit Storage Section 61i fastening hole 62a, 62b, 62c First connection terminal 63a, 63b, 63c Second connection terminal 64a U-phase output terminal 64b V phase output terminal 64c W-phase output terminal 65a, 65b, 65c control terminals 70 Metal base plate

Claims

1. A semiconductor chip formed of a wide-bandgap semiconductor, having a rectangular shape in plan view, including a control electrode and a main electrode on its front surface, wherein the control electrode is provided in a first region including one side of the front surface, and the main electrode is provided in a second region including the other side opposite to the first side of the front surface, and The back surface of the semiconductor chip is joined to a wiring board via a bonding member, Includes, In the aforementioned joining member, the second thickness on the other side is 1.2 times or more and 2.0 times or less the first thickness on the one side. Semiconductor equipment.

2. The second outward overhang width of the joining member in a direction perpendicular to the other side is longer than the first outward overhang width in a direction perpendicular to the one side. The semiconductor device according to claim 1.

3. The second overhang width is 1.2 times or more and 2.0 times or less the first overhang width. The semiconductor device according to claim 2.

4. A main current wire connected to the main electrode of the semiconductor chip, A control wire connected to the control electrode of the semiconductor chip, The main current conductor connected to the main electrode via the main current wire, A semiconductor device according to any one of claims 1 to 3, further comprising

5. The combined connection density of the main current wire and the control wire to the front surface of the semiconductor chip is greater on the other side than on the other side. The semiconductor device according to claim 4.

6. The main current wire is connected to the other side of the second region. The semiconductor device according to claim 4 or 5.

7. The second height from the second connection point in the second region of the main current wire to the reference plane horizontal to the wiring board passing through the apex of the main current wire is the same as, or lower than, the reference height from the reference connection point of the main current conductor of the main current wire to the reference plane. The semiconductor device according to claim 6.

8. When multiple main current wires are connected, The connection density of the multiple main current wires, including the control wire, is greater on the other side than on the other side. The semiconductor device according to claim 6 or 7.

9. The main current conductor is located at a higher position than the wiring board, The main current wire is connected to one side of the second region. The semiconductor device according to claim 4.

10. The combined connection density of the main current wire and the control wire to the front surface of the semiconductor chip is greater on one side than on the other side. The semiconductor device according to claim 9.

11. The first height from the first connection point in the second region of the main current wire to the reference plane horizontal to the wiring board passing through the apex of the main current wire is higher than the reference height from the reference connection point of the main current conductor of the main current wire to the reference plane. The semiconductor device according to claim 9 or 10.

12. When multiple main current wires are connected, The connection density of the multiple main current wires, including the control wire, is greater on one side than on the other side. A semiconductor device according to any one of claims 9 to 11.

13. The control electrode is provided in the center of one of the sides. Multiple main current wires are connected to the second region in equal halves, with the center line of the semiconductor chip perpendicular to one side in between. The semiconductor device according to any one of claims 4 to 12.

14. The control electrode is provided in the center of one of the sides. The multiple main current wires are connected to the second region in a manner symmetrical with respect to the center line of the semiconductor chip perpendicular to one side. The semiconductor device according to any one of claims 4 to 12.

15. The semiconductor chip further comprises a connection terminal including a flat electrode joint portion bonded to the second region of the semiconductor chip and an upper linking portion connected to the end of the electrode joint portion and extending upward relative to the electrode joint portion, The back surface of the electrode joint of the connection terminal includes a first portion on one side and a second portion on the other side, wherein the first portion is closer to the wiring board than the second portion. The semiconductor device according to any one of claims 1 to 3.

16. The electrode junction of the connection terminal is inclined such that the first portion is closer to the wiring board than the second portion. The semiconductor device according to claim 15.

17. The first portion and the second portion each protrude from the back surface of the electrode joint, The first portion is closer to the wiring board than the second portion. The semiconductor device according to claim 15.

18. The aforementioned semiconductor chip is formed mainly of silicon carbide. A semiconductor device according to any one of claims 1 to 17.

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