Silicon carbide semiconductor equipment

Abstract

To provide a silicon carbide semiconductor device capable of improving breakdown resistance.SOLUTION: Drift layers in an active region 10 and an edge termination region 20 have SJ structures comprising respective first and second parallel pn layers 3a, 3b. An n-type column region 31 and a p-type column region 32 in the first parallel pn layer 3a extend in stripes in a second direction Y in parallel with a main surface of a semiconductor substrate 40. The second parallel pn layer 3b is in contact with the first parallel pn layer 3a and surrounds the first parallel pn layer 3a. In the second parallel pn layer 3b, an n-type column region 33 and a p-type column region 34 are alternately and repeatedly disposed adjacent to each other so as to concentrically surround the active region 10. A double zone JTE structure 21 is provided between the front face of the semiconductor substrate 40 and the second parallel pn layer 3n. In the double zone JTE structure 21, a p--type region and a p---type region are disposed adjacent to each other so as to concentrically surround the active region 10.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a silicon carbide semiconductor device. [Background technology]

[0002] Conventionally, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: MOS-type field-effect transistors with an insulated gate consisting of a three-layer structure of metal-oxide-semiconductor) are known, which have a superjunction (SJ) structure in which the drift layer is a parallel pn layer formed by alternately arranging n-type and p-type regions adjacent to each other in a first direction parallel to the main surface of the semiconductor substrate.

[0003] By making the drift layer an SJ structure, n - Compared to a conventional drift layer composed only of mold regions, the impurity concentration of the drift layer can be increased, significantly reducing on-resistance. Furthermore, by using an SJ structure for the drift layer, the increase in on-resistance during high-temperature operation is suppressed. High-temperature operation refers to the operation of a semiconductor device when the semiconductor substrate (semiconductor chip) is at a high temperature due to a high-temperature environment, high voltage application, or high current flow.

[0004] Figure 11 is a plan view showing the layout of a conventional silicon carbide semiconductor device as seen from the front side of the semiconductor substrate. In Figure 11, the number of n-type column regions 131 and p-type column regions 132 is simplified and differs from that in Figure 12. Figures 12 to 14 are cross-sectional views showing the cross-sectional structure at the cutting lines AA-AA', BB-BB', and CC-CC' in Figure 11, respectively. In Figures 11, 12, and 14, the p-type column regions 132 are indicated by hatching.

[0005] The conventional silicon carbide semiconductor device 150 shown in Figures 11-14 is a trench gate type SiC-MOSFET with an SJ structure, comprising a parallel pn layer 103 acting as a drift layer inside a semiconductor substrate 140 made of silicon carbide (SiC) as the semiconductor material. The semiconductor substrate 140 is made of n +The material is formed by sequentially epitaxially growing parallel pn layers 103 and p-type base regions 104, respectively, on a starting substrate 141.

[0006] The parallel pn layer 103 is formed by alternately arranging n-type regions (hereinafter referred to as n-type column regions) 131 and p-type regions (hereinafter referred to as p-type column regions) 132 adjacent to each other in a first direction X parallel to the main surface of the semiconductor substrate 140. The n-type column regions 131 and p-type column regions 132 extend in a stripe-like manner across the entire area of ​​the semiconductor substrate 140 in a second direction Y parallel to the main surface of the semiconductor substrate 140 and perpendicular to the first direction X.

[0007] Both the active region 110 and the edge-terminal region 120 have drift layers composed of the same SJ structure. Both the n-type column region 131 and the p-type column region 132 have approximately the same width (short-direction width) Wn101 and Wp101, and approximately the same impurity concentration. Approximately the same width and approximately the same impurity concentration means that they have the same width, the same depth, and the same impurity concentration, respectively, within a range that includes tolerances due to process variations.

[0008] In both the active region 110 and the edge-terminal region 120, the charge balance is generally maintained between the adjacent n-type column region 131 and the p-type column region 132. Charge balance is an indicator of the degree of equilibrium between the charge amount, which is expressed as the product of the carrier concentration (impurity concentration) and width Wn101 of the n-type column region 131, and the charge amount, which is expressed as the product of the carrier concentration and width Wp101 of the p-type column region 132.

[0009] In the edge termination region 120, a breakdown structure is arranged between the front surface of the semiconductor substrate 140 and the parallel pn layer 103. In SiC-MOSFETs, the breakdown structure consists of two p-type regions (p) with different impurity concentrations. - type region 122, p -- It is known that a double-zone junction termination extension (JTE) structure 121 composed of type regions 123) is used.

[0010] The double-zone JTE structure 121 is arranged concentrically around the active region 110. Therefore, in the double-zone JTE structure 121, there are portions orthogonal and parallel to the n-type column region 131 and the p-type column region 132 that extend in a stripe shape in the second direction Y. In FIG. 11, the inner end (the inner end of the p - -type region 122) and the outer end (the outer end of the p -- -type region 123) of the double-zone JTE structure 121 are indicated by broken lines.

[0011] The parallel pn layer 103 is provided up to the outside of the double-zone JTE structure 121. The outermost column region in the first direction X of the parallel pn layer 103 is the p-type column region 132. The portion between the semiconductor substrate 140 and the parallel pn layer 103 is a normal n-type drift region 135 that is not of the SJ structure. The normal n-type drift region 135 is provided along the outer periphery of the semiconductor substrate 140 and surrounds the parallel pn layer 103.

[0012] Reference numerals 101, 102, 105 to 109, 114 to 116, 125 are an n + -type drain region, an n-type buffer region, an n + -type source region, a p ++ -type contact region, a gate trench, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, a drain electrode, and an n + -type channel stopper region, respectively. Reference numerals 111, 112 are p + -type regions for relaxing the electric field applied to the gate insulating film 108 on the bottom surface of the gate trench 107.

[0013] As a conventional SJ-structure vertical silicon carbide semiconductor device, inside a p-type RESURF layer formed across a plurality of p-type column regions extending in a stripe shape parallel to the front surface of a semiconductor substrate, in the depth direction, so as not to face the p-type column regions, p +A device has been proposed that ensures pressure resistance by arranging high-concentration regions of a p-type column to maintain an equal potential balance in each p-type column region of the edge-terminal region during avalanche yielding (see, for example, Patent Document 1 below).

[0014] As a conventional vertical silicon carbide semiconductor device with a different SJ structure, a device has been proposed in which multiple p-type regions with the same impurity concentration are arranged as a breakdown structure, spanning multiple p-type column regions extending in a stripe-like manner parallel to the front surface of the semiconductor substrate. These regions are arranged concentrically, spaced apart from each other, surrounding the active region, and extending outwards from the p-type column regions in the normal direction. This suppresses localized electric field concentration in the edge termination region and improves breakdown voltage (see, for example, Patent Document 2 below).

[0015] As a conventional vertical silicon carbide semiconductor device with a different SJ structure, a device has been proposed that reduces the overlap between a p-type column region extending in a stripe-like manner parallel to the front surface of the semiconductor substrate and a p-type resurf layer surrounding the active region between the front surface of the semiconductor substrate and the SJ structure, thereby obtaining the depletion conditions during the off state at key locations in the edge termination region and securing the breakdown voltage margin in the edge termination region (see, for example, Patent Document 3 below). [Prior art documents] [Patent Documents]

[0016] [Patent Document 1] International Publication No. 2017 / 212773 [Patent Document 2] International Publication No. 2017 / 183375 [Patent Document 3] Japanese Patent Publication No. 2010-040973 [Overview of the Initiative] [Problems that the invention aims to solve]

[0017] However, as mentioned above, in conventional SJ structure SiC-MOSFETs (see Figures 11-14), the drift layer is composed of the same SJ structure (n-type column region 131 and p-type column region 132) in both the active region 110 and the edge termination region 120. As a result, the breakdown voltage of the edge termination region 120 is lower than that of the active region 110, making it prone to avalanche breakdown in the edge termination region 120. This results in a problem where the breakdown withstand voltage is lower compared to the case where avalanche breakdown occurs in the active region 110, which has a large area occupying most of the surface area of ​​the semiconductor substrate 140.

[0018] The purpose of this invention is to provide a silicon carbide semiconductor device that can improve fracture resistance in order to solve the problems of the conventional technology described above. [Means for solving the problem]

[0019] To solve the above-mentioned problems and achieve the objectives of the present invention, the silicon carbide semiconductor device according to this invention has the following features: A semiconductor substrate made of silicon carbide is provided with an active region and a termination region surrounding the active region. A first parallel pn layer is provided inside the semiconductor substrate in the active region. The first parallel pn layer is formed by alternately and repeatedly arranging a first first conductivity type column region and a first second conductivity type column region adjacent to each other. A second parallel pn layer is provided inside the semiconductor substrate in the termination region, in contact with the first parallel pn layer.

[0020] The second parallel pn layer is formed by alternately and repeatedly arranging a second first conductivity type column region and a second second conductivity type column region adjacent to each other. A predetermined device structure is provided between the first main surface of the semiconductor substrate and the first parallel pn layer. The first electrode is provided on the first main surface and is electrically connected to the device structure. The second electrode is provided on the second main surface of the semiconductor substrate. The second first conductivity type column region and the second second conductivity type column region are arranged concentrically and alternately and repeatedly adjacent to each other surrounding the first parallel pn layer.

[0021] Furthermore, the silicon carbide semiconductor device according to this invention further comprises a breakdown structure in which a first second conductivity type region and a second second conductivity type region are concentrically arranged between the first main surface and the second parallel pn layer, surrounding the periphery of the active region. The first second conductivity type region is electrically connected to the first electrode. The second second conductivity type region is provided outside the first second conductivity type region and adjacent to it. The second second conductivity type region is characterized by having a lower impurity concentration than the first second conductivity type region.

[0022] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, among the plurality of second conductivity type column regions, the boundary column region located closest to the boundary between the first second conductivity type region and the second second conductivity type region is located at a position satisfying D1≧D2>D3, or at a position satisfying D2>D1 and D2-D1<1μm. D1 is the distance from the active region to the outer side surface of the boundary column region in the normal direction from the center of the semiconductor substrate outward. D2 is the distance from the active region to the boundary in the normal direction. D3 is the distance from the active region to the inner side surface of the boundary column region in the normal direction.

[0023] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the second conductivity type column region is electrically connected to the first electrode via the pressure-resistant structure.

[0024] Furthermore, the silicon carbide semiconductor device according to the present invention is characterized in that, in the invention described above, it further comprises a second conductivity type connecting region that is selectively provided in contact with the breakdown structure between the first main surface and the second parallel pn layer outside the breakdown structure, and partially connects all of the second conductivity type column regions located outside the breakdown structure.

[0025] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the second parallel pn layer extends to the first main surface and is exposed on the first main surface.

[0026] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the width of the second conductivity type column region is narrower as the second conductivity type column region is located on the outside.

[0027] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the spacing between adjacent second conductivity type column regions is increased towards the outside.

[0028] Furthermore, in the silicon carbide semiconductor device according to this invention, the device structure comprises a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type, a trench, a gate electrode, and a high-concentration region of a second conductivity type. The first semiconductor region is provided between the first main surface and the first parallel pn layer. The second semiconductor region is selectively provided between the first main surface and the first semiconductor region. The trench penetrates the second semiconductor region and the first semiconductor region to reach the first first conductivity type column region. The gate electrode is provided inside the trench via a gate insulating film.

[0029] The second conductivity type high-concentration region is selectively provided between the first semiconductor region and the first parallel pn layer, on the side of the trench closer to the second electrode than the bottom surface. The second conductivity type high-concentration region has a higher impurity concentration than the first semiconductor region. The first electrode is electrically connected to the second semiconductor region, the first semiconductor region, and the second conductivity type high-concentration region. The second conductivity type high-concentration region extends outward between the first main surface and the second parallel pn layer, contacting the second conductivity type column region in the depth direction and contacting the breakdown structure in the normal direction. The second conductivity type column region is electrically connected to the first electrode via the second conductivity type high-concentration region, or via the second conductivity type high-concentration region and the breakdown structure.

[0030] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the first conductivity type column region and the first second conductivity type column region are arranged alternately and repeatedly adjacent to each other in a first direction parallel to the first main surface, and extend in a stripe shape in a second direction parallel to the first main surface and perpendicular to the first direction.

[0031] According to the invention described above, the electric field applied to the termination region when the device is off can be uniformly distributed in the normal direction according to the distance from the outer edge of the active region, thereby improving the breakdown voltage of the termination region. This makes it possible to change the location where avalanche breakdown occurs to a large active region that occupies most of the surface area of ​​the semiconductor substrate. [Effects of the Invention]

[0032] The silicon carbide semiconductor device according to the present invention has the effect of improving fracture resistance. [Brief explanation of the drawing]

[0033] [Figure 1] This is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. [Figure 2]This is a cross-sectional view showing the cross-sectional structure along the cutting line A-A' in Figure 1. [Figure 3] This is a cross-sectional view showing the cross-sectional structure along the cutting line B-B' in Figure 1. [Figure 4] This is a cross-sectional view showing the cross-sectional structure at the cutting line C-C' in Figure 1. [Figure 5] This is an explanatory diagram illustrating the mechanism of electric field concentration in a double-zone JTE structure. [Figure 6] This is an explanatory diagram showing the positional relationship between the p-type column region and the double-zone JTE structure in the edge-terminal region of Embodiment 1. [Figure 7] This is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 2, as seen from the front side of the semiconductor substrate. [Figure 8] Figure 7 is a cross-sectional view showing the cross-sectional structure along the cutting line D-D'. [Figure 9A] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 3. [Figure 9B] Figure 9A is a characteristic diagram showing the relationship between the charge balance in the normal direction and the breakdown voltage of the second parallel pn layer. [Figure 10] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 4. [Figure 11] This is a plan view showing the layout of a conventional silicon carbide semiconductor device as seen from the front side of the semiconductor substrate. [Figure 12] This is a cross-sectional view showing the cross-sectional structure along the cutting line AA-AA' in Figure 11. [Figure 13] This is a cross-sectional view showing the cross-sectional structure at the cutting line BB-BB' in Figure 11. [Figure 14] Figure 11 is a cross-sectional view showing the cross-sectional structure along the cutting line CC-CC'. [Modes for carrying out the invention]

[0034] Preferred embodiments of the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted.

[0035] (Embodiment 1) The structure of the silicon carbide semiconductor device according to Embodiment 1 will now be described. Figure 1 is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. Figures 2 to 4 are cross-sectional views showing the cross-sectional structure at the cutting lines A-A', B-B', and C-C' in Figure 1, respectively. In Figures 2 to 4, the number of n-type column regions 31, 33 and p-type column regions 32, 34 is simplified and differs from that in Figure 1. In Figures 1 to 4, the p-type column regions 32 and 34 are shown with hatching (the same applies in Figures 7, 8, 9A, and 10). Note that in Figure 1, in order to clarify the planar arrangement of the p-type column regions 32 and 34, the p-type column region 32 and the p-type column region 34 are shown with different hatching (the same applies in Figure 7).

[0036] The silicon carbide semiconductor device 50 according to Embodiment 1 shown in Figures 1-4 is a vertical SiC-MOSFET with an SJ structure, in which a general trench gate structure (device structure) is provided on the front side (first main surface) of the semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC) in the active region 10, and the drift layers (drift regions) of the active region 10 and the edge termination region 20 are first and second parallel pn layers 3a and 3b, respectively. The trench gate structure is located between the front surface of the semiconductor substrate 40 and the first parallel pn layer 3a in the active region 10.

[0037] The active region 10 is the region through which the main current flows when the MOSFET is ON, and is located approximately in the center of the semiconductor substrate 40 (center of the chip). Multiple unit cells (constituent units of the element) with the same trench gate structure are arranged adjacent to each other in the active region 10. The active region 10 is located inward (towards the center of the chip) from the center of the outermost gate trench 7 (7a) (see Figure 2) in the first direction X, and in the second direction Y n + This is the portion inside the edge (not shown) of type source region 5 (see Figure 2).

[0038] The edge termination region 20 is the region between the active region 10 and the edge (chip edge) of the semiconductor substrate 40, and surrounds the active region 10. The edge termination region 20 has the function of mitigating the electric field on the front side of the semiconductor substrate 40 of the drift layer and maintaining the breakdown voltage. Breakdown voltage is the limit voltage at which leakage current does not increase excessively and the device does not malfunction or break down. In the edge termination region 20, a double-zone junction termination extension (JTE) structure 21 is arranged as a breakdown voltage structure between the front side of the semiconductor substrate 40 and the second parallel pn layer 3b (see Figures 2-4).

[0039] The double-zone JTE structure 21 consists of two p-type regions with different impurity concentrations (as described later). - type region 22, p -- This JTE structure is formed by concentrically arranging p-type regions (see Figures 2-4) adjacent to each other around the active region 10, such that the p-type regions have lower impurity concentrations as they move away from the active region 10. Figure 1 shows the inner end of the double-zone JTE structure 21 (p - (Inner end of type region 22) and outer end (p -- The outer edge of type region 23 is shown by a rough dashed line, p - Type region 22 and p -- The boundary 24 with type region 23 is shown by a fine dashed line.

[0040] p of double-zone JTE structure 21 - Type region (first second conductivity type region) 22 and p --The type region (second second conductivity type region) 23 is in contact with at least one of the n-type column region 33 and p-type column region 34 of the second parallel pn layer 3b, which will be described later. The double-zone JTE structure 21 is not required. If the double-zone JTE structure 21 is not provided, the second parallel pn layer 3b is p + Mold extensions 11a and n + The element reaches the front surface of the semiconductor substrate 40 between it and the channel stopper region 25, and is exposed on the front surface of the semiconductor substrate 40 (the second surface 40b, described later).

[0041] The layout of the SJ structure of the drift layer, as viewed from the front side of the semiconductor substrate 40, differs between the active region 10 and the edge termination region 20. The drift layer in the active region 10 is an SJ structure composed of first parallel pn layers 3a. The first parallel pn layers 3a are formed by alternately arranging n-type regions (hereinafter referred to as n-type column regions (first first conductivity type column regions)) 31 and p-type regions (hereinafter referred to as p-type column regions (first second conductivity type column regions)) 32 adjacent to each other in a first direction X parallel to the main surface of the semiconductor substrate 40.

[0042] The n-type column region 31 and p-type column region 32 of the first parallel pn layer 3a extend in a stripe-like manner in a second direction Y that is parallel to the main surface of the semiconductor substrate 40 and perpendicular to the first direction X, over almost the entire area of ​​the active region 10. A charge balance is generally maintained between adjacent n-type column region 31 and p-type column region 32. Charge balance is an indicator of the degree of equilibrium between the charge amount, which is expressed as the product of the carrier concentration and width of the n-type column region, and the charge amount, which is expressed as the product of the carrier concentration and width of the p-type column region.

[0043] For example, the width Wn1 in the short direction (first direction X) of the n-type column region 31 and the width Wp1 in the short direction of the p-type column region 32 are approximately the same and uniform throughout the entire active region 10. The impurity concentration in the n-type column region 31 and the impurity concentration in the p-type column region 32 are approximately the same and uniform throughout the entire active region 10. Approximately the same width and approximately the same impurity concentration mean that they are the same width and the same impurity concentration, respectively, within a range that includes tolerances due to process variations.

[0044] The drift layer in the edge-terminal region 20 is an SJ structure composed of a second parallel pn layer 3b. The second parallel pn layer 3b is adjacent to the first parallel pn layer 3a and surrounds the first parallel pn layer 3a. The second parallel pn layer 3b consists of n-type regions (n-type column regions (second first conductivity type column regions)) 33 and p-type regions (p-type column regions (second second conductivity type column regions)) 34 arranged concentrically and alternately adjacent to the active region 10. A charge balance is generally maintained between adjacent n-type column regions 33 and p-type column regions 34.

[0045] For example, the width Wn2 in the short direction of the n-type column region 33 and the width Wp2 in the short direction of the p-type column region 34 are approximately the same and uniform throughout the entire edge-terminal region 20. Alternatively, the width Wn2 in the short direction of the n-type column region 33 may be approximately the same as the width Wn1 in the short direction of the n-type column region 31, and the width Wp2 in the short direction of the p-type column region 34 may be approximately the same as the width Wp1 in the short direction of the p-type column region 32. The impurity concentration in the n-type column region 33 and the impurity concentration in the p-type column region 34 are approximately the same and uniform throughout the entire edge-terminal region 20.

[0046] The innermost column region of the second parallel pn layer 3b may be an n-type column region 33 or a p-type column region 34. When the innermost column region of the second parallel pn layer 3b is an n-type column region 33, the outermost column region of the first parallel pn layer 3a in the first direction X is a p-type column region 32 (not shown). When the innermost column region of the second parallel pn layer 3b is a p-type column region 34, the outermost column region of the first parallel pn layer 3a in the first direction X is an n-type column region 31 (see Figures 1-4).

[0047] The innermost column region of the second parallel pn layer 3b is in contact with the outermost column region of the first parallel pn layer 3a in the first direction X, forming a pn junction with that column region. A charge balance is generally maintained between the outermost column region of the first parallel pn layer 3a in the first direction X and the innermost column region of the second parallel pn layer 3b. The innermost column region of the second parallel pn layer 3b is in contact with the ends of all n-type column regions 31 and all p-type column regions 32 in the second direction Y.

[0048] For example, in conventional structures (see Figures 11-14), the n-type column region 131 and p-type column region 132 of the edge termination region 120 extend in a stripe-like manner. As a result, the edge termination region 120 has partially different structures concentrically at approximately the same distance from the outer periphery of the active region 110 in the normal direction from the center of the chip to the edge of the chip. Therefore, when the MOSFET is off, the electric field acting on the edge termination region 120 is not evenly distributed in the normal direction according to the distance from the outer periphery of the active region 110, resulting in concentrated electric field areas in the edge termination region 120 where the structure differs.

[0049] Furthermore, the conventional double-zone JTE structure 121 has both orthogonal and parallel portions to the n-type column region 131 and p-type column region 132 of the parallel pn layer 103. Therefore, when the double-zone JTE structure 121 is provided, the edge termination region 120 has a partially different structure in the portion where the double-zone JTE structure 121 is provided, concentrically at approximately the same distance from the outer periphery of the active region 110 in the normal direction. This portion of the double-zone JTE structure 121 that has a different structure from the parallel pn layer 103 also becomes an electric field concentration point.

[0050] On the other hand, in Embodiment 1, the n-type column region 33 and the p-type column region 34 are arranged concentrically around the active region 10 in the edge termination region 20, so that the edge termination region 20 has the same structure concentrically at approximately the same distance from the outer periphery of the active region 10 in the normal direction. For this reason, there are no electric field concentration points in the edge termination region 20 concentrically at approximately the same distance from the outer periphery of the active region 10 in the normal direction, as in the conventional structure. Therefore, when the MOSFET is off, the electric field applied to the edge termination region 20 can be distributed evenly in the normal direction according to the distance from the outer periphery of the active region 10.

[0051] Furthermore, in Embodiment 1, the double-zone JTE structure 21 consists only of the portion parallel to the n-type column region 33 and the p-type column region 34 of the second parallel pn layer 3b, and there is no portion with a different structure from the second parallel pn layer 3b. For this reason, even when the double-zone JTE structure 21 is provided, there are no electric field concentration points in the edge termination region 20 that are concentrically at approximately the same distance from the outer periphery of the active region 10 in the normal direction, as in the conventional structure. Therefore, when the MOSFET is off, the electric field applied to the edge termination region 20 can be evenly distributed in the normal direction according to the distance from the outer periphery of the active region 10.

[0052] The semiconductor substrate 40 is made of n + The semiconductor substrate 40 is formed by sequentially depositing a drift layer and epitaxial layers 42 and 43, which will become the p-type base region 4, on the front surface of the starting substrate 41. The main surface of the p-type epitaxial layer 43 is the front surface of the n+ The main surface on the mold starting substrate 41 side is designated as the back surface (second main surface). + The starting substrate 41 is n + This is the n-type drain region 1. The drift layer (n-type epitaxial layer 42) consists of a p-type base region 4 and n + These regions are provided in contact with the drain region 1.

[0053] The second parallel pn layer 3b extends from the boundary between the active region 10 and the edge-terminal region 20 to outside the double-zone JTE structure 21. The outermost column region of the second parallel pn layer 3b is the p-type column region 34. The second parallel pn layer 3b is described later as p + Mold extension part 11a, n + It is adjacent to the n-type channel stopper region 25 and the normal n-type drift region 35. The second parallel pn layer 3b is adjacent to the double-zone JTE structure 21 and n + It is exposed on the front surface (second surface 40b, described later) of the semiconductor substrate 40 between it and the type channel stopper region 25.

[0054] Among the multiple p-type column regions 34 of the second parallel pn layer 3b, directly below the double-zone JTE structure 21 (n + The p-type column region 34 (JTE boundary p-type column region 34a, described later) on the drain region 1 side is the p-type column region of the double-zone JTE structure 21. - Type region 22 and p -- It is preferable that the positional relationship between the boundary 24 and the type region 23 satisfies the conditions described later. The portion between the side surface of the semiconductor substrate 40 and the second parallel pn layer 3b is a normal n-type drift region 35 that is not an SJ structure. The impurity concentration of the normal n-type drift region 35 is less than or equal to the impurity concentration of the n-type column regions 31 and 33.

[0055] Between the front surface of the semiconductor substrate 40 and the normal n-type drift region 35, there is a second parallel pn layer 3b, separated from the n + A channel stopper region 25 is selectively provided. The normal n-type drift region 35 and n +The n-type channel stopper region 25 is provided along the outer periphery of the semiconductor substrate 40 and surrounds the second parallel pn layer 3b. + The channel stopper region 25 is exposed on the side surface of the semiconductor substrate 40. + Instead of the channel stopper region 25, p + A channel stopper region may be provided.

[0056] The drift layer has an SJ structure in which at least the surface region on the front side of the semiconductor substrate 40 consists of first and second parallel pn layers 3a and 3b. + The portion between the n-type drain region 1 may be an n-type buffer region (an n-type region that is not an SJ structure) 2. The n-type buffer region 2 consists of the first and second parallel pn layers 3a and 3b, and n + It is in contact with the n-type drain region 1 and the normal n-type drift region 35, which does not have an SJ structure. The impurity concentration in the n-type buffer region 2 is less than or equal to the impurity concentration in the n-type column regions 31 and 33.

[0057] n-type column regions 31, 33 and p-type column regions 32, 34 have an n-type buffer region 2 in the depth direction Z (if n-type buffer region 2 is not provided, then n + The drain region 1) is reached. The length in the depth direction Z is approximately the same for both the n-type column regions 31, 33 and the p-type column regions 32, 34. The length in the depth direction Z of the n-type column region 31 and the p-type column region 32 are, respectively, p + From type areas 11 and 12 to n-type buffer area 2 (if n-type buffer area 2 is not provided, then n + This is the length up to the drain region 1).

[0058] The length in the depth direction Z of the n-type column region 33 and the p-type column region 34 is the double-zone JTE structure 21 or the p described later. + From the extended n-type portion 11a to the n-type buffer region 2 (if the n-type buffer region 2 is not provided, then n + This is the length up to the type drain region 1). The width Wn1 in the shorter direction of the n-type column region 31 is p +It is wider than the width in the short direction of type region 11. The n-type column region 31 is p + It may be adjacent to the type region 12. The width Wp1 in the shorter direction of the p-type column region 32 is p + The width of the type region 12 in the shorter direction may be approximately the same.

[0059] The p-type column region 32 of the first parallel pn layer 3a is p + Type region 12, p-type base region 4 and p ++ The p-type column region 34 of the second parallel pn layer 3b, located inside the outer edge of the double-zone JTE structure 21, is connected to the p-type base extension 4a and p + The source electrode 15 is electrically connected via the type extension 11a, or via these regions and the double-zone JTE structure 21. The p-type column region 34 of the second parallel pn layer 3b, located outside the double-zone JTE structure 21, is electrically floating.

[0060] The trench gate structure consists of a p-type base region (first semiconductor region) 4, n + Type source region (second semiconductor region) 5, p ++ It consists of a p-type contact region 6, a gate trench (trench) 7, a gate insulating film 8, and a gate electrode 9. The p-type base region 4 is provided between the front surface of the semiconductor substrate 40 and the first parallel pn layer 3a. The p-type base region 4 is the n of the p-type epitaxial layer 43. + Type source region 5 and p ++ This is the portion excluding the type contact region 6. The p-type base region 4 extends outward from the active region 10 to the step 44, which will be described later.

[0061] n + Type source region 5 and p ++ The type contact region 6 is selectively provided between the front surface of the semiconductor substrate 40 and the p-type base region 4 in the active region 10. + Type source region 5 and p ++ The p-type contact region 6 is in contact with the p-type base region 4 and is exposed on the front surface of the semiconductor substrate 40.+ Type source region 5 and p ++ The contact area 6 being exposed on the front surface of the semiconductor substrate 40 means that these areas are in contact with the source electrode (first electrode) 15, which will be described later, on the first surface 40a of the front surface of the semiconductor substrate 40.

[0062] n + Type source region 5 and p ++ The type contact region 6 extends linearly in the second direction Y, for example, along the side wall of the gate trench 7. + Type source area 5 is p ++ It is positioned on the gate trench 7 side of the type contact region 6 and faces the gate electrode 9 via the gate insulating film 8 of the side wall of the gate trench 7. ++ The type contact area 6 does not need to be provided. In this case, p ++ Instead of the type contact region 6, the p-type base region 4 is exposed on the first surface 40a of the front surface of the semiconductor substrate 40.

[0063] Between the p-type base region 4 and the first parallel pn layer 3a, + Type regions (second conductivity type high concentration regions) 11 and 12 are selectively provided. + The n-type regions 11 and 12 are diffusion regions formed inside the n-type epitaxial layer 42 by ion implantation. + The type regions 11 and 12 are electrically connected to the source electrode 15 and have the function of depleting when the MOSFET is off, thereby mitigating the electric field near the bottom surface of the gate trench 7. + The mold regions 11 and 12 extend in a stripe-like manner in the second direction Y along the side wall of the gate trench 7.

[0064] p + An n-type column region 31 extends between type regions 11 and 12. + Between type regions 11 and 12, the n-type column region 31 extends to the p-type base region 4 and is in contact with the p-type base region 4. + The type region 11 is positioned separately from the p-type base region 4 and faces the bottom surface of the gate trench 7 in the depth direction Z. +Type region 11 is p in the part omitted from the illustration. + It is connected to type region 12. + The type region 11 is in contact with the n-type column region 31 opposite it in the depth direction Z. + The mold region 11 may be in contact with the gate insulating film 8 at the bottom surface of the gate trench 7.

[0065] The outermost p in the first direction X + The mold region 11 extends beyond the step 44, which will be described later, and is exposed on the second surface 40b of the front surface of the semiconductor substrate 40, which will be described later. Exposure to the second and third surfaces 40b and 40c of the front surface of the semiconductor substrate 40, as described later, means contact with the interlayer insulating film 14 on the front surface of the semiconductor substrate 40. + The type region 12 is in contact with the p-type base region 4 between adjacent gate trenches 7, and p + It is located away from the mold region 11 and the gate trench 7. + The type region 12 is in contact with the p-type column region 32 in the depth direction Z.

[0066] Between adjacent gate trenches 7, p + An n-type current diffusion region (not shown) may be provided between the type regions 11, 12, the p-type base region 4, and the n-type column region 31, in contact with these regions and reaching the side wall of the gate trench 7 in the first direction X. The n-type current diffusion region is a so-called current spreading layer (CSL) that reduces the carrier spreading resistance. The impurity concentration of the n-type current diffusion region is equal to or greater than the impurity concentration of the n-type column region 31.

[0067] The gate trench 7 extends from the first surface 40a of the front surface of the semiconductor substrate 40 to a depth in the Z direction n + It penetrates the p-type source region 5 and the p-type base region 4 to reach the n-type column region 31 (or the n-type current diffusion region if an n-type current diffusion region is provided). The bottom surface of the gate trench 7 is p +It may terminate inside the type region 11. The gate trench 7 extends in a stripe shape in a direction parallel to the front surface of the semiconductor substrate 40 (here, the second direction Y). Inside the gate trench 7, a gate electrode 9 is provided via a gate insulating film 8.

[0068] The interlayer insulating film 14 is provided on the entire front surface of the semiconductor substrate 40 and covers the gate electrode 9. The source electrode 15 makes an ohmic contact with the first surface 40a of the front surface of the semiconductor substrate 40 at the contact hole of the interlayer insulating film 14, and is electrically connected to the p-type base region 4, the n + -type source region 5 and the p ++ -type contact region 6. The drain electrode (second electrode) 16 is provided on the entire back surface of the semiconductor substrate 40 (the back surface of the n + -type starting substrate 41), and is electrically connected to the n + -type drain region 1.

[0069] The portion of the p-type epitaxial layer 43 in the edge termination region 20 is removed by etching, and a step 44 is formed on the front surface of the semiconductor substrate40. The front surface of the semiconductor substrate 40 is recessed toward the n + -type drain region 1 side at the portion (hereinafter referred to as the second surface) 40b on the edge termination region 20 side than the portion (hereinafter referred to as the first surface) 40a on the active region 10 side with this step 44 as a boundary. The second surface 40b of the front surface of the semiconductor substrate 40 is an exposed surface of the n-type epitaxial layer 42 exposed by removing the p-type epitaxial layer 43.

[0070] At the portion (hereinafter referred to as the third surface: mesa edge of the step 44) 40c connecting the first surface 40a and the second surface 40b of the front surface of the semiconductor substrate 40, the active region 10 and the edge termination region 20 are element-separated. In the edge termination region 20, a field oxide film may be provided between the front surface of the semiconductor substrate 40 and the interlayer insulating film 14. In the edge termination region 20, between the front surface of the semiconductor substrate 40 and the second parallel pn layer 3b, from the active region 10, the p-type base region 4 and the p + -type region 11 facing the bottom surface of the outermost gate trench 7 (7a) extend.

[0071] Thereafter, portions extending to the edge termination regions 20 of the p-type base region 4 and the p + -type region 11 are defined as a p-type base extension portion 4a and a p + -type extension portion 11a, respectively. The p-type base extension portion 4a is exposed on the first surface 40a of the front surface of the semiconductor substrate 40. A p ++ -type outer peripheral contact region (not shown) may be provided between the first surface 40a of the front surface of the semiconductor substrate 40 and the p-type base extension portion 4a. The p-type base extension portion 4a (p ++ -type outer peripheral contact region when provided) is in contact with the source electrode 15. ++

[0072] The p-type base extension portion 4a and the p + -type extension portion 11a extend along the boundary between the active region 10 and the edge termination region 20 and surround the periphery of the active region 10. The p + -type extension portion 11a is provided between the p-type base extension portion 4a and the second parallel pn layer 3b in contact with these regions. The p + -type extension portion 11a connects the ends of all the p + -type regions 11, 12 of the active region 10. Also, the p + -type extension portion 11a extends outside the step 44 on the front surface of the semiconductor substrate 40 and is exposed on the second surface 40b of the front surface of the semiconductor substrate.

[0073] A gate runner (not shown) is provided between the active region 10 and the double-zone JTE structure 21. The gate runner includes a gate polysilicon wiring layer provided on the first surface 40a of the front surface of the semiconductor substrate 40 via a field oxide film (not shown). The gate polysilicon wiring layer is covered with an interlayer insulating film 14. Each gate electrode 9 of all the unit cells of the active region 10 is connected to the gate polysilicon wiring layer. The gate runner electrically connects the gate electrode 9 and a gate pad (electrode pad: not shown).

[0074] In the edge termination region 20, the surface region of the second surface 40b of the front surface of the semiconductor substrate 40 has two p-type regions (p) that constitute the double-zone JTE structure 21 within the n-type epitaxial layer 42. - type region 22, p -- Each type region 23) is selectively provided, and outside of it, the double-zone JTE structure 21 is separated from n + A channel stopper region 25 is selectively provided. The double-zone JTE structure 21 is provided between the second surface 40b of the front surface of the semiconductor substrate 40 and the second parallel pn layer 3b, in contact with the second parallel pn layer 3b.

[0075] p - Type region 22 is p + Outside the mold extension portion 11a, p + Adjacent to the mold extension portion 11a. -- Type region 23 is p - Outside of type region 22, p - Adjacent to type region 22. - Type region 22 and p -- Type region 23 is p + The p-type extended portion 11a and the p-type base extended portion 4a are fixed to the potential of the source electrode 15. - type region 22, p -- Type region 23 and n + The n-type channel stopper region 25 is a diffusion region formed by ion implantation into the n-type epitaxial layer 42 and is exposed on the second surface 40b of the front surface of the semiconductor substrate 40.

[0076] n + The n-type channel stopper region 25 is provided between the second surface 40b of the front surface of the semiconductor substrate 40 and the normal n-type drift region 35. Double zone JTE structure 21 and n + Between the channel stopper region 25 and the second surface 40b of the front surface of the semiconductor substrate 40, the second parallel pn layer 3b and the normal n-type drift region 35 are exposed. The normal n-type drift region 35 is in contact with the second parallel pn layer 3b and surrounds the second parallel pn layer 3b. The impurity concentration of the normal n-type drift region 35 is less than or equal to the impurity concentration of the n-type column region 31.

[0077] The positional relationship between the p-type column region 34 of the edge termination region 20 and the double-zone JTE structure 21 will be explained. Figure 5 is an explanatory diagram illustrating the mechanism of electric field concentration in the double-zone JTE structure. Figure 6 is an explanatory diagram showing the positional relationship between the p-type column region of the edge termination region and the double-zone JTE structure in Embodiment 1. In Figures 5 and 6, only the JTE boundary p-type column region (boundary column region) 34a is shown among the multiple p-type column regions 34 of the edge termination region 20, and the other p-type column regions 34 are omitted from the illustration. Also, in Figures 5 and 6, the extent of the depletion layer is shown by fine dashed lines. The area between the two fine dashed lines is the depletion layer.

[0078] As shown in Figure 5, when a positive voltage (forward voltage) is applied to the drain electrode 16 relative to the source electrode 15, and a voltage less than the gate threshold voltage is applied to the gate electrode 9, in the edge termination region 20, the pn junction between the p-type column region 34 and the n-type column region 33 of the second parallel pn layer 3b and the p of the double-zone JTE structure 21 - Type region 22 and p -- The pn junction between the type region 23 and the n-type column region 33 of the second parallel pn layer 3b is reverse-biased, and from this pn junction, the p-type column region 34, p - Type region 22 and p -- A depletion layer 51 extends across type region 23.

[0079] p of double-zone JTE structure 21 - Type region 22 and p -- As the depletion layer 51 spreads across the mold region 23, the p on the outer side (towards the tip edge) of these regions -- The lower edge (n) outside of type region 23 + Electric field concentration 52 occurs at the corner of the drain region (on the drain side) (Figure 5(a)). As the forward voltage between the source and drain is increased, depletion progresses further, p -- Type region 23 is completely depleted, p -- From the type region 23 side, p - When the depletion layer 51 extends into the type region 22, p - Type region 22 and p --Electric field concentration 53 occurs at the lower end of the boundary 24 with the type region 23 (Figure 5(b)).

[0080] As described above, the n-type column region 33 and p-type column region 34 of the edge-terminal region 20, and the p of the double-zone JTE structure 21 - Type region 22 and p -- Since the type region 23 and the edge termination region 20 are both concentrically arranged surrounding the active region 10, the edge termination region 20 has the same structure and is concentrically located at approximately the same distance from the outer periphery of the active region 10 in the normal direction. -- The outer lower end corner portion of the mold region 23, and p - Type region 22 and p -- At the lower end of the boundary 24 with the type region 23, and around the entire circumference of the double-zone JTE structure 21, electric field concentrations 52 and 53 occur uniformly.

[0081] Therefore, by appropriately configuring the second parallel pn layer 3b so that the electric field is relaxed at the electric field concentration points 52 and 53 in the edge termination region 20, the breakdown voltage of the edge termination region 20 can be further improved. For example, among the multiple p-type column regions 34 of the second parallel pn layer 3b, the p of the double-zone JTE structure 21 - Type region 22 and p -- The p-type column region 34 closest to the boundary 24 with the type region 23 (hereinafter referred to as the JTE boundary p-type column region 34a) is preferably positioned such that its positional relationship with the boundary 24 satisfies one of the conditions shown in Figures 6(a) to 6(c).

[0082] As shown in Figure 6(a), the JTE boundary p-type column region 34a is the p-type of the double-zone JTE structure 21. - Type region 22 and p -- Directly below the lower end of the boundary 24 with the type region 23, p - Type region 22 and p -- It is preferable to position it adjacent to the type region 23. Also, as shown in Figure 6(b), the JTE boundary p-type column region 34a is such that the outer side surface 37 is normal to the p-type of the double-zone JTE structure 21. - Type region 22 and p -- p -It is preferable to place it adjacent to the type region 22.

[0083] Furthermore, as shown in Figure 6(c), the JTE boundary p-type column region 34a is defined as the p-type of the double-zone JTE structure 21, with the outer side surface 37 being normal to the p-type. - Type region 22 and p -- Located inside the boundary 24 with the type region 23, and such that the distance D4 from the outer side surface 37 to the boundary 24 is less than 1 μm, p - It is preferable to position it adjacent to the type region 22. That is, the JTE boundary p-type column region 34a is the p-type of the double-zone JTE structure 21. - Type region 22 and p -- The positional relationship between the boundary 24 and the type region 23 should preferably be such that it satisfies either equation (1) or (2) below.

[0084] D1≧D2>D3 ···(1)

[0085] D2 > D1, and D2 - D1 < 1 μm ···(2)

[0086] D1 is the distance from the active region 10 to the outer side surface 37 of the JTE boundary p-type column region 34a in the normal direction. D2 is the distance from the active region 10 to the p-type column region of the double-zone JTE structure 21 in the normal direction. - Type region 22 and p -- This is the distance to the boundary 24 with the type region 23. Therefore, (D2-D1) is the distance of the double-zone JTE structure 21 in the normal direction. - Type region 22 and p -- This is the distance from the boundary 24 with the type region 23 to the outer side surface 37 of the active region 10 and the JTE boundary p-type column region 34a.

[0087] D3 is the distance in the normal direction from the active region 10 to the inner side surface 36 of the JTE boundary p-type column region 34a. The inner side surface 36 of the JTE boundary p-type column region 34a is the interface between the JTE boundary p-type column region 34a and the n-type column region 33 adjacent to the inside of the JTE boundary p-type column region 34a. The outer side surface 37 of the JTE boundary p-type column region 34a is the interface between the JTE boundary p-type column region 34a and the n-type column region 33 adjacent to the outside of the JTE boundary p-type column region 34a.

[0088] The p-type column region 34a of the JTE boundary is formed such that it satisfies either equation (1) or equation (2) above, and the p-type column region of the double-zone JTE structure 21 - Type region 22 and p -- By placing it near the boundary 24 with the type region 23, the p of the double-zone JTE structure 21 - Type region 22 and p -- This makes it possible to suppress electric field concentration 53 (Figure 5(b)) at the lower end of the boundary 24 with the mold region 23. As a result, the breakdown voltage of the edge termination region 20 can be further improved, and thus the breakdown tolerance can be further improved.

[0089] The operation of the silicon carbide semiconductor device 50 according to this embodiment will now be described. When a positive voltage (forward voltage) is applied to the drain electrode 16 with respect to the source electrode 15, and a voltage greater than or equal to the gate threshold voltage is applied to the gate electrode 9, a channel (n-type inversion layer) is formed in the portion of the p-type base region 4 along the side wall of the gate trench 7. As a result, n + From type drain region 1 through channel n + The main current (drift current) flows towards the source region 5, and the SiC-MOSFET (silicon carbide semiconductor device 50) turns on.

[0090] On the other hand, when a forward voltage is applied between the source and drain, and a voltage less than the gate threshold voltage is applied to the gate electrode 9, p +When the pn junction (main junction of the active region 10) between the p-type regions 11 and 12 and the p-type base region 4 and the n-type column region 31 of the first parallel pn layer 3a is reverse-biased, the main current stops flowing, and the SiC-MOSFET remains in the off state. When the main junction (pn junction) of the active region 10 is reverse-biased, the depletion layer expands from the pn junction, and the predetermined breakdown voltage of the active region 10 is ensured.

[0091] Furthermore, when the SiC-MOSFET is off, the pn junction between the p-type column regions 32,34 and the n-type column regions 31,33 is reverse-biased, and the depletion layer expands from this pn junction, so that the breakdown voltage is borne by the first and second parallel pn layers 3a and 3b. This ensures a predetermined breakdown voltage that exceeds the breakdown voltage achievable with the impurity concentration of the drift layer (n-type column regions 31,33). In addition, the electric field of the edge termination region 20 is dispersed by the double-zone JTE structure 21 and the p-type column region 34 of the second parallel pn layer 3b, so the breakdown voltage of the edge termination region 20 can be improved.

[0092] Furthermore, when the SiC-MOSFET is off, in the edge termination region 20, the pn junction between the p-type column region 34 and the n-type column region 33 of the second parallel pn layer 3b and the p of the double-zone JTE structure 21 - Type region 22 and p -- The pn junction between the type region 23 and the n-type column region 33 of the second parallel pn layer 3b is reverse-biased, and from this pn junction, the p-type column region 34, p - Type region 22 and p -- A depletion layer 51 extends into the type region 23. At this time, there is a risk of localized electric field concentration 52, 53 occurring in the double-zone JTE structure 21 (see Figures 5(a) and 5(b)).

[0093] Furthermore, the JTE boundary p-type column region 34a is the p-type of the double-zone JTE structure 21. - Type region 22 and p -- The positional relationship between the boundary 24 and the type region 23 satisfies either equation (1) or equation (2) above, which indicates that the p of the double-zone JTE structure 21 - Type region 22 and p --This makes it possible to suppress electric field concentration 53 at the lower end of the boundary 24 with the type region 23. As a result, the electric field applied to the edge termination region 20 when the MOSFET is off can be further reduced, and the breakdown voltage of the edge termination region 20 can be further improved.

[0094] A method for manufacturing the silicon carbide semiconductor device 50 according to Embodiment 1 will be described. First, n + n becomes type drain region 1 + A drift layer including first and second parallel pn layers 3a and 3b is formed on the front surface of a starting substrate (semiconductor wafer) 41. At this time, for example, using a multi-stage epitaxial method, the n-type epitaxial layer 42 that will become the drift layer is grown epitaxially in multiple stages (multiple times), and each time p-type impurities such as aluminum (Al) are ion-implanted into each n-type epitaxial layer, thereby selectively forming the p-type column regions 32 and 34 of the first and second parallel pn layers 3a and 3b.

[0095] The portions of the n-type epitaxial layer 42 that remain n-type without ion implantation between adjacent p-type column regions 32 become the n-type column regions 31 and 33 of the first and second parallel pn layers 3a and 3b. + The entire area between the second parallel pn layer 3b and the starting substrate 41 may be left as an n-type buffer region 2 without ion implantation. The following explanation will use the case where an n-type buffer region 2 is provided as an example. The portion between the second parallel pn layer 3b and the chip edge (the edge of the part that will become a semiconductor chip) that remains n-type without ion implantation becomes a normal n-type drift region 35.

[0096] The n-type column regions 31 and 33 may be formed by ion implantation of n-type impurities. In this case, instead of the n-type epitaxial layer 42, an undoped epitaxial layer or n - The n-type epitaxial layer is divided into multiple stages and epitaxially grown in multiple stages. When an undoped epitaxial layer is epitaxially grown in multiple stages, the n-type buffer region 2 and the n-type drift region 35 are formed by ion implantation of n-type impurities. -When multiple n-type epitaxial layers are epitaxially grown, it is possible to form n-type buffer regions 2 and n-type drift regions 35 with lower impurity concentrations than n-type column regions 31 and 33.

[0097] Next, by ion implantation, p is implanted in the surface region of the n-type epitaxial layer 42 adjacent to the n-type column region 31 and p-type column region 32 of the first parallel pn layer 3a in the depth direction Z. + Selectively forms type regions 11 and 12. Also, p + Simultaneously with the type region 11, the second parallel pn layer 3b is adjacent to the p in the depth direction Z. + A mold extension portion 11a is formed. In the uppermost n-type epitaxial layer of the multi-stage epitaxially grown n-type epitaxial layer 42, p + Type regions 11, 12 and p + Only the mold extension portion 11a is formed, and adjacent p + An n-type current diffusion region (not shown) may be formed between type regions 11 and 12 by ion implantation.

[0098] Next, a p-type epitaxial layer 43, which will become the p-type base region 4, is epitaxially grown on the n-type epitaxial layer 42. + Epitaxial layers 42 and 43 are sequentially stacked on a type starting substrate 41 to create a semiconductor substrate (semiconductor wafer) 40 in which the n-type epitaxial layer 42 includes first and second parallel pn layers 3a and 3b. Next, the edge termination region 20 of the p-type epitaxial layer 43 is removed by etching to form a step 44 on the front surface of the semiconductor substrate 40, where the portion on the edge termination region 20 side (second surface 40b) is lower than the portion on the active region 10 side (first surface 40a).

[0099] An n-type epitaxial layer 42 is exposed on the second surface 40b, which has newly become the front surface of the semiconductor substrate 40 in the edge termination region 20. The portion of the front surface of the semiconductor substrate 40 between the first surface 40a and the second surface 40b (third surface 40c) may, for example, form an obtuse angle (inclined surface) with respect to the first and second surfaces 40a and 40b, or it may form a nearly right angle (vertical surface). The second and third surfaces 40b and 40c of the front surface of the semiconductor substrate 40 have a p-type base region 4 and p + The mold extension portion 11a is exposed. The etching that forms this step 44 may remove a small portion of the n-type epitaxial layer 42 along with the p-type epitaxial layer 43.

[0100] Next, by ion implantation, n + Type source area 5, p ++ Type contact area 6, double zone JTE structure 21(p - type region 22, p -- Type region 23) and n + Each type channel stopper region 25 is selectively formed. + Type source region 5 and p ++ The type contact regions 6 are selectively formed on the surface regions of the p-type epitaxial layer 43. ++ Type contact area 6 and simultaneously p ++ A type outer peripheral contact region may be formed. n of the p-type epitaxial layer 43 + Type source area 5, p ++ Type contact area 6 and p ++ The portion excluding the outer peripheral contact area of ​​the mold becomes the p-type base region 4 and the p-type base extension portion 4a.

[0101] Double-zone JTE structure 21 and n + The n-type channel stopper region 25 is selectively formed on the surface region of the n-type epitaxial layer 42 exposed on the second surface 40b of the front surface of the semiconductor substrate 40 in the edge termination region 20. + Type source area 5, p ++ Type contact area 6, p ++ Type outer peripheral contact region, double zone JTE structure 21 and n +The formation order of the channel stopper region 25 can be changed. Also, before the formation of the step 44 on the front surface of the semiconductor substrate 40, + Type source area 5, p ++ Type contact area 6 and p ++ A contact region may be formed on the outer periphery of the mold.

[0102] Next, a heat treatment is performed to activate the ion-implanted impurities in the epitaxial layers 42 and 43. This heat treatment may be performed each time a diffusion region is formed by ion implantation. Next, from the front surface of the semiconductor substrate 40, n + The p-type source region 5 and the p-type base region 4 are penetrated, + A gate trench 7 is formed opposite the mold region 11. Next, the gate insulating film 8, gate electrode 9, interlayer insulating film 14, source electrode 15, and drain electrode 16 are formed by a general method. After that, the semiconductor wafer (semiconductor substrate 40) is diced (cut) into individual chips to complete the silicon carbide semiconductor device 50 shown in Figures 1-4.

[0103] In the manufacturing method of the silicon carbide semiconductor device 50 according to Embodiment 1 described above, instead of the multi-stage epitaxial method, the trench-embedded epitaxial method may be used to form the first and second parallel pn layers 3a and 3b. When using the trench-embedded epitaxial method, trenches (SJ trenches) with the same depth as the length Z in the depth direction of the p-type column regions 32 and 34 are formed in the n-type epitaxial layer 42, leaving portions that become n-type column regions 31 and 33. These SJ trenches are then filled with p-type epitaxial layers that become p-type column regions 32 and 34 to form the first and second parallel pn layers 3a and 3b.

[0104] As described above, according to Embodiment 1, the n-type column region and the p-type column region of the edge termination region are arranged concentrically surrounding the active region, and the edge termination region has the same structure and is concentrically located at approximately the same distance from the outer periphery of the active region in the normal direction. Therefore, when the MOSFET is off, the electric field applied to the edge termination region can be distributed uniformly in the normal direction according to the distance from the outer periphery of the active region, thereby improving the breakdown voltage of the edge termination region. As a result, the location where avalanche breakdown occurs can be changed to the active region, which occupies a large area (surface area) of the semiconductor substrate, thereby improving the breakdown withstand capability.

[0105] Furthermore, according to Embodiment 1, the n-type column region and the p-type column region of the edge termination region are arranged concentrically surrounding the active region, so the double-zone JTE structure consists only of the portion parallel to the n-type column region and the p-type column region of the edge termination region, and has the same structure as the second parallel pn layer of the edge termination region. Therefore, even when a double-zone JTE structure is provided, the electric field applied to the edge termination region when the MOSFET is off can be distributed uniformly in the normal direction according to the distance from the outer periphery of the active region, thereby improving the breakdown voltage of the edge termination region.

[0106] (Embodiment 2) Next, the structure of the silicon carbide semiconductor device according to Embodiment 2 will be described. Figure 7 is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 2 as seen from the front side of the semiconductor substrate. Figure 8 is a cross-sectional view showing the cross-sectional structure at the cutting line D-D' in Figure 7. The cross-sectional structures at the cutting lines A-A', B-B', and C-C' in Figure 7 are the same as those in Figures 2-4, respectively. In Figure 7, the p-type linked region 61 is shown with different hatching than the p-type column regions 32 and 34.

[0107] The difference between the silicon carbide semiconductor device 60 according to Embodiment 2 and the silicon carbide semiconductor device 50 according to Embodiment 1 (see Figures 1-4) is that all p-type column regions 34 located outside the double-zone JTE structure 21 of the second parallel pn layer 3b are partially connected by p-type regions (hereinafter referred to as p-type connecting regions (second conductivity type connecting regions)) 61, and are electrically connected to the source electrode 15 via the p-type connecting regions 61.

[0108] In Embodiment 2, the p-type connecting region 61 is a double-zone JTE structure 21 and n + Between the channel stopper region 25 and n + The p-type linkage region 61 is provided separately from the type channel stopper region 25. The p-type linkage region 61 is located outside the double-zone JTE structure 21, between the second surface 40b of the front surface of the semiconductor substrate 40 and the second parallel pn layer 3b, and is in contact with the n-type column region 33 and the p-type column region 34 of the second parallel pn layer 3b.

[0109] The p-type connected region 61 is the p of the double-zone JTE structure 21. -- Outside of type region 23, p -- Adjacent to type region 23. p-type connected region 61, double-zone JTE structure 21 (p - type region 22, p -- Type region 23), p-type base extension portion 4a and p + All p-type column regions 34 located outside the double-zone JTE structure 21 are electrically connected to the source electrode 15 via the type extension portion 11a.

[0110] The impurity concentration in the p-type coupling region 61 is, for example, p + Mold extension part 11a, p - Type region 22 or p -- The impurity concentration is approximately the same as that of the type region 23. The p-type linking region 61 only needs to partially link all the p-type column regions 34 located outside the double-zone JTE structure 21 and electrically connect these p-type column regions 34 to the source electrode 15, and its arrangement and planar shape can be changed as appropriate.

[0111] For example, the p-type junction region 61 may be selectively provided at each of the four corners (near the vertices of the rectangle) of a semiconductor substrate 40 with a substantially rectangular planar shape. The p-type junction region 61 may extend linearly in the normal direction across all p-type column regions 34 located outside the double-zone JTE structure 21. The outer end of the p-type junction region 61 may be in contact with the outermost p-type column region 34 or terminate inside the outermost p-type column region 34.

[0112] The method for manufacturing the silicon carbide semiconductor device 60 according to Embodiment 2 is the same as the method for manufacturing the silicon carbide semiconductor device 50 according to Embodiment 1, but the p-type coupling region 61 is p + Mold extension part 11a, p - Type region 22 or p -- It should be formed at the same time as the mold region 23.

[0113] As described above, according to Embodiment 2, by partially connecting all p-type column regions located outside the double-zone JTE structure with the p-type connecting region, the same effects as in Embodiment 1 can be further obtained.

[0114] (Embodiment 3) Next, the structure of the silicon carbide semiconductor device according to Embodiment 3 will be described. Figure 9A is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 3. Figure 9A corresponds to the cross-sectional structure along the cutting line A-A' in Figure 1. Figure 9B is a characteristic diagram showing the relationship between the charge balance in the normal direction of the second parallel pn layer in Figure 9A and the breakdown voltage. The difference between the silicon carbide semiconductor device 70 according to Embodiment 3 and the silicon carbide semiconductor device 50 according to Embodiment 1 (see Figures 1-4) is that the width Wp12 in the short-side direction of the p-type column region 72 of the second parallel pn layer 71 in the edge termination region 20 is narrowed to the extent of the p-type column region 72 located on the outside.

[0115] In Embodiment 3, the second parallel pn layer 71 of the edge-terminal region 20 is formed by repeatedly arranging n-type column regions 33 and p-type column regions 72 concentrically adjacent to the active region 10. In the second parallel pn layer 71, the width Wn2 in the short direction is approximately the same for all n-type column regions 33, and the width Wp12 in the short direction becomes narrower for p-type column regions 72 located further out. The configuration of the second parallel pn layer 71, other than the width Wp12 in the short direction of the p-type column regions 72, is the same as that of the second parallel pn layer 3b in Embodiment 1.

[0116] The second parallel pn layer 71 is relatively p-rich on the inside and relatively n-rich on the outside. P-rich means that the charge amount, expressed as the product of the carrier concentration and the width in the short direction of the p-type column region, is greater than the charge amount, expressed as the product of the carrier concentration and the width in the short direction of the n-type column region. N-rich means that the charge amount, expressed as the product of the carrier concentration and the width in the short direction of the n-type column region, is greater than the charge amount, expressed as the product of the carrier concentration and the width in the short direction of the p-type column region.

[0117] By making the second parallel pn layer 71 relatively p-rich on the inside, the breakdown voltage can be reduced inside the edge termination region 20 compared to the outside, thus creating a structure that is more prone to avalanche yielding in the active region 10. Also, by making the second parallel pn layer 71 relatively n-rich on the outside, the p of the double-zone JTE structure 21 can be reduced. -- Type region 23 becomes more prone to depletion, p -- This makes it possible to suppress electric field concentration 52 (see Figure 5(a)) at the lower end corner of the outer part of the mold region 23.

[0118] Furthermore, in the second parallel pn layer 71, the charge balance between the n-type column region and the p-type column region 72 is maintained only at a predetermined location CB0 in the inner part. The region becomes p-richer as you move inward from CB0 and n-richer as you move outward. The breakdown voltage of the edge termination region 20 is highest at CB0, where the charge balance of the second parallel pn layer 71 is maintained, and decreases as you move inward (p-rich side) and outward (n-rich side) from CB0 (see Figure 9B).

[0119] Then, as the second parallel pn layer 71 becomes p-rich from CB0, where the charge balance is generally maintained, towards the inside (towards the active region 10), the n of the p-type column region 72 + Avalanche breakdown is predominantly observed at the end of the drain region 1, and the breakdown voltage drop from the generally balanced charge region CB0 becomes more gradual as one moves towards the p-rich side. As a result, the location of avalanche breakdown occurs in the active region 10 without excessively lowering the breakdown voltage of the active region 10, thus ensuring the breakdown voltage of the device itself.

[0120] Among the multiple p-type column regions 72 of the second parallel pn layer 71, the p of the double-zone JTE structure 21 - Type region 22 and p -- The configuration of the JTE boundary p-type column region 72a closest to the boundary 24 with the type region 23 is the same as that of the JTE boundary p-type column region 34a in Embodiment 1, except for the width Wp12 in the shorter direction. Embodiment 2 may be applied to the silicon carbide semiconductor device 70 according to Embodiment 3, so that all p-type column regions 72 located outside the double-zone JTE structure 21 are partially connected by p-type connecting regions 61 (see Figures 7 and 8).

[0121] The method for manufacturing the silicon carbide semiconductor device 70 according to Embodiment 3 is obtained by appropriately changing the opening pattern of the ion implantation mask for forming the p-type column regions 32 and 72 in the method for manufacturing the silicon carbide semiconductor device 50 according to Embodiment 1.

[0122] As described above, according to Embodiment 3, the width in the short direction of the p-type column region of the second parallel pn layer is narrowed as the p-type column regions are located on the outside. This suppresses electric field concentration in the double-zone JTE structure, making it possible to create a structure that is more prone to avalanche yielding in the active region, and thus further obtaining the same effects as in Embodiments 1 and 2.

[0123] Furthermore, according to Embodiment 3, the width in the short direction is narrower for p-type column regions located on the outside, so the effective concentration of p-type impurities in the second parallel pn layer decreases as you move outwards. Therefore, an effect similar to a spatially modulated JTE structure is expected, and the electric field is suppressed as you move outwards. This improves the breakdown voltage of the edge termination region.

[0124] A spatially modulated JTE structure is a p-type region with different impurity concentrations that concentrically surrounds the active region (p - type region, p -- This JTE structure is constructed by arranging multiple p-type regions such that the width in the normal direction becomes narrower as they are positioned further outwards, and the spacing between adjacent p-type regions widens towards the inside, thereby gradually decreasing the concentration of p-type impurities towards the outside.

[0125] (Embodiment 4) Next, the structure of the silicon carbide semiconductor device according to Embodiment 4 will be described. Figure 10 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 4. Figure 10 corresponds to the cross-sectional structure along the cutting line A-A' in Figure 1. The relationship between the charge balance in the normal direction of the second parallel pn layer and the breakdown voltage in Figure 10 is the same as in Figure 9B. The difference between the silicon carbide semiconductor device 80 according to Embodiment 4 and the silicon carbide semiconductor device 50 according to Embodiment 1 (see Figures 1-4) is that the width Wn12 in the short-side direction of the n-type column region 82 of the second parallel pn layer 81 in the edge termination region 20 is made wider, similar to the n-type column region 82 located on the outside.

[0126] In Embodiment 4, the second parallel pn layer 81 of the edge-terminal region 20 is formed by repeatedly arranging n-type column regions 82 and p-type column regions 34 concentrically adjacent to each other, surrounding the active region 10. In the second parallel pn layer 81, the width Wp2 in the short direction is approximately the same for all p-type column regions 34, and the width Wn12 in the short direction is wider for the n-type column regions 82 located further out. The configuration of the second parallel pn layer 81, other than the width Wn12 in the short direction of the n-type column regions 82, is the same as that of the second parallel pn layer 3b in Embodiment 1.

[0127] In other words, the spacing between adjacent p-type column regions 34 widens towards the outside. As a result, in Embodiment 4, similar to the second parallel pn layer 71 in Embodiment 3 (see Figures 9A and 9B), the second parallel pn layer 81 is relatively p-rich on the inside and relatively n-rich on the outside. Therefore, similar to Embodiment 3, it is possible to create a structure that is more prone to avalanche yielding in the active region 10. -- This makes it possible to suppress electric field concentration 52 (see Figure 5(a)) at the lower end corner of the outer part of the mold region 23.

[0128] Because the spacing between the outer p-type column regions 34 is as wide as the width Wp2 in the shorter direction, the effective p-type impurity concentration in the second parallel pn layer 81 decreases towards the outside. Therefore, similar to Embodiment 3, an effect like that of a spatially modulated JTE structure is expected, and the electric field is suppressed towards the outside. This improves the breakdown voltage of the terminal region.

[0129] By applying Embodiment 2 to the silicon carbide semiconductor device 80 according to Embodiment 4, a p-type connecting region 61 (see Figures 7 and 8) may be provided that partially connects all p-type column regions 34 located outside the double-zone JTE structure 21 of the second parallel pn layer 81.

[0130] The method for manufacturing the silicon carbide semiconductor device 80 according to Embodiment 4 is obtained by appropriately changing the aperture pattern of the ion implantation mask for forming the p-type column regions 32 and 34 in the method for manufacturing the silicon carbide semiconductor device 50 according to Embodiment 1.

[0131] As described above, according to Embodiment 4, the same effects as in Embodiment 3 can be obtained by increasing the spacing between adjacent p-type column regions in the second parallel pn layer as the distance increases towards the outside. Therefore, the same effects as in Embodiments 1 and 2 can be obtained even further.

[0132] In summary, the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of the invention. For example, when viewed from the front side of the semiconductor substrate, the first parallel pn layer of the active region may be arranged in a matrix of p-type column regions and n-type column regions arranged in a grid around the multiple p-type column regions. Furthermore, it is applicable not only to MOSFETs but also to silicon carbide semiconductor devices with various SJ structures in which the drift layer is a parallel pn layer. In addition, instead of a trench gate structure, a planar gate structure may be used in which an insulating gate is provided in a flat plate shape on the front surface of the semiconductor substrate. In the case of a planar gate structure, the portion between adjacent p-type base regions of the n-type column region of the first parallel pn layer becomes a JFET (Junction FET) region. Furthermore, the present invention also holds true when the conductivity type (n-type, p-type) is reversed. [Industrial applicability]

[0133] As described above, the silicon carbide semiconductor device according to the present invention is useful as a power semiconductor device used in power conversion devices, power supply devices for various industrial machines, and the like. [Explanation of Symbols]

[0134] 1 n + Type drain region 2 n-type buffer area 3,71,81 parallel pn layer 4 p-type base region 4a p type base extension 5 n + Type source area 6 p ++ Type Contact Area 7 Gate Trench 8 gate insulating film 9. Postal Service 10 Active area pp. 11, 12 + type area 11a p + Mold extension 14 Interlayer insulating film 15 Source electrodes 16 Drain electrode 20 Edge Termination Region 21. Double-zone JTE structure 22 p of double-zone JTE structure - type area 23 p of double-zone JTE structure -- type area 24 Double-zone JTE structure p - Type domain and p -- Boundary with type domain 25 n + Type channel stopper region 31,33,82 n-type column regions 32,34,72 p-type column regions 34a,72a JTE boundary p-type column region 35 Normal n-type drift region 40 Semiconductor substrates 40a~40c Front side of semiconductor substrate 41 n + Mold starting substrate 42 n-type epitaxial layer 43 p-type epitaxial layer 44 Steps on the front surface of the semiconductor substrate 50, 60, 70, 80 Silicon Carbide Semiconductor Devices 61 p-type connection region Wn1, Wn2, Wn12 n-type column region width in the short direction Wp1, Wp2, Wp12 p-type column area width in the short direction X First direction parallel to the front surface of the semiconductor substrate Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction. Z-direction (depth)

Claims

1. An active region provided on a semiconductor substrate made of silicon carbide, A terminal region surrounding the active region, In the active region, a first parallel pn layer is provided inside the semiconductor substrate, in which a first first conductivity type column region and a first second conductivity type column region are arranged alternately and repeatedly adjacent to each other, In the terminal region, a second parallel pn layer is provided inside the semiconductor substrate adjacent to the first parallel pn layer, in which a second first conductivity type column region and a second second conductivity type column region are arranged alternately and repeatedly adjacent to each other. A predetermined element structure is provided between the first main surface of the semiconductor substrate and the first parallel pn layer, A first electrode provided on the first main surface and electrically connected to the element structure, A second electrode provided on the second main surface of the semiconductor substrate, Equipped with, The second first conductivity type column region and the second second conductivity type column region are arranged concentrically and alternately adjacent to each other, surrounding the first parallel pn layer. Between the first main surface and the second parallel pn layer, A first second conductivity type region electrically connected to the first electrode, The current structure further comprises a pressure-resistant structure in which a second second conductivity type region, having a lower impurity concentration than the first second conductivity type region, is provided outside the first second conductivity type region and adjacent to the first second conductivity type region, and is arranged concentrically around the active region. A silicon carbide semiconductor device characterized in that the second conductivity type column region is electrically connected to the first electrode via the pressure-resistant structure.

2. An active region provided on a semiconductor substrate made of silicon carbide, A terminal region surrounding the active region, In the active region, a first parallel pn layer is provided inside the semiconductor substrate, in which a first first conductivity type column region and a first second conductivity type column region are arranged alternately and repeatedly adjacent to each other, In the terminal region, a second parallel pn layer is provided inside the semiconductor substrate adjacent to the first parallel pn layer, in which a second first conductivity type column region and a second second conductivity type column region are arranged alternately and repeatedly adjacent to each other. A predetermined element structure is provided between the first main surface of the semiconductor substrate and the first parallel pn layer, A first electrode provided on the first main surface and electrically connected to the element structure, A second electrode provided on the second main surface of the semiconductor substrate, Equipped with, The second first conductivity type column region and the second second conductivity type column region are arranged concentrically and alternately adjacent to each other, surrounding the first parallel pn layer. A pressure-resistant structure is provided between the first main surface and the second parallel pn layer, surrounding the periphery of the active region, A silicon carbide semiconductor device further comprising: a second conductivity type connecting region selectively provided in contact with the pressure-resistant structure between the first main surface and the second parallel pn layer on the outside of the pressure-resistant structure, and partially connecting all of the second conductivity type column regions located outside the pressure-resistant structure.

3. The pressure-resistant structure is Between the first main surface and the second parallel pn layer, A first second conductivity type region electrically connected to the first electrode, The silicon carbide semiconductor device according to claim 2, characterized in that a second second conductivity type region, having a lower impurity concentration than the first second conductivity type region, is provided outside the first second conductivity type region and adjacent to the first second conductivity type region, and is arranged concentrically surrounding the active region.

4. Among the plurality of second second conductivity type column regions, the boundary column region located closest to the boundary between the first second conductivity type region and the second second conductivity type region is: D1 is defined as the distance from the active region to the outer side surface of the boundary column region in the normal direction from the center of the semiconductor substrate outward. Let D2 be the distance from the active region to the boundary in the normal direction. When D3 is the distance from the active region to the inner side surface of the boundary column region in the normal direction, The silicon carbide semiconductor device according to claim 1 or 3, characterized in that it is positioned to satisfy D1 ≥ D2 > D3, or to satisfy D2 > D1 and D2 - D1 < 1 μm.

5. The silicon carbide semiconductor device according to claim 2 or 3, characterized in that the second second conductivity type column region is electrically connected to the first electrode via the pressure-resistant structure.

6. The silicon carbide semiconductor device according to any one of claims 1 to 5, characterized in that the portion of the second parallel pn layer located outside the breakdown structure reaches the first main surface and is exposed to the first main surface.

7. The silicon carbide semiconductor device according to any one of claims 1 to 6, characterized in that the width of the second second conductivity type column region is narrower in proportion to the second second conductivity type column region located on the outside.

8. A silicon carbide semiconductor device according to any one of claims 1 to 6, characterized in that the spacing between adjacent second conductivity type column regions is increased towards the outside.

9. The aforementioned device structure is A first semiconductor region of a second conductivity type is provided between the first main surface and the first parallel pn layer, A second semiconductor region of a first conductivity type is selectively provided between the first main surface and the first semiconductor region, A trench that penetrates the second semiconductor region and the first semiconductor region and reaches the first conductivity type column region, A gate electrode is provided inside the trench via a gate insulating film, Between the first semiconductor region and the first parallel pn layer, a second conductivity type high-concentration region with a higher impurity concentration than the first semiconductor region is selectively provided on the second electrode side of the bottom surface of the trench, The first electrode is electrically connected to the second semiconductor region, the first semiconductor region, and the second conductivity type high concentration region. The second conductivity type high-concentration region extends outward between the first main surface and the second parallel pn layer, is in contact with the second conductivity type column region in the depth direction, and is in contact with the pressure-resistant structure in the normal direction. The silicon carbide semiconductor device according to any one of claims 1 to 8, characterized in that the second conductivity type column region is electrically connected to the first electrode via the second conductivity type high concentration region, or via the second conductivity type high concentration region and the pressure-resistant structure.

10. The first conductivity type column region and the first second conductivity type column region are, They are arranged alternately and repeatedly adjacent to each other in a first direction parallel to the first main surface, The silicon carbide semiconductor device according to any one of claims 1 to 9, characterized in that it extends in a stripe-like manner in a second direction parallel to the first main surface and perpendicular to the first direction.

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