Method for manufacturing a wiring board, method for manufacturing a semiconductor device, and resin sheet

Abstract

This method for manufacturing a wiring board 20 comprises: a step for preparing a structure 1a in which a resin sheet 3, in which a glass cloth is disposed in an organic resin, is attached on a supporter 1 having a copper layer 2 on a surface thereof; a step for forming a recess section 7 by using excimer laser on the surface side of the resin sheet 3, that is, on a first resin layer region 4 in which the glass cloth is not present; a step for forming an opening section 8 extending from the surface of the resin sheet 3 to the copper layer 2 on the supporter 1; and a step for forming copper layers 10-12 in the recess section 7 and the opening section 8 to form a wiring layer 13.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a wiring board, a method for manufacturing a semiconductor device, and a resin sheet. More specifically, the present invention relates to a manufacturing method for efficiently and at low cost manufacturing a wiring board and a semiconductor device that are highly demanded for miniaturization or high density.

Background Art

[0002] For the purpose of increasing the density and performance of semiconductor packages, a mounting form in which chips with different performances are mixed and mounted in one package has been proposed, and a high-density interconnect technology between chips that is excellent in terms of cost has become important (see, for example, Patent Document 1).

[0003] Package-on-package that connects different packages on a package by laminating them by flip-chip mounting is widely adopted in smartphones and tablet terminals (see, for example, Non-Patent Document 1 and Non-Patent Document 2). Further, as a form for mounting at a higher density, package technologies using an organic substrate having high-density wiring (organic interposer), fan-out type package technology (FO-WLP) having through-molded vias (TMV), package technologies using a silicon or glass interposer, package technologies using silicon through electrodes (TSV), package technologies using chips embedded in a substrate for inter-chip transmission, and the like have been proposed.

[0004] Particularly in the case of an organic interposer or FO-WLP, when semiconductor chips are mounted in parallel, a fine wiring layer is required to conduct at a high density (see, for example, Patent Document 2). [[ID=​​​​​​​​​​​​​​U.S. Patent Application Publication No. 2001 / 0221071 [Non-patent literature]

[0006] [Non-Patent Document 1] Application of Through Mold Via (TMV) as PoP Base Package, Electronic Components and Technology Conference (ECTC), 2008 [Non-Patent Document 2] Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology, ECTC, 2012 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] The formation of the fine wiring layers described above requires a seed layer formation by sputtering, resist formation, electroplating, resist removal, and seed layer removal, resulting in a complicated manufacturing process. Therefore, a simpler method for forming fine wiring layers is desired.

[0008] Therefore, the present invention aims to provide a simplified method for forming a fine wiring layer. [Means for solving the problem]

[0009] The present invention relates, in one aspect, to a method for manufacturing a wiring board. This method for manufacturing a wiring board comprises the steps of: preparing a structure in which a resin sheet having glass cloth arranged in an organic resin is attached to a support having a metal layer on its surface or to a built-in wiring layer provided on the support; forming a recess in a first resin layer region on the surface side of the resin sheet where glass cloth is not present using an excimer laser; forming an opening from the surface of the resin sheet to the metal layer on the support; and forming a wiring layer in the recess and the opening.

[0010] In this method for manufacturing a wiring board, a resin sheet in which glass cloth is placed in an organic resin is used, and recesses are formed in the first resin layer region of the resin sheet where glass cloth is absent using an excimer laser, and a wiring layer is formed in these recesses. In this case, microfabrication of the recesses using an excimer laser becomes possible, and a fine wiring layer can be easily formed. In this manufacturing method, the step of forming the recesses and the step of forming the openings may be performed in either order, or they may be performed simultaneously. Furthermore, in this manufacturing method, plating may be used to form the wiring layer in the recesses and openings, or other methods may be used.

[0011] Another aspect of the present invention relates to another method for manufacturing a wiring board. This method for manufacturing a wiring board comprises the steps of: preparing a structure on which a resin sheet is attached, the resin sheet having a first resin layer region located on the outside and a high-elasticity layer region located on the inside and having a higher elastic modulus than the first resin layer region, in that order, on a support having a metal layer on its surface or on a built-in wiring layer provided on the support; forming a recess on the surface side of the resin sheet in the first resin layer region by laser or imprinting; forming an opening from the surface of the resin sheet to the metal layer on the support; and forming a wiring layer in the recess and the opening.

[0012] In this method for manufacturing a wiring board, a resin sheet is used, which has a first resin layer region and a high-elasticity layer region located on the outside. Recesses are formed in the first resin layer region of the resin sheet by laser or imprinting, and a wiring layer is formed in these recesses. In this case, microfabrication of the recesses by laser or imprinting becomes possible, and a fine wiring layer can be easily formed. In this manufacturing method, the step of forming the recesses and the step of forming the openings may be performed in any order, or they may be performed simultaneously. In addition, in this manufacturing method, plating may be used to form the wiring layer in the recesses and openings, or other methods may be used. Furthermore, in this manufacturing method, the high-elasticity layer region may be formed by arranging at least one of inorganic fibers and organic fibers in an organic resin material. The inorganic fibers may be at least one of glass fibers, ceramic fibers, and carbon fibers, and the organic fibers may be at least one of aramid fibers and polyethylene fibers.

[0013] In any of the above methods for manufacturing a wiring board, the thickness of the first resin layer region on the surface side of the resin sheet may be 20 μm or less. In this case, the layer region in which the fine wiring layer is formed can be made thinner, thereby reducing the height of the manufactured wiring board. In this case, the thickness of the first resin layer region may be 5 μm or more. This makes it possible to form recesses of appropriate depth and create fine wiring layers with excellent conductivity.

[0014] In any of the above methods for manufacturing a wiring board, the line width of the recess formed in the first resin layer region may be 0.5 μm or more and 5 μm or less. In this case, a fine wiring layer with excellent conductivity can be formed.

[0015] In any of the above methods for manufacturing a wiring board, the resin sheet has a second resin layer region on the side opposite to the first resin layer region, and in the step of preparing the structure, the resin sheet may be attached to the support or the built-in wiring layer by the second resin layer region to prepare the structure. In this case, the preparation of the structure can be carried out by a simple method such as lamination, and the manufacturing method can be simplified. Alternatively, in the step of preparing the structure, a structure in which the resin sheet is pre-attached to the support or the built-in wiring layer may be prepared and used in subsequent steps.

[0016] In any of the above methods for manufacturing a wiring board, when a recess is formed in the first resin layer region using an excimer laser, the pulse width of the excimer laser may be 10 nanoseconds or more and 50 nanoseconds or less, and the output of the excimer laser may be 10 mJ / pulse or more and 1000 mJ / pulse or less. In this case, finer recesses can be easily formed.

[0017] In any of the above methods for manufacturing a wiring board, in the step of forming the wiring layer, a plated metal layer is formed in the recesses and openings to form the wiring layer, and the resin sheet may contain a component consisting of a heteroaromatic ring that can form a coordination bond with the metal material constituting the seed layer for forming the plated metal layer. In this case, it becomes easier to form a finer wiring layer. The component consisting of a heteroaromatic ring that can form a coordination bond with the metal material constituting the seed layer may be, for example, at least one compound selected from the group consisting of maleimide compounds, bismaleimide compounds, triazole compounds, benzotriazole compounds, and benzoxazole compounds.

[0018] In any of the above methods for manufacturing a wiring board, the resin sheet or the coating layer covering the resin sheet may contain a laser light-absorbing coloring component consisting of at least one of an inorganic dye, an inorganic pigment, an organic dye, and an organic pigment. In this case, laser processing of recesses can be performed more reliably. The laser light-absorbing coloring component may be, for example, at least one of graphite, graphene, carbon nanotubes, carbon fibers, carbon black, phthalocyanine, cyanine, alkaline earth metals, and metal complexes.

[0019] In any of the above methods for manufacturing a wiring board, in the step of forming the wiring layer, a seed layer is provided in the recesses and openings by electroless plating to form a plated metal layer and then the wiring layer is formed, and the resin sheet may contain a catalyst for forming the electroless plating. In this case, it becomes easier to form a finer wiring layer. The catalyst for forming the electroless plating may be at least one of palladium particles, a palladium complex, copper particles, and a copper complex.

[0020] In any of the above methods for manufacturing a wiring board, the step of forming a wiring layer may include the steps of filling recesses and openings with conductive material and providing conductive material on the surface of the first resin layer region excluding the recesses and openings to form a conductive layer, and the step of flattening the conductivity. In the flattening step, at least a first portion of the conductive layer provided on the surface of the first resin layer region may be polished, and a wiring layer may be formed from a second portion of the conductive layer formed from the conductive material filled in the recesses and openings. In this case, fine wiring layers can be formed more efficiently.

[0021] The manufacturing method of any of the above wiring boards may further include a step of forming a built-in wiring portion having at least one built-in wiring layer on a support. In the step of preparing the structure, the attachment may be performed by attaching a resin sheet on the built-in wiring portion to prepare the structure. In this case, for example, a wiring board with an optimal layer configuration can be manufactured using different materials, such as forming the built-in wiring layer from a build-up material and forming the fine wiring layer on the surface from an organic resin material such as prepreg. Also, the design freedom of the wiring board can be increased.

[0022] The manufacturing method of any of the above wiring boards further includes a step of attaching another resin sheet on a resin sheet on which a wiring layer is formed, a step of forming another recess by laser on the first resin layer region of the other resin sheet, a step of forming another opening reaching the plating metal layer or the wiring layer of the opening from the surface of the other resin sheet, and a step of forming another plating metal layer in the other recess and the other opening to form another wiring layer. The steps of attaching another resin sheet, forming another recess, forming another opening, and forming another wiring layer may be repeated at least once or more. In this case, the manufacturing method of a wiring board having two or more fine wiring layers can be simplified.

[0023] In the manufacturing method of any of the above wiring boards, the step of forming a wiring layer may include a step of performing desmear treatment on at least the opening and the recess, a step of forming a seed layer by electroless plating on at least the opening and the recess, a step of performing electrolytic plating on the seed layer to form a plating metal layer, and a step of removing the seed layer and the plating metal layer on the surface of the first resin layer region so that the surface of the first resin layer region, the seed layer, and the plating metal layer are flattened. In this case, the conductive portion of the fine wiring layer can be formed more reliably.

[0024] As another aspect, the present invention relates to a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor device includes a step of preparing a wiring board manufactured by the method of manufacturing any of the above wiring boards, and a step of mounting a semiconductor element on a wiring layer or another wiring layer and electrically connecting the semiconductor element to the wiring layer or another wiring layer. In this case, a semiconductor device having a wiring board provided with a fine wiring layer can be manufactured by a simplified method. Further, since it is manufactured by a simplified method, it is also possible to improve the manufacturing yield or reduce the cost of the manufactured product. Furthermore, although not limited thereto, when mounting a plurality of semiconductor elements (chips) (especially when mounting them at high density), the semiconductor elements can be connected to each other by a fine wiring layer having excellent transmission characteristics, and a smaller semiconductor device with better performance can be provided.

[0025] As another aspect, the present invention relates to a resin sheet. The resin sheet is a resin sheet used in the method of manufacturing any of the above wiring boards, and includes an outer first resin layer region, and a high-elastic layer region located inside and having a higher elastic modulus than the first resin layer region, or a high-elastic layer region located inside and having a glass cloth. By providing such a resin sheet in advance, the method of manufacturing the above-described wiring board and the method of manufacturing the semiconductor device can be further simplified, and it becomes possible to improve the yield of the manufactured wiring board and semiconductor device or reduce the cost of the manufactured product.

[0026] The above resin sheet may further include a second resin layer region located on the opposite side of the first resin layer region via the high-elastic layer region, and the second resin layer region may have adhesiveness. In this case, it becomes possible to more easily form a structure including the resin sheet, and the method of manufacturing the above-described wiring board and the method of manufacturing the semiconductor device can be further simplified.

Effects of the Invention

[0027] According to the present invention, it is possible to provide a simplified method of manufacturing a wiring board and a semiconductor device provided with a fine wiring layer.

Brief Description of the Drawings

[0028] [Figure 1] Figures 1(a) to (d) show a part of the manufacturing method of a wiring board according to one embodiment of the present invention. [Figure 2] Figures 2(a) to 2(c) show a part of the manufacturing method of a wiring board according to one embodiment of the present invention, and are diagrams showing the process that follows the process in Figure 1. [Figure 3] Figure 3 shows an example of a semiconductor device in which semiconductor elements are mounted on a wiring board manufactured by the manufacturing methods shown in Figures 1 and 2. [Figure 4] Figure 4(a) shows a wiring board according to a modified example, and Figure 4(b) shows a semiconductor device according to a modified example. [Modes for carrying out the invention]

[0029] Embodiments of the present invention will be described in detail below with reference to the drawings. In the following description, the same or corresponding parts will be denoted by the same reference numerals, and redundant explanations will be omitted. Furthermore, unless otherwise specified, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings. Moreover, the dimensional ratios in the drawings are not limited to those shown.

[0030] Where terms such as "left," "right," "front," "back," "top," "bottom," "upper," and "downward" are used in this specification, they are for illustrative purposes only and do not necessarily imply that the relative position is permanent. Furthermore, the term "layer" includes not only structures formed across the entire surface when observed in a plan view, but also structures formed in only a portion of it. In this specification, the term "process" includes not only independent processes, but also processes that are not clearly distinguishable from others, as long as their intended function is achieved. Also, numerical ranges indicated using "~" represent a range that includes the numbers before and after "~" as the minimum and maximum values, respectively.

[0031] A method for manufacturing a wiring board and a semiconductor device according to one embodiment of the present invention will be described. The method for manufacturing a wiring board and a semiconductor device according to this embodiment is preferably applied to forms that require miniaturization and multi-pin configurations, but is not limited thereto. Furthermore, the manufacturing method according to this embodiment is preferably applied to package configurations that require an interposer for mounting different types of chips, but is not limited thereto. In the following description, for the sake of simplicity, the case in which one semiconductor element is mounted is described, but the same applies to configurations in which two or more (or two or more types) semiconductor elements are mounted.

[0032] <Structure preparation process> Figures 1 and 2 show a method for manufacturing a wiring board according to this embodiment. As shown in Figure 1(a), first, a structure 1a is prepared in which a resin sheet 3 is attached to a support 1 having a copper layer 2 (metal layer) on its surface. The resin sheet 3 is, for example, a sheet made by impregnating glass cloth with an organic resin, and has a first resin layer region 4 on the surface side where there is no glass sheet, a highly elastic layer region 5 located inside the first resin layer region 4, and a second resin layer region 6 located on the opposite side of the first resin layer region 4 via the highly elastic layer region 5 (glass cloth). The resin sheet 3 may be configured in which, for example, a highly elastic body such as glass cloth is arranged in an organic resin, or it may be configured in which both sides of the glass cloth are laminated with a resin sheet. The second resin layer region 6 is, for example, adhesive, and the resin sheet 3 is attached to the copper layer 2 of the support 1 by being attached via the second resin layer region 6. In the preparation step for structure 1a, the resin sheet 3 may be attached to the copper layer 2 on the support 1, or a structure 1a in which the resin sheet 3 is pre-attached to the support 1 via the copper layer 2 may be prepared and used.

[0033] The support 1 is not particularly limited, but for example, it may be a silicon plate, a glass plate, a SUS plate, a glass cloth-reinforced substrate, or a semiconductor element-reinforced encapsulated resin substrate, and is a substrate made of high rigidity. The thickness of the support 1 may be 0.2 mm or more and 2.0 mm or less. If the support 1 is 0.2 mm or more, handling can be improved, and if the support 1 is 2.0 mm or less, it is easier to reduce the height of the wiring board and it is possible to reduce material costs and thus reduce overall costs. The support 1 may be in the form of a wafer or a panel, and the size of the support 1 is not particularly limited. The support 1 may be a wafer with a diameter of 200 mm, a diameter of 300 mm, or a diameter of 450 mm, or a rectangular panel with sides of 300 mm or more and 700 mm or less.

[0034] The resin sheet 3 is a semi-cured film-like member, such as a prepreg. The organic resin material contained in the resin sheet 3 may include at least one of a thermosetting material and a thermoplastic material to ensure electrical insulation. The thermosetting material used here is, for example, epoxy resin, and the thermoplastic resin is, for example, acrylic resin, but is not limited to these. The organic resin material contained in the resin sheet 3 may be a film-like composite from the viewpoint of film thickness flatness and cost. The organic resin material may also contain a thermosetting material in order to form fine recesses. The size of the filler (filler) contained in the thermosetting material may be an average particle size of 500 nm or less. The thermosetting material does not have to contain fillers. The first resin layer region 4 and the second resin layer region 6 of the resin sheet 3 are formed from such organic resin material and are regions where glass cloth is absent. The first resin layer region 4 may have a film thickness of 20 μm or less, or 10 μm or less, in order to form a fine trench structure in the recess formation process described later. The thickness of the first resin layer region 4 may be 5 μm or more in order to ensure conductivity in the fine wiring structure.

[0035] The glass cloth contained in the resin sheet 3 is made of a woven or nonwoven fabric containing glass fibers. The glass fibers may be, for example, E-glass, S-glass, or quartz glass. The thickness of the glass cloth may be, for example, 0.01 μm or more and 0.2 μm or less. Such glass cloth is impregnated into the organic resin material described above to constitute the high-elasticity layer region 5. That is, the high-elasticity layer region 5 is made of glass cloth and organic resin material impregnated into or embedded in the glass cloth. Because the high-elasticity layer region 5 contains a rigid material such as glass, it is configured to have a higher elastic modulus, specifically Young's modulus, than the first resin layer region 4 and the second resin layer region 6. In addition, instead of glass fibers, at least one of other inorganic fibers and organic fibers may be impregnated into the organic resin material to form the high-elasticity layer region 5. Inorganic fibers may be, for example, ceramic fibers or carbon fibers, and organic fibers may be, for example, aramid fibers or polyethylene fibers.

[0036] The organic resin material contained in the resin sheet 3 may include components consisting of heteroaromatic rings that can form coordinate bonds with metals, such as maleimide compounds, bismaleimide compounds, triazole compounds, benzotriazole compounds, and benzoxazole compounds, in order to improve adhesion with the seed layer formed in a later process. The metal referred to here is the metal material that constitutes the seed layer. This component may also be included in the filler surface treatment agent. Furthermore, when the seed layer described later is formed by electroless plating, the resin sheet 3 may contain palladium particles, palladium complexes, copper particles, and copper complexes that act as catalysts in the electroless plating.

[0037] The resin sheet 3 may contain a laser light-absorbing coloring component, such as an inorganic dye or pigment like graphite, graphene, carbon nanotubes, carbon fiber, or carbon black, or an organic dye or pigment like phthalocyanine-based, cyanine-based, alkaline earth metal salts, or metal complexes, to enhance its absorption of laser light. This component may also be included in the filler surface treatment agent.

[0038] The resin sheet 3 has the configuration described above, and its thickness may be, for example, 10 μm or more and 100 μm or less. A thickness of 10 μm or more for the resin sheet 3 improves handling. Furthermore, a thickness of 100 μm or less for the resin sheet 3 allows the manufactured wiring board or semiconductor device to be packaged in a thin form.

[0039] The resin sheet 3 may be formed, for example, by impregnating glass cloth in an organic resin (varnish) to create a structure having a first resin layer region 4, a high-elasticity layer region 5, and a second resin layer region 6. Alternatively, it may be formed by placing glass cloth between the resin layer corresponding to the first resin layer region 4 and the resin layer corresponding to the second resin layer region 6 and then laminating or pressing. As a method for forming the resin sheet 3, such as lamination, vacuum lamination, roll lamination, vacuum roll lamination, atmospheric pressure pressing, or vacuum pressing can be used. When vacuum pressing is used, oxidation of the thermosetting material contained in the resin sheet 3 can be easily suppressed, and the film thickness flatness can be further improved. The temperature during the formation of the resin sheet 3 may be the temperature at which the thermosetting material contained in the resin sheet 3 heats up, for example, 100°C to 250°C. By setting the formation temperature to 100°C or higher, the tackiness of the organic resin material of the resin sheet 3 can be weakened, improving handling. By setting the formation temperature to 250°C or lower, warping of the resin sheet 3 can be suppressed.

[0040] Examples of such resin sheets 3 include "MCL-E-705G, 0.4mm or 0.6mm thick, 255mm square (manufactured by Hitachi Chemical Co., Ltd.)", "R-1766, 0.4mm or 0.6mm thick, 255mm square", "R-5715ES, 0.4mm or 0.6mm thick, 255mm square", "R-5670Kj, 0.4mm or 0.6mm thick, 255mm square (all manufactured by Panasonic Corporation)", or "GHPL830NS, 0.4mm or 0.6mm thick, 255mm square", "830NS, 0.4mm or 0.6mm thick, 255mm square", and "830NSF, 0.4mm or 0.6mm thick, 255mm square (all manufactured by Mitsubishi Gas Chemical Company, Inc.)".

[0041] A coating layer may also be provided on the surface of the resin sheet 3 (the side forming the recess). The coating layer may be, for example, an organic resin film containing polyethylene terephthalate (PET) resin, polyethylene naphthalate (PEN) resin, polyether ether ketone (PEEK) resin, polyimide (PI) resin, etc., or a metal foil such as Cu foil, Ni foil, or SUS foil. To enhance the absorption of laser light, the organic resin film constituting the coating layer may contain a laser light-absorbing coloring component consisting of an inorganic dye or inorganic pigment such as graphite, graphene, carbon nanotubes, carbon fiber, or carbon black, or an organic dye or organic pigment such as phthalocyanine-based, cyanine-based, alkaline earth metal salts, or metal complexes. Furthermore, the surface of the metal foil may be blackened.

[0042] <Process for forming recesses> Next, once the preparation process for structure 1a is complete, as shown in Figure 1(b), a plurality of recesses 7 are formed in the first resin layer region 4 on the surface side of the resin sheet 3 where glass cloth is not present, using an excimer laser. A recess 7 is a portion that is recessed in the thickness direction of the first resin layer region 4 relative to the surface of the first resin layer region 4, and includes the inner walls (side walls and bottom walls, etc.) of the recessed portion. The recesses 7 are formed like grooves with a width along the left-right direction shown in the figure and extending in the vertical direction shown in the figure, and have a shape corresponding to fine wiring in the planar direction. To form recesses in the first resin layer region 4 formed from a thermosetting material or thermoplastic material, from the viewpoint of miniaturization, processing may be done using an excimer laser, but processing using a carbon dioxide laser or UV-YAG laser, or imprinting may also be used.

[0043] In the recess formation process, the recess 7 may be formed such that the aperture width is 0.5 μm or more and 20 μm or less. From the viewpoint of miniaturization, the recess 7 may be formed such that the aperture width is 0.5 μm or more and 5 μm or less. This makes it possible to form a fine wiring layer and provide a high-density semiconductor device. To form recesses with such fine aperture widths, an excimer laser may be used as described above. The medium of the excimer laser used is argon-fluorine (ArF) or krypton-fluorine (KrF). From the viewpoint of versatility, an excimer laser with KrF as the medium may be used. Furthermore, as processing conditions with the excimer laser, the pulse energy may be 20 mJ or more and 100 mJ or less. The pulse repetition frequency may be 1 Hz or more and 4000 Hz or less. The pulse width may be 10 nanoseconds or more and 50 nanoseconds or less. The laser irradiation dose is greater than 0 and 1000 mJ / cm². 2 The following is also acceptable: The output power of the excimer laser may be between 10 mJ / pulse and 1000 mJ / pulse.

[0044] In the recess formation process, after forming the recess 7, the resin sheet 3 including the first resin layer region 4 may be further heat-cured. The heating temperature at this time may be between 100°C and 250°C, and the heating time may be between 30 minutes and 3 hours. Note that the recess 7 is configured so as not to reach the high-elasticity layer region 5.

[0045] <Process for forming openings> Next, once the formation of the recess 7 is complete, an opening 8 is formed from the surface of the resin sheet 3 to the copper layer 2 of the support 1, as shown in Figure 1(c). In the opening formation process, the opening 8 is formed by penetrating both the highly elastic layer region 5, which is composed of glass cloth, and the first resin layer region 4 and the second resin layer region 6, which are composed of organic resin material, in the resin sheet 3. As a method for forming the opening 8, for example, carbon dioxide laser processing or drilling can be used, but from the viewpoint of miniaturization, a carbon dioxide laser may be used.

[0046] In the aperture formation step, for example, an aperture 8 having an aperture diameter of 30 μm or more and 200 μm or less is formed. By forming an aperture 8 of such size, a semiconductor device that achieves high density can be provided, and a semiconductor device having a fine wiring layer can be manufactured with good yield and at low cost. The aperture formation step may be performed before, after, or simultaneously with the recess formation step described above, and the order is not particularly limited.

[0047] <The process of desmearing> Next, once the formation of the recess 7 and the opening 8 is complete, a desmearing step is performed to remove the smear formed by the laser aperture. A commercially available pretreatment solution and desmearing solution may be used as the desmearing solution. For example, a swelling solution (manufactured by Atotec Japan Co., Ltd., product name: Sweeling Dip Securigant) can be used as the pretreatment solution. For example, a roughening solution (manufactured by Atotec Japan Co., Ltd., product name: Concentrate Compact CP) can be used as the desmearing solution. For example, a neutralizing solution (manufactured by Atotec Japan Co., Ltd., product name: Reduction Securigant) can be used as the chemical solution used for neutralization after desmearing.

[0048] For the desmear treatment, the swelling conditions are that the temperature of the swelling solution is 50°C to 80°C, and the immersion time may be 1 minute to 30 minutes. After the swelling treatment, the recesses 7 and openings 8 may be washed with pure water or tap water. After the swelling treatment, a roughening treatment with desmear solution is performed. For the desmear conditions, the temperature of the desmear solution is 30°C to 80°C, and the immersion time may be 1 minute to 30 minutes. After the desmear treatment, the surface may be washed with pure water or tap water. After roughening with the desmear solution, a drag-out process is performed with pure water or tap water. The drag-out temperature is 25°C to 50°C, and the immersion time may be 1 minute to 5 minutes. After the drag-out, a neutralization process is performed. The neutralization temperature is 25°C to 50°C, and the immersion time may be 1 minute to 10 minutes. After the neutralization process, the surface may be washed with pure water or tap water. This completes the desmear treatment.

[0049] <Seed layer formation process> Once the desmearing process is complete, a seed layer 9 is formed on the surface of the first resin layer region 4, the side and bottom walls of the recess 7, the side walls of the opening 8, and the surface of the copper layer 2 exposed to the opening 8, as shown in Figure 1(d). In the seed layer formation process, the seed layer 9 can be formed using a copper paste method, a sputtering method, or an electroless plating method. An electroless plating method is suitable for panelization.

[0050] To form the seed layer 9, first, the surface of the first resin layer region 4, the side walls and bottom walls of the recess 7, the side walls of the opening 8, and the surface of the copper layer 2 exposed to the opening 8 (hereinafter also referred to as "the surface of the first resin layer region 4, etc.") are washed with a pretreatment solution in order to adsorb palladium, which serves as a catalyst for electroless copper plating, onto the surface of the first resin layer region 4, the side walls and bottom walls of the recess 7, the side walls of the opening 8, and the surface of the copper layer 2 exposed to the opening 8 (hereinafter also referred to as "the surface of the first resin layer region 4, etc."). The pretreatment solution is, for example, a commercially available alkaline pretreatment solution containing sodium hydroxide or potassium hydroxide. The pretreatment may be carried out with a concentration of sodium hydroxide or potassium hydroxide between 1% and 30%, an immersion time in the pretreatment solution between 1 minute and 60 minutes, and an immersion temperature in the pretreatment solution between 25°C and 80°C. After pretreatment, the surface may be washed with tap water, pure water, ultrapure water, or an organic solvent to remove excess pretreatment solution.

[0051] After removing the pretreatment solution, the surface of the first resin layer region 4 is immersed in an acidic aqueous solution to remove alkaline ions. The immersion cleaning may be carried out using a sulfuric acid aqueous solution as the acidic aqueous solution, with a concentration of 1% to 20% and an immersion time of 1 minute to 60 minutes. To remove the acidic aqueous solution, the surface may be washed with tap water, pure water, ultrapure water, or an organic solvent. After that, palladium is attached to the first resin layer region 4, etc., which has been immersed in the acidic aqueous solution. For palladium attachment, commercially available palladium-tin colloidal solutions, aqueous solutions containing palladium ions, or palladium ion suspensions may be used, but an aqueous solution containing palladium ions that effectively adsorb to the modified layer may also be used. When immersing in the aqueous solution containing palladium ions, the temperature of the aqueous solution containing palladium ions may be between 25°C and 80°C, and the immersion time for adsorption may be between 1 minute and 60 minutes. After adsorbing the palladium ions, the surface may be washed with tap water, pure water, ultrapure water, or an organic solvent to remove excess palladium ions.

[0052] Next, after adsorbing palladium ions, activation is performed to allow the palladium ions to act as a catalyst. A commercially available activator (activation treatment solution) may be used as the reagent to activate the palladium ions. The temperature of the activator used for immersion to activate the palladium ions is between 25°C and 80°C, and the immersion time may be between 1 minute and 60 minutes. After activating the palladium ions, the material may be washed with tap water, pure water, ultrapure water, or an organic solvent to remove excess activator. Subsequently, a seed layer 9 is formed by electroless plating using palladium as a catalyst. The seed layer 9 is an electroless plating layer selected from the group consisting of, for example, a copper layer, a nickel layer, a copper-nickel alloy layer, a nickel-phosphorus alloy layer, and a copper-nickel-phosphorus alloy layer. From a cost standpoint, the material of the seed layer 9 may be a copper layer.

[0053] When forming a copper layer as seed layer 9, a commercially available electroless plating solution can be used as the electroless plating solution. For example, an electroless copper plating solution (manufactured by Atotec Japan Co., Ltd., product name: Copper Solution Print Gant MSK) can be used. The electroless copper plating is formed in the electroless copper plating solution at a temperature between 20°C and 40°C. The thickness of seed layer 9 may be 0.1 nm to 500 nm, 0.1 nm to 400 nm, or 0.1 nm to 300 nm. By making the thickness of seed layer 9 0.1 nm or more, it becomes easier to form wiring with a uniform thickness in the subsequent electroplating. On the other hand, by making the thickness of seed layer 9 500 nm or less, excessive etching of the wiring can be prevented in the etching process of seed layer 9, and fine wiring can be formed with good yield.

[0054] After electroless plating, the surface may be washed with water or an organic solvent to remove excess plating solution. After electroless plating, thermosetting (annealing: age curing treatment by heating) may be performed to increase the adhesion between the seed layer 9 and the surface of the first resin layer region 4. The surface may be heated to a thermosetting temperature of 80°C to 200°C. To further accelerate the reactivity, the surface may be heated to a thermosetting temperature of 120°C to 200°C, or to a thermosetting temperature of 120°C to 180°C. The thermosetting time may be 5 minutes to 60 minutes, 10 minutes to 60 minutes, or 20 minutes to 60 minutes.

[0055] <Copper layer formation process> Once the seed layer formation process is complete, as shown in Figure 2(a), a step is performed to form copper layers 10, 11, and 12 (plated metal layer and conductive layer) on the seed layer 9 by electrolytic copper plating (conductive material). More specifically, a copper layer formed by electroless copper plating is used as the seed layer 9, and copper layers 10 to 12 are formed on it by electrolytic copper plating. In this embodiment, electrolytic copper plating is used as the method for forming copper layers 10 to 12, but other methods, such as electroless plating, may also be used.

[0056] In the copper layer formation process, copper layer 10 (second portion) is filled into recesses 7 provided on the surface of the first resin layer region 4, copper layer 11 (second portion) is filled into openings 8 provided from the surface of the first resin layer region 4 to copper layer 2, and copper layer 12 (first portion) is formed on the surface of the first resin layer region 4 excluding recesses 7 and openings 8. Because copper layer 10 is filled into recesses 7 and copper layer 11 is filled into openings 8, in subsequent processes, it becomes possible to flatten the copper layers 10 to 12 formed on the surface of the first resin layer region 4 and on recesses 7 and openings 8, respectively, simply by removing copper layer 12, seed layer, and palladium adsorption layer from the surface of the first resin layer region 4 excluding recesses 7 and openings 8, without removing the surface of the first resin layer region 4. After removing the copper layer, seed layer, and palladium adsorption layer, the surface of the first resin layer region 4 may be further scraped to flatten the surface of the first resin layer region 4 and the copper layers 10 and 11 formed in the recess 7 and opening 8, respectively.

[0057] To fill the recess 7 with a copper layer 10 or the opening 8 with a copper layer 11 by electrolytic copper plating, a so-called filled plating method may be used, in which the amount of electrolytic copper plating deposited in the recess 7 and the opening 8 is greater than that deposited on the surface of the first resin layer region 4 (plating thickness). The copper layers 10 and 11 do not necessarily have to be filled into the recess 7 or the opening 8, but may be formed along the inner walls (bottom walls and side walls) of the recess 7 or the opening 8. In this case, in addition to removing the copper layer 12, seed layer, and palladium adsorption layer from the surface of the first resin layer region 4 excluding the recess 7 and the opening 8, the surface of the first resin layer region 4 can be further scraped to expose the copper layer 10 in the recess 7 (bottom wall of the recess 7) and the copper layer 11 in the opening 8, thereby making it possible to flatten the surface of the first resin layer region 4 and the copper layers 10 to 12 formed in the recess 7 and the opening 8.

[0058] <Process for forming wiring layers> Next, once the formation of the copper layer is complete, as shown in Figure 2(b), a process is performed to form a wiring layer 13 consisting of the copper layer 10 formed in the recesses 7 and the copper layer 11 formed in the openings 8 by removing the copper layer 12, seed layer, and palladium catalyst from the surface of the first resin layer region 4, excluding the recesses 7 and openings 8. That is, by removing the copper layer 12, seed layer, and palladium adsorption layer from the surface of the first resin layer region 4, the copper layers 10 and 11 (specifically, including the seed layer and palladium adsorption layer corresponding to the copper layers 10 and 11) remain only in the recesses 7 and openings 8 on the surface of the first resin layer region 4, including the recesses 7, and the copper layers 10 and 11 in the recesses 7 and openings 8 form the wiring layer 13. The main part of the wiring layer 13 is formed from the copper layers 10 formed in the multiple recesses 7. The wiring layer 13 is connected to the connection terminals of the semiconductor element 22, which will be described later.

[0059] When removing the copper layer 12, seed layer, and palladium adsorption layer from the surface of the first resin layer region 4, excluding the recess 7, the surface of the first resin layer region 4 and the copper layer 10 formed in the recess 7 may be flattened. Furthermore, when removing the copper layer 12, seed layer, and palladium adsorption layer from the upper part of the first resin layer region 4, a portion in the thickness direction may be removed from the upper (surface) side of the first resin layer region 4. As a method for removing the copper layer 12, seed layer, palladium adsorption layer, and the first resin layer region 4 from the upper part of the first resin layer region 4, back grinding, fly cutting, or chemical mechanical polishing (CMP) can be used. Multiple removal methods may also be used in combination. For example, in the fly cutting method, a grinding device using a diamond bit can be used. A specific example is an automatic surface planer compatible with 300mm wafers (manufactured by DISCO Corporation, product name "DAS8930"). The removal of the metal layer and palladium adsorption layer by the fly-cut method involves uniformly polishing the entire surface from the upper side (surface side) of the first resin layer region 4, resulting in a flat polished surface. Therefore, it can also be considered a planarization treatment.

[0060] When polishing by chemical mechanical polishing (CMP), a CMP polishing system compatible with 300mm wafers (manufactured by Applied Materials, product name "F-REX300X") can be used as a specific example. During CMP polishing, polishing can be performed using a polishing solution containing abrasive components such as silica, alumina, and ceria. Multiple polishing solutions may be used in combination or sequentially. After polishing, polishing debris and excess abrasive particles may be removed with a cleaning solution such as pure water or a solvent.

[0061] In order to facilitate the adsorption of palladium onto the seed layer and copper layer 10 during the next step of electroless plating, the copper layer 12 above the first resin layer region 4, the seed layer, the palladium adsorption layer, and the first resin layer region 4 may be removed, and then the exposed surfaces of the seed layer and copper layers 10 and 11 may be roughened chemically or physically.

[0062] <The process of capping> Next, once the wiring layer formation process is complete, as shown in Figure 2(c), cap plating 14 and 15 may be formed on the exposed seed layer, copper layers 10 and 11 (wiring layer 13), and palladium adsorption layer by electroless plating. As the metal species for cap plating 14 and 15, a metal containing one of Cu, Ni, Cr, or W may be used. Through this process, a wiring substrate 20 having fine wiring layers 13 is manufactured.

[0063] <Manufacturing method for semiconductor devices> Next, as shown in Figure 3, a semiconductor element 22 is mounted on a wiring layer 13 on a wiring substrate 20, and the connection terminals of the semiconductor element 22 are electrically connected to the wiring layer 13. This creates a semiconductor device 25 connected by fine wiring layers 13.

[0064] In the manufacturing method of the wiring substrate and semiconductor device according to this embodiment, a resin sheet 3 in which glass cloth is placed in an organic resin is used, and recesses 7 are formed in the first resin layer region 4 in the resin sheet 3 where glass cloth is not present using an excimer laser, and a wiring layer 13 is formed in the recesses 7 and the like. In this case, microfabrication of the recesses 7 by laser becomes possible, and a fine wiring layer can be easily formed.

[0065] In the manufacturing method of the wiring substrate and semiconductor device according to this embodiment, the thickness of the first resin layer region 4 on the surface side of the resin sheet 3 may be 20 μm or less. In this case, the layer region in which the fine wiring layer 13 is formed can be made thinner, thereby reducing the height of the manufactured wiring substrate 20. Alternatively, in this manufacturing method, the thickness of the first resin layer region 4 may be 5 μm or more. This allows for the formation of recesses 7 of appropriate depth, thereby forming fine wiring layers 13 with excellent conductivity.

[0066] In the method for manufacturing the wiring substrate and semiconductor device according to this embodiment, the line width of the recess 7 formed in the first resin layer region 4 may be 0.5 μm or more and 5 μm or less. In this case, a fine wiring layer 13 with excellent conductivity can be formed.

[0067] In the manufacturing method for the wiring board and semiconductor device according to this embodiment, the resin sheet 3 has a second resin layer region 6 on the side opposite to the first resin layer region 4, and in the process of preparing the structure, the structure 1a is prepared by attaching the resin sheet 3 to the support 1 by the second resin layer region 6. In this case, the preparation of the structure 1a can be carried out by a simple method such as lamination, and the manufacturing method can be simplified.

[0068] In the manufacturing method of the wiring substrate and semiconductor device according to this embodiment, the step of forming the plating layer includes a step of performing a desmear treatment on the recess 7 and the opening 8 and the surface of the first resin layer region; a step of forming a seed layer 9 on the recess 7 and the opening 8 and the surface of the first resin layer region by electroless plating; a step of forming copper layers 10 to 12 by electroplating on the seed layer 9; and a step of removing the seed layer 9 and copper layers 10 to 12 from the surface of the first resin layer region 4 so that the surface of the first resin layer region 4, the seed layer 9 and the copper layers 10 to 12 become flat. This makes it possible to more reliably form conductive portions of the fine wiring layer 13.

[0069] Furthermore, in the semiconductor device manufacturing method according to this embodiment, a semiconductor device 25 having a wiring substrate 20 equipped with a fine wiring layer 13 can be manufactured in a simplified manner by the various methods described above. In addition, because it is manufactured in a simplified manner, it is possible to improve the manufacturing yield or reduce the cost of the manufactured product. Moreover, although not limited to this, when mounting multiple semiconductor elements (chips) (especially when mounting at high density), the semiconductor elements can be connected to each other with fine wiring layers that have excellent transmission properties, making it possible to provide a smaller semiconductor device with better performance.

[0070] The resin sheet 3 according to this embodiment comprises a first resin layer region 4 located on the outside and a high-elasticity layer region 5 located on the inside with a higher elastic modulus than the first resin layer region 4. By prefabricating such a resin sheet 3, the manufacturing method of the wiring board and the semiconductor device described above can be simplified, making it possible to improve the yield of the manufactured wiring board 20 and semiconductor device 25 or reduce the cost of the manufactured products.

[0071] The resin sheet 3 according to this embodiment further comprises a second resin layer region 6 located on the opposite side of the first resin layer region 4 via a high-elasticity layer region 5, and the second resin layer region 6 is adhesive. Therefore, it becomes possible to form the structure 1a including the resin sheet 3 more easily, and the manufacturing method of the wiring board 20 and the semiconductor device 25 described above can be further simplified.

[0072] Although embodiments of the present invention have been described in detail above, the present invention is not limited to the above embodiments and can be applied to various embodiments. For example, in the above embodiments, as shown in Figures 1 to 3, a semiconductor device 25 was manufactured by providing one wiring layer 13 and arranging a semiconductor element 22 on it, but there may be two or more wiring layers 13. In this case, after performing the wiring layer 13 formation process shown in Figure 2(b), the wiring layer 13 may be further multilayered by repeating one or more steps: attaching another resin sheet 3 to the first resin layer region 4 on which the wiring layer 13 is formed by bonding, forming another recess 7 in the first resin layer region 4 of the other resin sheet 3, forming another opening 8 in the other resin sheet 3, and forming another wiring layer 13 in the other recess 7 and the other opening 8. When multilayering, the other opening 8 is formed so that it extends from the surface side of the other resin sheet 3 to the copper layer 11 or wiring layer 13 of the inner opening 8. This makes it possible to obtain a wiring substrate and a semiconductor device with fine wiring layers 13 multilayered.

[0073] Furthermore, as shown in Figure 4(a), a multilayer wiring substrate 30 may be formed by providing one or more built-in wiring layers 31 on a support 1 to form a built-in wiring section, attaching a resin sheet 3 on top of it by bonding or other means, and performing the steps of forming a recess 7, forming an opening 8, and forming a wiring layer 13. Then, as shown in Figure 4(b), a semiconductor element 32 may be mounted on the multilayer wiring substrate 30 to form a semiconductor device 35. In this case, the built-in wiring layer 31 can be formed using a build-up method. This makes it possible to multilayer the built-in wiring layer 31 using a conventional method, and to make only the wiring layer 13 on the surface (i.e., the connection part with the semiconductor element) a finer wiring layer. In this case, for example, the built-in wiring layer 31 may be made from a build-up material, and the fine wiring layer 13 on the surface may be formed by laser processing an organic resin material such as a prepreg to form a recess, thereby creating a wiring substrate with an optimal configuration using different materials. Furthermore, according to the manufacturing method related to such modifications, the design freedom of the wiring substrate can be increased. [Explanation of symbols]

[0074] 1...Support, 1a...Structure, 2...Copper layer (metal layer), 3...Resin sheet, 4...First resin layer region, 5...High elasticity layer region, 6...Second resin layer region, 7...Recess, 8...Opening, 9...Seed layer, 10,11...Copper layer (plated metal layer, second part), 12...Copper layer (first part), 13...Wiring layer, 14,15...Cap plating, 20...Wiring substrate, 22...Semiconductor element, 25...Semiconductor device, 30...Wiring substrate, 31...Built-in wiring layer, 32...Semiconductor element, 35...Semiconductor device.

Claims

1. A step of preparing a structure in which a resin sheet having glass cloth arranged in organic resin is attached to a support having a metal layer on its surface or to a built-in wiring layer provided on the support, A step of forming a recess with an aperture width of 0.5 μm or more and 20 μm or less in a first resin layer region on the surface side of the resin sheet where the glass cloth is not present, using an excimer laser, wherein the recess is formed so as not to reach the region where the glass cloth is present. A step of forming an opening from the surface of the resin sheet to the metal layer on the support, the opening having a diameter of 30 μm or more and 200 μm or less, A step of forming a wiring layer in the recess and the opening, A method for manufacturing a wiring board, comprising:

2. The medium of the excimer laser is argon-fluorine (ArF) or krypton-fluorine (KrF). A method for manufacturing a wiring board according to claim 1.

3. A step of preparing a structure in which a resin sheet is attached to a support having a metal layer on its surface or to an internal wiring layer provided on the support, the resin sheet having a first resin layer region located on the outside and a high-elasticity layer region located on the inside with a higher elastic modulus than the first resin layer region, in that order, A step of forming a recess on the surface side of the resin sheet in the first resin layer region, wherein the recess has an opening width of 0.5 μm or more and 20 μm or less by laser or imprinting, wherein the recess is formed so as not to reach the high-elasticity layer region. A step of forming an opening from the surface of the resin sheet to the metal layer on the support, the opening having a diameter of 30 μm or more and 200 μm or less, A step of forming a wiring layer in the recess and the opening, A method for manufacturing a wiring board, comprising:

4. The aforementioned highly elastic layer region is formed by arranging at least one of inorganic fibers and organic fibers in an organic resin material. A method for manufacturing a wiring board according to claim 3.

5. The inorganic fiber is at least one of glass fiber, ceramic fiber, and carbon fiber, and the organic fiber is at least one of aramid fiber and polyethylene fiber. The method for manufacturing a wiring board according to claim 4.

6. The thickness of the first resin layer region on the surface side of the resin sheet is 5 μm or more and 20 μm or less. A method for manufacturing a wiring board according to any one of claims 1 to 5.

7. The resin sheet has a second resin layer region on the side opposite to the first resin layer region. In the step of preparing the structure, the resin sheet is attached to the support or the built-in wiring layer by the second resin layer region to prepare the structure. A method for manufacturing a wiring board according to any one of claims 1 to 6.

8. In the case where the recess is formed in the first resin layer region by an excimer laser, the pulse width of the excimer laser is 10 nanoseconds or more and 50 nanoseconds or less, and the output of the excimer laser is 10 mJ / pulse or more and 1000 mJ / pulse or less. A method for manufacturing a wiring board according to any one of claims 1 to 7.

9. In the step of forming the wiring layer, a plated metal layer is formed in the recess and the opening to form the wiring layer. The resin sheet contains a component consisting of a heteroaromatic ring capable of coordinating with the metal material constituting the seed layer for forming the plated metal layer. A method for manufacturing a wiring board according to any one of claims 1 to 8.

10. The resin sheet or the coating layer covering the resin sheet contains a laser light absorbing coloring component consisting of at least one of an inorganic dye, an inorganic pigment, an organic dye, and an organic pigment. A method for manufacturing a wiring board according to any one of claims 1 to 9.

11. In the process of forming the wiring layer, a seed layer is provided in the recess and the opening by electroless plating to form a plated metal layer and thus form the wiring layer. The resin sheet contains a catalyst for forming the electroless plating. A method for manufacturing a wiring board according to any one of claims 1 to 10.

12. The step of forming the wiring layer is, A step of filling the recesses and openings with a conductive material and providing a conductive material on the surface of the first resin layer region excluding the recesses and openings to form a conductive layer, The process includes a step of planarizing the conductive layer, In the planarization step, at least a first portion of the conductive layer provided on the surface of the first resin layer region is polished, and the wiring layer is formed from a second portion of the conductive layer formed from the conductive material filling the recess and the opening. A method for manufacturing a wiring board according to any one of claims 1 to 11.

13. The process further comprises forming an internal wiring section having at least one internal wiring layer on the support, The process of preparing the aforementioned structure involves attaching the resin sheet to the built-in wiring section to prepare the structure. A method for manufacturing a wiring board according to any one of claims 1 to 12.

14. A step of attaching another resin sheet on the resin sheet on which the wiring layer is formed, A step of forming another recess in the first resin layer region of the aforementioned other resin sheet using a laser, A step of forming another opening from the surface of the other resin sheet to the plated metal layer or the wiring layer of the opening, The process further comprises the step of forming another plating metal layer in the other recess and the other opening to form another wiring layer, The steps of attaching the other resin sheet, forming the other recess, forming the other opening, and forming the other wiring layer are repeated at least once. A method for manufacturing a wiring board according to any one of claims 1 to 13.

15. The step of forming the wiring layer is, A step of performing desmear treatment on at least the opening and the recess, A step of forming a seed layer on at least the opening and the recess by electroless plating, A step of forming a plated metal layer by performing electroplating on the seed layer, The process includes a step of removing the seed layer and the plated metal layer from the surface of the first resin layer region so that the surface of the first resin layer region, the seed layer and the plated metal layer become flat. A method for manufacturing a wiring board according to any one of claims 1 to 14.

16. A step of preparing a wiring board manufactured by the wiring board manufacturing method described in any one of claims 1 to 15, A step of mounting a semiconductor element on the aforementioned wiring layer or another wiring layer, and electrically connecting the semiconductor element to the aforementioned wiring layer or the other wiring layer, A method for manufacturing semiconductor devices.

17. A semiconductor device having a structure manufactured using the manufacturing method described in claim 16.

18. A resin sheet used in a method for manufacturing a wiring board according to any one of claims 1 to 15, comprising: a first resin layer region located on the outside; and a high-elasticity layer region located on the inside with a higher elastic modulus than the first resin layer region, or a high-elasticity layer region located on the inside having glass cloth.

19. The first resin layer region is further comprising a second resin layer region located on the opposite side of the high-elasticity layer region, wherein the second resin layer region is adhesive. The resin sheet according to claim 18.

20. The first resin layer region comprises at least one compound selected from the group consisting of maleimide compounds, bismaleimide compounds, triazole compounds, benzotriazole compounds, and benzoxazole compounds. The resin sheet according to claim 18 or 19.

21. The first resin layer region includes graphite, graphene, carbon nanotubes, carbon fibers, carbon black, phthalocyanine, cyanine, alkaline earth metals, and at least one of a metal complex. A resin sheet according to any one of claims 18 to 20.

22. The first resin layer region includes at least one of palladium particles, a palladium complex, copper particles, and a copper complex. A resin sheet according to any one of claims 18 to 21.

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