Semiconductor devices and semiconductor modules

Abstract

Provided is a semiconductor device comprising: a semiconductor substrate having an active part on which a transistor section is provided; an emitter electrode provided above the front surface of the semiconductor substrate; and a protective film provided above the emitter electrode. The active part is provided with a first electrically conductive-type emitter region provided on the front surface of the semiconductor substrate, a second electrically conductive-type contact region, and a plurality of trench parts. The emitter electrode has an exposed part that is not covered by the protective film. In the region in which the exposed part is provided, the active part has a first region, and a second region that is provided in the outer periphery of the first region and has a lower channel density than the first region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a semiconductor module.

Background Art

[0002] Patent Document 1 describes using a solder joint to electrically connect an element electrode and a lead terminal with a connecting conductor. [Prior Art Document] [Patent Document] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-38140

Summary of the Invention

Problems to be Solved by the Invention

[0003] During the operation of the transistor section, it is required to suppress local concentration of current.

Means for Solving the Problems

[0004] In a first aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having an active portion provided with a transistor section, an emitter electrode provided above the front surface of the semiconductor substrate, and a protective film provided above the emitter electrode. The active portion has an emitter region of a first conductivity type, a contact region of a second conductivity type, and a plurality of trench portions provided on the front surface of the semiconductor substrate. The emitter electrode has an exposed portion not covered by the protective film. The active portion has a first region and a second region provided on the outer periphery of the first region and having a lower channel density than the first region in a region where the exposed portion is provided.

[0005] In a top view of the semiconductor substrate, the second region may be provided surrounding the entire outer periphery of the first region.

[0006] In a top view of the semiconductor substrate, the area of the first region may be 0.5 times or more and 10 times or less the area of the second region.

[0007] In a top view of the semiconductor substrate, the first region may be spaced at least 0 μm and no more than 1500 μm from the edge of the exposed portion.

[0008] The channel density of the mesa portion of the transistor in the second region may be smaller than the channel density of the mesa portion of the transistor in the first region.

[0009] The emitter region and the contact region are alternately provided in the trench extension direction in the mesa portion of the transistor portion, and in a top view of the semiconductor substrate, the ratio of the emitter region to the contact region in the mesa portion of the transistor portion in the first region may be greater than the ratio of the emitter region to the contact region in the mesa portion of the transistor portion in the second region.

[0010] In a top view of the semiconductor substrate, the trench extension length of the contact region provided in the mesa portion of the transistor portion in the second region may be greater than the trench extension length of the contact region provided in the mesa portion of the transistor portion in the first region.

[0011] In a top view of the semiconductor substrate, the emitter region of the transistor in the second region may be provided in correspondence with the emitter region of the transistor in the first region in the trench arrangement direction, and in a top view of the semiconductor substrate, the emitter region of the transistor in the first region may be provided in correspondence with either the emitter region or the contact region of the transistor in the second region in the trench arrangement direction.

[0012] The channel density of the mesa portion of the transistor in the second region may be 50% or less of the channel density of the mesa portion of the transistor in the first region.

[0013] The active portion has diode portions arranged alternately with the transistor portions in the trench arrangement direction, and in a top view of the semiconductor substrate, the ratio of the diode portions to the transistor portions in the second region may be greater than the ratio of the diode portions to the transistor portions in the first region.

[0014] In a top view of the semiconductor substrate, the area of ​​the transistor portion in the second region may be larger than the area of ​​the diode portion.

[0015] In a second embodiment of the present invention, a semiconductor module is provided that comprises a semiconductor device according to any of the first embodiments.

[0016] The semiconductor module may include a solder portion provided above the emitter electrode, and a lead frame provided on the solder portion and electrically connected to the emitter electrode.

[0017] In a top view of the semiconductor substrate, the boundary between the first region and the second region may be located inward from the end of the lead frame.

[0018] The distance between the boundary between the first region and the second region and the end of the lead frame may be 400 μm or more and 800 μm or less.

[0019] The outer peripheral edge of the second region may be located outside the edge of the solder portion.

[0020] The distance between the outer edge of the second region and the edge of the solder portion may be 0 μm or more and 1500 μm or less.

[0021] It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0022] [Figure 1] It is a top view showing an example of the semiconductor device 100 according to the embodiment. [Figure 2] It is an example of an enlarged view of the active part 120. [Figure 3] It is a view showing an example of the a-a cross section in FIG. 2. [Figure 4] It is a view showing an example of the configuration of the first region 121 and the second region 122. [Figure 5] It is a top view showing an example of the mesa part 60. [Figure 6] It is another example of an enlarged view of the active part 120. [Figure 7] It is a view showing an example of the b-b cross section in FIG. 6. [Figure 8] It is a view showing an example of the arrangement of the transistor part 70 and the diode part 80. [Figure 9] It is a top view showing an example of the semiconductor module 300 according to the embodiment. [Figure 10] It is a side view of the semiconductor substrate 10 in a state of being mounted on the mounting substrate 200.

Mode for Carrying Out the Invention

[0023] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments patent do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0024] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of the substrate, layer or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction at the time of mounting the semiconductor device.

[0025] In this specification, technical matters may be described using the Cartesian coordinate axes X, Y, and Z. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z axis and the -Z axis. Also in this specification, viewing from the +Z axis direction may be referred to as a top view.

[0026] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0027] In this specification, the conductivity type of a doped region containing impurities is described as P-type or N-type. However, the conductivity types of each doped region may have opposite polarities. Furthermore, in this specification, when P+-type or N+-type is mentioned, it means that the doping concentration is higher than that of P-type or N-type, and when P--type or N--type is mentioned, it means that the doping concentration is lower than that of P-type or N-type.

[0028] In this specification, doping concentration refers to the concentration of an impurity activated as a donor or acceptor. In this specification, the concentration difference between the donor and acceptor may be taken as the concentration of the greater of the two. This concentration difference can be measured by the voltage-capacitance (CV) method. Alternatively, the carrier concentration measured by the spreading resistance (SR) method may be taken as the concentration of the donor or acceptor. Furthermore, if the concentration distribution of the donor or acceptor has a peak, the peak value may be taken as the concentration of the donor or acceptor in that region. In cases where the concentrations of the donor or acceptor are nearly uniform in a region where the donor or acceptor is present, the average value of the donor or acceptor concentrations in that region may be taken as the donor or acceptor concentration.

[0029] Figure 1 is a top view showing an example of a semiconductor device 100 according to an embodiment. The semiconductor device 100 comprises a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material such as silicon or a compound semiconductor. The semiconductor substrate 10 has edges 102 when viewed from above. In this example, the semiconductor substrate 10 has two pairs of edges 102 that face each other when viewed from above. In Figure 1, a pair of opposing first edges 102-1 and second edges 102-2 are shown. In Figure 1, the direction parallel to the first edges 102-1 and second edges 102-2 is the Y-axis direction, and the direction perpendicular to the first edges 102-1 and second edges 102-2 is the X-axis direction.

[0030] The semiconductor substrate 10 is provided with an active section 120. The active section 120 is a region in which the main current flows in the depth direction between the front and back surfaces of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be ON. In this example, the region corresponding to the emitter electrode 52 is defined as the active section 120. The active section 120 may be provided with a transistor section including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor). The active section 120 may also be provided with a diode section including a diode element such as an FWD (Freewheeling Diode).

[0031] The semiconductor device 100 includes an emitter electrode 52 and a pad 50 provided on the upper side of the front surface of the semiconductor substrate 10. The emitter electrode 52 and pad 50 are electrodes containing a metal such as aluminum. An insulating film is provided between the emitter electrode 52 and pad 50 and the semiconductor substrate 10. The emitter electrode 52 and pad 50 and the semiconductor substrate 10 are connected via contact holes provided in the insulating film. In Figure 1, the insulating film and contact holes are omitted.

[0032] The emitter electrode 52 is positioned above the active portion 120. The emitter electrode 52 is connected to the active portion 120 via the contact hole described above. The emitter electrode 52 has an exposed portion 53 that is not covered by the protective film described later. The exposed portion 53 is a region that includes the central Ac of the active portion 120. The central Ac of the active portion 120 is the geometric centroid of the active portion 120 in a top view. A lead frame, described later, is positioned on the upper surface of the exposed portion 53. The emitter electrode 52 is electrically connected to the lead frame, and a predetermined emitter voltage is applied.

[0033] The emitter electrode 52 is formed from a material containing metal. For example, at least a portion of the emitter electrode 52 is formed from aluminum or an aluminum-silicon alloy. The emitter electrode 52 may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum or the like. The emitter electrode 52 may further have a plug made of tungsten or the like that is filled in the contact hole so as to be in contact with the barrier metal and the aluminum or the like. A plating layer may be provided on the upper surface of the emitter electrode 52. The plating layer may be made of a different metallic material from the emitter electrode 52, such as nickel or gold.

[0034] Pad 50 is, for example, a gate pad. The emitter electrode 52 and pad 50 are provided separated from each other in a top view. A wire or the like is connected to the top surface of pad 50, and a predetermined gate voltage is applied. The gate voltage applied to pad 50 is supplied to the transistor section of the active section 120 by a gate runner or the like, which will be described later. Pad 50 in this example is, 1 It is located near edge 102-1.

[0035] In addition to the configuration of the semiconductor device 100, it is further equipped with an anode pad 174, a cathode pad 176, and a current detection pad 172. The semiconductor device 100 may further be equipped with a current sensor that has a structure similar to that of the transistor section of a semiconductor substrate and simulates the operation of the transistor section, and detects the current flowing between the front and back surfaces of the semiconductor substrate. The anode pad 174, cathode pad 176, and current detection pad 172 in this example are 2nd These pads are located near edge 102-2, and the area where these pads are provided is sometimes referred to as the pad area.

[0036] The semiconductor device 100 includes a protective film 150 provided on the upper surface of the semiconductor substrate 10. The protective film 150 is made of polyimide or the like and covers the front side of the semiconductor substrate 10, protecting the front surface element structure. In Figure 1, the area where the protective film 150 is provided is shown with hatched lines. The protective film 150 has an opening on the emitter electrode 52 corresponding to the exposed portion 53. The protective film 150 may also have openings at positions and in pad areas corresponding to the pad 50, anode pad 174, cathode pad 176, and current detection pad 172.

[0037] In Figure 1, additional active areas may be provided above and below the pad 50 and the pad area (in the +Y axis direction and the -Y axis direction). In this case, the emitter electrode 52 may be extended and provided above the additional active areas.

[0038] Figure 2 is an example of an enlarged view of the active section 120. In this example, the active section 120 has a transistor section 70. Figure 2 shows the region of the active section 120 centered on the -Y axis side end.

[0039] The semiconductor device 100 may have gate runners 48 arranged around the active portion 120 in a top view. The gate runners 48 are wirings formed of polysilicon with impurities added, or a conductive material such as metal. The gate runners 48 supply the gate voltage applied to the gate pad 50 to the transistor portion 70. The gate runners 48 may be positioned above the well region 11, which will be described later.

[0040] The semiconductor device 100 in this example includes a gate trench 40, a dummy trench 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15, all located inside the front side of the semiconductor substrate 10.

[0041] Figure 2 shows the area where the emitter electrode 52 is provided. In this example, the emitter electrode 52 is provided in an area that does not overlap with the gate runner 48, but it may overlap with the gate runner 48. In this case, an insulating film is provided between the emitter electrode 52 and the gate runner 48. An interlayer insulating film is provided between the emitter electrode 52 and the front surface of the semiconductor substrate 10, but this is omitted in Figure 2. In this example, contact holes 56 and 54 are provided in the interlayer insulating film, penetrating the interlayer insulating film.

[0042] The emitter electrode 52 is in contact with the emitter region 12, contact region 15, and base region 14 on the front surface of the semiconductor substrate 10 through the contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through the contact hole 56. A connection portion 25 made of a conductive material such as impurity-doped polysilicon may be provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is provided above the front surface of the semiconductor substrate 10. An insulating film is provided between the connection portion 25 and the front surface of the semiconductor substrate 10.

[0043] An insulating film is provided between the gate runner 48 and the front surface of the semiconductor substrate 10. The gate runner 48 is connected to the gate conductive portion in the gate trench portion 40 on the front surface of the semiconductor substrate 10. The gate runner 48 is not connected to the dummy conductive portion in the dummy trench portion 30. In this example, the gate runner 48 is provided overlapping the tip portion 41 of the gate trench portion 40. The tip portion 41 is the end of the gate trench portion 40 closest to the gate runner 48. At the tip portion 41 of the gate trench portion 40, the gate conductive portion is exposed on the front surface of the semiconductor substrate 10 and is in contact with the gate runner 48.

[0044] One or more gate trenches 40 and one or more dummy trenches 30 are arranged at predetermined intervals along a predetermined arrangement direction in the transistor section 70. In this example, the arrangement direction (also referred to as the trench arrangement direction) is the X-axis direction. In this example, one or more gate trenches 40 and one or more dummy trenches 30 may be alternately provided along the arrangement direction.

[0045] The gate trench section 40 in this example may have two extended portions 39 (the trench portion which is linear along the extension direction) that extend along an extension direction perpendicular to the arrangement direction (also referred to as the trench extension direction), and a tip portion 41 that connects the two extended portions 39. In this example, the extension direction is the Y-axis direction. It is preferable that at least a part of the tip portion 41 is provided in a curved shape. In the two extended portions 39 of the gate trench section 40, the tip portion 41 connects the ends which are linear ends along the extension direction, thereby mitigating electric field concentration at the ends of the extended portions 39.

[0046] In this example, the dummy trench section 30 is provided between each of the extended portions 39 of the gate trench section 40. These dummy trench sections 30 may have a linear shape that extends in the extension direction.

[0047] The emitter electrode 52 is located above the gate trench 40, dummy trench 30, well region 11, emitter region 12, base region 14, and contact region 15. The well region 11 is located away from the contact hole 54 and is provided within a predetermined range. The diffusion depth of the well region 11 may be deeper than the depths of the gate trench 40 and dummy trench 30. The ends of the gate trench 40 and dummy trench 30 in the extension direction are located in the well region 11.

[0048] A base region 14 is provided in the mesa region 60 sandwiched between adjacent trench regions. The mesa region is the area of ​​the semiconductor substrate 10 sandwiched between trench regions that is on the surface side of the deepest bottom of the trench region. The base region 14 is a second conductivity type with a lower doping concentration than the well region 11. In this example, the base region 14 is P-type and the well region 11 is P+ type.

[0049] A second conductivity type contact region 15 with a higher doping concentration than the base region 14 is provided on the upper surface of the base region 14 of the mesa portion 60. The contact region 15 in this example is of type P+. The well region 11 may be provided away from the contact region 15 located at the outermost edge in the trench extension direction (in the -Y axis direction in Figure 2) in the direction of the gate runner 48. In addition, in the transistor portion 70, the base region 14 Upward In this example, an emitter region 12 of a first conductivity type with a higher doping concentration than the drift region 18 described later is selectively provided. The emitter region 12 in this example is of the N+ type.

[0050] Each of the contact region 15 and emitter region 12 extends from one adjacent trench to the other. One or more contact regions 15 and one or more emitter regions 12 of the transistor 70 are arranged to be alternately exposed on the upper surface of the mesa 60 along the direction of extension of the trench.

[0051] In other examples, the mesa portion 60 in the transistor portion 70 may have contact regions 15 and emitter regions 12 arranged in a stripe pattern along the extension direction. For example, the emitter region 12 may be provided in the region adjacent to the trench portion, and the contact region 15 may be provided in the region sandwiched between the emitter regions 12.

[0052] In the transistor section 70, the contact holes 54 are provided above the contact region 15 and the emitter region 12. The contact holes 54 are not provided in the regions corresponding to the base region 14 and the well region 11.

[0053] Figure 3 shows an example of the aa cross-section in Figure 2. The aa cross-section is the XZ plane passing through the emitter region 12. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section. The emitter electrode 52 is provided on the upper surface of the semiconductor substrate 10 and the interlayer insulating film 38.

[0054] The collector electrode 24 is provided on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as metal. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction. In this example, the depth direction is the Z-axis direction.

[0055] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. In this example, the semiconductor substrate 10 is a silicon substrate. A P-type base region 14 is provided on the front surface 21 side of the semiconductor substrate 10 in the cross-section.

[0056] In the cross-section, an N+ type emitter region 12, a P- type base region 14, and an N+ type storage region 16 are provided in order from the front surface 21 side of the semiconductor substrate 10 in the transistor portion 70.

[0057] In the transistor section 70, an N-type drift region 18 is provided below the storage region 16. By providing a storage region 16 with a higher concentration than the drift region 18 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced.

[0058] In this example, the storage region 16 is provided in each mesa portion 60 of the transistor portion 70. The storage region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60. An N+ type buffer region 20 is provided below the drift region 18. In addition, multiple storage regions 16 may be provided in the depth direction.

[0059] The buffer region 20 is located below the drift region 18. The doping concentration in the buffer region 20 is higher than that in the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the bottom surface of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82. Below the buffer region 20 is the P+ type collector region 22.

[0060] The front surface 21 of the semiconductor substrate 10 is provided with one or more gate trenches 40 and one or more dummy trenches 30. Each trench is provided so as to extend from the front surface 21 of the semiconductor substrate 10, through the base region 14, and reach the drift region 18. In regions where at least one of the emitter region 12, contact region 15, and storage region 16 is provided, each trench also extends through these regions to reach the drift region 18.

[0061] The statement that a trench penetrates a doping area is not limited to cases where the doping area is formed first and then the trench is formed during manufacturing. Cases where the doping area is formed between the trenches after the trenches have been formed are also included in cases where the trench penetrates the doping area.

[0062] The gate trench portion 40 has a gate insulating film 42 and a gate conductive portion 44 provided on the front surface 21 side of the semiconductor substrate 10. The gate insulating film 42 is provided covering the inner wall of the gate trench portion 40. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench portion 40. The gate conductive portion 44 is provided inside the gate trench portion 40, on the inside of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0063] The gate conductive portion 44 includes a region facing the base region 14 across the gate insulating film 42. The gate trench portion 40 in this cross-section is covered by an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is created on the surface layer of the interface in contact with the gate trench in the base region 14.

[0064] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in its cross-section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the front surface 21 side of the semiconductor substrate 10. The dummy insulating film 32 is provided covering the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is located inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed from the same material as the gate conductive portion 44.

[0065] Figure 4 shows an example of the configuration of the first region 121 and the second region 122. The protective film 150 has an opening on the emitter electrode 52 corresponding to the exposed portion 53. In Figure 4, the area where the protective film 150 is provided is shown with hatched lines. A lead frame is placed on the upper surface of the exposed portion 53, and the emitter electrode 52 is electrically connected to the lead frame. The dimensions of the exposed portion 53 are determined by the dimensions of the lead frame on which it is placed.

[0066] In this example, the first region 121 is, Active part 120 The region corresponding to the exposed portion 53 includes the central Ac of the active portion 120. The central Ac of the active portion 120 is the geometric centroid of the active portion 120 in a top view. The lead frame is positioned to cover the first region 121. In a top view, the distance W between the first region 121 and the edge of the exposed portion 53 is at least 0 μm and 1500 μm or less.

[0067] The second region 122 is a region with a lower channel density than the first region 121, located on the outer periphery of the first region 121, in the region corresponding to the exposed portion 53 of the active portion 120. In this example, the second region 122 surrounds the entire outer periphery of the first region 121 when viewed from above, and the outer edge of the second region 122 coincides with the edge of the exposed portion 53. However, in other examples, the second region 122 may be provided only in a portion of the outer periphery of the first region 121. The end of the lead frame is located in the second region 122.

[0068] During operation of the transistor section 70, current generated around the area where the lead frame is located on the semiconductor substrate 10 flows towards the lead frame. In particular, current concentrates in the region from near the end of the lead frame to the end of the solder joint that connects the lead frame to the upper surface of the emitter electrode 52. In this region, the current density increases, which may lead to a decrease in turn-off withstand capability and a decrease in reliability due to heat generation.

[0069] In the semiconductor device 100 of this example, the channel density of the second region 122 where the ends of the lead frame are located is made lower than the channel density of the first region 121 directly below the lead frame, thereby suppressing current generation in the second region 122. As a result, when the transistor section 70 is operating, current concentration in the second region 122 is mitigated, and a decrease in turn-off withstand capability and a decrease in reliability due to heat generation can be suppressed.

[0070] Viewed from above, the area of ​​the first region 121 is between 0.5 and 10 times the area of ​​the second region 122. This area ratio within this range allows for sufficient current flow throughout the semiconductor device 100 while mitigating current concentration in the second region 122.

[0071] In this example, the outer edge of the second region 122 coincides with the edge of the exposed portion 53, but in other examples, it may be located inside the edge of the exposed portion 53. In that case, the outside of the second region 122 may have the same surface element structure as the first region 121. This makes it possible to promote current generation throughout the entire active portion 120 while mitigating current concentration in the second region 122.

[0072] Figure 5 is a top view showing an example of the mesa portion 60. The active portion 120 in this example has a transistor portion 70, as shown in Figures 2 and 3. The emitter region 12 and the contact region 15 are alternately provided in the trench extension direction in the mesa portion 60 of the transistor portion 70.

[0073] In this example, the channel density of the mesa portion 60 of the transistor portion 70 in the second region 122 is smaller than that of the mesa portion 60 of the transistor portion 70 in the first region 121. The channel density in the transistor portion 70 is determined by the ratio of the contact region 15 to the emitter region 12 in the trench extension direction. Viewed from above, the ratio of the emitter region 12 to the contact region 15 in the mesa portion 60 of the transistor portion 70 in the first region 121 is larger than the ratio of the emitter region 12 to the contact region 15 in the mesa portion 60 of the transistor portion 70 in the second region 122.

[0074] In a top view, the trench extension length L2 of the contact region 15 provided in the mesa portion 60 of the transistor portion 70 in the second region 122 is greater than the trench extension length L1 of the contact region 15 provided in the mesa portion 60 of the transistor portion 70 in the first region 121.

[0075] In a top view, the emitter region 12 of the transistor section 70 in the second region 122 may be provided in correspondence with the emitter region 12 of the transistor section 70 in the first region 121 in the trench arrangement direction, and the emitter region 12 of the transistor section 70 in the first region 121 may be provided in correspondence with either the emitter region 12 or the contact region 15 of the transistor section 70 in the second region 122 in the trench arrangement direction.

[0076] In this example, the emitter region 12 extends across multiple mesa portions 60 in the trench arrangement direction of the first region 121. However, a portion of the emitter region 12 also extends across multiple mesa portions 60 in the second region 122, while the other emitter regions 12 do not extend into the second region 122 but terminate within the first region 121.

[0077] In other words, in the second region 122, compared to the first region 121, a portion of the emitter region 12 is thinned out, so the channel density decreases. For example, the second region 122 The channel density of the mesa portion 60 of the transistor portion 70 in the second region 122 is 50% or less of the channel density of the mesa portion 60 of the transistor portion 70 in the first region 121. This suppresses current generation in the second region 122.

[0078] Figure 6 shows another example of an enlarged view of the active section 120. In this example, the active section 120 has transistor sections 70 and diode sections 80 arranged alternately in the trench arrangement direction. Here, we will mainly explain the differences from the example in Figure 2, which has only transistor sections 70, and will omit explanations of common features.

[0079] In the diode section 80, an N+ type cathode region 82 is provided in the region adjacent to the back surface of the semiconductor substrate 10. In Figure 6, the region where the cathode region 82 is provided is shown by a dotted line. In the active section 120, a P+ type collector region may be provided in the region on the back surface side of the semiconductor substrate 10 where the cathode region 82 is not provided.

[0080] In the active section 120, the projection region that overlaps with the cathode region 82 in the Z-axis direction is defined as the diode section 80. That is, the projection region obtained when the cathode region 82 is projected onto the front surface of the semiconductor substrate 10 in a direction perpendicular to the back surface of the semiconductor substrate 10 is defined as the diode section 80. The region obtained by extending the projection region in the Y-axis direction to the well region may also be defined as the diode section 80. Furthermore, in the active section 120, the projection region obtained when the collector region 22 is projected onto the front surface of the semiconductor substrate 10 in a direction perpendicular to the back surface of the semiconductor substrate 10, and in which a predetermined unit configuration including the emitter region 12 and the contact region 15 is regularly arranged is defined as the transistor section 70.

[0081] Figure 6 shows one mesa portion 60 of the diode portion 80, but the diode portion 80 may have multiple mesa portions 60 in the X-axis direction. A contact region 15 is provided in the mesa portion 60 of the diode portion 80, and in the areas where the contact region 15 is not provided, the base region 14 is exposed on the front surface of the semiconductor substrate 10. An emitter region 12 is not required to be provided in the mesa portion 60 of the diode portion 80. A contact region 15 is provided on the front surface of the semiconductor substrate 10 in the mesa portion 60 adjacent to the transistor portion 70. A contact hole 54 is provided above the contact region 15 and the base region 14.

[0082] In the diode section 80, one or more dummy trench sections 30 are arranged at predetermined intervals along the X-axis. The dummy trench sections 30 of the diode section 80 may have an extended portion 29 and a tip portion 31. The tip portion 31 and the extended portion 29 have the same shape as the tip portion 41 and the extended portion 39. The length in the extension direction of the dummy trench section 30 having a tip portion 31 and the length of the linear dummy trench section 30 may be the same.

[0083] In the transistor section 70, an intermediate region may be provided at the boundary adjacent to the diode section 80, where no emitter region is provided on the surface. The mesa section 60 of the intermediate region may have a contact region 15 over a larger area than the mesa section 60 of the transistor section 70. In addition, in the transistor section 70, a plurality of dummy trench sections 30 may be arranged in a continuous line in the portion adjacent to the intermediate region. The dummy trench sections 30 provided in the portion adjacent to the intermediate region may also have an extended portion 29 and a tip portion 31.

[0084] Figure 7 shows an example of the bb cross-section in Figure 6. In this cross-section, a base region 14 is provided on the front surface 21 side of the semiconductor substrate 10 in the diode portion 80. In this example, the diode portion 80 does not have a storage region 16. In other examples, the diode portion 80 may also have a storage region 16. In addition, multiple storage regions 16 may be provided in the depth direction.

[0085] In the diode section 80, a drift region 18 is provided below the base region 14. In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20.

[0086] Figure 8 shows an example of the arrangement of the transistor section 70 and the diode section 80. In Figure 8, the transistor section 70 is denoted as I and the diode section 80 as F. In the active section 120 of this example, the transistor sections 70 and diode sections 80 shown in Figures 6 and 7 are arranged alternately in the X-axis direction. In a top view, the area of ​​each transistor section 70 is larger than the area of ​​each diode section 80.

[0087] In a top view, the ratio of the diode section 80 to the transistor section 70 in the second region 122 is greater than the ratio of the diode section 80 to the transistor section 70 in the first region 121. In the first region 121 of this example, the transistor section 70 in the X-axis direction widthThe width of the diode portion 80 is greater than the width of the diode portion 80. In the second region 122 of this example, some of the diode portions 80 have the same width as the diode portions 80 in the first region 121, but the width of the other diode portions 80 is greater than the width of the diode portions 80 in the first region 121.

[0088] Thus, in the second region 122, the area ratio of the diode section 80 to the transistor section 70 is higher compared to the first region 121, resulting in a lower channel density than in the first region 121. This suppresses current generation in the second region 122.

[0089] Furthermore, even in the second region 122, where the area ratio of the diode section 80 is high when viewed from above, the area of ​​the transistor section 70 is larger than the area of ​​the diode section 80. This allows for sufficient current to be secured throughout the semiconductor device 100 while mitigating current concentration in the second region 122.

[0090] Figure 9 is a top view showing an example of a semiconductor module 300 according to an embodiment. The semiconductor module 300 comprises a first semiconductor device 100-1 and a second semiconductor device 100-2. The first semiconductor device 100-1 and the second semiconductor device 100-2 are each one of the semiconductor devices 100 shown in Figures 1 to 8. The semiconductor module 300 may comprise multiple sets of the first semiconductor device 100-1 and the second semiconductor device 100-2.

[0091] The semiconductor module 300 in this example includes a housing 88. The housing 88 houses each semiconductor device 100. A coolant flows inside the housing 88 to cool the semiconductor devices 100. The semiconductor module 300 further includes at least one of a temperature sensor and a current sensor.

[0092] The housing 88 has a main terminal 86 and a control terminal 99. At least a portion of the main terminal 86 is electrically connected to the emitter electrode 52 of the semiconductor device 100. At least a portion of the control terminal 99 is electrically connected to the pad 50 of the semiconductor device 100. In addition, at least a portion of the control terminal 99 is electrically connected to the sensor of the semiconductor device 100.

[0093] Figure 10 is a side view of the semiconductor substrate 10 mounted on the mounting substrate 200. In Figure 10, the collector electrode 24, interlayer insulating film 38, etc., are omitted. The semiconductor substrate 10 is fixed to the mounting substrate 200 by connection parts 160 such as solder. Above the exposed portion 53 of the emitter electrode 52, there is a solder portion 162 and a lead frame 163 provided on the solder portion 162 and electrically connected to the emitter electrode 52. In addition, a protective film 150 having an opening corresponding to the exposed portion 53 is provided on the front surface 21 of the semiconductor substrate 10 and above the emitter electrode 52.

[0094] As shown in Figure 10, the solder portion 162 has a flared cross-sectional shape to increase the bonding strength with the emitter electrode 52. By providing the protective film 150, it is possible to prevent the solder portion 162 from spreading to the pad 50 or pad area provided around the emitter electrode 52.

[0095] Furthermore, the protective film 150 can suppress the uneven positioning of the solder portion 162 by limiting the spread of the solder portion 162. If the position of the solder portion 162 is uneven, the center of gravity of the semiconductor device 100 will shift, and in the process of mounting the semiconductor substrate 10 onto the mounting substrate 200 by the connection portion 160, the semiconductor substrate 10 may be fixed in a tilted position. By providing the protective film 150, the uneven positioning of the solder portion 162 can be suppressed, thereby suppressing the tilting of the semiconductor substrate 10 during mounting.

[0096] As described above, when the transistor section 70 is in operation, current generated around the area where the lead frame 163 is placed on the semiconductor substrate 10 flows towards the lead frame 163. Therefore, current concentrates particularly in the area from near the end of the lead frame 163 to the end of the solder section 162. In this area, the current density increases, which may lead to a decrease in turn-off withstand capability and a decrease in reliability due to heat generation.

[0097] Therefore, in this example, the region from near the end of the lead frame 163 to the end of the solder portion 162, where current concentrates during the operation of the transistor portion 70, is placed in the second region 122, which has a low channel density. The boundary between the first region 121 and the second region 122 in this example is located inside the end of the lead frame 163. The distance D1 between the boundary between the first region 121 and the second region 122 and the end of the lead frame 163 is between 400 μm and 800 μm.

[0098] Furthermore, in this example, the outer edge of the second region 122 is located outside the edge of the solder portion 162. The distance D2 between the outer edge of the second region 122 and the edge of the solder portion 162 is 0 μm or more and 1500 μm or less. In this way, in this example, by suppressing current generation in the second region 122, current concentration in the second region 122 is mitigated during operation of the transistor portion 70, thereby suppressing a decrease in turn-off withstand capability and a decrease in reliability due to heat generation.

[0099] Figures 1 to 10 have shown an example in which a first region 121 and a second region 122 are provided in the exposed region 53, which includes the central Ac of the active region, corresponding to the lead frame. However, if additional active regions are provided above and below the pad 50 and the pad region (in the +Y axis direction and -Y axis direction), an exposed region 53 for arranging the lead frame may also be provided in the emitter electrode 52 which is extended above the additional active region, and a first region 121 and a second region 122 may be provided in each of these exposed regions 53.

[0100] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. Such modified or improved forms may also be included within the technical scope of the present invention. patent This is clear from the description of the scope of the claim.

[0101] patent It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before" or "prior to," and that these processes can be implemented in any order unless the output of a previous process is used in a later process. patent Even if the claims, specifications, and operation flows in the drawings are explained using phrases such as "first," "next," etc., for convenience, this does not mean that they must be performed in that order. [Explanation of Symbols]

[0102] 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 15...Contact region, 16...Storage region, 18...Drift region, 20...Buffer region, 21...Front surface, 22...Collector region, 23...Back surface, 24...Collector electrode, 25...Connection portion, 29...Extended portion, 30...Dummy trench portion, 31...Tip portion, 32...Dummy insulating film, 34...Dummy conductive portion, 38...Interlayer insulating film, 39...Extended portion, 40...Gate trench portion, 41...Tip portion, 42...Gate insulating film, 44...Gate conductive portion, 48...Gate runner, 50...Pack 52...Emitter electrode, 53...Exposed area, 54...Contact hole, 56...Contact hole, 60...Mesa area, 70...Transistor area, 80...Diode area, 82...Cathode region, 86...Main terminal, 88...Housing, 99...Control terminal, 100...Semiconductor device, 102...Edge, 120...Active area, 121...First region, 122...Second region, 150...Protective film, 160...Connection area, 162...Solder area, 163...Lead frame, 172...Current detection pad, 174...Anode pad, 176...Cathode pad, 200...Mounting board, 300...Semiconductor module

Claims

1. A semiconductor substrate having an active portion on which a transistor portion is provided, An emitter electrode provided above the front surface of the semiconductor substrate, A protective film provided above the emitter electrode, Equipped with, The active portion has a first conductivity type emitter region, a second conductivity type contact region, and a plurality of trench portions provided on the front surface of the semiconductor substrate. The emitter electrode has an exposed portion that is not covered by the protective film, The active portion comprises, in the region where the exposed portion is provided, a first region and a second region provided on the outer periphery of the first region, having a lower channel density than the first region. It has, The emitter region and the contact region are each provided extending in the trench arrangement direction from one of the plurality of trenches to an adjacent trench. The emitter region and the contact region are arranged alternately in the trench extension direction, and the contact region provided in the mesa portion of the transistor portion in the second region includes a first contact region and a second contact region having a different trench extension direction length from the first contact region. Semiconductor equipment.

2. A semiconductor substrate having an active portion provided with a transistor portion, An emitter electrode provided above the front surface of the semiconductor substrate, A protective film provided above the emitter electrode, Equipped with, The active portion has a first conductivity type emitter region, a second conductivity type contact region, and a plurality of trench portions provided on the front surface of the semiconductor substrate. The emitter electrode has an exposed portion that is not covered by the protective film, The active portion comprises, in the region where the exposed portion is provided, a first region and a second region provided on the outer periphery of the first region, having a lower channel density than the first region. It has, The emitter region and the contact region are alternately provided in the trench extension direction within the mesa portion of the transistor section. In a top view of the semiconductor substrate, the emitter region of the transistor in the second region is a region in which the emitter region of the transistor in the first region extends to the transistor in the second region in the trench arrangement direction. Semiconductor equipment.

3. In a top view of the semiconductor substrate, the second region is provided surrounding the entire outer periphery of the first region. The semiconductor device according to claim 1 or 2.

4. In a top view of the semiconductor substrate, the area of ​​the first region is 0.5 times or more and 10 times or less the area of ​​the second region. The semiconductor device according to claim 1 or 2.

5. In a top view of the semiconductor substrate, the first region is spaced at least 0 μm and no more than 1500 μm from the edge of the exposed portion. The semiconductor device according to claim 1 or 2.

6. The channel density of the mesa portion of the transistor in the second region is smaller than the channel density of the mesa portion of the transistor in the first region. The semiconductor device according to claim 1 or 2.

7. The emitter region and the contact region are alternately provided in the trench extension direction within the mesa portion of the transistor section. In a top view of the semiconductor substrate, the ratio of the emitter region to the contact region in the mesa portion of the transistor in the first region is greater than the ratio of the emitter region to the contact region in the mesa portion of the transistor in the second region. The semiconductor device according to claim 1 or 2.

8. In a top view of the semiconductor substrate, the trench extension length of the contact region provided in the mesa portion of the transistor portion in the second region is greater than the trench extension length of the contact region provided in the mesa portion of the transistor portion in the first region. The semiconductor device according to claim 7.

9. In a top view of the semiconductor substrate, the emitter region of the transistor in the second region is provided in a manner corresponding to the emitter region of the transistor in the first region in the trench arrangement direction. In a top view of the semiconductor substrate, the emitter region of the transistor in the first region is provided in correspondence with either the emitter region or the contact region of the transistor in the second region, in the trench arrangement direction. The semiconductor device according to claim 8.

10. The channel density of the mesa portion of the transistor in the second region is 50% or less of the channel density of the mesa portion of the transistor in the first region. The semiconductor device according to claim 6.

11. The active portion has diode portions arranged alternately with the transistor portions in the trench arrangement direction. In a top view of the semiconductor substrate, the ratio of the diode portion to the transistor portion in the second region is greater than the ratio of the diode portion to the transistor portion in the first region. The semiconductor device according to claim 1 or 2.

12. In a top view of the semiconductor substrate, in the second region, the area of ​​the transistor portion is larger than the area of ​​the diode portion. The semiconductor device according to claim 11.

13. A semiconductor module comprising the semiconductor device described in claim 1 or 2.

14. A solder portion provided above the emitter electrode, A lead frame provided on the aforementioned solder portion and electrically connected to the emitter electrode, Equipped with, The semiconductor module according to claim 13.

15. In a top view of the semiconductor substrate, the boundary between the first region and the second region is located inward from the end of the lead frame. The semiconductor module according to claim 14.

16. The distance between the boundary between the first region and the second region and the end of the lead frame is 400 μm or more and 800 μm or less. The semiconductor module according to claim 15.

17. The outer peripheral end of the second region is located outside the end of the solder portion. The semiconductor module according to claim 15.

18. The distance between the outer edge of the second region and the end of the solder portion is 0 μm or more and 1500 μm or less. The semiconductor module according to claim 17.

19. In a top view of the semiconductor substrate, at least one emitter region of the transistor portion in the first region terminates within the first region in the trench arrangement direction. The emitter region terminated within the first region is adjacent to the contact region of the transistor portion in the second region, across the trench, in the trench arrangement direction. The semiconductor device according to claim 2.

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