Semiconductor equipment

Abstract

To preferably improve characteristics such as a turn-on power loss in a semiconductor device.SOLUTION: A semiconductor device in which a plurality of trench parts is provided on an upper surface side of a semiconductor substrate and in which a first mesa part and a second mesa part being regions between the trench parts are formed comprises a drift region of a first conductivity type, a base region of a second conductivity type provided in the first and second mesa parts above the drift region, and a high-concentration region of the first conductivity type provided between the drift and base regions in a depth direction of the semiconductor substrate and having a higher doping concentration than the drift region. A depth position of a lower end of the high-concentration region between the base and drift regions of the first mesa part is deeper than a depth position of a lower end of the high-concentration region between the base and drift regions of the second mesa part.SELECTED DRAWING: Figure 7a

Description

[Technical Field]

[0001] This invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, semiconductor devices such as insulated-gate bipolar transistors (IGBTs) are known (see, for example, Patent Document 1). Patent Document 1: Japanese Unexamined Patent Publication No. 2007-311627 [Overview of the project] [Problems that the invention aims to solve]

[0003] In semiconductor devices, Diode section It is preferable to improve the characteristics. [Means for solving the problem]

[0004] In the first embodiment of the present invention, The present invention provides a trench-type semiconductor device comprising a transistor section and a diode section, wherein the semiconductor substrate is provided with an n-type drift region, a p-type base region, and a plurality of trench sections. In the above semiconductor device, the transistor section may have an n-type storage region provided below the base region in a first mesa section, and having a higher doping concentration than the drift region. In any of the above semiconductor devices, the diode section may have a hole injection suppression section provided on the upper surface side of the semiconductor substrate and an electron injection suppression section provided on the lower surface side of the semiconductor substrate.

[0005] the above In any semiconductor device, at the same depth position of the diode portion as the deepest position of the storage region, an n-type high-concentration region with a higher doping concentration than the drift region does not need to be formed on the semiconductor substrate.

[0006] In any of the above semiconductor devices, The hole injection suppression portion is provided below the base region in the second mesa portion of the diode portion and may be an n-type high-concentration region with a higher doping concentration than the drift region.

[0007] In any of the above semiconductor devices, The transistor portion may be selectively provided in the first mesa portion in contact with the upper surface of the semiconductor substrate and may have a p-type first contact region with a higher doping concentration than the base region. In any of the above semiconductor devices, at least a portion of the mesa portion of the diode portion may be provided with a p-type second contact region that is selectively provided in contact with the upper surface of the semiconductor substrate and has a higher doping concentration than the base region. In any of the above semiconductor devices, the second mesa portion of the diode portion in which the area of ​​the second contact region on the upper surface is smaller than the area of ​​the first contact region on the upper surface of the first mesa portion may be the hole injection suppression portion.

[0008] In any of the above semiconductor devices, the diode portion may have an n-type cathode region provided in contact with the lower surface of the semiconductor substrate. In any of the above semiconductor devices, the electron injection suppression portion may be a p-type floating region located above the cathode region and covering a part of the cathode region.

[0009] the above In any of the semiconductor devices, the diode portion may have an n-type cathode region provided in contact with the lower surface of the semiconductor substrate. In any of the above semiconductor devices, the electron injection suppression portion may be a p-type dummy region provided in contact with the lower surface of the semiconductor substrate. The semiconductor device according to any one of claims 1 to 4.

[0010] In any of the above semiconductor devices, The accumulation region may cover the entire lower surface of the base region in the first mesa portion.

[0011] In any of the above semiconductor devices, The aforementioned accumulation region may have multiple doping concentration peaks.

[0012] In any of the semiconductor devices described above, The first mesa portion may have an outer mesa portion that is located on the outermost side in the arrangement direction of the trench portions among the first mesa portion in which the accumulation region is formed. In any of the above semiconductor devices, the trench portion may have a first trench portion that is in contact with the outer mesa portion on the outside. In any of the above semiconductor devices, the depth of the base region of the outer mesa portion may be shallower than the depth of the base region provided in the mesa portion opposite to the outer mesa portion with respect to the first trench portion in the arrangement direction.

[0013] A second embodiment of the present invention provides a semiconductor device having a plurality of trenches on the upper surface side of a semiconductor substrate, and having at least a first mesa portion and a second mesa portion formed thereon. The semiconductor device may comprise a drift region of a first conductivity type, a base region of a second conductivity type provided in the first mesa portion and the second mesa portion above the drift region, and a high-concentration region of a first conductivity type provided between the drift region and the base region in the depth direction of the semiconductor substrate, having a higher doping concentration than the drift region. In any of the above semiconductor devices, the integrated concentration obtained by integrating the doping concentration of the high-concentration region between the base region and the drift region of the first mesa portion in the depth direction may be higher than the integrated concentration obtained by integrating the doping concentration of the high-concentration region between the base region and the drift region of the second mesa portion in the depth direction. In any of the above semiconductor devices, the upper ends of the high-concentration regions in the first mesa portion and the second mesa portion may be in contact with the base region. In any of the semiconductor devices described above, the upper ends of the high-concentration regions in the first mesa portion and the second mesa portion may be located at the same depth and have the same doping concentration. any of the semiconductor devices may be selectively provided on the upper surface side of the semiconductor substrate and may include an emitter region of a first conductivity type having a doping concentration higher than that of the drift region.

[0014] In any of the semiconductor devices described above, the high-concentration region may be provided below the emitter region of the first mesa portion and below the emitter region of the second mesa portion.

[0015] any of the semiconductor devices may be selectively provided on the upper surface side of the semiconductor substrate and may include a contact region of a second conductivity type having a doping concentration higher than that of the base region.

[0016] In any of the semiconductor devices described above, the high-concentration region may be provided below the contact region of the first mesa portion and below the contact region of the second mesa portion.

[0017] any of the semiconductor devices may include, as the plurality of trench portions, one or more dummy trench portions and one or more gate trench portions.

[0018] In any of the semiconductor devices described above, the dummy trench portion and the gate trench portion may each extend linearly in the extending direction in a top view and may be arranged at a predetermined interval in the arrangement direction.

[0019] any of the semiconductor devices may be provided so as to surround the active region of the semiconductor substrate and may include an edge termination structure portion including at least any one of a guard ring, a field plate, and RESURF.

[0020] any of the semiconductor devices may be provided in a predetermined range at an end of the active region and may include a well region of a second conductivity type formed deeper than the trench portion in the depth direction.

[0021] In any of the above semiconductor devices, the end of the high-concentration region in the stretching direction may be separated from the well region when viewed from above.

[0022] In any of the above semiconductor devices, the end of the high-concentration region in the stretching direction may extend toward the well region in the first mesa portion and the second mesa portion to the same position when viewed from above.

[0023] Any of the above semiconductor devices may include a first lower surface region of a second conductivity type provided on the lower surface side of the semiconductor substrate.

[0024] In any of the semiconductor devices described above, the first lower surface region may be located below the first mesa portion and the second mesa portion.

[0025] In any of the above-described semiconductor devices, the high-concentration region may be an accumulation region.

[0026] Any of the above semiconductor devices may include a second lower surface region of a first conductivity type provided on the lower surface side of the semiconductor substrate.

[0027] In any of the above-described semiconductor devices, the semiconductor substrate may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate.

[0028] The above summary of the invention does not enumerate all of its features. Subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0029] [Figure 1] This figure partially shows the upper surface of a semiconductor device 100 according to an embodiment of the present invention. [Figure 2a] This figure shows an example of a d-d' section. [Figure 2b] This figure shows another example of the d-d' section in Figure 1. [Figure 2c] This figure shows another example of the d-d' section in Figure 1. [Figure 2d] This figure shows another example of the d-d' section in Figure 1. [Figure 2e] This figure shows the concentration distribution of the crystal defect layer 89 in the n-n' cross-section in Figure 2d. [Figure 2f] This figure shows an example of a cross-section of a semiconductor device 150 according to an embodiment of the present invention. [Figure 2g] This figure shows another example of a cross-section of a semiconductor device 150 according to an embodiment of the present invention. [Figure 3] This figure shows an example of the doping concentration distribution in the e-e' and f-f' sections of Figure 2a. [Figure 4] This figure shows an example of the collector current Ic waveform during turn-on. [Figure 5] This figure shows another example of the doping concentration distribution in the e-e' and f-f' sections of Figure 2a. [Figure 6] This figure shows the electron current and displacement current during turn-on in a semiconductor device 100 having a first storage region 16-1, a second storage region 16-2, and a third storage region 16-3. [Figure 7a] This figure shows another example of the d-d' section in Figure 1. [Figure 7b] Figure 7a shows an example of the doping concentration distribution in the e-e', f-f', and g-g' sections. [Figure 8] This figure shows another example of the d-d' section in Figure 1. [Figure 9] This is a cross-sectional view illustrating an example of the arrangement of the floating region 84. [Figure 10] This is a top view showing an example of the arrangement of the floating region 84 in the diode section 80. [Figure 11] This is a top view showing an example of the arrangement of the floating region 84 in the diode section 80. [Figure 12]This is a top view showing another example of the arrangement of the floating region 84 in the diode section 80. [Figure 13] This figure shows another example of the d-d' section in Figure 1. [Figure 14] This figure shows another example of the d-d' section in Figure 1. [Figure 15] This figure shows other possible configurations of Lifetime Killer 88. [Figure 16] This figure shows an example of the configuration of the diode section 80. [Figure 17] This figure shows another example of the configuration of the diode section 80. [Figure 18] This figure shows another example of the semiconductor device 100. [Figure 19] This figure partially shows the top surface of a semiconductor device 200 according to another embodiment of the present invention. [Figure 20] Figure 19 shows an example of a d-d' section. [Figure 21a] This figure partially shows the top surface of a semiconductor device 300 according to another embodiment of the present invention. [Figure 21b] Figure 21a shows an example of an s-s' cross section. [Figure 21c] This figure shows an example of a t-t' cross section in Figure 21a. [Figure 22] This is a cross-sectional view of the comparative example semiconductor device 350. [Figure 23a] This figure partially shows the top surface of a semiconductor device 300 according to another embodiment of the present invention. [Figure 23b] This figure shows an example of a u-u' cross-section in Figure 23a. [Figure 23c] This figure shows an example of a v-v' section in Figure 23a. [Figure 24] This figure partially shows the top surface of a semiconductor device 300 according to another embodiment of the present invention. [Figure 25] This figure partially shows the top surface of a semiconductor device 300 according to another embodiment of the present invention. [Figure 26] This figure shows an example of a semiconductor chip 120 according to an embodiment of the present invention. [Figure 27a] This is a magnified view of region A in Figure 26. [Figure 27b] This is a magnified view of region B1 in Figure 27a. [Figure 27c] This is a magnified view of region B2 in Figure 27b. [Figure 27d] Figure 27b shows an example of an h-h' cross section. [Figure 27e] This figure shows an example of a j-j' section in Figure 27b. [Figure 28a] This is another enlarged view of region A in Figure 26. [Figure 28b] This is a magnified view of region C1 in Figure 28a. [Figure 28c] This is a magnified view of region C2 in Figure 28b. [Figure 28d] This figure shows an example of a k-k' cross-section in Figure 28b. [Figure 28e] This figure shows an example of the m-m' cross-section in Figure 28b. [Modes for carrying out the invention]

[0030] The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0031] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "upper," and the other side as "lower." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the upper surface, and the other surface as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity.

[0032] In each embodiment, an example is shown where the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment will have opposite polarities.

[0033] Figure 1 is a diagram showing a partial view of the top surface of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 in this example is a semiconductor chip comprising a transistor section 70, a diode section 80, and a boundary section 90. The boundary section 90 may be a part of the transistor section 70. The transistor section 70 includes a transistor such as an IGBT. The diode section 80 is provided adjacent to the transistor section 70 on the top surface of the semiconductor substrate and includes a diode such as an FWD (Free Wheel Diode). The boundary section 90 is provided between the transistor section 70 and the diode section 80 on the top surface of the semiconductor substrate. Figure 1 shows the top surface of the chip around the chip edge, and other areas are omitted.

[0034] Furthermore, Figure 1 shows the active region of the semiconductor substrate in the semiconductor device 100, but the semiconductor device 100 may have an edge termination structure surrounding the active region. The active region refers to the region through which current flows when the semiconductor device 100 is controlled to the ON state. The edge termination structure mitigates electric field concentration on the upper surface side of the semiconductor substrate. The edge termination structure may have, for example, a guard ring, a field plate, a resurf, or a combination thereof.

[0035] The semiconductor device 100 in this example includes a gate trench 40, a dummy trench 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 formed inside the upper surface of a semiconductor substrate. The gate trench 40 and the dummy trench 30 are examples of trenches. The semiconductor device 100 in this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the upper surface of the semiconductor substrate. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0036] An interlayer insulating film is formed between the emitter electrode 52 and the gate metal layer 50 and the upper surface of the semiconductor substrate, but this is omitted in Figure 1. In this example, contact holes 56, 49, and 54 are formed through the interlayer insulating film.

[0037] The emitter electrode 52 contacts the emitter region 12, contact region 15, and base region 14 on the upper surface of the semiconductor substrate through the contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through the contact hole 56. A connection portion 25 made of a conductive material such as impurity-doped polysilicon may be provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is formed on the upper surface of the semiconductor substrate.

[0038] The gate metal layer 50 contacts the gate runner 48 through the contact hole 49. The gate runner 48 is formed of polysilicon doped with impurities. The gate runner 48 is connected to the gate conductive portion in the gate trench 40 on the upper surface of the semiconductor substrate. The gate runner 48 is not connected to the dummy conductive portion in the dummy trench 30. In this example, the gate runner 48 is formed from below the contact hole 49 to the tip of the gate trench 40. At the tip of the gate trench 40, the gate conductive portion is exposed on the upper surface of the semiconductor substrate and contacts the gate runner 48.

[0039] The emitter electrode 52 and the gate metal layer 50 are formed from a metal-containing material. For example, at least a portion of each electrode is formed from aluminum or an aluminum-silicon alloy. Each electrode may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum, and may have a plug formed from tungsten or the like within the contact hole.

[0040] One or more gate trenches 40 and one or more dummy trenches 30 are arranged at predetermined intervals along a predetermined arrangement direction in the region of the transistor 70. In the transistor 70, one or more gate trenches 40 and one or more dummy trenches 30 may be formed alternately along the arrangement direction.

[0041] The gate trench portion 40 in this example may have two extended portions that extend along an extension direction parallel to the upper surface of the semiconductor substrate and perpendicular to the alignment direction, and a connecting portion that connects the two extended portions. Preferably, at least a part of the connecting portion is formed in a curved shape. By connecting the ends of the two extended portions of the gate trench portion 40, electric field concentration at the ends of the extended portions can be mitigated. The gate runner 48 may be connected to the gate conductive portion at the connecting portion of the gate trench portion 40.

[0042] In this example, the dummy trench section 30 is provided between each extended portion of the gate trench section 40. The dummy trench section 30 may have a U-shape on the upper surface of the semiconductor substrate, similar to the gate trench section 40. In other examples, the dummy trench section 30 has two extended portions that extend along the extension direction and a connecting portion that connects the two extended portions. In other examples, the dummy trench section 30 may have a linear shape that extends in the extension direction.

[0043] In the boundary section 90 and the diode section 80, multiple dummy trench sections 30 are arranged in a continuous pattern. Furthermore, in the transistor section 70, multiple dummy trench sections 30 may also be arranged in a continuous pattern in the region adjacent to the boundary section 90. In this example, the linear extensions of each trench section are treated as a single trench section.

[0044] The emitter electrode 52 is formed above the gate trench 40, dummy trench 30, well region 11, emitter region 12, base region 14, and contact region 15. The well region 11 is of the second conductivity type and is formed over a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 11 may be deeper than the depth of the gate trench 40 and dummy trench 30. A portion of the gate trench 40 and dummy trench 30 on the gate metal layer 50 side is formed in the well region 11. The bottom of the extending end of the dummy trench 30 may be covered by the well region 11.

[0045] A base region 14 is formed in the mesa region sandwiched between each trench. The base region 14 is a second conductivity type with a lower doping concentration than the well region 11. In this example, the base region 14 is P-type. The mesa region is the portion of the semiconductor substrate sandwiched between two adjacent trenches, and may be the portion from the top surface of the semiconductor substrate to the deepest bottom of each trench.

[0046] A second-conductivity contact region 15 with a higher doping concentration than the base region 14 is selectively formed on the upper surface of the mesa base region 14. In this example, the contact region 15 is of the P+ type. In the transistor region 70, a first-conductivity emitter region 12 with a higher doping concentration than the semiconductor substrate is selectively formed on a portion of the upper surface of the contact region 15. In this example, the emitter region 12 is of the N+ type.

[0047] Each of the contact region 15 and emitter region 12 is formed from one adjacent trench to the other. One or more contact regions 15 and one or more emitter regions 12 of the transistor 70 are formed to alternately expose themselves on the upper surface of the mesa along the direction of extension of the trench. Each of the contact region 15 and emitter region 12 may be in contact with one adjacent trench or the other for a predetermined length along the direction of extension of each trench.

[0048] In other examples, the mesa portion of the transistor portion 70 may have a contact region 15 and an emitter region 12 formed in a stripe pattern along the extension direction of the trench portion. For example, the emitter region 12 may be formed in a region adjacent to the trench portion, and the contact region 15 may be formed in a region sandwiched between the emitter regions 12.

[0049] In this example, the emitter region 12 is not formed in the mesa portion of the diode section 80 and the boundary section 90. Furthermore, in the mesa portion of the diode section 80, a contact region 15 is formed in the region facing at least one contact region 15 of the transistor section 70. In the mesa portion of the boundary section 90, a contact region 15 is formed in the region facing the contact region 15 and the emitter region 12 of the transistor section 70. The boundary portion 90 may have multiple mesa portions. In the boundary portion 90, one or more mesa portions located on the diode portion 80 side may have a smaller surface area on the semiconductor substrate of the contact region 15 than the mesa portions adjacent to the transistor portion 70. In the boundary portion 90, one or more mesa portions located on the diode portion 80 side may have the base region 14 exposed on the upper surface of the semiconductor substrate.

[0050] In the transistor section 70, the contact holes 54 are formed above the contact region 15 and the emitter region 12. The contact holes 54 are not formed in the regions corresponding to the base region 14 and the well region 11.

[0051] In the diode portion 80, the contact holes 54 are formed above the contact region 15 and the base region 14. In this example, the contact holes 54 are not formed in the base region 14 that is closest to the gate metal layer 50 among the multiple base regions 14 in the mesa portion of the diode portion 80.

[0052] The diode portion 80 has a cathode region 82 of a first conductivity type on the lower surface side of the semiconductor substrate. In this example, the cathode region 82 is of the N+ type. In Figure 1, the area where the cathode region 82 is provided is shown by a dashed line in a top view of the semiconductor substrate. The diode portion 80 may be the area obtained by projecting the cathode region 82 onto the upper surface of the semiconductor substrate. The area obtained by projecting the cathode region 82 onto the upper surface of the semiconductor substrate may be separated from the contact region 15 in the +X axis direction.

[0053] In the diode portion 80, a P+ type collector region may be formed in the region on the lower surface of the semiconductor substrate where the cathode region 82 is not formed. In this example, with respect to the dummy trench portion 30 or mesa portion 95 on the upper surface of the semiconductor substrate onto which the cathode region 82 of the lower surface 23 is projected, a collector region is formed at the position where the outer edge (-X axis direction) of the contact hole 54 of the mesa portion 95 is projected onto the lower surface of the semiconductor substrate. As an example, in a dummy trench portion 30 or mesa portion 95 on a part of the lower surface of the semiconductor substrate where the cathode region 82 is formed, the dummy trench portion 30 or mesa portion 95 up to the end in the extension direction of the dummy trench portion 30 (including the U-shaped connected portion) may be conveniently treated as the diode portion 80 even if a collector region is formed on the lower surface of the semiconductor substrate. The transistor portion 70 may be the region on the upper surface of the semiconductor substrate onto which the trench portion or mesa portion is formed.

[0054] At the boundary portion 90, the contact holes 54 are formed above the contact region 15. In this example, the contact holes 54 are not formed relative to the base region 14 of the boundary portion 90. At the boundary portion 90, in one or more mesa portions located on the diode portion 80 side, the contact holes 54 may be formed above the base region 14. In this example, the contact holes 54 of the transistor portion 70, the contact holes 54 of the diode portion 80, and the contact holes 54 of the boundary portion 90 have the same length in the extension direction of each trench portion.

[0055] The semiconductor device 100 has a storage region 16 of a first conductivity type and a high-concentration region 17 of the first conductivity type, which are selectively formed below the base region 14 within the semiconductor substrate. In Figure 1, the areas where the storage region 16 and the high-concentration region 17 are formed are indicated by dashed lines. The storage region 16 is formed in the transistor portion 70, and the high-concentration region 17 is formed in the diode portion 80.

[0056] Figure 2a shows an example of the d-d' cross-section in Figure 1. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section. The emitter electrode 52 is formed on the upper surface 21 of the semiconductor substrate 10 and the interlayer insulating film 38.

[0057] The collector electrode 24 is formed on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a conductive material such as metal. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction.

[0058] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. In this example, the semiconductor substrate 10 is a silicon substrate. A P-type base region 14 is formed on the upper surface of the semiconductor substrate 10.

[0059] In the cross-section, an N+ type emitter region 12, a P- type base region 14, and one or more N+ type storage regions 16 are formed sequentially on the upper surface 21 side of the transistor portion 70, starting from the upper surface 21 side. In the cross-section, a P- type base region 14 and one or more N+ type high-concentration regions 17 are formed sequentially on the upper surface 21 side of the diode portion 80, starting from the upper surface 21 side. In the cross-section, a P+ type contact region 15 and a P- type base region 14 are formed sequentially on the upper surface 21 side of the boundary portion 90, starting from the upper surface 21 side.

[0060] In the transistor section 70, an N-type drift region 18 is formed on the lower surface of the storage region 16. By providing one or more storage regions 16 with a higher concentration than the drift region 18 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced.

[0061] In this example, the region sandwiched between trenches within the semiconductor substrate 10 is defined as the mesa portion 95. Specifically, it is the portion of the semiconductor substrate 10 sandwiched between two adjacent trenches, and may extend from the upper surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of either of the two adjacent trenches. One or more storage regions 16 are formed in each mesa portion 95 of the transistor portion 70. In this example, each mesa portion 95 of the transistor portion 70 is provided with a first storage region 16-1, a second storage region 16-2, and a third storage region 16-3 at different positions in the depth direction of the semiconductor substrate 10. The storage regions 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 95.

[0062] One or more high-density regions 17 are formed in each mesa portion 95 of the diode portion 80. In this example, a first high-density region 17-1 and a second high-density region 17-2 are provided in the mesa portion 95 of the diode portion 80 at different positions in the depth direction of the semiconductor substrate 10. The high-density regions 17 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 95. No high-density regions 17 are formed in the mesa portions 95 at the boundaries.

[0063] By providing one or more N+-type high-concentration regions 17 in each mesa region 95 of the diode section 80, one or more N+-type high-concentration regions 17 with a higher concentration than the drift region 18 are inserted between the base region 14, which is the P-type anode layer of the diode section 80, and the N-type drift region 18. In these one or more high-concentration regions 17, the hole concentration decreases compared to the drift region 18 due to the charge neutrality condition. That is, one or more high-concentration regions 17 suppress the injection of holes from the base region 14 to the drift region 18. As a result, the minority carrier injection efficiency is significantly reduced. The more high-concentration regions 17 there are, the greater the reduction in minority carrier injection efficiency. As a result, the reverse recovery characteristics of the diode section 80, especially the recovery current, are greatly reduced.

[0064] In this example, minority carrier injection efficiency refers to the ratio of the minority carrier current density (hole current density in this example) to the total current density flowing through the emitter electrode 52 when a higher voltage is applied to the emitter electrode 52 than to the collector electrode 24. The sum of the hole current density and the electron current density is the total current density.

[0065] In each of the transistor section 70, diode section 80, and boundary section 90, an N+ type buffer region 20 is formed on the lower surface of the drift region 18. The buffer region 20 is formed on the lower side of the drift region 18. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower side of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0066] In the transistor section 70, a P+ type collector region 22 exposed on the lower surface 23 is formed below the buffer region 20. In the diode section 80, an N+ type cathode region 82 exposed on the lower surface 23 is formed below the buffer region 20. In the boundary section 90, either the collector region 22 or the cathode region 82 is formed below the buffer region 20. In this example, the collector region 22 is formed below the buffer region 20 in the boundary section 90. The diode section 80 is defined as the region that overlaps with the cathode region 82 in a direction perpendicular to the lower surface 23. The transistor section 70 is defined as the region that overlaps with the collector region 22 in a direction perpendicular to the lower surface 23, in which predetermined unit configurations including the emitter region 12 and the contact region 15 are regularly arranged.

[0067] One or more gate trenches 40 and one or more dummy trenches 30 are formed on the upper surface 21. Each trench extends from the upper surface 21, through the base region 14, and reaches the drift region 18. In regions where at least one of the emitter region 12, contact region 15, storage region 16, and high-concentration region 17 is provided, each trench also extends through these regions to reach the drift region 18. The statement that a trench penetrates an impurity region is not limited to manufacturing processes where the impurity region is formed before the trenches are formed. Manufacturing processes where impurity regions are formed between the trenches after the trenches have been formed also include cases where the trenches penetrate an impurity region.

[0068] The gate trench portion 40 has a gate trench formed on the upper surface 21 side, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, on the inside of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0069] The gate conductive portion 44 includes, in the depth direction, at least a region facing the adjacent base region 14. The gate trench portion 40 in this cross-section is covered on the upper surface 21 by an interlayer insulating film 38. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed in the surface layer of the interface of the base region 14 that is in contact with the gate trench.

[0070] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in that cross-section. The dummy trench portion 30 has a dummy trench formed on the upper surface 21 side, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed from the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 may be formed from a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction. In that cross-section, the dummy trench portion 30 is covered by an interlayer insulating film 38 on the upper surface 21.

[0071] In this example, the region where an emitter region 12 is formed on the upper surface 21, a collector region 22 is formed on the lower surface 23, and one or more storage regions 16 are formed is defined as the transistor section 70. The region where one or more high-concentration regions 17 are formed on the upper surface 21 and a cathode region 82 is formed on the lower surface 23 is defined as the diode section 80. The region between the transistor section 70 and the diode section 80 where no emitter region 12 is formed on the upper surface 21 and no cathode region 82 is formed on the lower surface 23 of the diode section 80 is defined as the boundary section 90.

[0072] In this specification, the integral of the doping concentration in the depth direction of the semiconductor substrate 10 is referred to as the integral concentration. In at least one mesa portion 95 of the transistor portion 70, the integral concentration of one or more storage regions 16 (i.e., the integral concentration of an N-type region with a higher concentration than the drift region 18 between the base region 14 and the drift region 18) may be higher than the integral concentration of one or more high-concentration regions 17 in the mesa portion 95 of the diode portion 80 (i.e., the integral concentration of an N-type region with a higher concentration than the drift region 18 between the base region 14 and the drift region 18).

[0073] Alternatively, the integral concentration of the storage region 16 may be higher than the integral concentration of the high-concentration region 17 at the boundary 90. In this case, for example, minority carriers during turn-off can be extracted more easily than in the transistor section 70, and latch-up in the mesa section 95, particularly on the diode section 80 side of the transistor section 70, can be suppressed.

[0074] Alternatively, the integrated concentration of the high-concentration region 17 of the boundary 90 may be higher than the integrated concentration of the high-concentration region 17 of the diode 80. In this case, when a higher voltage than that applied to the collector electrode 52 is applied and the diode 80 conducts, the injection of minority carriers (holes in this example) in the boundary 90 can be suppressed more than the injection of minority carriers in the diode 80. Alternatively, the integrated concentration of the high-concentration region 17 of the boundary 90 may be approximately the same as, or lower than, the integrated concentration of the high-concentration region 17 of the diode 80.

[0075] The integral concentration of the storage region 16 of the transistor section 70 and the integral concentration of the high-concentration region 17 of the boundary section 90 may be approximately the same. Also, the integral concentration of the storage region 16 of the transistor section 70 and the integral concentration of the high-concentration region 17 of the diode section 80 may be approximately the same.

[0076] In this example, the integrated concentration in each mesa portion 95 of the diode portion 80 is the same. All mesa portions 95 of the diode portion 80 may have the same doping concentration distribution. The integrated concentration in all mesa portions 95 of the transistor portion 70 may be the same as or lower than the integrated concentration in each mesa portion 95 of the diode portion 80. On the other hand, the integrated concentration in all mesa portions 95 of the transistor portion 70 may be higher than the integrated concentration in each mesa portion 95 of the diode portion 80. All mesa portions 95 of the transistor portion 70 may have the same integrated concentration. Also, all mesa portions 95 of the transistor portion 70 may have the same doping concentration distribution.

[0077] By providing a storage region 16 or a high-concentration region 17 in the transistor section 70 and the diode section 80, the injection of holes from the upper surface 21 side into the drift region 18 can be suppressed when the diode section 80 is operating. This improves the reverse recovery characteristics of the semiconductor device 100.

[0078] In this example, the boundary 90 does not need to have a region of the first conductivity type with a higher concentration than the drift region 18 (high-concentration region 17) formed between the base region 14 and the drift region 18. Alternatively, the number of high-concentration regions 17 in the boundary 90 may be smaller or the integrated concentration may be smaller than that of the storage region 16 of the transistor section 70 and the high-concentration regions 17 of the diode section 80. This allows holes from the drift region 18 to be extracted through the boundary 90. Therefore, when the transistor section 70 is turned off, etc., it is possible to suppress the flow of holes in the drift region 18 of the diode section 80 into the transistor section 70. In the examples of Figures 1 and 2a, the boundary 90 has one mesa section 95, but the boundary 90 may have multiple mesa sections 95.

[0079] Figure 2b shows another example of the d-d' cross section in Figure 1. The semiconductor device 100 shown in Figure 2b differs from the semiconductor device 100 shown in Figure 2a in that a high-density region 17-1 is provided in the mesa portion 95 of the boundary portion 90. Figure 2b shows an example in which one high-density region 17-1 is provided, but multiple high-density regions 17 may be formed in each mesa portion 95 of the boundary portion 90.

[0080] The number of high-concentration regions 17 in the boundary 90 may be less than the number of storage regions 16 in the transistor section 70. In this case, for example, minority carriers during turn-off can be extracted more easily than in the transistor section 70, and latch-up in the mesa section 95, particularly on the diode section 80 side of the transistor section 70, can be suppressed. Alternatively, the number of high-concentration regions 17 in the boundary 90 may be the same as or greater than the number of storage regions 16 in the transistor section 70.

[0081] The number of high-concentration regions 17 in the boundary 90 may be less than or equal to the number of high-concentration regions 17 in the diode 80. That is, if Nt is the number of storage regions 16 in the transistor 70, Nk is the number of high-concentration regions 17 in the boundary 90, and Nd is the number of high-concentration regions 17 in the diode 80, then Nt ≥ Nd ≥ Nk may be satisfied. Also, the relationship between Nt, Nk, and Nd may be Nd ≥ Nt ≥ Nk. Furthermore, Nt > Nd ≥ Nk, Nt ≥ Nd > Nk, and Nt > Nd > Nk may be satisfied. Alternatively, Nd > Nt ≥ Nk, Nd ≥ Nt > Nk, and Nd > Nt > Nk may be satisfied. In this example, as shown in Figure 2b, one high-concentration region 17-1 is formed.

[0082] Figure 2c shows another example of the d-d' cross section in Figure 1. The semiconductor device 100 shown in Figure 2c differs from the semiconductor device 100 shown in Figure 2a in that two high-density regions 17-1 and 17-2 are provided in the mesa portion 95 of the boundary portion 90, and one high-density region 17-1 is provided in the mesa portion 95 of the diode portion. In this example as well, the number of storage regions 16 in the transistor portion 70 is three.

[0083] The number of high-concentration regions 17 provided in one mesa portion 95 of the boundary portion 90 may be greater than the number of high-concentration regions 17 in the diode portion 80, as shown in Figure 2c. In this case, when a higher voltage than that applied to the collector electrode 52 is applied and the diode portion 80 conducts, the injection of minority carriers (holes in this example) in the boundary portion 90 can be suppressed more than the injection of minority carriers in the diode portion 80.

[0084] The number of storage regions 16 in the transistor section 70, the number of high-concentration regions 17 in the boundary section 90, and the number of high-concentration regions 17 in the diode section 80 may be the same. That is, if the number of storage regions 16 in the transistor section 70 is Nt, the number of high-concentration regions 17 in the boundary section 90 is Nk, and the number of high-concentration regions 17 in the diode section 80 is Nd, then Nt ≥ Nk ≥ Nd may be satisfied. Also, the relationship between Nt, Nk, and Nd may be Nk ≥ Nt ≥ Nd. Furthermore, Nt ≥ Nk > Nd may be satisfied, Nt > Nk ≥ Nd may be satisfied, or Nk > Nt > Nd may be satisfied.

[0085] Furthermore, in the depth direction from the upper surface 21 to the lower surface 23 of the semiconductor substrate 10, the doping concentration distribution of the accumulation region 16 of the transistor portion 70, the doping concentration distribution of the high-concentration region 17 of the boundary portion 90, and the doping concentration distribution of the high-concentration region 17 of the diode portion 80 may be substantially the same. In this case, the accumulation region 16 of the transistor portion 70, the high-concentration region 17 of the boundary portion 90, and the high-concentration region 17 of the diode portion 80 may all be formed by the same ion implantation and annealing process, or they may be formed by different processes.

[0086] Figure 2d shows another example of the d-d' cross section in Figure 1. The semiconductor device 100 shown in Figure 2d differs from the semiconductor device 100 shown in Figure 2a in that a crystal defect layer 89 is provided in the drift region 18 at a depth position on the upper surface 21 side of the intermediate depth position of the semiconductor substrate 10, extending in the Y-axis direction from the region adjacent to the boundary portion 90 of the transistor portion 70 to the diode portion 80. The crystal defect layer 89 may be formed, for example, by locally injecting a lifetime killer such as helium.

[0087] The crystal defect layer 89 is a layer containing crystal defects. The crystal defects can be any defects that serve as recombination centers, such as vacancies, double vacancies, dislocations, interstitial atoms, helium atoms, or metal atoms. This also improves the reverse recovery characteristics. The crystal defect layer 89 may be formed in the arrangement direction of the trench portion (Y-axis direction) between the diode portion 80 and the boundary portion 90, and may be further extended to include one or more predetermined mesa portions 95 of the transistor portion. Alternatively, the crystal defect layer 89 may be arranged to cover the entire dummy trench portion 30 in the stretching direction of the trench portion (X-axis direction), such that, when viewed from above, it includes at least the end of the dummy trench portion 30 in the stretching direction.

[0088] Figure 2e shows the concentration distribution of the crystal defect layer 89 in the n-n' cross-section of Figure 2d. As shown in Figure 2e, the crystal defect layer 89 is sufficient if the location of the peak concentration Pe of the crystal defects is in the drift region 18 at a depth position on the upper surface 21 side of the midpoint in the depth direction of the semiconductor substrate 10. That is, a portion of the crystal defect layer 89 on the lower surface 23 side in the depth direction from the location of the peak concentration Pe of the crystal defects may be distributed on the lower surface 23 side of the midpoint in the depth direction of the semiconductor substrate 10.

[0089] Furthermore, the crystal defect concentration distribution of the crystal defect layer 89 in the diode portion 80 may be a distribution that extends from the upper surface 21 to the position of the peak concentration Pe. In this case, the crystal defect concentration distribution does not need to reach the lower surface 23. Also, if the distribution extends from the upper surface 21 to the position of the peak concentration Pe, the depth position of the peak concentration Pe may be on the lower surface 23 side of the midpoint in the depth direction of the semiconductor substrate 10. In this example, the depth position of the peak concentration Pe is inside the crystal defect layer 89.

[0090] Figure 2f shows an example of a cross-section of a semiconductor device 150 according to an embodiment of the present invention. The semiconductor device 150 shown in Figure 2f differs from the semiconductor device 100 shown in Figure 2a in that multiple mesa portions 95 are provided in the boundary portion 90. The semiconductor device 150 also differs from the semiconductor device 100 shown in Figure 2a in that a crystal defect layer 89 is provided in a drift region 18 at a depth position on the upper surface 21 side of the intermediate position in the depth direction of the semiconductor substrate 10, extending in the Y-axis direction from a region adjacent to the boundary portion 90 of the transistor portion 70 to the diode portion 80. The crystal defect layer 89 may be vacancies, double vacancies, dislocations, interstitial atoms, helium atoms, etc., as in the example in Figure 2d.

[0091] In this example, the semiconductor device 150 has a number of high-density regions 17 in the mesa portion 95 of the boundary portion 90 that is adjacent to the diode portion 80, which is greater than the number of high-density regions 17 in the diode portion 80. In addition, in this example, the semiconductor device 150 does not have a high-density region 17 in the mesa portion 95 of the boundary portion 90 that is adjacent to the transistor portion 70.

[0092] Furthermore, in the mesa portion 95 of the boundary portion 90, the mesa portion 95 sandwiched between the mesa portion 95 adjacent to the diode portion 80 and the mesa portion 95 adjacent to the transistor portion 70 may have a greater number of high-concentration regions 17 than the number of high-concentration regions 17 provided in the mesa portion 95 adjacent to the diode portion 80, or it may have a smaller number of high-concentration regions 17, or it may not have any high-concentration regions 17 at all.

[0093] According to the semiconductor device 150 in this example, minority carriers during turn-off can be extracted more easily than in the transistor section 70. Therefore, latch-up in the mesa section 95, particularly on the diode section 80 side of the transistor section 70, can be suppressed.

[0094] Furthermore, in the semiconductor device 150 of this example, among the mesa portions 95 of the boundary portion 90, the mesa portion 95 adjacent to the diode portion 80 has a greater number of high-concentration regions 17 than the number of high-concentration regions 17 in the diode portion 80. Therefore, similar to the example shown in Figure 2c, in the operating mode in which a higher voltage than that of the collector electrode 24 is applied to the emitter electrode 52 and the diode portion 80 conducts, the injection of minority carriers (holes in this example) in the boundary portion 90 can be suppressed more than the injection of minority carriers in the diode portion 80.

[0095] Figure 2g shows another example of a cross-section of a semiconductor device 150 according to an embodiment of the present invention. The semiconductor device 150 shown in Figure 2g differs from the semiconductor device 150 shown in Figure 2f in that one high-density region 17-1 is provided in the mesa portion 95 of the boundary portion 90 that is adjacent to the transistor portion 70. As a result, when the diode portion 80 is in an operating mode in which it conducts, the injection of minority carriers (holes in this example) from the mesa portion 95 can be suppressed more than the injection of minority carriers from the diode portion 80.

[0096] Furthermore, as shown in Figure 2g, among the mesa portions 95 of the boundary portion 90, the mesa portion 95 adjacent to the transistor portion 70 may be provided with a number of high-concentration regions 17 that is fewer than the number of storage regions 16 provided in the transistor portion 70. In this case, for example, minority carriers during turn-off can be extracted more easily than in the transistor portion 70, and latch-up in the mesa portion 95 of the transistor portion 70, particularly on the diode portion 80 side, can be suppressed.

[0097] If Nt is the number of storage regions 16 in the transistor section 70, Nkt is the number of high-concentration regions 17 provided in the mesa section 95 adjacent to the transistor section 70 within the boundary section 90, Nkd is the number of high-concentration regions 17 provided in the mesa section 95 adjacent to the diode section 80 within the boundary section 90, and Nd is the number of high-concentration regions 17 in the diode section 80, then in the examples of Figures 2f and 2g, it is sufficient that Nkd ≥ Nd and Nt ≥ Nkt. Furthermore, the relationship between Nkt and Nkd may be Nkt ≥ Nkd or Nkd ≥ Nkt.

[0098] On the other hand, injecting a lifetime killer may worsen the on-voltage-off loss trade-off in the transistor section 70. In this example, since the lifetime killer can be omitted or reduced, the deterioration of the on-voltage-off loss characteristics can be suppressed while improving the reverse recovery characteristics. Furthermore, characteristic variations and leakage current caused by the lifetime killer can be suppressed. In addition, manufacturing costs can be reduced by using a resist mask, which has a lower unit cost than a metal mask for lifetime killer injection.

[0099] Furthermore, if the integrated concentration of the high-concentration region 17 in the diode section 80 becomes too high, the trade-off between the switching loss during reverse recovery and the on-loss with respect to the forward voltage in the diode section 80 may worsen. To counteract this, the deterioration of the trade-off can be suppressed by making the integrated concentration of the high-concentration region 17 in the diode section 80 lower than the integrated concentration of the storage region 16 in the transistor section 70. The integrated concentration in the diode section 80 may be 70% or less of the integrated concentration in the transistor section 70, or it may be 50% or less.

[0100] Figure 3 shows an example of the doping concentration distribution in the e-e' and f-f' cross-sections of Figure 2a. The e-e' cross-section is a cross-section of the mesa portion 95 of the transistor portion 70, and the f-f' cross-section is a cross-section of the mesa portion 95 of the diode portion 80.

[0101] In each accumulation region 16 and high-concentration region 17, the doping concentration distribution in the depth direction of the semiconductor substrate 10 has one peak. If multiple accumulation regions 16 or high-concentration regions 17 are formed in the depth direction of the semiconductor substrate 10, the accumulation regions 16 and high-concentration regions 17 have multiple peaks (maximum values) and minimum values ​​in the doping concentration distribution in the depth direction, located between these multiple peaks. In other words, the region between the multiple minimum values ​​may be considered as one accumulation region 16 or one high-concentration region 17. Each accumulation region 16 and high-concentration region 17 may be formed by injecting impurities from the upper surface 21 or the lower surface 23.

[0102] Figure 3 shows the doping concentration distribution from the emitter region 12 to the upper end of the drift region 18. As shown in Figure 3, the vertical axis of the graph showing the impurity concentration is a logarithmic scale. One division on the vertical axis represents a factor of 10. In this specification, doping concentration refers to the concentration of donor or acceptor impurities. The doping concentrations shown in Figure 3 correspond to the concentration difference between the donor and acceptor.

[0103] Each mesa portion 95 of the transistor section 70 in this example has multiple storage regions 16. In the example shown in Figure 3, the transistor section 70 has a first storage region 16-1, a second storage region 16-2, and a third storage region 16-3. The doping concentration of the first storage region 16-1 is D1, the doping concentration of the second storage region 16-2 is D2, and the doping concentration of the third storage region 16-3 is D3. The doping concentration values ​​may be peak values.

[0104] Furthermore, the doping concentration Dv at the boundary of each accumulation region 16 is the minimum value of the doping concentration distribution in the accumulation region 16. The doping concentration Dv is greater than the doping concentration Dd in the drift region 18. The doping concentration Dv may be 1 / 10 or less of the doping concentration D1, or it may be 1 / 100 or less.

[0105] In multiple accumulation regions 16, there may be multiple boundaries for each accumulation region 16. There may also be multiple minimum values ​​(Dv) of doping concentration at each boundary of each accumulation region 16. The multiple minimum values ​​(Dv) of doping concentration may be different. In this example, the two doping concentration Dv values ​​are approximately the same.

[0106] Each mesa portion 95 of the diode portion 80 in this example has multiple high-concentration regions 17. However, the number of high-concentration regions 17 formed in the depth direction in each mesa portion 95 of the diode portion 80 may be less than the number of storage regions 16 formed in the depth direction in each mesa portion 95 of the transistor portion 70. This makes it easy to make the integrated concentration of one or more high-concentration regions 17 in each mesa portion 95 of the diode portion 80 smaller than the integrated concentration of one or more storage regions 16 in each mesa portion 95 of the transistor portion 70. In the example of Figure 3, the diode portion 80 has a first high-concentration region 17-1 and a second high-concentration region 17-2. The doping concentration of the first high-concentration region 17-1 is D4, and the doping concentration of the second high-concentration region 17-2 is D5.

[0107] Each high-concentration region 17 of the diode section 80 may be located at the same depth as any of the storage regions 16 of the transistor section 70. The depth of each region may be the position where the doping concentration distribution peaks in that region. In this example, the first high-concentration region 17-1 is formed at the same depth as the first storage region 16-1, and the second high-concentration region 17-2 is formed at the same depth as the second storage region 16-2. The same depth position may have a predetermined error. For example, even if the position of the peak has an error of within 10% of the full width at half maximum of the bell-shaped doping concentration distribution including that peak, it can still be considered the same depth position. By forming each region at the same depth position, it becomes easier to simplify the manufacturing process.

[0108] Furthermore, the doping concentration in each high-concentration region 17 of the diode section 80 may be equal to the doping concentration in the storage region 16 provided at the same depth in the transistor section 70. Here, the doping concentration may be the peak value of the doping concentration in that region. In this example, the doping concentration D4 of the first high-concentration region 17-1 is equal to the doping concentration D1 of the first storage region 16-1. Also, the doping concentration D5 of the second high-concentration region 17-2 is equal to the doping concentration D2 of the second storage region 16-2. Note that the doping concentrations being equal may have a predetermined error. For example, even if the doping concentrations have an error of 10% or less, they can be considered to be the same doping concentration. Also, the doping concentration Dv at the boundary between the two high-concentration regions 17 may be equal to the doping concentration Dv at the boundary between the two storage regions 16.

[0109] In this way, by making the depth position and doping concentration of each high-concentration region 17 the same as that of any of the accumulation regions 16, the high-concentration regions 17 can be formed using the same manufacturing process as the accumulation regions 16. Therefore, the manufacturing process can be simplified.

[0110] In each mesa portion 95 of the transistor section 70, the doping concentration of one of the multiple storage regions 16 may be higher than the doping concentrations of the other storage regions 16 formed at different depths. In the transistor section 70 of this example, the doping concentration D3 of the third storage region 16-3, located at the deepest position, is higher than the doping concentrations (D1, D2) of any of the other storage regions 16 of the transistor section 70. The doping concentration D3 may be approximately 3 to 7 times the doping concentration D1. The doping concentrations D1 and D2 may be the same.

[0111] Furthermore, in the multiple storage regions 16 of each mesa portion 95 of the transistor section 70, the multiple doping concentrations Dv may decrease as the depth increases from the upper surface 21. The doping concentration Dv corresponds to the valleys in the doping concentration distribution with respect to the peak concentrations D1, D2, and D3. By making the concentrations of the multiple doping concentration valleys lower in the depth direction, the capacitance between the gate and collector can be adjusted to a predetermined size.

[0112] The diode section 80 does not need to have a high-concentration region 17 corresponding to the region with the highest doping concentration in the storage region 16 of the transistor section 70. This makes it possible to make the integrated concentration of the high-concentration region 17 of the diode section 80 sufficiently lower than the integrated concentration of the storage region 16 in the transistor section 70. In this example, the diode section 80 does not have a high-concentration region 17 at the same depth as the third storage region 16-3 located at the deepest position in the transistor section 70.

[0113] If three or more high-concentration regions 17 are formed in the diode portion 80, the multiple doping concentrations Dv may decrease as the depth increases from the upper surface 21. If three or more high-concentration regions 17 are formed in the boundary portion 90, the multiple doping concentrations Dv may decrease as the depth increases from the upper surface 21.

[0114] As an example, the peak positions of the doping concentrations in each storage region 16 are arranged at equal intervals in the depth direction. In other examples, the peak positions of the doping concentrations in each storage region 16 may be arranged at unequal intervals in the depth direction. By providing multiple storage regions 16 in the transistor section 70, the transient capacitance between the gate conductive section 44 and the collector electrode 24 during turn-on can be increased. This makes it possible to reduce turn-on losses while improving the trade-off between on-voltage and turn-off losses in the transistor section 70.

[0115] Figure 4 shows an example of the collector current Ic waveform during turn-on. Waveform 93 shows the collector current Ic when the storage region 16 is not provided. Waveform 94 shows the collector current Ic when the first storage region 16-1 is provided. Since the first storage region 16-1 is provided near the base region 14, it increases the negative capacitance between the gate and collector. As a result, the di / dt of the collector current Ic during turn-on increases. By providing the first storage region 16-1, the trade-off between on-voltage and turn-off loss can be improved, but since the di / dt during turn-on increases, if the gate resistance is increased to suppress the increase in di / dt, the turn-on loss will increase.

[0116] Waveform 91 shows the collector current Ic when a first storage region 16-1 and a third storage region 16-3 are provided. Since the third storage region 16-3 is located away from the base region 14, it increases the capacitance between the gate and collector. As a result, the di / dt of the collector current Ic at turn-on decreases. Therefore, it is possible to reduce turn-on losses while improving the trade-off between on-voltage and turn-off losses.

[0117] Waveform 92 shows the collector current Ic when a first storage region 16-1, a second storage region 16-2, and a third storage region 16-3 are provided. By providing the second storage region 16-2, the capacitance between the gate and collector is further increased. Therefore, it is possible to further reduce turn-on losses while improving the trade-off between on-voltage and turn-off losses.

[0118] Figure 5 shows another example of the doping concentration distribution in the e-e' and f-f' sections of Figure 2a. In this example, the doping concentration distribution in the transistor section 70 is the same as in the example in Figure 3.

[0119] In this example, the diode section 80 has one high-concentration region 17 in each mesa section 95. That is, between the base region 14 and the drift region 18, there is one peak in the N-type doping concentration distribution which is more concentrated than that of the drift region 18. The high-concentration region 17 in this example may be formed over a longer range in the depth direction than any of the storage regions 16. The doping concentration D6 of the high-concentration region 17 is set such that the integrated concentration of the high-concentration region 17 is lower than the integrated concentration of one or more storage regions 16 in the transistor section 70. The doping concentration D6 of the high-concentration region 17 may be lower or higher than the doping concentration D1 of the first storage region 16.

[0120] This configuration also allows for improved reverse recovery characteristics while suppressing deterioration of the on-voltage-off-loss characteristics in the transistor section 70. Furthermore, it suppresses deterioration of the trade-off between switching loss and on-loss during reverse recovery with respect to the forward voltage in the diode section 80.

[0121] Figure 6 shows the electron current and displacement current at turn-on when the transistor section 70 has a predetermined mesa section 95 and a gate trench section 40 and dummy trench section 30 in contact with the mesa section 95, and is equipped with a first storage region 16-1, a second storage region 16-2, and a third storage region 16-3. Electrons that have passed through the channel begin to move in the alignment direction (X-axis direction) in the first storage region 16-1. However, in this example, the second storage region 16-2 and the third storage region 16-3 are provided below the first storage region 16-1.

[0122] In this example, the impedance for the electron current is lower for the direct path from the first storage region 16-1 to the second storage region 16-2 than for the path from near the center of the first storage region 16-1 back to near the gate trench 40 and then to the second storage region 16-2. Similarly, the impedance is lower for the direct path from the second storage region 16-2 to the third storage region 16-3 than for the path from near the center of the second storage region 16-2 back to near the gate trench 40 and then to the third storage region 16-3.

[0123] Of the areas below each of the accumulation regions 16, holes tend to accumulate in the hole-high concentration regions 87 adjacent to the gate trench 40. Furthermore, the accumulation of holes in the hole-high concentration regions 87 is promoted when the electron current flows near the center of the mesa 95 rather than near the gate trench 40. Therefore, the flow of the electron current near the center of the mesa 95 is promoted. In Figure 6, a hole-high concentration region 87 where holes have accumulated is schematically shown, but the hole-high concentration region 87 may exist only near the boundary between the gate trench 40 and the semiconductor substrate 10.

[0124] As described above, the electron current in this example does not return to the vicinity of the gate trench 40, but instead travels downward through the central part of the mesa 95 sandwiched between the gate trench 40 and the dummy trench 30. In other words, the electron current in this example flows through the central part of the mesa 95, not near the gate trench 40. This effect of the electron current flowing through the central part of the mesa 95 is achieved by arranging the multiple storage regions 16-1 to 16-3 in the depth direction.

[0125] When the electron current flows near the center of the mesa portion 95, the hole distribution near the bottom of the mesa portion 95 is interrupted near the center of the mesa portion 95. As a result, holes on the dummy trench portion 30 side of the electron current path do not flow to the gate trench portion 40 side. This interruption of the hole distribution in the center of the mesa portion 95 suppresses the accumulation of holes at the lower end of the gate trench portion 40. As a result, the displacement current can be reduced. Since the displacement current can be reduced, the charging of the gate conductive portion 44 is also reduced, and the instantaneous increase in the gate electrode Vge is also suppressed. This also suppresses the voltage decrease rate (dV / dt) between the collector electrode 24 and the emitter electrode 52. The hole distribution in the example shown in Figure 6 is thought to be due to the disruption of the hole distribution between the gate trench section 40 and the dummy trench section 30 by the electron current. Furthermore, due to this hole distribution, the displacement current flowing from near the lower end of the dummy trench section 30 to near the lower end of the gate trench section 40 can be reduced during turn-on.

[0126] Furthermore, the second storage region 16-2 and the third storage region 16-3 do not necessarily have to be in contact with the dummy trench portion 30. In this case, holes can exist from the lower end of the dummy trench portion 30 to directly below the first storage region 16-1 on the side of the dummy trench portion 30. This facilitates the extraction of holes to the emitter electrode 52 during turn-off.

[0127] Figure 7a shows another example of the d-d' cross section in Figure 1. In this example, the structure of the diode section 80 and the boundary section 90 is the same as in any of the examples shown in Figures 1 to 5.

[0128] In this example, the integral concentration of one or more storage regions 16 in mesa portion 95-1, which is located closest to the diode portion 80, is lower than the integral concentration of one or more storage regions 16 in other mesa portions 95 of the transistor portion 70 (e.g., mesa portion 95-2). This makes it possible to slow down the change in integral concentration between adjacent mesa portions 95, thereby suppressing the concentration of electric fields or currents. In the mesa portions 95 of the transistor portion 70, the integral concentration may decrease as it gets closer to the diode portion 80 in multiple mesa portions 95 on the diode portion 80 side.

[0129] Furthermore, the integrated concentration of one or more storage regions 16 in the mesa portion 95-1 may be higher than the integrated concentration of one or more high-concentration regions 17 in the mesa portion 95-3 of the diode portion 80. By making the integrated concentration in the mesa portion 95-1 at the end of the transistor portion 70 higher than the integrated concentration in the mesa portion 95-3 of the diode portion 80, the injection of holes from the transistor portion 70 into the diode portion 80 can be suppressed.

[0130] Figure 7b shows an example of the doping concentration distribution in the e-e', f-f', and g-g' sections shown in Figure 7a. The e-e' section is a cross-section at mesa 95-2, the f-f' section is a cross-section at mesa 95-3, and the g-g' section is a cross-section at mesa 95-1.

[0131] In this example, the number of storage regions 16 in the mesa portion 95-1 at the end of the transistor portion 70 is less than the number of storage regions 16 in the other mesa portion 95-2 of the transistor portion 70. Also, the number of high-concentration regions 17 in the diode portion 80 is less than the number of storage regions 16 in the mesa portion 95-1. With this configuration, the integral concentration in each mesa portion 95 can be easily adjusted.

[0132] In this example, each accumulation region 16 in mesa section 95-1 is located at the same depth as any of the accumulation regions 16 in mesa section 95-2. The doping concentrations of the accumulation regions 16 formed at the same depth are the same. In the example in Figure 7b, mesa section 95-1 does not have an accumulation region 16 corresponding to the third accumulation region 16-3, which has the highest doping concentration among the accumulation regions 16 provided in mesa section 95-2. In other examples, mesa section 95-1 may have an accumulation region 16 corresponding to the third accumulation region 16-3, which has the highest doping concentration. In this case, mesa section 95-1 does not have an accumulation region 16 corresponding to the first accumulation region 16-1 or the second accumulation region 16-2.

[0133] The high-concentration region 17 in mesa section 95-3 is located at the same depth as one of the accumulation regions 16 in mesa section 95-1. In this example, it is located at the same depth as the first accumulation region 16-1.

[0134] In mesa sections 95-1, 95-2, and 95-3, the high-concentration N-type regions formed at the same depth may have the same doping concentration. In the example shown in Figure 7b, D1=D6=D8 and D2=D7. This configuration simplifies the manufacturing process.

[0135] It should be noted that the doping concentration distribution of the high-concentration N-type region in each mesa 95 is not limited to the example shown in Figure 7b. For example, one high-concentration N-type region may be formed in mesa 95-1 and one in mesa 95-3. In this case, the doping concentration of the high-concentration N-type region in mesa 95-1 is higher than the doping concentration of the high-concentration N-type region in mesa 95-3.

[0136] Figure 8 shows another example of the d-d' cross section in Figure 1. The semiconductor device 100 in this example further comprises a floating region 84 in addition to the configuration of any of the semiconductor devices 100 described in Figures 2a to 7b. The floating region 84 is provided on the lower surface 23 side of the diode portion 80. In this example, the lower surface 23 side refers to the region between the center of the semiconductor substrate 10 in the depth direction and the upper end of the cathode region 82. The floating region 84 in this example is formed in contact with the upper end of the cathode region 82.

[0137] The floating region 84 is a region of the second conductivity type (P+ in this example) that is electrically floating. Electrically floating means that it is not electrically connected to either the collector electrode 24 or the emitter electrode 52. By providing the floating region 84, electron injection from the cathode region 82 can be suppressed. This allows for adjustment of the carrier distribution in the depth direction of the semiconductor substrate 10 without forming a lifetime killer on the back side of the semiconductor substrate 10. Therefore, costs can be reduced, and leakage current caused by the lifetime killer can be reduced.

[0138] The floating region 84 is formed to partially cover the cathode region 82. In other words, a portion of the cathode region 82 is not covered by the floating region 84. This allows the diode section 80 to operate as a diode even with the floating region 84 present. To suppress electron injection, the floating region 84 may be formed to cover an area larger than half of the upper surface of the cathode region 82.

[0139] Figure 9 is a cross-sectional view illustrating an example of the arrangement of the floating region 84. In Figure 9, the vicinity of the floating region 84 is shown in an enlarged view. Note that the collector electrode 24 is omitted in Figure 9. In Figure 9, the boundary portion 90 is provided adjacent to the diode portion 80, but in other examples, the transistor portion 70 may be provided adjacent to the diode portion 80.

[0140] In this example, P1 is defined as the boundary position between the collector region 22 and the cathode region 82 in a plane parallel to the lower surface 23. In Figure 9, P1 is defined as the boundary position in a cross section parallel to the d-d' cross section. For example, the d-d' cross section is a plane perpendicular to the lower surface 23 and parallel to the arrangement direction of each trench section.

[0141] Furthermore, in a plane parallel to the lower surface 23, the end position of the floating region 84 is defined as P2. End position P2 is the end position of the floating region 84 closest to the boundary position P1. The distance from the boundary position P1 to the end position P2 in a plane parallel to the lower surface 23 is defined as L1. Distance L1 may be the distance L1 in a cross section parallel to the d-d' cross section.

[0142] Furthermore, the width of the floating region 84 in a plane parallel to the lower surface 23 is defined as L2. The width L2 of the floating region 84 is the width of the floating region 84 in the linear direction connecting the boundary position P1 and the end position P2. The linear direction may be parallel to the arrangement direction of the trench sections.

[0143] In this example, the distance L1 from the boundary position P1 to the end position P2 is smaller than the width L2 of the floating region 84. The distance L1 may be less than or equal to half of the width L2, or less than or equal to one-quarter of the width L2. The distance L1 may be greater than 0. In other words, the floating region 84 does not have to be connected to the collector region 22. In other examples, the floating region 84 may be formed above the collector region 22.

[0144] Furthermore, if multiple floating regions 84 are provided in the cross-section, the width L2 of the floating region 84 may be the average value of the widths of the multiple floating regions 84. By reducing the distance L1, the injection of electrons from the cathode region 82 at the end of the diode portion 80 can be suppressed.

[0145] Furthermore, the diode section 80 has an opening region 85 at the same depth as the floating region 84, where the floating region 84 is not provided. The opening region 85 may refer to the region sandwiched between the floating regions 84. For example, the opening region 85 is an N-type region. The doping concentration of the opening region 85 may be the same as the doping concentration of the drift region 18 or buffer region 20. The opening region 85 may be the drift region 18 or buffer region 20 that remains without the formation of the floating region 84.

[0146] In this example, the width of the opening region 85 in the linear direction described above is denoted as L3. The distance L1 from the boundary position P1 to the end position P2 may be smaller than the width L3 of the opening region 85. The distance L1 may be half or less of the width L3, or one-quarter or less. Also, the width L2 may be twice or more the width L3, three or more, or five or more.

[0147] Furthermore, if multiple opening regions 85 are provided in the cross-section, the width L3 of the opening region 85 may be the average value of the widths of the multiple opening regions 85. By reducing the distance L1, electron injection from the cathode region 82 can be suppressed at the end of the diode portion 80.

[0148] Furthermore, the length of the floating region 84 in the depth direction is denoted as L4. The depth direction refers to the direction perpendicular to the bottom surface 23. The distance L1 from the boundary position P1 to the end position P2 may be greater than the length L4 of the floating region 84 in the depth direction. The distance L1 may be more than twice the length L4, or more than three times the length L4. L4 may be 1 μm or less, or 0.75 μm or less. In addition, the doping concentration distribution of the floating region 84 in at least one of the depth direction and the direction parallel to the bottom surface 23 of the semiconductor substrate 10 may be a Gaussian distribution or a distribution close to it. The peak concentration of the floating region 84 is 5 × 10⁻¹⁴. 16 / cm 3 The above is 1 x 10 18 / cm 3 The following may be true, and in this example, 3 × 10 17 / cm 3 That is the case.

[0149] Figure 10 is a top view showing an example of the arrangement of the floating region 84 in the diode portion 80 when projected from the lower surface 23 of the semiconductor substrate 10 onto the upper surface 21 of the semiconductor substrate 10. The floating region 84 is located on the upper surface 21 of the semiconductor substrate 10 in the region where the dummy trench portion 30 is provided. In this example, the floating region 84 is located in the X-axis direction to a position beyond the longitudinal (extension direction) end of the dummy trench portion 30, or beyond the position of the connection portion 25 where the dummy trench portion 30 is electrically connected to the emitter electrode 52. In this example, the floating region 84 does not reach a position that overlaps with the gate runner 48 or the gate metal layer 50. The end of the floating region 84 in the extension direction of the trench portion may be located at a position that overlaps with the well region 11.

[0150] In this example, the cathode region 82 is located inside (in the +X-axis direction) of the contact region 15 formed at the end of the contact hole 54. The end of the floating region 84 in the extension direction of the dummy trench portion 30 is located on the outer circumference (in the -X-axis direction) of the X-axis end of the contact hole 54.

[0151] Figure 11 is a top view showing an example of the arrangement of the floating region 84 in the diode section 80. While Figure 10 showed only a part of the diode section 80, Figure 11 shows the entire region in the diode section 80 where the dummy trench section 30 is provided. The diode section 80 may also be the region in which the cathode region 82 is formed.

[0152] In this example, multiple floating regions 84 are discretely arranged on the upper surface of the semiconductor substrate 10. Aperture regions 85 are arranged between each floating region 84. Each aperture region 85 may be connected to one another. On the upper surface of the semiconductor substrate 10, the area ratio of the floating region 84 to the total area of ​​the floating region 84 and aperture region 85 may be 80% or more, 90% or more, or 95% or more. The distance L2 between the floating regions 84 may be 5 μm or more and 1000 μm or less, and in this example it is 720 μm. The distance L3 between adjacent floating regions 84 and aperture region 85 may be 1 μm or more and 200 μm or less, and in this example it is 180 μm.

[0153] Figure 12 is a top view showing another example of the arrangement of floating regions 84 in the diode section 80. In this example, multiple aperture regions 85 are discretely arranged on the top surface of the semiconductor substrate 10. Floating regions 84 are arranged between each aperture region 85. Each floating region 84 may be connected to one another. The diode section 80 may be the region in which the cathode region 82 is formed.

[0154] On the upper surface of the semiconductor substrate 10, the area ratio of the floating region 84 to the total area of ​​the floating region 84 and aperture region 85 may be 80% or more, 90% or more, or 95% or more. The distance L2 between the floating regions 84 may be 5 μm or more and 1000 μm or less, and in this example it is 720 μm. The distance L3 between adjacent floating regions 84 and aperture region 85 may be 1 μm or more and 200 μm or less, and in this example it is 180 μm.

[0155] Figure 13 shows another example of the d-d' cross section in Figure 1. The semiconductor device 100 in this example further comprises a dummy region 86 of a second conductivity type (P+ in this example) compared to any of the semiconductor device 100 configurations shown in Figures 2a to 7b. On the lower surface 23 of the diode portion 80, the dummy region 86 and the cathode region 82 are alternately exposed. The dummy region 86 may be electrically connected to the collector electrode 24.

[0156] This configuration also suppresses electron injection from the cathode region 82. The area where the dummy region 86 is formed on the lower surface 23 may be larger than the area where the cathode region 82 is formed.

[0157] Figure 14 shows another example of the d-d' cross section in Figure 1. The semiconductor device 100 in this example further includes a lifetime killer 88 compared to any of the semiconductor device 100 configurations shown in Figures 2a to 7b. The lifetime killer 88 is formed on the lower surface 23 side. In this example, the lower surface 23 side refers to the region between the center of the semiconductor substrate 10 in the depth direction and the lower surface 23.

[0158] Furthermore, the lifetime killer 88 is formed locally in the depth direction of the semiconductor substrate 10. In other words, the region where the lifetime killer 88 is formed has a higher defect density compared to other regions of the semiconductor substrate 10. In this example, the lifetime killer 88 is helium injected at a predetermined depth. By injecting helium, crystal defects can be formed inside the semiconductor substrate 10. The lifetime killer 88 may be formed over the entire surface of the transistor portion 70, the diode portion 80, and the boundary portion 90.

[0159] Furthermore, localized lifetime killers do not need to be provided on the upper surface 21. In this example, the upper surface 21 refers to the region between the center of the semiconductor substrate 10 in the depth direction and the bottom of the trench. In this example, no region with locally high helium concentration (or crystal defect density) is formed on the upper surface 21.

[0160] As described above, since the semiconductor device 100 has high-density N-type regions in each mesa portion 95 of the transistor portion 70 and the diode portion 80, it is possible to either not form a crystal defect layer due to lifetime killers on the upper surface 21 side, or to reduce the crystal defect density of the crystal defect layer, thereby adjusting the minority carrier injection efficiency of the diode portion 80. This reduces the cost of forming lifetime killers and suppresses leakage current and other issues caused by lifetime killers.

[0161] Furthermore, a localized lifetime killer does not necessarily need to be formed on the lower surface 23. In this case, it is preferable that the lower surface 23 has a structure as shown in Figure 8 or Figure 13. This further reduces the cost of forming a lifetime killer and further suppresses leakage current and other issues caused by the lifetime killer.

[0162] Figure 15 shows another example of the arrangement of the lifetime killer 88. In this example, the diode section 80 is provided with a floating region 84 and an aperture region 85. In this example, the lifetime killer 88 is provided in at least a portion of the area above the floating region 84, and the lifetime killer 88 is not provided in at least a portion of the area above the aperture region 85. This allows for adjustment of the lifetime of carriers injected from the floating region 84. In addition, the density of defects caused by the injection of the lifetime killer can be reduced above the aperture region 85.

[0163] A lifetime killer 88 may be provided over the entire upper part of the floating region 84. However, a lifetime killer 88 may not be provided over the entire upper part of the opening region 85.

[0164] The semiconductor device 100 in this example has multiple buffer regions 20 located at different depth positions. These multiple buffer regions 20 can be formed by injecting impurities such as protons multiple times with varying injection ranges. Figure 15 shows the peak positions in the depth direction of the doping concentration for each buffer region 20. The doping concentration between each buffer region 20 may be higher than the doping concentration in the drift region 18.

[0165] Furthermore, in Figure 15, the peak position of the lifetime killer 88 concentration in the depth direction is indicated by an "X". Preferably, the peak position of the lifetime killer 88 is different from the peak position of the buffer region 20. This prevents defects in the lifetime killer 88 from being terminated by protons in the buffer region 20. The peak position of the lifetime killer 88 concentration may be located between the peak positions of the doping concentrations of the two buffer regions 20.

[0166] Figure 16 shows an example of the configuration of the diode section 80. In this example, the diode section 80 has two or more high-concentration regions 17 in each mesa section 95. For example, each mesa section 95 may have two high-concentration regions 17.

[0167] Furthermore, the structure on the lower surface 23 side may be the same as any of the diode sections 80 shown in Figures 1 to 15. The diode section 80 in the example of Figure 16 has a floating region 84 and an opening region 85, similar to the example shown in Figure 8.

[0168] Figures 1 to 15 illustrate a semiconductor device 100 comprising a transistor section 70, a boundary section 90, and a diode section 80. In other examples, the semiconductor device 100 may comprise only the diode section 80.

[0169] Figure 17 shows another example of the configuration of the diode section 80. The diode section 80 in this example is identical to the diode section 80 shown in Figure 16, except for the arrangement of the high-concentration region 17. In this example, the integrated concentration of the high-concentration region 17 in at least one of the mesa sections 95 located above the floating region 84 is lower than the integrated concentration of the high-concentration region 17 in at least one of the mesa sections 95 located above the opening region 85. For example, a mesa section 95 in which the entire mesa section 95 is located above the floating region 84 has a lower integrated concentration of the high-concentration region 17 than a mesa section 95 in which the entire mesa section 95 is located above the opening region 85.

[0170] In the example shown in Figure 17, the number of high-concentration regions 17 arranged in the depth direction in the mesa portion 95 located above the floating region 84 is less than the number of high-concentration regions arranged in the depth direction in the mesa portion 95 located above the opening region 85. This structure makes it possible to reduce the difference in diode characteristics between the portion with the floating region 84 and the portion with the opening region 85.

[0171] Figure 18 shows another example of the semiconductor device 100. This example of the semiconductor device 100 includes a floating region 84 and does not include a storage region 16 and a high-concentration region 17. The other structures are the same as those of the semiconductor device 100 shown in Figures 1 to 17. A local lifetime killer may or may not be provided on at least one of the upper surface 21 side and the lower surface 23 side. The boundary portion 90 may also not be provided.

[0172] Figure 19 is a diagram showing a partial view of the upper surface of a semiconductor device 200 according to another embodiment of the present invention. The semiconductor device 200 in this example differs from the semiconductor device 100 shown in Figure 1 in that the base region 14 and the contact region 15 on the upper surface of the diode portion 80 are arranged alternately adjacent to each other so as to be exposed on the upper surface of the mesa portion 95 along the extending direction of the trench portion. As an example, the width of the base region 14 in the extending direction of the trench portion may be made larger than the width of the contact region 15 in the extending direction of the trench portion.

[0173] In the diode section 80, the length of the contact region 15 along the extending direction of the trench section is L A , and the length of the base region 14 along the extending direction of the trench section is L B . When this is done, L A >L B may be satisfied. For example, dI AK / dV AK increases at 2 to 3 times the rated current density, and the surge current withstand capacity can be strongly ensured.

[0174] Alternatively, in the diode section 80, the length of the contact region 15 along the extending direction of the trench section is L A , and the length of the base region 14 along the extending direction of the trench section is L B . When this is done, L A <L B may also be satisfied. For example, dI AK / dV AK increases, so the reduction effect of the reverse recovery current is maintained for the reverse recovery at about the rated current density, and the surge current withstand capacity can be strongly ensured for a surge current of 5 times or more the rated current density. For example, the ratio obtained by dividing the length L A by the length L B , L A / L B may be 10% or more and 90% or less.

[0175] At the position where the position of the outer peripheral side end of the cathode region 82 in the X-axis direction is projected onto the upper surface 21, there may be a region sandwiched between the adjacent contact regions 15 in the X-axis direction and where the contact region 15 is not formed. On the surface of the mesa portion 95 on the outer peripheral side (-X-axis direction) from the position where the position of the outer peripheral side end of the cathode region 82 in the X-axis direction is projected onto the upper surface 21, the base region 14 may be exposed.

[0176] Figure 20 shows an example of the d-d' cross-section in Figure 19. The semiconductor device 200 in this example differs from the semiconductor device 100 shown in Figure 2a in that it has a contact region 15 on the base region 14 in this cross-section. By arranging the upper surface of the diode portion 80 in an alternating configuration where the base region 14 and the contact region 15 are adjacent to each other, the forward voltage Vf at high currents can be reduced.

[0177] Figure 21a is a diagram showing a partial view of the top surface of a semiconductor device 300 according to another embodiment of the present invention. The semiconductor device 300 in this example differs from the semiconductor device 100 shown in Figure 1 in that the contact holes 54 are provided above the semiconductor substrate 10, extending from the negative side in the Y-axis direction to the positive side in the Y-axis direction of the dummy trench portion 30.

[0178] From the region adjacent to the boundary 90 of the transistor section 70 to the diode section 80, the gate trench section 40 is not provided, but a dummy trench section 30 is provided. Therefore, the width of the contact hole 54 in the Y-axis direction from the region adjacent to the boundary 90 of the transistor section 70 to the diode section 80 is wider than the contact hole 54 provided in the region of the transistor section 70 excluding the boundary 90.

[0179] Furthermore, the position of the +X-axis direction (inner circumference side of the semiconductor device) end of the contact region 15 formed at the X-axis end of the diode portion 80 may be in the -X-axis direction (outer circumference side) rather than the position obtained by projecting the cathode region 82 onto the front surface of the semiconductor substrate 10, similar to the semiconductor device 100 shown in Figure 1. The area of ​​the base region 14 of the diode portion 80 on the front surface may be larger than the area obtained by projecting the cathode region 82 onto the front surface of the semiconductor substrate 10.

[0180] The contact holes 54 of the diode portion 80 may be formed across multiple mesa portions 95 and dummy trench portions 30 in the direction of arrangement of the dummy trench portions 30. By forming the contact holes 54 across multiple mesa portions 95 and dummy trench portions 30 in the diode portion 80, the contact area between the diode portion 80 and the emitter electrode 52 is increased. As a result, carriers are less likely to accumulate directly beneath the interlayer insulating film 38, and the minority carrier injection efficiency can be reduced.

[0181] The contact hole 54 of the diode section 80 may extend to the boundary section 90. Furthermore, the contact hole 54 of the diode section 80 may extend, including the boundary section 90, to the mesa section 95 that contacts the gate trench section 40 of the transistor section 70 that is located closest to the diode section 80 in the Y-axis direction. This makes it easier to extract accumulated carriers from the boundary region between the transistor section 70 and the diode section 80, including the boundary section 90.

[0182] Figure 21b shows an example of the s-s' cross section in Figure 21a. The s-s' cross section is the YZ plane in the transistor section 70 of the semiconductor device 300 in this example, extending from adjacent dummy trench sections 30 on the negative Y-axis side of the gate trench section 40 to adjacent dummy trench sections 30 on the positive Y-axis side, passing through the emitter region 12.

[0183] In the s-s' cross-section, the semiconductor device 300 has a collector electrode 24 provided on the lower surface 23 and an emitter electrode 52 provided on the upper surface 21. On the upper surface 21 side, an N+ type emitter region 12, a P- type base region 14, and one or more N+ type storage regions 16 are arranged in order from the upper surface 21 side. Below the storage region 16, an N- type drift region 18 is formed. Below the drift region 18, an N+ type buffer region 20 is formed. Below the buffer region 20, a P+ type collector region 22 is formed that is exposed on the lower surface 23.

[0184] An interlayer insulating film 38 is provided on the upper surface 21 above the gate trench portion 40. In the Y-axis direction, there is no interlayer insulating film 38 on the upper surface 21 between the dummy trench portion 30 and the interlayer insulating film 38 on the gate trench portion 40. Also, there is no interlayer insulating film 38 on the upper surface 21 above the dummy trench portion 30.

[0185] In the s-s' section, the width Wi is the width in the Y-axis direction from the Y-axis end P3 of the gate trench section 40 to the end P4 of the contact hole 54. End P3 is the position in the XZ plane where the trench side wall of the gate trench section 40 contacts the upper surface 21. End P4 is the position of the end face of the interlayer insulating film 38 in the XZ plane in a section parallel to the YZ plane. More specifically, end P4 may be the position where the end face of the interlayer insulating film 38 in the XZ plane contacts the upper surface 21. If the upper or side surface of the interlayer insulating film 38 is curved rather than flat, end P4 may be the position where the interlayer insulating film 38 contacts the upper surface 21.

[0186] The width Wm is the width from the end P3 of the gate trench section 40 to the end P3' of the dummy trench section 30 adjacent to the gate trench section 40, i.e., the mesa width. The width Wm may be 1.5 to 3.5 times the width Wi. For example, the width Wm may be 0.5 μm. For example, the width Wi may be 0.2 μm.

[0187] The width from end P4 to end P3' of the dummy trench section 30 adjacent to the gate trench section 40 may be longer than the width Wi. A width longer than the width Wi from end P4 to end P3' makes it easier to extract the carrier from the transistor section 70, especially during turn-off. Furthermore, latch-up of the transistor section 70 is suppressed.

[0188] Alternatively, the width from end P4 to end P3' of the dummy trench section 30 adjacent to the gate trench section 40 may be shorter than the width Wi. A shorter width from end P4 to end P3' than the width Wi makes it easier to increase the carrier concentration around the gate trench section 40. This leads to a reduction in the on-voltage of the transistor section 70.

[0189] In this example, the semiconductor device 300 does not have an interlayer insulating film 38 above the dummy trench portion 30, nor above the semiconductor substrate 10 on the positive and negative Y-axis sides of the dummy trench portion 30. That is, the emitter electrode 52 is in continuous contact along the Y-axis direction across the multiple dummy trench portions 30 and the upper surface of the mesa portion 95. Therefore, in the mesa portion 95, a large margin can be set for setting the position of the end P4 of the contact hole 54 in the Y-axis direction. In other words, even if the width Wi is increased relative to the width Wm, and the ratio of width Wi to width Wm is increased, the contact area between the emitter region 12 and the emitter electrode 52 provided in the contact hole 54 can be secured. Furthermore, by increasing the width Wi relative to the width Wm, the gate metal layer 50 and the gate conductive portion 44 can be more reliably insulated.

[0190] Furthermore, in this example, the semiconductor device 300 does not have an interlayer insulating film 38 above the emitter region 12 between the end P4 and the end P3'. Therefore, even if the width Wm is reduced relative to the width Wi and the ratio of width Wi to the width Wm is increased, the contact area between the emitter region 12 and the emitter electrode 52 provided in the contact hole 54 can be secured. In other words, the mesa width Wm can be reduced. As a result, the characteristics of the transistor section 70 can be improved. In addition, since microfabrication of the contact hole 54 is unnecessary, the manufacturing cost of the semiconductor device 300 can be reduced.

[0191] Figure 21c shows an example of a t-t' cross-section in Figure 21a. The t-t' cross-section is the YZ plane that extends from the transistor section 70 to the diode section 80 of the semiconductor device 300 in this example, passing through the emitter region 12, the contact region 15, and the base region 14.

[0192] In the t-t' cross-section, the transistor 70 has a collector electrode 24 provided on the lower surface 23 and an emitter electrode 52 provided on the upper surface 21. On the upper surface 21 side, an N+ type emitter region 12, a P- type base region 14, and one or more N+ type storage regions 16 are formed sequentially from the upper surface 21 side. Below the storage region 16, an N- type drift region 18 is formed.

[0193] Below the drift region 18, an N+ type buffer region 20 is formed. Below the buffer region 20, a P+ type collector region 22 is formed, exposed on the lower surface 23. Above the gate trench portion 40, an interlayer insulating film 38 is provided on the upper surface 21.

[0194] In the Y-axis direction of the t-t' cross-section of the transistor section 70, the interlayer insulating film 38 is not provided on the upper surface 21 between the dummy trench section 30 and the interlayer insulating film 38 on the gate trench section 40. Furthermore, the interlayer insulating film 38 is not provided on the upper surface 21 above the dummy trench section 30. In other words, the emitter electrode 52 is in continuous contact along the Y-axis direction across the upper surfaces of the multiple dummy trench sections 30 and the mesa section 95.

[0195] In the t-t' cross section, the boundary portion 90 has a collector electrode 24 provided on the lower surface 23 and an emitter electrode 52 provided on the upper surface 21. On the upper surface 21 side, a P+ type contact region 15 and a P- type base region 14 are formed sequentially from the upper surface 21 side. Below the base region 14, an N- type drift region 18 is formed.

[0196] Below the drift region 18, an N+ type buffer region 20 is formed. Below the buffer region 20, a P+ type collector region 22 is formed, which is exposed on the lower surface 23. The collector region 22 may be an extension of the collector region 22 of the transistor portion 70 in the Y-axis direction. In the Y-axis direction of the t-t' cross section of the boundary portion 90, the interlayer insulating film 38 is not provided on the upper surface 21 above the dummy trench portion 30 and above the contact region 15.

[0197] The emitter electrode 52 is in continuous contact with the dummy trench portion 30 and the upper surface of the mesa portion 95 along the Y-axis direction, without including the interlayer insulating film 38, from the gate trench portion 40 located closest to the boundary portion 90 to the boundary portion 90.

[0198] In the t-t' cross-section, the diode portion 80 has a collector electrode 24 provided on the lower surface 23 and an emitter electrode 52 provided on the upper surface 21. On the upper surface 21 side, a P-type base region 14 and one or more N+-type storage regions 16 are formed sequentially from the upper surface 21 side. Below the storage region 16, an N-type drift region 18 is formed. Below the drift region 18, an N+-type buffer region 20 is formed. Below the buffer region 20, an N+-type cathode region 82 is formed which is exposed on the lower surface 23.

[0199] In the t-t' cross-section, the diode portion 80 does not have an interlayer insulating film 38 on its upper surface 21 above the dummy trench portion 30 and above the base region 14. That is, the emitter electrode 52 is in continuous contact with the upper surfaces of the multiple dummy trench portions 30 and mesa portions 95 along the Y-axis direction. The emitter electrode 52 is in continuous contact with the upper surfaces of the dummy trench portions 30 and mesa portions 95 without including an interlayer insulating film 38 between the boundary portion 90 and the diode portion 80.

[0200] In this example, the semiconductor device 300 has contact holes 54 that are continuously provided in the Y-axis direction, extending from the region of the transistor section 70 adjacent to the boundary section 90 to the diode section 80. Here, "continuous provision of contact holes 54 in the Y-axis direction" means that there is no region in the Y-axis direction from the region of the transistor section 70 adjacent to the boundary section 90 to the diode section 80 where contact holes 54 are not provided.

[0201] In this example, the semiconductor device 300 does not have an interlayer insulating film 38 above the emitter region 12 between edge P4 and edge P3'. Therefore, even if the width Wi is increased relative to the width Wm, and the ratio of width Wi to the width Wm is increased, the contact area between the emitter region 12 and the emitter electrode 52 provided in the contact hole 54 can be secured. That is, a larger margin can be taken between edge P3 and edge P4. In addition, by increasing the width Wi relative to the width Wm, the gate metal layer 50 and the gate conductive part 44 can be more reliably insulated.

[0202] Furthermore, in this example, the semiconductor device 300 does not have an interlayer insulating film 38 above the emitter region 12 between the end P4 and the end P3'. Therefore, even if the width Wm is reduced relative to the width Wi and the ratio of width Wi to the width Wm is increased, the contact area between the emitter region 12 and the emitter electrode 52 provided in the contact hole 54 can be secured. In other words, the mesa width Wm can be reduced. As a result, the characteristics of the transistor section 70 can be improved. In addition, since microfabrication of the contact hole 54 is unnecessary, the manufacturing cost of the semiconductor device 300 can be reduced.

[0203] Figure 22 is a cross-sectional view of the comparative example semiconductor device 350. In the comparative example semiconductor device 350, an interlayer insulating film 38 is provided above the gate trench portion 40 and above the dummy trench portion 30. Therefore, in addition to the end P4, the end P4' of the interlayer insulating film 38 above the dummy trench portion 30 is positioned with a width Wi from the end P3' of the dummy trench portion 30 towards the gate trench portion 40. Therefore, in the comparative example semiconductor device 350, if the width Wi is increased relative to the width Wm, and the ratio of width Wi to width Wm is increased, the ends P4 and P4' become close together. Therefore, in the comparative example semiconductor device 350, compared to the semiconductor device 300 of Figure 21b, it is difficult to secure a contact area between the emitter region 12 and the emitter electrode 52 provided in the contact hole 54. That is, it is difficult to provide a large margin between the ends P3 and P4. Also, it is difficult to provide a large margin between the ends P3' and P4'.

[0204] Furthermore, in the comparative example semiconductor device 350, in addition to the end P4, the end P4' of the interlayer insulating film 38 above the dummy trench portion 30 is located on the side of the gate trench portion 40 from the end P3' of the dummy trench portion 30. Therefore, if the width Wm is reduced relative to the width Wi and the ratio of width Wi to width Wm is increased, the end P4 and end P4' become close together. For this reason, the comparative example semiconductor device 350 has difficulty securing the contact area between the emitter region 12 and the emitter electrode 52 provided in the contact hole 54 compared to the semiconductor device 300 in Figure 21b. In other words, it is difficult to reduce the mesa width Wm. For this reason, it is difficult to improve the characteristics of the transistor portion 70. Also, since microfabrication of the contact hole 54 is required, it is difficult to reduce the manufacturing cost of the semiconductor device 300.

[0205] Figure 23a is a diagram showing a partial view of the top surface of a semiconductor device 300 according to another embodiment of the present invention. The semiconductor device 300 in this example differs from the semiconductor device 300 in Figure 21a in that the dummy trench portion 30 has a U-shape when viewed from above, and multiple dummy trench portions 30 are sandwiched in the gate trench portion 40 in the Y-axis direction above the emitter region 12 and the contact region 15. In the semiconductor device 300 in this example, multiple dummy trench portions 30 are sandwiched in the gate trench portion 40 in the Y-axis direction above the emitter region 12 and the contact region 15, so the width of the contact hole 54 in the Y-axis direction is larger in the transistor portion 70 than in the semiconductor device 300 shown in Figure 21a.

[0206] At the position where the outer edge of the cathode region 82 in the X-axis direction is projected onto the upper surface 21, there may be a region sandwiched between adjacent contact regions 15 in the X-axis direction, where no contact region 15 is formed. The base region 14 may be exposed on the surface of the mesa portion 95 on the outer side (-X-axis direction) of the position where the outer edge of the cathode region 82 in the X-axis direction is projected onto the upper surface 21.

[0207] Figure 23b shows an example of the u-u' cross-section in Figure 23a. The u-u' cross-section is the YZ plane that passes through the emitter region 12 in the transistor section 70 of the semiconductor device 300 in this example, extending from the dummy trench section 30 located on the positive Y-axis side of the two dummy trench sections 30 located on the positive Y-axis side of the gate trench section 40 to the dummy trench section 30 located on the negative Y-axis side of the two dummy trench sections 30 located on the negative Y-axis side of the gate trench section 40.

[0208] In this example, the semiconductor device 300 does not have an interlayer insulating film 38 above the emitter region 12 between edge P4 and edge P3'. Therefore, similar to the semiconductor device 300 shown in Figure 21b, even if the width Wi is increased relative to the width Wm, and the ratio of width Wi to width Wm is increased, the contact area between the emitter region 12 and the emitter electrode 52 provided in the contact hole 54 can be secured. That is, a larger margin can be provided between edge P3 and edge P4. In addition, by increasing the width Wi relative to the width Wm, the gate metal layer 50 and the gate conductive part 44 can be more reliably insulated.

[0209] Furthermore, in this example, the semiconductor device 300 does not have an interlayer insulating film 38 above the emitter region 12 between the end P4 and the end P3'. Therefore, similar to the semiconductor device 300 shown in Figure 21b, even if the width Wm is reduced relative to the width Wi and the ratio of width Wi to the width Wm is increased, the contact area between the emitter region 12 and the emitter electrode 52 provided in the contact hole 54 can be secured. In other words, the mesa width Wm can be reduced. As a result, the characteristics of the transistor section 70 can be improved. In addition, since microfabrication of the contact hole 54 is unnecessary, the manufacturing cost of the semiconductor device 300 can be reduced.

[0210] Figure 23c shows an example of the v-v' cross-section in Figure 21a. The v-v' cross-section is the YZ plane that extends from the transistor section 70 to the diode section 80 of the semiconductor device 300 in this example, passing through the emitter region 12, the contact region 15, and the base region 14.

[0211] In this example, the semiconductor device 300, like the semiconductor device 300 shown in Figure 21c, has contact holes 54 extending from the transistor section 70 to the diode section 80. In this example, the semiconductor device 300 does not have an interlayer insulating film 38 above the emitter region 12 between the end P4 and the end P3'. Therefore, similar to the semiconductor device 300 shown in Figure 21c, even if the width Wi is increased relative to the width Wm, and the ratio of width Wi to width Wm is increased, the contact area between the emitter region 12 and the contacts provided in the contact holes 54 can be secured. In other words, a larger margin can be provided between the end P3 and the end P4.

[0212] Furthermore, in this example, the semiconductor device 300 does not have an interlayer insulating film 38 above the emitter region 12 between the end P4 and the end P3'. Therefore, similar to the semiconductor device 300 shown in Figure 21c, even if the width Wm is reduced relative to the width Wi and the ratio of width Wi to the width Wm is increased, the contact area between the emitter region 12 and the emitter electrode 52 provided in the contact hole 54 can be secured. In other words, the mesa width Wm can be reduced. As a result, the characteristics of the transistor section 70 can be improved. In addition, since microfabrication of the contact hole 54 is unnecessary, the manufacturing cost of the semiconductor device 300 can be reduced.

[0213] Figure 24 is a diagram showing a partial view of the top surface of a semiconductor device 300 according to another embodiment of the present invention. The semiconductor device 300 of this example differs from the semiconductor device 300 of Figure 21a in that a gate runner 48 is not provided to electrically connect the gate trench portion 40 and the gate metal layer 50, and the gate metal layer 50 is electrically connected to the gate trench portion 40 through a contact hole 49 provided on the gate trench portion 40 at the most negative side in the X-axis direction of the gate trench portion 40.

[0214] In this example, the semiconductor device 300 does not have an interlayer insulating film 38 above the dummy trench portion 30. Therefore, compared to the semiconductor device 300 shown in Figures 21a to 21c, where an interlayer insulating film 38 is provided above the dummy trench portion 30, the contact area between the contacts provided in the contact holes 54 and the emitter region 12 can be secured. As a result, the characteristics of the transistor portion 70 can be improved. Furthermore, since microfabrication of the contact holes 54 is unnecessary, the manufacturing cost of the semiconductor device 300 can be reduced.

[0215] Figure 25 is a diagram showing a partial view of the top surface of a semiconductor device 300 according to another embodiment of the present invention. The semiconductor device 300 of this example differs from the semiconductor device 300 of Figure 23a in that a gate runner 48 is not provided to electrically connect the gate trench portion 40 and the gate metal layer 50, and the gate metal layer 50 is electrically connected to the gate trench portion 40 through a contact hole 49 provided on the gate trench portion 40 at the most negative side in the Y-axis direction of the gate trench portion 40.

[0216] In this example, the semiconductor device 300 does not have an interlayer insulating film 38 above the dummy trench portion 30. Therefore, compared to the semiconductor device 300 shown in Figures 23a to 23c, where an interlayer insulating film 38 is provided above the dummy trench portion 30, the contact area between the contacts provided in the contact holes 54 and the emitter region 12 can be secured. As a result, the characteristics of the transistor portion 70 can be improved. Furthermore, since microfabrication of the contact holes 54 is unnecessary, the manufacturing cost of the semiconductor device 300 can be reduced.

[0217] Figure 26 shows an example of a semiconductor chip 120 according to an embodiment of the present invention. As shown in Figure 26, in this example, the semiconductor chip 120 has transistor sections 70 and diode sections 80 arranged alternately and periodically in the XY plane. Figure 26 shows an example in which three transistor sections 70 are provided in the X-axis direction and seven in the Y-axis direction, and three diode sections 80 are provided in the X-axis direction and six in the Y-axis direction.

[0218] Width WI is the width of the transistor section 70 in the Y-axis direction. Width WF is the width of the diode section 80 in the Y-axis direction. Width Wh is the width of the portion from the end of the well region 11 on the positive X-axis side to the end of the well region 11 on the negative X-axis side, as will be described later in Figure 27a, where the base region 14 is formed on the upper surface 21 of the semiconductor substrate 10 and the well region 11 is not formed.

[0219] In the transistor section 70, the width Wh is the width from the end of the base section 14 that is in contact with the well section 11, which is in contact with the end of the well section 11 on the negative X-axis side and exposed to the upper surface 21 of the semiconductor substrate 10, through the contact section 15 and emitter section 12 that are exposed to the upper surface 21 of the semiconductor substrate 10, to the end of the base section 14 that is in contact with the well section 11, which is in contact with the end of the well section 11 on the positive X-axis side and exposed to the upper surface 21 of the semiconductor substrate 10. In the diode section 80, the width Wh is the width from the end of the base section 14 that is in contact with the well section 11, which is in contact with the end of the well section 11, which is in contact with the end of the well section 11 on the negative X-axis side and exposed to the upper surface 21 of the semiconductor substrate 10, through the contact section 15 and base section 14 that are exposed to the upper surface 21 of the semiconductor substrate 10, to the end of the base section 14 that is in contact with the well section 11, which is in contact with the end of the well section 11 on the positive X-axis side and exposed to the upper surface 21 of the semiconductor substrate 10.

[0220] An edge termination portion may be present between the outer edge of the semiconductor chip 120 and the transistor portion 70 and the diode portion 80. Furthermore, a gate metal layer 50 and a gate pad portion (not shown) where the gate metal layer 50 is concentrated, or other predetermined pad portions, may be present between the edge termination portion and the transistor portion 70 and the diode portion 80. In the arrangement direction (Y-axis direction) of the transistor portion 70 and the diode portion 80, the transistor portion 70 may be positioned at the outer edge and facing the edge termination portion.

[0221] Figure 27a is an enlarged view of region A in Figure 26. Figure 27a shows the configuration of the cathode region 82 and the floating region 84 in the diode section 80. In Figure 27a, components other than the cathode region 82 and the floating region 84, such as the gate trench section 40 and the dummy trench section 30 provided in the diode section 80 and the transistor section 70, are omitted.

[0222] As shown in Figure 27a, the semiconductor device 300 in this example has floating regions 84 provided in the diode section 80, for example, 10 in the X-axis direction and 2 in the Y-axis direction, inside the cathode region 82 in the XY plane. Furthermore, the end S of a P+ type well region 11 is provided on the positive X-axis side of the diode section 80 and the transistor section 70. Furthermore, the end S' of a P+ type well region 11 is provided on the negative X-axis side of the diode section 80 and the transistor section 70. The well region 11 is formed outside the region in which the transistor section 70 and the diode section 80 are arranged alternately. In other words, the well region 11 is not formed inside the transistor section 70 and the diode section 80 beyond the end S.

[0223] The positional relationship between the cathode region 82 and other components such as the contact hole 54, the dummy trench portion 30, the contact region 15 formed at the X-axis end of the contact hole 54, and the high-concentration region 17 may be the positional relationship shown in the top views of Figures 1, 19, 21a, 23a, 24, and 25.

[0224] As shown in Figure 27a, the semiconductor device 300 in this example has a transistor section 70 adjacent to the diode section 80 on both the positive Y-axis side, which is one side of the arrangement direction of the diode section 80 and the negative Y-axis side, which is the other side of the arrangement direction. The width WI of the transistor section 70 in the Y-axis direction may be larger than the width WF of the diode section 80 in the Y-axis direction. The width WI may be between 2 and 5 times the width WF. For example, the width WI may be 1500 μm. For example, the width WF may be 500 μm. In other words, the semiconductor device 300 in this example is an example with a smaller width WF compared to the semiconductor device 100 shown in Figures 1 to 18 and the semiconductor device 200 shown in Figures 19 to 20.

[0225] Furthermore, the width Wh from the end S of the well region 11 on the positive side in the X-axis direction to the end S' of the well region 11 on the negative side in the X-axis direction may be greater than the width WI. The width Wh may be 1.5 times or more and 3 times or less the width WI. For example, the width Wh may be 3100 μm.

[0226] The width Wh may be greater than the sum of the widths WI and WF. When the transistor section 70 is turned on, or when the diode section 80 is conducted, the snapback phenomenon in which the voltage between the collector electrode 24 and the emitter electrode 52 decreases suddenly in response to an increase in the current flowing between the collector electrode 24 and the emitter electrode 52 can be suppressed.

[0227] Figure 27b is an enlarged view of region B1 in Figure 27a. Figure 27b shows an enlarged view of the well region 11 on the positive X-axis side to the negative X-axis side of the diode section 80 in Figure 27a, from edge S to edge S' of the well region 11 on the negative X-axis side. As shown in Figure 27b, in the semiconductor device 300 of this example, floating regions 84 are provided in the diode section 80, for example, 10 in the X-axis direction and 2 in the Y-axis direction, inside the cathode region 82 in the XY plane.

[0228] The width Wwc in the X-axis direction in a top view, from the end S of the well region 11 on the positive X-axis side to the end of the cathode region 82 on the positive X-axis side, may be smaller than the width WF of the diode portion 80. The width Wwc may be 0.25 times or more and 0.75 times or less of the width WF. For example, the width Wwc may be 250 μm.

[0229] The positive end T of the contact hole 54 in the X-axis direction is provided with a width Wwca in the negative X-axis direction from the positive end S of the well region 11 in the X-axis direction, as shown in Figure 27b. The negative end T' of the contact hole 54 in the X-axis direction is provided with a width Wwca in the positive X-axis direction from the negative end S' of the well region 11 in the X-axis direction. The contact hole 54 is provided in the X-axis direction from end T to end T'.

[0230] Although only one contact hole 54 is shown in Figure 27b, in reality, as is clear from the top views in Figures 1, 19, 21a, 23a, 24, and 25, multiple contact holes 54 are provided in the Y-axis direction, each having the same Y-axis position at both end T and end T'.

[0231] The width Wwca from the positive X-axis end S of the well region 11 to the positive X-axis end T of the multiple contact holes 54 formed in the diode portion 80 may be smaller than the width Wwcb in the X-axis direction as seen from above, from the end T to the positive X-axis end of the cathode region 82. The width Wwca may be 0.1 to 0.9 times the width Wwcb. For example, the width Wwca may be 100 μm and the width Wwcb may be 150 μm. The sum of the width Wwca and the width Wwcb is the width Wwc. Also, the width from the negative X-axis end S' of the well region 11 to the negative X-axis end T' of the multiple contact holes 54 formed in the diode portion 80 may be equal to the width Wwca. The width in the X-axis direction as seen from above, from the end T' to the negative X-axis end of the cathode region 82, may also be equal to the width Wwcb.

[0232] Furthermore, the width in the X-axis direction in a top view, from the end S' of the well region 11 on the negative X-axis side to the negative X-axis side end of the cathode region 82, may also be equal to the width Wwc. The contact hole 54 in Figure 27b is one of several contact holes. Alternatively, the contact hole 54 may be one of the contact holes shown in Figures 21a to 25.

[0233] A floating region 84 is provided inside the cathode region 82 in the XY plane, as shown in Figure 27b. The floating region 84 is a region of second conductivity type that is electrically floating. In this example, the floating region 84 is of type P+. Being electrically floating means that it is not connected to either the collector electrode 24 or the emitter electrode 52.

[0234] In the semiconductor device 300 of this example, the floating regions 84 are arranged in a grid pattern in the XY plane. Here, a grid pattern means that the floating regions 84 are arranged periodically in both the X-axis direction and the Y-axis direction. Figure 27b shows an example in which two floating regions 84 are provided in the Y-axis direction, and 10 floating regions are provided in the X-axis direction, extending from the negative X-axis side to the positive X-axis side of the cathode region 82, flanking the opening region 85.

[0235] The width Wff1 is the width of the aperture region 85 in the X-axis direction. The width Wff1 is smaller than the width Wf1 of the floating region 84 in the X-axis direction. The width Wff1 may be smaller than the width WF of the diode portion 80. The width Wff1 may be between 0.01 and 0.05 times the width WF. The width Wff1 may be 10 μm as an example.

[0236] The width Wf1 in the X-axis direction of the floating region 84 may be smaller than the width WF of the diode portion 80. The width Wf1 may be between 0.25 and 0.75 times the width WF. For example, the width Wf1 may be 240 μm.

[0237] The width Wf2 in the Y-axis direction of the floating region 84 may be smaller than the width WF of the diode portion 80. The width Wf2 may be between 0.25 and 0.75 times the width WF. The width Wf2 may be equal to or different from the width Wf1. The width Wf2 may be 240 μm as an example.

[0238] The width Wcf1 from the positive X-axis end of the cathode region 82 to the positive X-axis end of the floating region 84 located on the most positive X-axis side may be smaller than the width Wff1. The width Wcf1 may be between 0.1 and 0.9 times the width Wff1. The width Wcf1 must not be zero. For example, the width Wcf1 may be 5 μm. The width from the negative X-axis end of the cathode region 82 to the negative X-axis end of the floating region 84 located on the most negative X-axis side may also be equal to the width Wcf1.

[0239] In the semiconductor device 300 of this example, two floating regions 84 are provided in the Y-axis direction, flanking the aperture region 85. Here, width Wff2 is the width of the aperture region 85 in the Y-axis direction. Width Wff2 may be smaller than width Wf2. Width Wff2 may be between 0.01 and 0.05 times the width WF of the diode portion 80. Width Wff2 may be equal to or different from width Wff1. For example, width Wff2 may be 10 μm.

[0240] The ratio of the area of ​​the floating region 84 to the area of ​​the cathode region 82 in the XY plane may be between 50% and 99%. In other words, the area of ​​the floating region 84 in the XY plane may be smaller than the area of ​​the cathode region 82 in the XY plane. For example, if Wh is 3100 μm, Wwc is 250 μm, Wf1 and Wf2 are 240 μm, Wcf1 and Wcf2 are 5 μm, and Wff1 and Wff2 are 10 μm, then the total area of ​​the floating region 84 to the area of ​​the cathode region 82 in the XY plane will be 88.6%.

[0241] The width Wcf2 from the positive Y-axis end of the cathode region 82 to the positive Y-axis end of the floating region 84 on the positive Y-axis side may be smaller than the width WF of the diode portion 80. The width Wcf2 may be between 0.01 and 0.05 times the width WF. The width Wcf2 must not be zero. Also, the width Wcf2 may be equal to or different from the width Wcf1. Furthermore, the width from the negative Y-axis end of the cathode region 82 to the negative Y-axis end of the floating region 84 on the negative Y-axis side is also equal to the width Wcf2.

[0242] In this example, the width Wcnt of the contact holes 54 in the alignment direction (Y-axis direction) may be smaller than Wff1. In this example, the width Wcnt may be smaller than Wff2. In this example, the width Wcnt may be smaller than Wcf1. In this example, the width Wcnt may be smaller than Wcf2. As an example, the width Wcnt is 0.5 μm.

[0243] Figure 27c is an enlarged view of region B2 in Figure 27b. As shown in Figure 27c, in the semiconductor device 300 of this example, width Wcf1 is the width from the positive X-axis end of the cathode region 82 to the positive X-axis end of the floating region 84 located on the most positive side in the X-axis direction. Width Wcf2 is the width from the positive Y-axis end of the cathode region 82 to the positive Y-axis end of the floating region 84 on the positive Y-axis side. Width Wcf2 may be 5 μm as an example. Width Wff1 is the width in the X-axis direction of the aperture region 85. Width Wf1 is the width in the X-axis direction of the floating region 84.

[0244] Figure 27d shows an example of the h-h' cross-section in Figure 27b. In this example, the semiconductor device 300 has a floating region 84 in the diode section 80, which is located within a buffer region 20 above the cathode region 82. Two floating regions 84 are provided in the Y-axis direction in the h-h' cross-section.

[0245] In this example, as shown in Figure 27d, there are two boundary positions between the collector region 22 and the cathode region 82 in a plane parallel to the lower surface 23 of the semiconductor substrate 10. Boundary position P1 is the boundary position on the positive side in the Y-axis direction of these two boundary positions. Boundary position P1' is the boundary position on the negative side in the Y-axis direction of these two boundary positions. Boundary positions P1 and P1' are boundary positions in a cross section parallel to the h-h' cross section. For example, the h-h' cross section is perpendicular to the lower surface 23 and parallel to the arrangement direction of the dummy trench portion 30.

[0246] In this example, as shown in Figure 27d, there are two end positions of the floating region 84 in the plane parallel to the bottom surface 23. Boundary position P2 is the end position closest to boundary position P1 of the floating region 84 located on the positive side of the Y-axis direction, out of two floating regions 84 arranged in the Y-axis direction in the plane parallel to the bottom surface 23. Boundary position P2' is the end position closest to boundary position P1' of the floating region 84 located on the negative side of the Y-axis direction, out of two floating regions 84 arranged in the Y-axis direction in the plane parallel to the bottom surface 23.

[0247] Furthermore, in this example, in the Z-axis direction, there is an open region 85 at approximately the same depth as the floating region 84, where the floating region 84 is not provided. The open region 85 may refer to the region sandwiched between the floating regions 84. For example, the open region 85 is an N+ type region. The doping concentration of the open region 85 may be approximately the same as the doping concentration of the drift region 18 or buffer region 20. The open region 85 may be the drift region 18 or buffer region 20 that remained without the formation of the floating region 84.

[0248] The width Wcf2 is the distance from end position P1 to end position P2. Also, the width Wcf2 is the distance from end position P1' to end position P2'. The width Wcf2 may be the same as the distance L1 in the example in Figure 9.

[0249] The width Wff2 is the distance between adjacent floating regions 84 sandwiching the opening region 85 in the Y-axis direction. The width Wff2 may be the same as the distance L3 in the example of FIG. 9.

[0250] The width Wd is the width of the floating region 84 in the Z-axis direction. The width Wd may be the same as the distance L4 in the example of FIG. 9. The width Wd of the floating region 84 in the Z-axis direction may be smaller than the width Wcf2. The width Wd may be 0.05 times or more and 0.5 times or less of the width Wcf2. As an example, the width Wd may be 0.5 μm.

[0251] FIG. 27e is a diagram showing an example of the j-j' cross section in FIG. 27b. The j-j' cross section is the XZ plane passing through the line J''-J''' in FIG. 27d. In the semiconductor device 300 of this example, in the buffer region 20 provided above the cathode region 82 in the diode portion 80, a floating region 84 is provided.

[0252] In this example, as shown in FIG. 27e, in a plane parallel to the lower surface 23 of the semiconductor substrate 10, there are two boundary positions between the collector region 22 and the cathode region 82. The boundary position P5 is the boundary position on the negative side in the X-axis direction among the two boundary positions. Also, the boundary position P5' is the boundary position on the positive side in the X-axis direction among the two boundary positions. The boundary positions P5 and P5' are the boundary positions in a cross section parallel to the j-j' cross section. As an example, the j-j' cross section is a plane perpendicular to the lower surface 23 and parallel to the extending direction of the dummy trench portion 30.

[0253] In this example, as shown in FIG. 27e, in a plane parallel to the lower surface 23, there are two end positions of the floating region 84. The boundary position P6 is the end position of the floating region 84 arranged on the most negative side in the X-axis direction among the floating regions 84 arranged in a plurality in the X-axis direction in a plane parallel to the lower surface 23, which is the closest to the boundary position P5. Also, the boundary position P6' is the end position of the floating region 84 arranged on the most positive side in the X-axis direction among the floating regions 84 arranged in a plurality in the Y-axis direction in a plane parallel to the lower surface 23, which is the closest to the boundary position P5'.

[0254] Also, in this example, in the Z-axis direction, at a depth position substantially the same as that of the floating region 84, there is an opening region 85 where no floating region 84 is provided. The opening region 85 may refer to a region sandwiched by the floating regions 84. As an example, the opening region 85 is an N+-type region. The doping concentration of the opening region 85 may be substantially the same as the doping concentration of the drift region 18 or the buffer region 20. The opening region 85 may be the drift region 18 or the buffer region 20 remaining without the formation of the floating region 84.

[0255] The width Wf1 is the width of the floating region 84 in the X-axis direction. The width Wcf1 is the distance in the X-axis direction from the end position P5 to the end position P6. Also, the width Wcf1 is the distance in the X-axis direction from the end position P5' to the end position P6'. Also, the width Wff1 is the interval between the floating regions 84 adjacent to each other with the opening region 85 interposed therebetween in the X-axis direction. The width Wcf1 may be smaller than the width Wff1. Since the semiconductor device 300 in this example provides the floating regions 84 in a lattice pattern in the XY plane in the diode portion 80, the surge voltage (overshoot voltage) during reverse recovery of the diode portion 80 can be suppressed.

[0256] Figure 28a is another enlarged view of region A in Figure 26. In this example, the semiconductor device 300 is similar to the semiconductor device 300 shown in Figure 27a, with transistor units 70 provided adjacent to the diode unit 80 on the positive and negative Y-axis sides of the diode unit 80.

[0257] The semiconductor device 300 in this example differs from the semiconductor device 300 shown in Figure 27a in the arrangement of the floating region 84 in the diode section 80. As shown in Figure 28a, in the semiconductor device 300 in this example, the floating region 84 is provided continuously inside the cathode region 82 in the XY plane, from the positive Y-axis boundary of the cathode region 82, indicated by the dashed line, to the negative Y-axis boundary, also indicated by the dashed line. Here, the continuous provision of the floating region 84 in the Y-axis direction means that at any point in the Y-axis direction from the positive Y-axis boundary to the negative Y-axis boundary of the cathode region 82, there is no region in the X-axis direction where the floating region 84 is not provided.

[0258] Figure 28b is an enlarged view of region C1 in Figure 28a. Figure 28b shows an enlarged view of the diode portion 80 from the edge S of the well region 11 on the positive X-axis side to the edge S' of the well region 11 on the negative X-axis side in Figure 28a.

[0259] In this example, the floating regions 84 are arranged in a stripe pattern in the XY plane. Here, "stripe pattern" means that multiple rectangular floating regions 84 are provided at predetermined intervals along the shorter side of the rectangle. Figure 28b shows an example in which multiple rectangular floating regions 84, with the Y-axis direction as the longer side and the X-axis direction as the shorter side, are provided along the X-axis direction with a width Wff1', extending from the most negative side to the most positive side in the X-axis direction of the cathode region 82 in the XY plane. The width Wff1' may be smaller than the width WF of the diode portion 80. The width Wff1' may be between 0.01 and 0.05 times the width WF. The width Wff1' may be 10 μm as an example.

[0260] The width Wf1' in the X-axis direction of the floating region 84 may be smaller than the width WF of the diode portion 80. The width Wf1' may be between 0.04 and 0.13 times the width WF. For example, the width Wf1' may be 40 μm.

[0261] The width Wf2' in the Y-axis direction of the floating region 84 may be smaller than the width WF of the diode portion 80. The width Wf2' may be between 0.5 and 0.99 times the width WF. For example, the width Wf2' may be 490 μm.

[0262] The width Wcf1 is the distance from the positive X-axis end of the cathode region 82 to the positive X-axis end of the floating region 84 located on the most positive X-axis side. The width Wcf1 may be smaller than the width Wff1'. The width Wcf1 may be between 0.1 and 0.9 times the width Wff1'. The width Wcf1 must not be zero. As an example, the width Wcf1 may be 5 μm, similar to the example in Figure 27b. The distance from the negative X-axis end of the cathode region 82 to the negative X-axis end of the floating region 84 located on the most negative X-axis side is also equal to the width Wcf1.

[0263] The ratio of the area of ​​the floating region 84 in the XY plane to the area of ​​the cathode region 82 in the XY plane may be between 50% and 99%, as in the example in Figure 27b. That is, the area of ​​the floating region 84 in the XY plane may be smaller than the area of ​​the cathode region 82 in the XY plane. For example, if Wh is 3100 μm, Wwc is 250 μm, Wf1' is 40 μm, Wf2' is 490 μm, Wcf1 and Wcf2 are 5 μm, and Wff1' is 10 μm, then, when viewed from above, 51 floating regions 84 are provided inside the cathode region 82 in the X-axis direction and 1 in the Y-axis direction. In this case, the total area of ​​the floating regions 84 in the XY plane to the area of ​​the cathode region 82 in the XY plane is 76.8%.

[0264] The width Wcf2 from the positive Y-axis end of the cathode region 82 to the positive Y-axis end of the floating region 84 may be smaller than the width WF of the diode section 80, as in the example in Figure 27b. The width Wcf2 may be between 0.01 and 0.05 times the width WF. Also, the width Wcf2 may be equal to or different from the width Wcf1. The width Wcf2 just needs to be non-zero. Note that the width from the negative Y-axis end of the cathode region 82 to the negative Y-axis end of the floating region 84 is also equal to the width Wcf2.

[0265] Figure 28c is an enlarged view of region C2 in Figure 28b. As shown in Figure 28c, in the semiconductor device 300 of this example, width Wcf1 is the width from the positive X-axis end of the cathode region 82 to the positive X-axis end of the floating region 84, which is located on the most positive side in the X-axis direction. Also, in the semiconductor device 300 of this example, width Wcf2 is the width from the positive Y-axis end of the cathode region 82 to the positive Y-axis end of the floating region 84. Width Wcf2 may be 5 μm as an example. Width Wff1' is the width in the X-axis direction of the aperture region 85. Width Wf1' is the width in the X-axis direction of the floating region 84.

[0266] Figure 28d shows an example of the k-k' cross-section in Figure 28b. In this example, the semiconductor device 300 has a floating region 84 in the diode section 80, which is located within a buffer region 20 above the cathode region 82. In the k-k' cross-section, the floating region 84 is continuously provided from the positive side to the negative side in the Y-axis direction.

[0267] In this example, as shown in Figure 28d, boundary positions P1 and P2, and boundary positions P1' and P2' exist, similar to the example in Figure 27d. In this example, since the floating region 84 is provided continuously from end position P2 to end position P2', there is no opening region 85. Also, the width Wcf2 is the distance from end position P1 to end position P2, similar to the example in Figure 27d. Also, the width Wcf2 is the distance from end position P1' to end position P2'. The width Wd of the floating region 84 in the Z-axis direction may be smaller than the width Wcf2, similar to Figure 27c. The width Wd may be between 0.05 and 0.5 times the width Wcf2. For example, the width Wd may be 0.5 μm.

[0268] Figure 28e shows an example of the m-m' cross section in Figure 28b. The m-m' cross section is the XZ plane passing through the m''-m''' line in Figure 28d. In this example, the semiconductor device 300 has a floating region 84 in the diode section 80, within a buffer region 20 located above the cathode region 82.

[0269] In this example, as shown in Figure 28e, boundary positions P5 and P6, as well as boundary positions P5' and P6', exist, similar to the example in Figure 27e. For example, the m-m' cross section is perpendicular to the lower surface 23 of the semiconductor substrate 10 and parallel to the extension direction of the dummy trench portion 30. In this example, as with the example in Figure 27e, in the Z-axis direction, there is an opening region 85 at the same depth as the floating region 84 where the floating region 84 is not provided.

[0270] Width Wf1' is the width of the floating region 84 in the X-axis direction. Width Wcf1 is the distance from end position P5 to end position P6, as in the example in Figure 27e. Also, width Wcf1 is the distance from end position P5' to end position P6'. Furthermore, width Wff1' is the distance between adjacent floating regions 84 with the opening region 85 in between, in the X-axis direction. Width Wcf1 may be smaller than width Wff1'.

[0271] In the semiconductor device 300 of this example, in the diode portion 80, a plurality of floating regions 84 are provided across the end position P6 to the end position P6', sandwiching the opening region 85. Since the semiconductor device 300 of this example provides the floating regions 84 in a stripe shape in the XY plane, it is possible to suppress the surge during reverse recovery of the diode portion 80.

[0272] As described above, the present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that embodiments with such changes or improvements can also be included in the technical scope of the present invention. As an example, in the boundary portion 90, a high-concentration region of the first conductivity type may be formed. In this case, the integrated concentration of the high-concentration region in the boundary portion 90 may be smaller than the integrated concentration of the storage region 16 in the transistor portion 70, and may be smaller than the integrated concentration of the high-concentration region 17 in the diode portion 80.

[0273] It should be noted that the execution order of each process such as operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, the specification, and the drawings is not explicitly stated as "earlier" or "preceding" etc., and can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flows in the claims, the specification, and the drawings, even if "first," "next," etc. are used for convenience of explanation, it does not mean that it is essential to be implemented in this order.

Explanation of Reference Numerals

[0274] 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 15...Contact region, 16...Storage region, 16-1...Storage region, 16-2...Storage region, 16-3...Storage region, 17...High concentration region, 17-1...High concentration region, 17-2...High concentration region, 18...Drift region, 20...Buffer region, 21...Top surface, 22...Collector region, 23...Bottom surface, 24...Collector electrode, 25...Connection portion, 30...Dummy trench portion, 32...Dummy insulating film, 34...Dummy conductive portion, 38...Interlayer insulating film, 40...Gate trench portion, 42...Gate insulating film, 44...Gate conductive portion, 48...Gate trench Inner, 49... Contact hole, 50... Gate metal layer, 52... Emitter electrode, 54... Contact hole, 56... Contact hole, 70... Transistor section, 80... Diode section, 82... Cathode region, 84... Floating region, 85... Aperture region, 86... Dummy region, 87... High-density hole region, 88... Lifetime killer, 89... Crystal defect layer, 90... Boundary region, 91, 92, 93, 94... Waveform, 95... Mesa region, 95-1... Mesa region, 95-2... Mesa region, 95-3... Mesa region, 100... Semiconductor device, 150... Semiconductor device, 200... Semiconductor device, 300... Semiconductor device, 350... Semiconductor device

Claims

1. A trench-type semiconductor device comprising a transistor section and a diode section, wherein the semiconductor substrate is provided with an n-type drift region, a p-type base region, and a plurality of trench sections, The aforementioned transistor section is In the first mesa portion, an n-type accumulation region is provided below the base region, and the doping concentration is higher than that of the drift region. In the first mesa portion, a p-type first contact region is selectively provided in contact with the upper surface of the semiconductor substrate and has a higher doping concentration than the base region. It has, The diode portion includes a hole injection suppression portion provided on the upper surface side of the semiconductor substrate and an electron injection suppression portion provided on the lower surface side of the semiconductor substrate. At least a portion of the mesa portion of the diode is provided with a p-type second contact region, which is selectively provided in contact with the upper surface of the semiconductor substrate and has a higher doping concentration than the base region. The hole injection suppression portion is the second mesa portion of the diode portion in which the area of ​​the second contact region on the upper surface is smaller than the area of ​​the first contact region on the upper surface of the first mesa portion. Semiconductor equipment.

2. A trench-type semiconductor device comprising a transistor section and a diode section, wherein the semiconductor substrate is provided with an n-type drift region, a p-type base region, and a plurality of trench sections, The transistor portion is provided below the base region in the first mesa portion and has an n-type storage region with a higher doping concentration than the drift region. The diode portion includes a hole injection suppression portion provided on the upper surface side of the semiconductor substrate and an electron injection suppression portion provided on the lower surface side of the semiconductor substrate. The accumulation region has multiple doping concentration peaks. Semiconductor equipment.

3. A trench-type semiconductor device comprising a transistor section and a diode section, wherein a semiconductor substrate is provided with an n-type drift region, a p-type base region, and a plurality of trench sections, The transistor portion is provided below the base region in the first mesa portion and has an n-type storage region with a higher doping concentration than the drift region. The diode portion includes a hole injection suppression portion provided on the upper surface side of the semiconductor substrate and an electron injection suppression portion provided on the lower surface side of the semiconductor substrate. The first mesa portion has an outer mesa portion which is located furthest outward in the direction of arrangement of the trench portions among the first mesa portion in which the accumulation region is formed, The trench portion has a first trench portion that is in contact with the outer mesa portion on the outside, The depth of the base region of the outer mesa is shallower than the depth of the base region of the mesa on the opposite side of the outer mesa, with reference to the first trench in the arrangement direction. Semiconductor equipment.

4. At the same depth position of the diode portion as the deepest position of the storage region, no n-type high-concentration region with a higher doping concentration than the drift region is formed on the semiconductor substrate. The semiconductor device according to any one of claims 1 to 3.

5. The hole injection suppression portion is provided below the base region in the second mesa portion of the diode portion and is an n-type high-concentration region with a higher doping concentration than the drift region. The semiconductor device according to claim 2 or 3.

6. The diode portion has an n-type cathode region provided in contact with the lower surface of the semiconductor substrate. The electron injection suppression portion is a p-type floating region that covers a part of the cathode region above the cathode region. The semiconductor device according to any one of claims 1 to 5.

7. The diode portion has an n-type cathode region provided in contact with the lower surface of the semiconductor substrate. The electron injection suppression portion is a p-shaped dummy region provided in contact with the lower surface of the semiconductor substrate. The semiconductor device according to any one of claims 1 to 5.

8. The accumulation region covers the entire lower surface of the base region in the first mesa portion. The semiconductor device according to any one of claims 1 to 7.

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