Semiconductor equipment

Abstract

A semiconductor apparatus includes a first and a second semiconductor devices, and a circuit board. The first semiconductor device has a first electrode, a second electrode and a third electrode. On-off control is used between the first electrode and the second electrode. The second semiconductor device has a fourth electrode, a fifth electrode and a sixth electrode. On-off control is used between the fourth electrode and the fifth electrode. The circuit board includes a substrate, a main surface wiring layer, a back surface wiring layer, and a metal member inserted into the substrate to lead to an electrical connection between the main surface wiring layer and the back surface wiring layer. The second electrode and the fourth electrode are connected, so that the first semiconductor device and the second semiconductor device are connected in series. The metal member intervenes in a conduction path between the second electrode and the fourth electrode.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices.

Background Art

[0002] Conventionally, semiconductor devices including power semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are known. For example, Patent Document 1 discloses a semiconductor device including two semiconductor elements connected in series. Such semiconductor devices are mounted on a circuit board of, for example, an electronic device, and are used in a power supply circuit (for example, a DC / DC converter or an inverter) or a motor drive circuit.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In recent years, with the improvement in performance of electronic devices, an increase in current capacity of semiconductor devices used in such electronic devices has been demanded.

[0005] This disclosure has been conceived in view of the above circumstances, and one of its objectives is to provide a semiconductor device capable of increasing current capacity.

Means for Solving the Problems

[0006] The semiconductor device of this disclosure includes: a first semiconductor element having a first electrode, a second electrode, and a third electrode, the on / off control between the first electrode and the second electrode by a first drive signal input to the third electrode; a second semiconductor element having a fourth electrode, a fifth electrode, and a sixth electrode, the on / off control between the fourth electrode and the fifth electrode by a second drive signal input to the sixth electrode; and a wiring substrate having a substrate main surface and a substrate back surface spaced apart in the thickness direction, a main surface wiring layer formed on the main surface of the substrate, a back surface wiring layer formed on the back surface of the substrate, and a metal member inserted into the substrate to provide conductivity between the main surface wiring layer and the back surface wiring layer. The first semiconductor element and the second semiconductor element are connected in series by connecting the second electrode and the fourth electrode, and the metal member is interposed in the conductive path between the second electrode and the fourth electrode. [Effects of the Invention]

[0007] The semiconductor device described herein enables high current operation. [Brief explanation of the drawing]

[0008] [Figure 1] This is a perspective view showing a semiconductor device according to the first embodiment. [Figure 2] This is a perspective view of Figure 1, with the resin component omitted. [Figure 3] This is a plan view showing a semiconductor device according to the first embodiment, in which resin members are indicated by dashed lines. [Figure 4] Figure 3 is a plan view in which several connecting members have been omitted. [Figure 5] Figure 4 is a plan view in which a portion of the wiring board (main surface wiring layer) has been omitted. [Figure 6] Figure 5 is a plan view in which a portion of the wiring board (base material) has been omitted. [Figure 7] Figure 6 is a plan view in which a portion of the wiring board (the back wiring layer) has been omitted. [Figure 8]A bottom view showing the semiconductor device according to the first embodiment, in which the resin member 8 is shown by an imaginary line (two-dot chain line). [Figure 9] A side view (left side view) showing the semiconductor device according to the first embodiment, in which the resin member is omitted. [Figure 10] A side view (right side view) showing the semiconductor device according to the first embodiment, in which the resin member is omitted. [Figure 11] A cross-sectional view taken along the line XI-XI in FIG. 3, in which the resin member is omitted. [Figure 12] A partially enlarged view obtained by enlarging a part of FIG. 11. [Figure 13] A partially enlarged view obtained by enlarging a part of FIG. 11. [Figure 14] A plan view showing the semiconductor device according to the second embodiment, corresponding to FIG. 4. [Figure 15] A plan view showing the semiconductor device according to the third embodiment, corresponding to FIG. 4. [Figure 16] A plan view showing the semiconductor device according to the fourth embodiment, corresponding to FIG. 4.

Embodiments for Carrying Out the Invention

[0009] Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the drawings. The same or similar elements are denoted by the same reference numerals, and redundant descriptions are omitted.

[0010] FIGS. 1 to 13 show a semiconductor device A1 according to the first embodiment. The semiconductor device A1 includes a plurality of first semiconductor elements 1, a plurality of second semiconductor elements 2, a support member 3, a wiring board 4, a pair of signal terminals 61A and 61B, a pair of detection terminals 62A and 62B, a plurality of dummy terminals 63, a plurality of connection members 7, and a resin member 8. The plurality of connection members 7 include connection members 71, 72, 73A, 73B, 74A, 74B, 75A, 75B, 76A, and 76B.

[0011] FIG. 1 is a perspective view showing a semiconductor device A1. FIG. 2 is a view of the perspective view of FIG. 1 with the resin member 8 omitted. FIG. 3 is a plan view showing the semiconductor device A1, with the resin member 8 indicated by an imaginary line (a two-dot chain line). FIG. 4 is a view of the plan view of FIG. 3 with a plurality of connection members 7 omitted. FIG. 5 is a view of the plan view of FIG. 4 with a part of the wiring substrate 4 (the main surface wiring layer 42) omitted. FIG. 6 is a view of the plan view of FIG. 5 with a part of the wiring substrate 4 (the base material 41) omitted. FIG. 7 is a view of the plan view of FIG. 6 with a part of the wiring substrate 4 (the back surface wiring layer 43) omitted. FIG. 8 is a bottom view showing the semiconductor device A1, with the resin member 8 indicated by an imaginary line (a two-dot chain line). FIG. 9 is a side view (left side view) showing the semiconductor device A1, with the resin member 8 omitted. FIG. 10 is a side view (right side view) showing the semiconductor device A1, with the resin member 8 omitted. FIG. 11 is a cross-sectional view taken along the line XI-XI of FIG. 3, with the resin member 8 omitted. FIG. 12 is a partially enlarged view of a part of FIG. 11. FIG. 13 is a partially enlarged view of a part of FIG. 11.

[0012] For convenience of explanation, three mutually perpendicular directions, namely, the x direction, the y direction, and the z direction are referred to. The z direction is the thickness direction of the semiconductor device A1. The x direction is the left-right direction in the plan view of the semiconductor device A1 (see FIG. 3). The y direction is the up-down direction in the plan view of the semiconductor device A1 (see FIG. 3). One of the x directions is the x1 direction, and the other of the x directions is the x2 direction. Similarly, one of the y directions is the y1 direction, the other of the y directions is the y2 direction, one of the z directions is the z1 direction, and the other of the z directions is the z2 direction. In the following description, "plan view" means when viewed in the z direction. The x direction is an example of the "second direction", and the y direction is an example of the "first direction".

[0013] Each of the multiple first semiconductor elements 1 and the multiple second semiconductor elements 2 is, for example, a MOSFET. Each of the multiple first semiconductor elements 1 and the multiple second semiconductor elements 2 is not limited to MOSFETs, but may also be a switching element such as a field-effect transistor including a MISFET (Metal-Insulator-Semiconductor FET) or a bipolar transistor including an IGBT. Each of the multiple first semiconductor elements 1 and the multiple second semiconductor elements 2 is constructed using a semiconductor material mainly composed of SiC (silicon carbide). This semiconductor material is not limited to SiC, but may also be Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), or Ga2O3 (gallium oxide), etc.

[0014] Each of the multiple first semiconductor elements 1 has a main surface 1a and a back surface 1b, as shown in Figure 12. The main surface 1a and the back surface 1b are spaced apart from each other in the z direction. The main surface 1a faces the z2 direction, and the back surface 1b faces the z1 direction.

[0015] Each of the multiple first semiconductor elements 1 has a first electrode 11, a second electrode 12, and a third electrode 13. As shown in Figure 12, in each first semiconductor element 1, the first electrode 11 is formed on the back surface 1b of the element, and the second electrode 12 and the third electrode 13 are formed on the main surface 1a of the element. In the example where each first semiconductor element 1 is a MOSFET, the first electrode 11 is the drain electrode, the second electrode 12 is the source electrode, and the third electrode 13 is the gate electrode. When a first drive signal (for example, a gate voltage) is input to the third electrode 13 (gate electrode) of each first semiconductor element 1, it switches between a conduction state and an interruption state in response to this first drive signal. This operation of switching between a conduction state and an interruption state is called switching operation. In the conduction state, current flows from the first electrode 11 (drain electrode) to the second electrode 12 (source electrode), and in the interruption state, this current does not flow. In other words, each first semiconductor element 1 is controlled on / off between the first electrode 11 (drain electrode) and the second electrode 12 (source electrode) by a first drive signal (for example, a gate voltage) input to the third electrode 13 (gate electrode).

[0016] Multiple first semiconductor elements 1 are arranged along the y-direction, as shown in Figure 3 and other figures. Each first semiconductor element 1 is bonded to a conductive plate 31A via a conductive bonding material 19, as shown in Figure 12. The conductive bonding material 19 is, for example, solder, metal paste, or sintered metal.

[0017] Each of the multiple second semiconductor elements 2 has a main surface 2a and a back surface 2b, as shown in Figure 13. The main surface 2a and the back surface 2b are spaced apart from each other in the z direction. The main surface 2a faces the z2 direction, and the back surface 2b faces the z1 direction.

[0018] Each of the multiple second semiconductor elements 2 has a fourth electrode 21, a fifth electrode 22, and a sixth electrode 23. As shown in Figure 13, in each second semiconductor element 2, the fourth electrode 21 is formed on the back surface 2b of the element, and the fifth electrode 22 and sixth electrode 23 are formed on the main surface 2a of the element. In the example where each second semiconductor element 2 is a MOSFET, the fourth electrode 21 is the drain electrode, the fifth electrode 22 is the source electrode, and the sixth electrode 23 is the gate electrode. When a second drive signal (for example, a gate voltage) is input to the sixth electrode 23 (gate electrode), each second semiconductor element 2 performs a switching operation in response to this second drive signal (switching between a conduction state and an interruption state). In the conduction state, current flows from the fourth electrode 21 (drain electrode) to the fifth electrode 22 (source electrode), and in the interruption state, this current does not flow. In other words, each second semiconductor element 2 has its connection between the fourth electrode 21 (drain electrode) and the fifth electrode 22 (source electrode) controlled on or off in accordance with a second drive signal (for example, a gate voltage) input to the sixth electrode 23 (gate electrode).

[0019] As shown in Figure 3 and other figures, the multiple second semiconductor elements 2 are arranged along the y-direction. When viewed in the x-direction, the multiple second semiconductor elements 2 overlap the multiple first semiconductor elements 1. Each second semiconductor element 2 is bonded to the conductive plate 31B via a conductive bonding material 29, as shown in Figure 13. The conductive bonding material 29 is, for example, solder, metal paste, or sintered metal.

[0020] The semiconductor device A1 is configured, for example, as a half-bridge type switching circuit. Multiple first semiconductor elements 1 constitute the upper arm circuit of the semiconductor device A1, and multiple second semiconductor elements 2 constitute the lower arm circuit of the semiconductor device A1. In the semiconductor device A1, the multiple first semiconductor elements 1 are electrically connected in parallel with each other, and the multiple second semiconductor elements 2 are electrically connected in parallel with each other. Then, each first semiconductor element 1 and each second semiconductor element 2 are connected in series to form a bridge. In the example shown in Figure 3, the semiconductor device A1 comprises four first semiconductor elements 1 and four second semiconductor elements 2. The number of each first semiconductor element 1 and second semiconductor element 2 is not limited to this configuration and can be appropriately changed according to the performance required of the semiconductor device A1.

[0021] As shown in Figures 7 and 11, the support member 3 supports a plurality of first semiconductor elements 1 and a plurality of second semiconductor elements 2. As shown in Figures 7 and 9 to 13, the support member 3 has a pair of conductive plates 31A, 31B and a pair of insulating plates 32A, 32B.

[0022] As shown in Figures 7, 11, and 12, the conductive plate 31A supports a plurality of first semiconductor elements 1. The conductive plate 31A is electrically connected to the first electrode 11 (drain electrode) of each first semiconductor element 1. The conductive plate 31A is, for example, rectangular parallelepiped. The dimension of the conductive plate 31A along the z-direction is larger than the dimension of the main surface wiring layer 42 and the back surface wiring layer 43 along the z-direction. As shown in Figures 11 and 12, the conductive plate 31A has a bonding surface 310A to which each first semiconductor element 1 is bonded. The bonding surface 310A faces the z2 direction. In addition to each first semiconductor element 1, a part of the wiring substrate 4 (the first back surface wiring portion 431 of the back surface wiring layer 43, described later) is bonded to the bonding surface 310A. The conductive plate 31A is bonded to the insulating plate 32A via a bonding material 319. The bonding material 319 may be conductive or insulating.

[0023] As shown in Figures 7, 11, and 13, the conductive plate 31B supports a plurality of second semiconductor elements 2. The conductive plate 31B is electrically connected to the fourth electrode 21 (drain electrode) of each second semiconductor element 2. The conductive plate 31B is, for example, rectangular parallelepiped. The dimension of the conductive plate 31B along the z-direction is larger than the dimension of the main surface wiring layer 42 and the back surface wiring layer 43 along the z-direction. As shown in Figures 11 and 13, the conductive plate 31B has a bonding surface 310B to which each second semiconductor element 2 is bonded. The bonding surface 310B faces the z2 direction. A part of the wiring substrate 4 (the second back surface wiring portion 432 of the back surface wiring layer 43, described later) is bonded to the bonding surface 310B. The conductive plate 31B is bonded to the insulating plate 32B via a bonding material 319.

[0024] As shown in Figures 12 and 13, each pair of conductive plates 31A and 31B has multiple first metal layers 311 and multiple second metal layers 312 laminated in the z direction. Each of the multiple first metal layers 311 is made of, for example, copper. Each of the multiple second metal layers 312 is made of, for example, molybdenum. The surface layer in the z direction of conductive plate 31A and the surface layer in the z direction of conductive plate 31B are each made of the first metal layer 311. As shown in Figures 12 and 13, in each conductive plate 31A and 31B, the z-direction dimension of each second metal layer 312 is smaller than the z-direction dimension of each first metal layer 311. Each conductive plate 31A and 31B is not limited to a configuration in which multiple first metal layers 311 and multiple second metal layers 312 are laminated, but may be made of a single metal.

[0025] Each of the pair of insulating plates 32A and 32B is made of an insulating material, which is, for example, Al2O3. Each insulating plate 32A and 32B is, for example, rectangular in plan view. Insulating plate 32A supports the conductive plate 31A. Insulating plate 32B supports the conductive plate 31B. On each insulating plate 32A and 32B, a plating layer 321 is formed on the surface to which each conductive plate 31A and 31B are joined, as shown in Figure 7. The plating layer 321 is, for example, made of silver or a silver alloy.

[0026] The wiring board 4, along with the support members 3 (conductive plates 31A, 31B) and the multiple connecting members 7, forms a conductive path in the semiconductor device A1. The wiring board 4 includes a base material 41, a main surface wiring layer 42, a back surface wiring layer 43, and a multiple metal members 44.

[0027] The base material 41 is made of an insulating material, and in one example, it is made of a ceramic with excellent thermal conductivity. Examples of such ceramics include AlN (aluminum nitride), SiN (silicon nitride), and Al2O3 (aluminum oxide). The base material 41 is, for example, a rectangular plate in plan view.

[0028] As shown in Figures 9 to 13, the substrate 41 has a main substrate surface 41a and a back substrate surface 41b. The main substrate surface 41a and the back substrate surface 41b are spaced apart from each other in the z direction. The main substrate surface 41a faces the z2 direction, and the back substrate surface 41b faces the z1 direction.

[0029] As shown in Figures 5, 11, and 13, the base material 41 includes a plurality of through holes 411. As shown in Figures 11 and 13, the plurality of through holes 411 penetrate the base material 41 in the z direction from the main surface 41a to the back surface 41b of the base material. A metal member 44 is inserted into each through hole 411. As shown in Figures 5, 11, and 13, the inner surface of each through hole 411 is not in contact with the metal member 44. In contrast to this configuration, the inner surface of each through hole 411 may be in contact with the metal member 44. Therefore, in this disclosure, "inserted" (or "placed," etc.) means that a certain member (e.g., a metal member 44) is in a certain hole (e.g., a through hole 411), and it is not limited to whether or not the member is in contact with the inner surface of the hole. As an example, an insulating member different from the base material 41 may be provided in the gap between the metal member 44 and the through hole 411.

[0030] The main surface wiring layer 42 is formed on the main surface 41a of the substrate, as shown in Figure 11 and other figures. The main surface wiring layer 42 is a plate material made of copper or a copper alloy, for example. The thickness (dimension in the z direction) of the main surface wiring layer 42 is approximately 0.4 mm in one example. However, the thickness of the main surface wiring layer 42 is not limited to this value and is appropriately changed according to the specifications of the semiconductor device A1 (rated current, allowable current, rated voltage, withstand voltage, internal inductance of the entire device, and size of the device, etc.). For example, the above example of 0.4 mm is set based on specifications such as a rated current of 600 A and an internal inductance of approximately 4.0 nH for the entire device. When the planar dimensions of the main surface wiring layer 42 are the same, the greater the thickness of the main surface wiring layer 42, the greater the reduction in parasitic inductance and parasitic resistance of the entire device, the improvement in heat dissipation, and the increase in allowable current.

[0031] As shown in Figures 3, 4, and 11, the main surface wiring layer 42 includes a first main surface wiring section 421, a second main surface wiring section 422, a pair of third main surface wiring sections 423A and 423B, and a pair of fourth main surface wiring sections 424A and 424B. The first main surface wiring section 421, the second main surface wiring section 422, the pair of third main surface wiring sections 423A and 423B, and the pair of fourth main surface wiring sections 424A and 424B are spaced apart from each other.

[0032] As shown in Figures 3 and 11, the first main surface wiring section 421 is electrically connected to the fifth electrode 22 (source electrode) of each second semiconductor element 2 via a plurality of connecting members 72.

[0033] As shown in Figures 3 and 11, the second main surface wiring section 422 is electrically connected to the second electrode 12 (source electrode) of each first semiconductor element 1 via a plurality of connecting members 71. As shown in Figures 3 and 4, the second main surface wiring section 422 is located in the x1 direction of the first main surface wiring section 421.

[0034] The second main surface wiring section 422 includes a plurality of through holes 422a, as shown in Figures 4, 11, and 13. The plurality of through holes 422a penetrate the second main surface wiring section 422 in the z direction, as shown in Figures 11 and 13. A metal member 44 is fitted into each through hole 422a. As shown in Figures 4, 11, and 13, the inner surface of each through hole 422a is in contact with the metal member 44. In this disclosure, "fitted" means a state in which a member (for example, a metal member 44) is placed in a hole (for example, a through hole 422a) and the member is in contact with the inner surface of the hole. In other words, the state of "fitted" is limited to the state of "inserted" in which it is in contact with the inner surface of the hole.

[0035] As shown in Figure 3, the third main surface wiring section 423A is electrically connected to each third electrode 13 (gate electrode) of a plurality of first semiconductor elements 1 via a connecting member 73A. As shown in Figure 3, the third main surface wiring section 423B is electrically connected to each sixth electrode 23 (gate electrode) of a plurality of second semiconductor elements 2 via a connecting member 73B. The pair of third main surface wiring sections 423A and 423B are each strip-shaped and extend in the y direction.

[0036] As shown in Figure 3, the fourth main surface wiring section 424A is electrically connected to each second electrode 12 (source electrode) of the plurality of first semiconductor elements 1 via a connecting member 74A. As shown in Figure 3, the fourth main surface wiring section 424B is electrically connected to each fifth electrode 22 (source electrode) of the plurality of second semiconductor elements 2 via a connecting member 74B. The pair of fourth main surface wiring sections 424A and 424B are each strip-shaped and extend in the y direction. As shown in Figures 3 and 4, in a plan view, the fourth main surface wiring section 424A is arranged substantially parallel to the third main surface wiring section 423A. In the example shown in Figures 3 and 4, in the x direction, the third main surface wiring section 423A and the plurality of first semiconductor elements 1 are located on opposite sides of the fourth main surface wiring section 424A. Also, in a plan view, the fourth main surface wiring section 424B is arranged substantially parallel to the third main surface wiring section 423B. In the examples shown in Figures 3 and 4, in the x-direction, the third main surface wiring section 423B and the multiple second semiconductor elements 2 are located on opposite sides of the fourth main surface wiring section 424B.

[0037] The back wiring layer 43 is formed on the back surface 41b of the substrate, as shown in Figure 11 and other figures. The back wiring layer 43 is made of a plate material, for example, copper or a copper alloy. The thickness (dimension in the z direction) of the back wiring layer 43 is the same as that of the main surface wiring layer 42, for example, about 0.4 mm in one example. However, the thickness of the back wiring layer 43 is not limited to this value and is changed as appropriate depending on the specifications of the semiconductor device A1 (rated current, allowable current, rated voltage, withstand voltage, internal inductance of the entire device, and size of the device, etc.). For example, the above example of 0.4 mm is set based on specifications such as a rated current of 600 A and an internal inductance of about 4.0 nH for the entire device, similar to the main surface wiring layer 42.

[0038] As shown in Figures 6 and 11, the back wiring layer 43 includes a first back wiring section 431 and a second back wiring section 432. The first back wiring section 431 and the second back wiring section 432 are spaced apart from each other.

[0039] The first back-side wiring section 431 is bonded to the bonding surface 310A of the conductive plate 31A, as shown in Figures 11 and 12. The first back-side wiring section 431 is electrically connected to each of the first electrodes 11 (drain electrodes) of the plurality of first semiconductor elements 1 via the conductive plate 31A. As can be seen from Figures 3, 6 and 11, the first back-side wiring section 431 overlaps the first main surface wiring section 421 in a plan view.

[0040] The second back-side wiring section 432 is bonded to the bonding surface 310B of the conductive plate 31B, as shown in Figures 11 and 13. The second back-side wiring section 432 is electrically connected to each of the fourth electrodes 21 (drain electrodes) of the multiple second semiconductor elements 2 via the conductive plate 31B. As can be seen from Figures 3, 6 and 11, the second back-side wiring section 432 overlaps the second main surface wiring section 422 in a plan view. The second back-side wiring section 432 is located in the x1 direction of the first back-side wiring section 431, as shown in Figure 6.

[0041] The second back wiring section 432 includes a plurality of through holes 432a, as shown in Figures 6, 11, and 13. The plurality of through holes 432a penetrate the second back wiring section 432 in the z direction, as shown in Figures 11 and 13. Each through hole 432a overlaps each through hole 411 and each through hole 422a in a plan view. Each metal member 44 is fitted into each through hole 432a, and the inner surface of each through hole 432a is in contact with each metal member 44, as shown in Figures 6, 11, and 13.

[0042] Each of the multiple metal members 44 is fitted into the wiring board 4, and the main surface wiring layer 42 and the back surface wiring layer 43 are electrically connected. In the semiconductor device A1, the current flowing through each metal member 44 flows approximately parallel to the z direction. Each metal member 44 is columnar in shape with a circular shape in plan view. Each metal member 44 is not limited to having a circular shape in plan view, but may also be elliptical or polygonal. The constituent material of each metal member 44 is, for example, copper or a copper alloy. The length L1 (dimension in the z direction) of each metal member 44 (see Figure 13) is, for example, about 1.2 mm, and the thickness (radius) of each metal member 44 in plan view is about 1.5 mm. The length and thickness in plan view of each metal member 44 are not limited to the examples described above.

[0043] Each metal member 44 is fitted into the through-hole 422a of the second main surface wiring section 422 and the through-hole 432a of the second back surface wiring section 432, and is also inserted into the through-hole 411 of the base material 41. Each metal member 44 is in contact with the inner surface of the through-hole 422a and the inner surface of the through-hole 432a. Each metal member 44 is supported by being fitted into the through-hole 422a of the second main surface wiring section 422 and the through-hole 432a of the second back surface wiring section 432. In this case, if a gap occurs between each metal member 44 and the inner surface of the through-hole 422a and the inner surface of the through-hole 432a, solder may be poured into the gap. This fills the gap with solder and fixes each metal member 44 to the wiring board 4. When solder is poured, the gap between each metal member 44 and the inner surface of the through-hole 411 of the base material 41 may also be filled with solder. Furthermore, each metal member 44 provides electrical conductivity between the second main surface wiring portion 422 of the main surface wiring layer 42 and the second back surface wiring portion 432 of the back surface wiring layer 43.

[0044] Multiple metal members 44 are arranged in region R1 as shown in Figure 4, and in a plan view, they are located between multiple first semiconductor elements 1 and multiple second semiconductor elements 2. Therefore, in a plan view, region R1 is located between multiple first semiconductor elements 1 and multiple second semiconductor elements 2. Multiple metal members 44 are arranged in a line along the y direction at approximately the center of region R1 in the x direction. In semiconductor device A1, for example, region R1 has a dimension W along the x direction (see Figure 4) of about 5 mm and a dimension L along the y direction. R1(See Figure 4) is approximately 45 mm. Multiple metal members 44 are arranged in a line at equal pitches along the y-direction in the region R1. The distance D (see Figure 4) between the centers of two adjacent metal members 44 in a plan view is greater than or equal to a predetermined value. This predetermined value is the value at which the mutual inductance between the two adjacent metal members 44 is approximately 0 (zero). In the example where the length L1 of each metal member 44 is approximately 1.2 mm and the thickness (dimension in the z-direction) of the main surface wiring layer 42 and the back surface wiring layer 43 is approximately 0.4 mm, this value is approximately 0.3 mm. Specifically, if M is the mutual inductance between two metal members 44, L2 (see Figure 13) is the path length of the current flowing through each metal member 44 along the z-direction, and D is the distance between the centers of two adjacent metal members 44 in a plan view, then the following equation (1) is obtained. As shown in Figure 13, the above path length L2 is calculated by subtracting the respective thicknesses (dimensions in the z direction) of the main surface wiring layer 42 and the back surface wiring layer 43 from the length L1 of each metal member 44. Equation (2) below can be obtained from the following equation (1), and by setting the above planar center-to-center distance D to satisfy equation (2), the mutual inductance M becomes approximately 0 (zero). In semiconductor device A1, since the above path length L2 is approximately 0.4 mm (= 1.2 (length L1) - 0.4 (thickness of main surface wiring layer 42) - 0.4 (thickness of back surface wiring layer 43)), in order to keep the mutual inductance M approximately 0 (zero), the above predetermined value should be set to approximately 0.3 mm (≒ 0.74 × 0.4 mm). In semiconductor device A1, the distance D between the centers of two adjacent metal members 44 in a planar view is approximately 12 mm. Therefore, since it is larger than the above predetermined value (approximately 0.3 mm), the mutual inductance value between the two adjacent metal members 44 is approximately 0 (zero). M∝L2×(ln(2L2 / D)-1) (1) D≧2L2 / e(≒0.74×L2) (2)

[0045] Furthermore, multiple metal members 44 are located in region R1 (x-direction dimension W × y-direction dimension L R1In order to allow them to be placed within the area, an upper limit is set on the distance D between the centers of two adjacent metal members 44 in a plan view, depending on the number of metal members 44. Specifically, if the number of metal members 44 is n and the thickness (radius) of each metal member 44 in a plan view is r, then equation (4) below can be obtained from equation (3) below, and the upper limit on the distance D between the centers in a plan view is determined from equation (4) below. For example, the y-direction dimension L of region R1 R1 Assuming a diameter of 45 mm and a thickness (radius) r of the metal member 44 in plan view of 1.5 mm, when four metal members 44 are placed within region R1, D ≤ (45 - 2 × 1.5) / (4 - 1), or D ≤ approximately 14.3 mm, is obtained based on equation (4) below. In other words, in order to place four metal members 44 within region R1, the above-mentioned distance D between the centers in plan view must be approximately 14.3 mm or less. Similarly, in order to place five metal members 44 within region R1, the above-mentioned distance D between the centers in plan view must be 10.5 mm or less, and in order to place six metal members 44 within region R1, the above-mentioned distance D between the centers in plan view must be 8.4 mm or less. Therefore, when four metal members 44 are placed within region R1 in semiconductor device A1, taking into account the above-mentioned mutual inductance M, the above-mentioned distance D between the centers in plan view should be between 0.9 mm and 14.3 mm. L R1 ≥ 2r + (n-1) × D (3) D≦(L R1 -2r) / (n-1) (4)

[0046] The wiring board 4 includes a first power terminal section 401, a second power terminal section 402, and two third power terminal sections 403. The first power terminal section 401, the second power terminal section 402, and the two third power terminal sections 403 are spaced apart from each other.

[0047] In semiconductor device A1, the first power terminal portion 401 is part of the first back wiring portion 431. In the examples shown in Figures 3 and 10, the first power terminal portion 401 includes the edge of the first back wiring portion 431 in the y1 direction. Since the first back wiring portion 431 is electrically connected to the first electrode 11 (drain electrode) of each first semiconductor element 1 via the conductive plate 31A, the first power terminal portion 401 is electrically connected to the first electrode 11 of each first semiconductor element 1. The surface of the first power terminal portion 401 is plated. A part of the first power terminal portion 401 is exposed from the resin member 8.

[0048] In semiconductor device A1, the second power terminal portion 402 is part of the first main surface wiring portion 421. In the examples shown in Figures 8 and 10, the second power terminal portion 402 includes the edge of the first main surface wiring portion 421 in the y1 direction. Since the first main surface wiring portion 421 is conductive to the fifth electrode 22 (source electrode) of each second semiconductor element 2, the second power terminal portion 402 is conductive to the fifth electrode 22 of each second semiconductor element 2. The surface of the second power terminal portion 402 is plated. The first power terminal portion 401 and the second power terminal portion 402 overlap each other in a plan view. A part of the second power terminal portion 402 is exposed from the resin member 8.

[0049] In semiconductor device A1, one of the two third power terminal portions 403 is part of the second main surface wiring portion 422, and the other of the two third power terminal portions 403 is part of the second back surface wiring portion 432. In the examples shown in Figures 3, 8, and 9, each third power terminal portion 403 includes the respective y1-direction edges of the second main surface wiring portion 422 and the second back surface wiring portion 432. Since the second main surface wiring portion 422 and the second back surface wiring portion 432 are conductive to the second electrode 12 (source electrode) of each first semiconductor element 1 and the fourth electrode 21 (drain electrode) of each second semiconductor element 2, the two third power terminal portions 403 are conductive to the second electrode 12 (source electrode) of each first semiconductor element 1 and the fourth electrode 21 of each second semiconductor element 2. The surface of each third power terminal portion 403 is plated. The two third power terminal portions 403 overlap each other in a plan view. In semiconductor device A1, an example is shown in which the wiring board 4 includes two third power terminal portions 403, but the configuration may differ from this, and only one of the two third power terminal portions 403 may be provided. A portion of each third power terminal portion 403 is exposed from the resin member 8.

[0050] The first power terminal section 401 and the second power terminal section 402 are connected to, for example, an external DC power supply, and a power supply voltage (DC voltage) is applied to them. For example, the first power terminal section 401 is a P terminal connected to the positive terminal of the DC power supply, and the second power terminal section 402 is an N terminal connected to the negative terminal of the DC power supply. The DC voltage applied to the first power terminal section 401 and the second power terminal section 402 is converted to an AC voltage by the switching operations of the multiple first semiconductor elements 1 and the multiple second semiconductor elements 2. Each third power terminal section 403 outputs the converted voltage (AC voltage).

[0051] As shown in Figure 3, the wiring board 4 includes a plurality of first openings 45 and a plurality of second openings 46.

[0052] Each of the multiple first openings 45 penetrates in the z-direction from the main surface wiring layer 42 to the back surface wiring layer 43. Each of the multiple first openings 45 accommodates one of the multiple first semiconductor elements 1. In a plan view, each first opening 45 surrounds each first semiconductor element 1.

[0053] Each of the multiple first openings 45 includes an upper through-hole 451, an intermediate through-hole 452, and a lower through-hole 453, as shown in Figures 4 to 6, 11, and 12. In each first opening 45, the upper through-hole 451, the intermediate through-hole 452, and the lower through-hole 453 overlap each other in a plan view.

[0054] The upper penetration portion 451 is formed in the first main surface wiring portion 421 and penetrates the first main surface wiring portion 421 in the z direction. In the example shown in Figure 4, the upper penetration portion 451 is an L-shaped notch or a U-shaped notch in plan view.

[0055] The intermediate penetration portion 452 is formed in the base material 41 and penetrates the base material 41 in the z direction. In the example shown in Figure 5, the intermediate penetration portion 452 is a U-shaped notch or a rectangular through-hole in plan view.

[0056] The downward penetration portion 453 is formed in the first back wiring portion 431 and penetrates the first back wiring portion 431 in the z direction. In the example shown in Figure 6, the downward penetration portion 453 is a U-shaped notch or a rectangular through-hole in plan view. The main surface 1a of each first semiconductor element 1 overlaps the downward penetration portion 453 when viewed in a direction perpendicular to the z direction (for example, the y direction). As a result, each first semiconductor element 1 does not protrude above the wiring substrate 4 in the z direction (z2 direction).

[0057] Each of the multiple second openings 46 penetrates in the z-direction from the main surface wiring layer 42 to the back surface wiring layer 43. The multiple second openings 46 accommodate each second semiconductor element 2 and surround each second semiconductor element 2 in a plan view. Each second semiconductor element 2 is housed in each second opening 46.

[0058] Each of the multiple second openings 46 includes an upper through-hole 461, an intermediate through-hole 462, and a lower through-hole 463, as shown in Figures 4 to 6, 11, and 13. In each second opening 46, the upper through-hole 461, the intermediate through-hole 462, and the lower through-hole 463 overlap each other in a plan view.

[0059] The upper penetration portion 461 is formed in the second main surface wiring portion 422 and penetrates the second main surface wiring portion 422 in the z direction. In the example shown in Figure 4, the upper penetration portion 461 is a U-shaped notch in plan view.

[0060] The intermediate penetration portion 462 is formed in the base material 41 and penetrates the base material 41 in the z direction. In the example shown in Figure 5, the intermediate penetration portion 462 is a rectangular through-hole in plan view.

[0061] The downward penetration portion 463 is formed in the second back wiring portion 432 and penetrates the second back wiring portion 432 in the z direction. In the example shown in Figure 6, the downward penetration portion 463 is a rectangular through-hole in plan view. The main surface 2a of each second semiconductor element 2 overlaps the downward penetration portion 463 when viewed in a direction perpendicular to the z direction (for example, the y direction). As a result, each second semiconductor element 2 does not protrude above the wiring substrate 4 in the z direction (z2 direction).

[0062] The pair of signal terminals 61A, 61B, the pair of detection terminals 62A, 62B, and the multiple dummy terminals 63 are substantially the same shape. The pair of signal terminals 61A, 61B, the pair of detection terminals 62A, 62B, and the multiple dummy terminals 63 each form an L shape when viewed in the x direction, as can be seen from Figures 9 and 10. The pair of signal terminals 61A, 61B, the pair of detection terminals 62A, 62B, and the multiple dummy terminals 63 are arranged substantially parallel to the x direction in a plan view. The pair of signal terminals 61A, 61B, the pair of detection terminals 62A, 62B, and the multiple dummy terminals 63 are each supported by the resin member 8, with a portion of each being covered by the resin member 8.

[0063] Signal terminal 61A is connected to the third electrode 13 (gate electrode) of each first semiconductor element 1, and a first drive signal is input to control the switching operation of each first semiconductor element 1. Signal terminal 61B is connected to the sixth electrode 23 (gate electrode) of each second semiconductor element 2, and a second drive signal is input to control the switching operation of each second semiconductor element 2.

[0064] Each pair of signal terminals 61A and 61B includes a pad portion 611 and a terminal portion 612. As shown in Figure 3, the pad portion 611 of each signal terminal 61A and 61B is covered by a resin member 8. A connecting member 73A is connected to the pad portion 611 of signal terminal 61A, and through this connecting member 73A, it is electrically connected to the third main surface wiring portion 423A. A connecting member 73B is connected to the pad portion 611 of signal terminal 61B, and through this connecting member 73B, it is electrically connected to the third main surface wiring portion 423B. As shown in Figure 3, the terminal portions 612 of each signal terminal 61A and 61B are exposed from the resin member 8. An external control device (e.g., a gate driver) is connected to the terminal portion 612 of each signal terminal 61A and 61B, and a first drive signal and a second drive signal (gate voltage) are input from the control device.

[0065] The detection terminal 62A is connected to the second electrode 12 (source electrode) of each first semiconductor element 1, and outputs the voltage applied to the second electrode 12 of each first semiconductor element 1 (voltage corresponding to the source current). The detection terminal 62B is connected to the fifth electrode 22 (source electrode) of each second semiconductor element 2, and outputs the voltage applied to the fifth electrode 22 of each second semiconductor element 2 (voltage corresponding to the source current).

[0066] Each of the pair of detection terminals 62A and 62B includes a pad portion 621 and a terminal portion 622. As shown in Figure 3, the pad portion 621 of each detection terminal 62A and 62B is covered by a resin member 8. A connecting member 74A is connected to the pad portion 621 of detection terminal 62A, and electrical conductivity is provided to the fourth main surface wiring portion 424A via the connecting member 74A. A connecting member 74B is connected to the pad portion 621 of detection terminal 62B, and electrical conductivity is provided to the fourth main surface wiring portion 424B via the connecting member 74B. As shown in Figure 3, the terminal portions 622 of each detection terminal 62A and 62B are exposed from the resin member 8. An external control device (e.g., a gate driver) is connected to the terminal portion 622 of each detection terminal 62A and 62B, and each detection signal (source signal) is output to the control device.

[0067] Each of the dummy terminals 63 is not electrically connected to any other component of the semiconductor device A1. Part of each dummy terminal 63 is covered by the resin member 8, while the other parts are exposed from the resin member 8.

[0068] Multiple connecting members 7 provide electrical conductivity to two points that are spaced apart from each other. As shown in Figures 2 and 3, each connecting member 7 is, for example, a bonding wire. Unlike this example, some of the connecting members 7 may be metal plates instead of bonding wires. The constituent material of each of the multiple connecting members 7 may be gold, aluminum, or copper. As described above, the multiple connecting members 7 include connecting members 71, 72, 73A, 73B, 74A, 74B, 75A, 75B, 76A, and 76B.

[0069] As shown in Figure 3, the multiple connecting members 71 are joined to the second electrodes 12 (source electrodes) of each of the multiple first semiconductor elements 1 and to the second main surface wiring section 422, thereby creating electrical conductivity between them. In the example shown in Figure 3, some of the connecting members 71 may be joined to one of the multiple metal members 44 instead of the second main surface wiring section 422.

[0070] As shown in Figure 3, the multiple connecting members 72 are joined to each of the fifth electrodes 22 (source electrodes) of the multiple second semiconductor elements 2 and to the first main surface wiring section 421, thereby creating electrical conductivity between them.

[0071] As shown in Figure 3, multiple connecting members 73A are joined to the third electrodes 13 (gate electrodes) of each of the multiple first semiconductor elements 1 and to the third main surface wiring section 423A, thereby making them electrically conductive. As shown in Figure 3, multiple connecting members 73B are joined to the sixth electrodes 23 (gate electrodes) of each of the multiple second semiconductor elements 2 and to the third main surface wiring section 423B, thereby making them electrically conductive.

[0072] As shown in Figure 3, multiple connecting members 74A are joined to the second electrodes 12 (source electrodes) of each of the multiple first semiconductor elements 1 and to the fourth main surface wiring section 424A, thereby making them electrically conductive. As shown in Figure 3, multiple connecting members 74B are joined to the fifth electrodes 22 (source electrodes) of each of the multiple second semiconductor elements 2 and to the fourth main surface wiring section 424B, thereby making them electrically conductive.

[0073] As shown in Figure 3, connecting member 75A is joined to the third main surface wiring section 423A and the pad portion 611 of the signal terminal 61A, thereby providing electrical conductivity between them. Connecting member 75B is joined to the third main surface wiring section 423B and the pad portion 611 of the signal terminal 61B, as shown in Figure 3, thereby providing electrical conductivity between them.

[0074] As shown in Figure 3, connecting member 76A is joined to the fourth main surface wiring section 424A and the pad section 621 of the detection terminal 62A, thereby providing electrical conductivity between them. Connecting member 76B is joined to the fourth main surface wiring section 424B and the pad section 621 of the detection terminal 62B, as shown in Figure 3, thereby providing electrical conductivity between them.

[0075] The resin member 8 covers a plurality of first semiconductor elements 1, a plurality of second semiconductor elements 2, a support member 3, a part of the wiring board 4, a part of each of the pair of signal terminals 61A and 61B, a part of each of the pair of detection terminals 62A and 62B, a part of each of the plurality of dummy terminals 63, and a plurality of connecting members 7. The resin member 8 is made of an insulating resin material such as epoxy resin. As shown in Figure 3, the resin member 8 is rectangular in plan view. On the side surface in the y1 direction, the resin member 8 has notches formed on both the z1 direction side and the z2 direction side. As shown in Figures 1, 3, and 8, the first power terminal portion 401, the second power terminal portion 402, and the third power terminal portion 403 of the wiring board 4 are exposed from the resin member 8 by these notches.

[0076] The operation and effects of semiconductor device A1 are as follows:

[0077] The semiconductor device A1 comprises a first semiconductor element 1, a second semiconductor element 2, and a wiring substrate 4. The wiring substrate 4 includes a base material 41, a main surface wiring layer 42, a back surface wiring layer 43, and a metal member 44. The main surface wiring layer 42 is formed on the main surface 41a of the base material 41, and the back surface wiring layer 43 is formed on the back surface 41b of the base material 41. The metal member 44 is inserted into the base material 41 and provides electrical conductivity between the main surface wiring layer 42 and the back surface wiring layer 43. Conventionally, in a double-sided substrate in which wiring patterns are formed on the upper and lower surfaces of an insulating substrate, a method of using through vias is known to provide electrical conductivity between the wiring pattern formed on the upper surface and the wiring pattern formed on the lower surface. Through vias are formed by, for example, applying metal plating to the surface of a through hole that penetrates the substrate. Since the thickness of the metal plating is limited by the size of the through hole, in a configuration in which the main surface wiring layer 42 and the back surface wiring layer 43 are provided electrical conductivity by this through via, there was a limitation in increasing the allowable current of the current path interposed by this through via. On the other hand, in semiconductor device A1, conductivity between the main surface wiring layer 42 and the back surface wiring layer 43 is achieved by a metal member 44 inserted into the substrate 41. With this configuration, the allowable current can be increased in the conductivity between the main surface wiring layer 42 and the back surface wiring layer 43 compared to using through vias. In particular, in semiconductor device A1, the metal member 44 is interposed in the conductivity path between the second electrode 12 (e.g., source electrode) of the first semiconductor element 1 and the fourth electrode 21 (e.g., drain electrode) of the second semiconductor element 2. In other words, the current between the second electrode 12 (source electrode) of the first semiconductor element 1 and the fourth electrode 21 (drain electrode) of the second semiconductor element 2 can be increased. Therefore, by using the metal member 44 in the conductivity between the main surface wiring layer 42 and the back surface wiring layer 43, semiconductor device A1 can increase the allowable current in the main current path. The main current in semiconductor device A1 is the current flowing between the first power terminal section 401, the second power terminal section 402 and each of the third power terminal sections 403. In other words, semiconductor device A1 can handle high currents.

[0078] In semiconductor device A1, the wiring board 4 includes a plurality of metal members 44. Of the plurality of metal members 44, two adjacent metal members 44 in a plan view are arranged such that the distance D between their centers in a plan view is greater than or equal to a predetermined value. With this configuration, it is possible to make the mutual inductance value between two adjacent metal members 44 approximately 0 (zero). In semiconductor device A1, the above path length L2 is approximately 0.4 mm, and the distance D between the centers of two adjacent metal members 44 in a plan view is approximately 12 mm. As described above, the mutual inductance M between two adjacent metal members 44 is approximately 0 (zero). Therefore, semiconductor device A1 can reduce its internal inductance.

[0079] In semiconductor device A1, the multiple metal members 44 are located between the multiple first semiconductor elements 1 and the multiple second semiconductor elements 2 in a plan view. In semiconductor device A1, for example, the main current flows through the second main surface wiring section 422. This main current concentrates in region R1 in the second main surface wiring section 422. Therefore, by arranging the multiple metal members 44 in region R1, the main current path can be secured. As shown in Figure 4, region R1 is located between the multiple first semiconductor elements 1 and the multiple second semiconductor elements 2 in a plan view. In other words, by arranging the multiple metal members 44 between the multiple first semiconductor elements 1 and the multiple second semiconductor elements 2 in a plan view, the main current path can be secured. Consequently, semiconductor device A1 does not place metal members 44 in regions where little main current flows (regions other than region R1), thus suppressing the unnecessary addition of metal members 44.

[0080] In semiconductor device A1, a first main surface wiring section 421 that conducts to the fifth electrode 22 (source electrode) of each second semiconductor element 2, and a first back surface wiring section 431 that conducts to the first electrode 11 (drain electrode) of each first semiconductor element 1 are arranged in the z direction with the substrate 41 in between. The first back surface wiring section 431 includes a first power terminal section 401, and the first main surface wiring section 421 includes a second power terminal section 402. The first power terminal section 401, the second power terminal section 402, and the substrate 41 overlap each other in a plan view. With this configuration, the first power terminal section 401 (first back surface wiring section 431) and the second power terminal section 402 (first main surface wiring section 421) to which the power supply voltage is applied can be made into laminate wiring, so that the inductance between the first power terminal section 401 and the second power terminal section 402 can be reduced. Therefore, the semiconductor device A1 can reduce its internal inductance. Furthermore, when connecting an external power supply, busbar, or capacitor to the first power terminal section 401 and the second power terminal section 402, the connection can be made by sandwiching the first power terminal section 401 and the second power terminal section 402 between them.

[0081] In semiconductor device A1, each first semiconductor element 1 is mounted on a conductive plate 31A. The conductive plate 31A functions as a heat spreader that dissipates heat from each first semiconductor element 1. This configuration improves heat dissipation compared to when each first semiconductor element 1 is bonded to a wiring substrate 4 (for example, the main surface wiring layer 42). Similarly, each second semiconductor element 2 is mounted on a conductive plate 31B. The conductive plate 31B functions as a heat spreader that dissipates heat from each second semiconductor element 2. This configuration improves heat dissipation compared to when each second semiconductor element 2 is bonded to a wiring substrate 4 (for example, the main surface wiring layer 42).

[0082] In semiconductor device A1, the conductive plate 31A is constructed by laminating a first metal layer 311 made of copper and a second metal layer 312 made of molybdenum. Molybdenum has a lower coefficient of thermal expansion than copper. This configuration suppresses the thermal expansion coefficient of the conductive plate 31A. Therefore, the thermal stress on the conductive bonding material 19 added by the heat from each first semiconductor element 1 bonded to the conductive plate 31A can be alleviated. Similarly, since the conductive plate 31B is also constructed by laminating a first metal layer 311 and a second metal layer 312, the thermal expansion coefficient of the conductive plate 31B can be suppressed. Therefore, the thermal stress on the conductive bonding material 29 added by the heat from each second semiconductor element 2 bonded to the conductive plate 31B can be alleviated. As a result, semiconductor device A1 can suppress delamination of each first semiconductor element 1 and each second semiconductor element 2.

[0083] In semiconductor device A1, a portion of the main current path is formed by a wiring board 4. The wiring board 4 includes a base material 41, a main surface wiring layer 42, and a back surface wiring layer 43, and is a double-sided substrate. With this configuration, semiconductor device A1 can be made smaller in plan view than conventional semiconductor devices (for example, Patent Document 1).

[0084] In semiconductor device A1, each first semiconductor element 1 is housed in each first opening 45 and overlaps the wiring board 4 when viewed in a direction perpendicular to the z direction (for example, the y direction). Similarly, each second semiconductor element 2 is housed in each second opening 46 and overlaps the wiring board 4 when viewed in a direction perpendicular to the z direction (for example, the y direction). With this configuration, the wiring board 4 can be bonded to each conductive plate 31A, 31B without interfering with each first semiconductor element 1 and each second semiconductor element 2. Therefore, semiconductor device A1 can be made lower profile (reduced dimensions in the z direction).

[0085] Figure 14 shows a semiconductor device A2 according to the second embodiment. Figure 14 is a plan view of the semiconductor device A2 and corresponds to Figure 4 of the first embodiment. That is, Figure 14 omits the multiple connecting members 7 and resin members 8. The semiconductor device A2 differs from the semiconductor device A1 in that it has a larger number of metal members 44.

[0086] The wiring board 4 of semiconductor device A2 includes eight metal members 44, as shown in Figure 14. In the example shown in Figure 14, the eight metal members 44 are arranged in a line at equal pitches along the y-direction. In semiconductor device A2, the multiple metal members 44 are arranged at, for example, a pitch of 4.5 mm. That is, the distance D between the centers of two adjacent metal members 44 in a plan view is approximately 4.5 mm. In semiconductor device A2, the length and thickness of each metal member 44 are the same as those of each metal member 44 in semiconductor device A1. Also, the dimension W along the x-direction and the dimension L along the y-direction of region R1 are... R1 This is the same as region R1 of semiconductor device A1. In semiconductor device A2, the distance D between the centers of two adjacent metal members 44 in a plan view is set to approximately 4.5 mm, which is larger than the predetermined value (approximately 0.3 mm). Therefore, the mutual inductance M between the two adjacent metal members 44 is approximately 0 (zero).

[0087] In semiconductor device A2, the combined inductance value of the self-inductance values ​​of the multiple metal components 44 is within 5% of the total internal inductance value of semiconductor device A2. For example, if the total internal inductance value of semiconductor device A2 is 4nH, then 5% of that is 0.2nH (=4[nH] × (5 / 100)[%]). In contrast, if the self-inductance value of each metal component 44 is 1nH, then by arranging five or more of the metal components 44, the combined inductance value of the self-inductance values ​​of the multiple metal components 44 can be made within 5% of the total internal inductance value of semiconductor device A2. Since the multiple metal components 44 are electrically connected in parallel, the combined inductance value of the multiple metal components 44 is calculated by summing the reciprocals of the self-inductance values ​​of each metal component 44 and then taking the reciprocal of that sum. In semiconductor device A2, there are eight metal components 44, so the combined inductance value of the multiple metal components 44 is within 5% of the total internal inductance value of semiconductor device A2. The number of metal components 44 can be appropriately changed depending on the total internal inductance value of the semiconductor device A2, the ratio of the composite inductance value to the internal inductance value, and the self-inductance value of each metal component 44.

[0088] In the semiconductor device A2 as well, in order to arrange multiple metal members 44 in region R1, an upper limit D of the distance between the centers of two adjacent metal members 44 in a plan view is set based on equations (1) and (2) above. Therefore, the y-direction dimension L of region R1 is set. R1 In an example where the area is 45 mm and the diameter (radius) r of each metal member 44 in plan view is 1.5 mm, if the number of metal members 44 is 5, then the calculation in equation (2) above yields D ≤ 10.5 mm. In other words, in order to place 5 metal members 44 within the area R1, the distance D between the centers in plan view must be 10.5 mm or less. In semiconductor device A2, since 8 metal members 44 are arranged, the distance D between the centers in plan view is set to 6 mm or less.

[0089] The semiconductor device A2 can achieve the same effects as the semiconductor device A1.

[0090] Semiconductor device A2 has a larger number of metal members 44 than semiconductor device A1. This configuration reduces the combined inductance of the multiple metal members 44, thus suppressing the internal inductance of semiconductor device A2 compared to semiconductor device A1. In particular, in semiconductor device A2, the combined inductance of the individual self-inductances of the multiple metal members 44 is within 5% of the total internal inductance of semiconductor device A2. The greater the number of metal members 44, the greater the reduction in combined inductance. However, there are physical limitations on arranging multiple metal members 44 in region R1. Specifically, based on equation (5) obtained from equation (3) above, the number is limited to the calculated value on the right-hand side of equation (5) below. That is, the upper limit of the number n of metal members 44 is determined based on equation (5) below. In semiconductor device A2 as well, the distance D between the centers in the plan view is considered such that the mutual inductance M is approximately 0 (zero). n≦((L R1 -2r) / D)+1 (5)

[0091] Figure 15 shows a semiconductor device A3 according to the third embodiment. Figure 15 is a plan view of the semiconductor device A3 and corresponds to Figure 4 of the first embodiment. That is, Figure 15 omits the multiple connecting members 7 and resin members 8. The semiconductor device A3 differs from the semiconductor device A1 in that the multiple metal members 44 are not arranged at equal pitches.

[0092] As shown in Figure 15, the multiple metal members 44 in semiconductor device A3 are arranged in a line along the y-direction, similar to semiconductor devices A1 and A2. However, in semiconductor device A3, as shown in Figure 15, the distance D1 between the centers of two adjacent metal members 44 in the y1 direction is smaller than the distance D2 between the centers of two adjacent metal members 44 in the y2 direction. In other words, in a plan view, the arrangement spacing of the multiple metal members 44 is shorter on the y1 direction side than on the y2 direction side, and the arrangement density of metal members 44 on the y1 direction side of region R1 is higher than the arrangement density of metal members 44 on the y2 direction side. In this case, the multiple metal members 44 may be arranged such that the arrangement spacing gradually decreases from the y1 direction side to the y2 direction side in a plan view. Note that the distance D1 between the centers in a plan view is greater than or equal to the predetermined value mentioned above to make the mutual inductance M between two metal members 44 approximately 0 (zero).

[0093] The semiconductor device A3 can achieve the same effects as the semiconductor devices A1 and A2.

[0094] In semiconductor device A3, the arrangement of multiple metal members 44 is shorter on the y1 side than on the y2 side in a plan view. That is, the distance D1 between the centers of two adjacent metal members 44 in the y1 side is smaller than the distance D2 between the centers of two adjacent metal members 44 in the y2 side in a plan view. In semiconductor device A3, the first power terminal section 401 and the second power terminal section 402 are located on the y1 side of region R1. In this configuration, the main current is more concentrated in the portion of region R1 sandwiched between the pair of first semiconductor elements 1 and second semiconductor elements 2 located relatively on the y1 side than in the portion sandwiched between the pair of first semiconductor elements 1 and second semiconductor elements 2 located relatively on the y2 side. Therefore, by making the distance D1 between the centers in the plan view smaller than the distance D2 between the centers in the plan view, a larger number of metal members 44 can be arranged in the portion where the main current is concentrated. As a result, semiconductor device A3 can increase the allowable current in the main current path. In other words, semiconductor device A3 is preferable for achieving high current.

[0095] In the third embodiment, an example was shown where the distance D1 between the centers in the plan view is smaller than the distance D2 between the centers in the plan view. However, the embodiment is not limited to this, and the thickness of the metal member 44 located relatively on the y1 side in the plan view may be larger than the thickness of the metal member 44 located relatively on the y2 side in the plan view. In this case, the metal member 44 may be configured such that the thickness of each metal member 44 in the plan view gradually decreases from the y1 side to the y2 side in the plan view. Since the allowable current increases as the thickness of the metal member 44 increases, this configuration also allows for an increase in the allowable current in the main current path.

[0096] In the third embodiment, an example was shown where the planar center distance D1 is smaller than the planar center distance D2. Conversely, the planar center distance D2 may be smaller than the planar center distance D1. In other words, the arrangement density of metal members 44 on the y2 direction side of region R1 may be higher than the arrangement density of metal members 44 on the y1 direction side. As described above, in the semiconductor device A3, the main current is more concentrated in the portion of region R1 sandwiched between the pair of first semiconductor elements 1 and second semiconductor elements 2 located relatively on the y1 direction side than in the portion sandwiched between the pair of first semiconductor elements 1 and second semiconductor elements 2 located relatively on the y2 direction side. Therefore, by making the planar center distance D2 smaller than the planar center distance D1, a current path to the metal members 44 located on the y2 direction side of region R1 can be secured, thereby mitigating the current concentration within region R1. This suppresses the bias in the current flowing through each first semiconductor element 1 and each second semiconductor element 2, thereby preventing uneven degradation of each first semiconductor element 1 and each second semiconductor element 2. In this modified example, instead of creating a difference in the distances D1 and D2 between the centers in the plan view, the thickness of the metal member 44 in the plan view may be changed. In other words, the thickness of the metal member 44 located relatively on the y2 side in the plan view may be made larger than the thickness of the metal member 44 located relatively on the y1 side in the plan view.

[0097] In the first to third embodiments, the multiple metal members 44 were shown arranged in a line along the y-direction approximately in the center of the x-direction of region R1, but the invention is not limited to this, and may be positioned closer to the edge on the x1-direction side (or x2-direction side) of region R1. An alternating current flows through region R1 (the second main surface wiring section 422 and the second back surface wiring section 432) due to the switching operation of each first semiconductor element 1 and each second semiconductor element 2. The higher the frequency of the alternating current, the more easily it flows through the surface of the conductor due to the skin effect. Therefore, multiple metal members 44 can be arranged in regions R1 (the second main surface wiring section 422 and the second back surface wiring section 432) at positions where alternating current flows easily.

[0098] Figure 16 shows a semiconductor device A4 according to the fourth embodiment. Figure 16 is a plan view of the semiconductor device A4 and corresponds to Figure 4 of the first embodiment. That is, Figure 16 omits the multiple connecting members 7 and resin members 8. The semiconductor device A4 differs from the semiconductor device A1 in that the multiple metal members 44 are arranged in multiple rows in the y direction, rather than in a single row. In the example shown in Figure 16, the multiple metal members 44 arranged in the y direction are arranged in two rows in the x direction. Note that each row of the multiple metal members 44 arranged in two rows may be evenly distributed in the x direction within the region R1, or, considering the skin effect described above, they may be arranged closer to each edge in the x direction.

[0099] In semiconductor device A1, the dimension W along the x-direction of region R1 was approximately 5 mm, and the thickness (radius) of each metal member 44 in plan view was approximately 1.5 mm, so only one row could be arranged in the x-direction. Therefore, assuming the same dimension W, in semiconductor device A4, the thickness (radius) of each metal member 44 in plan view is made smaller than that of each metal member 44 in semiconductor device A1, allowing for multiple rows to be arranged in the x-direction. In semiconductor device A4, when considering the mutual inductance M between two adjacent metal members 44, the distance D between the centers of two adjacent metal members 44 in the y-direction in plan view is set to be greater than or equal to a predetermined value, and the distance Dx between the centers of two adjacent metal members 44 in the x-direction in plan view is set to be greater than or equal to a predetermined value.

[0100] The semiconductor device A4 can achieve the same effects as the semiconductor device A1.

[0101] In the first to fourth embodiments, examples were shown in which each metal member 44 is not in contact with the inner surface of the through hole 411, but the invention is not limited to this, and may be in contact with the inner surface of the through hole 411. In other words, each metal member 44 may be fitted into the through hole 411. With this configuration, each metal member 44 is supported not only by the main surface wiring layer 42 and the back surface wiring layer 43 but also by the base material 41, so that each metal member 44 does not fall out. Furthermore, in the configuration in which each metal member 44 is fitted into the through hole 411, each metal member 44 may not be fitted into the main surface wiring layer 42 (second main surface wiring portion 422), but rather the upper surface (surface facing the z2 direction) of each metal member 44 may be in contact with the main surface wiring layer 42. Similarly, each metal member 44 may be configured such that, instead of being fitted into the back wiring layer 43 (second back wiring section 432), the lower surface (the surface facing the z1 direction) of each metal member 44 is in contact with the back wiring layer 43.

[0102] The semiconductor devices described herein are not limited to the embodiments described above. The specific configuration of each part of the semiconductor device described herein can be modified in various ways. For example, the semiconductor device described herein includes the embodiments described in the following appendix. Note 1. A first semiconductor element having a first electrode, a second electrode, and a third electrode, wherein the connection between the first electrode and the second electrode is controlled on and off by a first drive signal input to the third electrode, A second semiconductor element having a fourth electrode, a fifth electrode, and a sixth electrode, wherein the connection between the fourth electrode and the fifth electrode is controlled on and off by a second drive signal input to the sixth electrode, A wiring board comprising a substrate having a main surface and a back surface spaced apart in the thickness direction, a main surface wiring layer formed on the main surface of the substrate, a back surface wiring layer formed on the back surface of the substrate, and a metal member inserted into the substrate to provide electrical conductivity between the main surface wiring layer and the back surface wiring layer, It is equipped with, The first semiconductor element and the second semiconductor element are connected in series by connecting the second electrode and the fourth electrode. A semiconductor device in which the metal member is interposed in the conductive path between the second electrode and the fourth electrode. Note 2. The aforementioned wiring board includes a first power terminal section, a second power terminal section, and a third power terminal section that are spaced apart from each other. The first power terminal portion is electrically connected to the first electrode, The second power terminal is electrically connected to the fifth electrode, The semiconductor device described in Appendix 1, wherein the third power terminal portion is electrically connected to the second electrode and the fourth electrode. Note 3. The wiring board comprises a resin member that covers a portion of the first semiconductor element and the second semiconductor element, The semiconductor device described in Appendix 2, wherein the first power terminal portion, the second power terminal portion, and the third power terminal portion of the wiring board are exposed from the resin member. Note 4. The main surface wiring layer includes a first main surface wiring section and a second main surface wiring section that are spaced apart from each other. The first main surface wiring section is electrically connected to the fifth electrode, The second main surface wiring section is electrically connected to the second electrode and the fourth electrode. The semiconductor device according to either Appendix 2 or Appendix 3, wherein the second power terminal portion is part of the first main surface wiring portion. Note 5. The aforementioned back-side wiring layer includes a first back-side wiring section and a second back-side wiring section that are spaced apart from each other. The first back wiring section is electrically connected to the first electrode, The second back wiring section is electrically connected to the second electrode and the fourth electrode. The semiconductor device described in Appendix 4, wherein the first power terminal portion is part of the first back wiring portion. Note 6. The semiconductor device described in Appendix 5, wherein the second main surface wiring section and the second back surface wiring section are electrically connected via the metal member. Note 7. The second main surface wiring section includes a main surface through-hole that penetrates in the thickness direction, The second back surface wiring section includes a back surface through-hole that penetrates in the thickness direction, The semiconductor device described in Appendix 6, wherein the metal member is fitted into the main surface through hole and the back surface through hole and supported by the wiring board. Note 8. The semiconductor device according to either Appendix 6 or Appendix 7, wherein the first power terminal portion and the second power terminal portion overlap each other when viewed in the thickness direction. Note 9. The semiconductor device according to Appendix 8, wherein the third power terminal portion is part of the second main surface wiring portion or part of the second back surface wiring portion. Note 10. The first semiconductor element has a first element main surface that faces the same direction as the main surface of the substrate in the thickness direction and a first element back surface that faces the same direction as the back surface of the substrate in the thickness direction. The aforementioned first electrode is provided on the back surface of the aforementioned first element, The second electrode is provided on the main surface of the first element, The second semiconductor element has a second element main surface that faces the same direction as the main surface of the substrate in the thickness direction and a second element back surface that faces the same direction as the back surface of the substrate in the thickness direction. The fourth electrode is provided on the back surface of the second element, The semiconductor device described in Appendix 9, wherein the fifth electrode is provided on the main surface of the second element. Note 11. A first conductive plate having a first bonding surface to which the first electrode is bonded, and supporting the first semiconductor element, A second conductive plate having a second bonding surface to which the fourth electrode is bonded, and supporting the second semiconductor element, It also has the following features: The first conductive plate and the second conductive plate overlap the wiring substrate when viewed in the thickness direction, The first back wiring section is bonded to the first bonding surface and is electrically connected to the first electrode via the first conductive plate. The semiconductor device according to Appendix 10, wherein the second back wiring portion is bonded to the second bonding surface and is electrically connected to the fifth electrode via the second conductive plate. Note 12. Each of the wiring boards includes a first opening and a second opening that penetrate from the main surface wiring layer to the back surface wiring layer in the thickness direction, The first opening surrounds the first semiconductor element when viewed in the thickness direction, The semiconductor device as described in Appendix 11, wherein the second opening surrounds the second semiconductor element when viewed in the thickness direction. Note 13. A first connecting member that connects the second electrode and the second main surface wiring section, A second connecting member that connects the fifth electrode and the first main surface wiring section, A semiconductor device as described in Appendix 12, further comprising the features described therein. Note 14. The aforementioned metal members are a plurality of metal members, A semiconductor device according to any one of Appendix 1 to Appendix 13, wherein two adjacent metal members, as viewed in the thickness direction, are arranged such that the distance between their centers as viewed in the thickness direction is greater than or equal to a predetermined value. Note 15. The first semiconductor element and the second semiconductor element are a plurality of first semiconductor elements and a plurality of second semiconductor elements, The plurality of first semiconductor elements are electrically connected in parallel to one another and are arranged along a first direction perpendicular to the thickness direction. The semiconductor device according to Appendix 14, wherein the plurality of second semiconductor elements are electrically connected in parallel to one another and arranged along the first direction. Note 16. The plurality of first semiconductor elements and the plurality of second semiconductor elements overlap when viewed in the thickness direction and in a second direction perpendicular to the first direction. The semiconductor device described in Appendix 15, wherein the plurality of metal members are located between the plurality of first semiconductor elements and the plurality of second semiconductor elements when viewed in the thickness direction. Note 17. The semiconductor device according to Appendix 16, wherein the plurality of metal members are arranged along the first direction. Note 18. The semiconductor device described in Appendix 17, wherein, when viewed in the thickness direction, the spacing between the plurality of metal members is shorter on one side in the first direction than on the other side. Note 19. The semiconductor device according to any one of Appendix 14 to Appendix 18, wherein the combined inductance value of the plurality of metal members is within 5% of the total inductance value of the semiconductor device. [Explanation of symbols]

[0103] A1~A4: Semiconductor device 1: First semiconductor device 1a: Main surface of the element 1b: Back surface of the element 11: 1st electrode 12: 2nd electrode 13: Third electrode 19: Conductive bonding material 2: Second semiconductor element 2a: Main surface of the element 2b: Back surface of the element 21: Fourth electrode 22: 5th electrode 23: 6th electrode 29: Conductive bonding material 3: Support member 31A, 31B: Conductive plate 311: First metal layer 312: Second metal layer 319: Bonding material 310A, 310B: Joint surface; 32A, 32B: Insulating plate 321: Plating layer 4: Wiring board 401: First power terminal section 402: Second power terminal section 403: Third power terminal part 41: Base material 41a: Main surface of base material 41b: Back surface of base material 411: Through hole 42: Main surface wiring layer 421: First main surface wiring section 422: Second main surface wiring section 422a: Through hole 423A, 423B: Third main surface wiring section 424A, 424B: Fourth main surface wiring section; 43: Rear surface wiring layer 431: First rear wiring section 432: Second rear wiring section 432a: Through hole 44: Metal member 45: First opening 451: Upper penetration part 452: Intermediate penetration section 453: Lower penetration section 46: Second opening 461: Upper penetration part 462: Intermediate penetration section 463: Lower penetration section 61A, 61B: Signal terminals; 611: Pad section 612: Terminal section 62A, 62B: Detection terminals 63: Dummy terminal 621: Pad section 622:Terminal section 7, 71, 72, 73A, 73B: Connecting members 74A, 74B, 75A, 75B: Connecting members 76A, 76B: Connecting members 8: Resin members

Claims

1. A first semiconductor element having a first electrode, a second electrode, and a third electrode, wherein the connection between the first electrode and the second electrode is controlled on and off by a first drive signal input to the third electrode, A second semiconductor element having a fourth electrode, a fifth electrode, and a sixth electrode, wherein the connection between the fourth electrode and the fifth electrode is controlled on and off by a second drive signal input to the sixth electrode, A wiring board comprising a substrate having a main surface and a back surface spaced apart in the thickness direction, a main surface wiring layer formed on the main surface of the substrate, a back surface wiring layer formed on the back surface of the substrate, and a metal member inserted into the substrate to provide electrical conductivity between the main surface wiring layer and the back surface wiring layer, A resin member covering a part of the wiring board, the first semiconductor element, and the second semiconductor element, It is equipped with, The first electrode is connected to the first power terminal, The fifth electrode is connected to the second power terminal, The second electrode and the fourth electrode are connected in series via the metal member and are also connected to the third power terminal. The first power terminal portion and the second power terminal portion include portions that face each other via the substrate, A portion of the substrate and a portion of each of the opposing parts of the first power terminal and the second power terminal are exposed from the resin member. The aforementioned metal member is a plurality of metal members, Of the plurality of metal members, two adjacent metal members viewed in the thickness direction are arranged such that the distance between their centers viewed in the thickness direction is greater than or equal to a predetermined value. The first semiconductor element and the second semiconductor element are a plurality of first semiconductor elements and a plurality of second semiconductor elements, The plurality of first semiconductor elements are electrically connected in parallel to one another and are arranged along a first direction perpendicular to the thickness direction. The plurality of second semiconductor elements are electrically connected in parallel to each other and are arranged along the first direction. The plurality of first semiconductor elements and the plurality of second semiconductor elements overlap when viewed in the thickness direction and in a second direction perpendicular to the first direction. The plurality of metal members are located between the plurality of first semiconductor elements and the plurality of second semiconductor elements when viewed in the thickness direction. The plurality of metal members are arranged along the first direction, The first power terminal portion, the second power terminal portion, and the third power terminal portion are located on one side in the first direction of the plurality of first semiconductor elements and the plurality of second semiconductor elements. A semiconductor device in which, when viewed in the thickness direction, the spacing between the plurality of metal members is shorter on one side in the first direction than on the other side.

2. The semiconductor device according to claim 1, wherein the wiring board includes a first power terminal portion, a second power terminal portion, and a third power terminal portion that are spaced apart from each other.

3. The semiconductor device according to claim 2, wherein the first power terminal portion, the second power terminal portion, and the third power terminal portion of the wiring board are exposed from the resin member.

4. The main surface wiring layer includes a first main surface wiring section and a second main surface wiring section that are spaced apart from each other. The first main surface wiring section is electrically connected to the fifth electrode, The second main surface wiring section is electrically connected to the second electrode and the fourth electrode. The semiconductor device according to claim 2 or claim 3, wherein the second power terminal portion is part of the first main surface wiring portion.

5. The aforementioned back-side wiring layer includes a first back-side wiring section and a second back-side wiring section that are spaced apart from each other. The first back wiring section is electrically connected to the first electrode, The second back wiring section is electrically connected to the second electrode and the fourth electrode. The semiconductor device according to claim 4, wherein the first power terminal portion is part of the first back wiring portion.

6. The semiconductor device according to claim 5, wherein the second main surface wiring portion and the second back surface wiring portion are electrically connected via the metal member.

7. The second main surface wiring portion includes a main surface through-hole that penetrates in the thickness direction, The second back surface wiring section includes a back surface through-hole that penetrates in the thickness direction, The semiconductor device according to claim 6, wherein the metal member is fitted into the main surface through hole and the back surface through hole and supported by the wiring board.

8. The semiconductor device according to claim 6 or claim 7, wherein the first power terminal portion and the second power terminal portion overlap each other when viewed in the thickness direction.

9. The semiconductor device according to claim 8, wherein the third power terminal portion is a part of the second main surface wiring portion or a part of the second back surface wiring portion.

10. The first semiconductor element has a first element main surface that faces the same direction as the main surface of the substrate in the thickness direction and a first element back surface that faces the same direction as the back surface of the substrate in the thickness direction. The aforementioned first electrode is provided on the back surface of the aforementioned first element, The second electrode is provided on the main surface of the first element, The second semiconductor element has a second element main surface that faces the same direction as the main surface of the substrate in the thickness direction and a second element back surface that faces the same direction as the back surface of the substrate in the thickness direction. The fourth electrode is provided on the back surface of the second element, The semiconductor device according to claim 9, wherein the fifth electrode is provided on the main surface of the second element.

11. A first conductive plate having a first bonding surface to which the first electrode is bonded, and supporting the first semiconductor element, The device further comprises a second conductive plate having a second bonding surface to which the fourth electrode is bonded, and supporting the second semiconductor element, The first conductive plate and the second conductive plate overlap the wiring board when viewed in the thickness direction, The first back wiring portion is bonded to the first bonding surface and is electrically connected to the first electrode via the first conductive plate. The semiconductor device according to claim 10, wherein the second back wiring portion is bonded to the second bonding surface and is electrically connected to the fifth electrode via the second conductive plate.

12. Each of the wiring boards includes a first opening and a second opening that penetrate from the main surface wiring layer to the back surface wiring layer in the thickness direction, The first opening surrounds the first semiconductor element when viewed in the thickness direction, The semiconductor device according to claim 11, wherein the second opening surrounds the second semiconductor element when viewed in the thickness direction.

13. A first connecting member that connects the second electrode and the second main surface wiring section, A second connecting member that connects the fifth electrode and the first main surface wiring section, The semiconductor device according to claim 12, further comprising:

14. The semiconductor device according to any one of claims 1 to 13, wherein the combined inductance value of the plurality of metal members is within 5% of the total inductance value of the semiconductor device.

15. The aforementioned third power terminal section consists of two third power terminal sections, The semiconductor device according to any one of claims 1 to 14, wherein each of the two third power terminals includes a portion facing each other via the substrate.

16. The semiconductor device according to claim 15, wherein a portion of each of the two third power terminal portions that face each other is individually exposed from the resin member.

17. The resin member has a plurality of recesses formed therein. The semiconductor device according to claim 16, wherein a portion of each of the opposing portions of the first power terminal portion and the second power terminal portion, and a portion of each of the opposing portions of the two third power terminal portions are individually exposed from one of the plurality of recesses.

18. The aforementioned metal member is a plurality of metal members, The semiconductor device according to any one of claims 1 to 17, wherein the mutual inductance between two adjacent metal members among the plurality of metal members is approximately 0.

19. The semiconductor device according to any one of claims 1 to 18, wherein the first semiconductor element and the second semiconductor element are made of a semiconductor material mainly composed of silicon carbide.

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