Method and apparatus for high-speed charge-coupled CMOS TDI imaging

Abstract

A method and apparatus (e.g., circuit) provides high-speed charge-coupled CMOS TDI imaging based on parallel readout of multiple TDI stages. Multiple (N) output registers are reset and globally precharged in parallel, ready to receive charges transferred from the same number (N) of TDI pixel registers. Each signal charge in each output register is converted in parallel to a signal voltage. Each analog signal voltage is then converted in parallel to a digital value by each of N ADCs. A-D conversion continues in parallel while the next N TDI registers are processed. The N output registers are linked to receive charges from the top to the bottom of the register. The conversion of each signal voltage is performed by a S / H capacitor array circuit in a ping-pong fashion using a CDS voltage.

Description

Technical Field

[0001] The present disclosure relates to a complementary metal-oxide-semiconductor (CMOS) time delay and integral (time delay and integration, TDI) high fidelity imaging method and apparatus therefor for parallel readout operation.

Background Art

[0002] In a conventional CMOS TDI imager, the readout operation is sequentially executed as follows: 1. A floating diffusion (FD) is reset to a reset drain voltage (VDD) via a reset gate (RST). At that point, the reset signal accumulated in the floating diffusion is sampled to a sample and hold (S / H) capacitor via a source follower (SF). This operation takes about 500 ns. 2. The signal charge of the final TDI stage is transferred to the FD. This operation takes about 800 ns. 3. The signal charge is converted to a signal voltage at the FD, and the signal voltage is sampled to the S / H capacitor via the SF for a correlated double sampling (CDS) operation. This operation takes about 500 ns. 4. Next, the analog signal voltage is converted to a digital value by an analog-to-digital converter (ADC). This operation takes about 1.2 μs. Accordingly, the total time required to complete one line process takes about 3 μs. In this sequential readout operation, the sensor speed, i.e., the TDI scan rate, is currently limited to about 300 kHz.

[0003] Texas Instruments' U.S. Patent Application Publication No. 4,309,624A relates to a "Floating gate amplifier method of operation for noise minimization in charge-coupled devices." It describes a method for minimizing noise on a floating gate by operating a charge-coupled device (CCD) having a non-destructive readout floating gate amplifier. [Overview of the Initiative]

[0004] According to one embodiment, a method and apparatus (e.g., circuit) for high-speed TDI stages-based parallel readout operation is provided. Multiple (N) output registers are reset and globally precharged in parallel, ready to receive charges transferred from the same number (N) TDI pixel registers. Each signal charge in each output register is converted in parallel to a signal voltage. Each analog signal voltage is then converted in parallel to a digital value by each of the (N) ADCs. The N output registers are linked to receive charges from the beginning to the end of the registers. The AD conversion is also performed in parallel while the next (N) TDI registers are processed. The conversion of each signal voltage is performed in a ping-pong fashion by an S / H capacitor array circuitry using its respective CDS voltage.

[0005] One embodiment provides a method that includes reading out a plurality of TDI pixel registers to receive the respective signal charges to a plurality of output registers, performing parallel conversion of the plurality of output registers by converting the respective signal charges in parallel to their respective signal voltages, and converting the respective signal voltages in parallel to their respective digital values.

[0006] In one embodiment, the method includes resetting a plurality of output registers in parallel and receiving their respective signal charges. Resetting a plurality of output registers in parallel includes emptying the output registers in parallel via reset gates to zero reset drain voltage.

[0007] In one embodiment, output registers are linked one after the other from beginning to end, and performing a read involves transferring each signal charge to be received at the beginning for further transfers within the multiple output registers (e.g., to the end to fill the registers).

[0008] Performing a readout, in one embodiment, involves receiving the respective signal charge in each potential well beneath each floating gate, which in turn contains each output register. In one embodiment, the channel potential of the potential well is set by a reference voltage via a precharge gate. In one embodiment, each of the floating gates is coupled to its respective SF to provide its respective signal voltage for conversion to its respective digital value.

[0009] In one embodiment, converting each signal voltage involves the following operations of an S / H capacitor array circuit in a ping-pong manner: sampling each reference voltage at the current time in parallel to each first reference capacitor of each S / H capacitor array; sampling each earlier-time signal voltage in parallel to each signal capacitor; and providing each CDS voltage from each earlier-time reference voltage sampled by each second reference capacitor and each earlier-time signal voltage sampled by the signal capacitor in parallel to each ADC to generate each earlier-time digital value. In one embodiment, the method further includes receiving each reference voltage at the next time to each second reference capacitor and the current signal voltage to each signal capacitor in parallel, and providing each CDS voltage from each current reference voltage sampled by each first reference capacitor and each current signal voltage sampled by the signal capacitor in parallel to each ADC to generate each current digital value.

[0010] In one embodiment, the conversion of each signal voltage into its respective digital value in parallel is performed at the present time, and further, in parallel with the subsequent readout of each of the multiple signal charges into multiple output registers.

[0011] In one embodiment, the reading of multiple TDI registers for receiving each signal charge is performed at the present time, and further, in parallel with the conversion from the earlier-time signal voltage to the earlier-time digital value.

[0012] In one embodiment, a high-speed CMOS TDI image sensor comprises a plurality of CCD pixels (e.g., a pixel array having a plurality of rows and columns) arranged in a matrix, and includes a TDI pixel register and an output register coupled thereto. A column slice comprises a plurality of TDI pixel registers from the column and a plurality of output registers from the column. In one embodiment, the column slice further comprises an S / H capacitor array circuit coupled to the plurality of output registers, and a column-parallel ADC coupled to the S / H capacitor array circuit for parallel operation.

[0013] In one embodiment, the pixel array may have multiple output registers at both ends of the TDI pixel register for bidirectional scanning operation. Each output register at each end (e.g., the upper (first) output register and the lower (second) output register) may be connected to the respective S / H capacitor arrays and column-parallel ADCs at both ends of the pixel array, or each output register at each end may be multiplexed to the S / H array and column-parallel ADC located at one end of the pixel array (e.g., the lower end). In one embodiment, the method is performed using one of the upper output register and the lower output register as multiple output registers in response to the reverse and forward directions of TDI scanning, respectively.

[0014] A device is provided comprising multiple output registers coupled to receive signal charges read from each of multiple TDI registers, each of which is configured to include circuits providing parallel reset functionality, parallel charge sensing functionality, and charge transfer functionality, and each of the multiple output registers is coupled to a column-parallel ADC to generate a respective digital value for each of the respective signal charges.

[0015] In one embodiment, each output register is coupled to the ADC via its respective S / H capacitor for CDS operation.

[0016] In one embodiment, a parallel charge sensing function for each of the multiple output registers converts the respective signal charge accumulated in the group of potential wells into the respective signal voltages for the parallel ADCs.

[0017] In one embodiment, the device is configured to read each signal charge into an output register at the next time point while the parallel ADC converts each signal charge from the current time point.

[0018] In one embodiment, each output register is coupled to a parallel ADC via its respective S / H capacitor array, each array comprising two reference capacitors and a signal capacitor for ping-pong S / H operation.

[0019] In one embodiment, each S / H capacitor array operates collectively as follows: In one embodiment, each reference voltage is sampled in parallel with the first reference capacitor of each S / H capacitor array at the current time, and the earlier in time signal voltage is sampled in parallel with each signal capacitor. The CDS voltages from the earlier in time reference voltages sampled by each second reference capacitor and the earlier in time signal voltages sampled by the signal capacitors are then supplied in parallel to each ADC to generate the earlier in time digital value.

[0020] In one embodiment, the device includes a CMOS TDI image sensor, in which a plurality of CCD pixels are arranged in a matrix, and a plurality of TDI pixel registers are provided, in which the column slices are coupled to a plurality of output registers.

[0021] In one embodiment, the apparatus includes a CMOS TDI image sensor in which a plurality of CCD pixels are arranged in a matrix form, and its column slices are coupled to a first output register at a first end of a plurality of TDI pixel registers and to a second output register at a second end of the plurality of TDI pixel registers. The apparatus includes a plurality of TDI pixel registers, and a plurality of S / H capacitor array circuits and a plurality of column parallel ADCs are coupled to the first and second output registers for bidirectional operation (e.g., the first or second output register is selective according to the scanning direction). In one embodiment, each instance of the plurality of S / H capacitor array circuits and the plurality of column parallel ADCs is coupled to the first and second output registers. In one embodiment, a single instance of the plurality of S / H capacitor array circuits and the plurality of column parallel ADCs is coupled to the first and second output registers for shared use, such as by multiplexing.

[0022] In one embodiment, an apparatus (e.g., a CMOS TDI image sensor) is provided that includes a circuit configured to execute a method according to any of the method aspects described above.

[0023] These and other aspects will be apparent to those skilled in the art.

Brief Description of the Drawings

[0024] [Figure 1] It is a block diagram showing a column slice of a high-speed charge-coupled CMOS TDI imager pixel matrix. [Figure 2] It is a block diagram of an output register in one embodiment having a floating gate configuration. [Figure 3] It is a block diagram showing the global reset function of the floating gate of FIG. 2 in one embodiment. [Figure 4] It is a block diagram showing an embodiment of an S / H capacitor circuit and a column parallel ADC that provide a parallel conversion function. [Figure 5] It is a block diagram showing the operation timing in one embodiment. [Figure 6]A and B are block diagrams showing column slices of a high-speed charge-coupled CMOS TDI imager pixel matrix configured for bidirectional operation according to respective embodiments.

[0025]

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[0027]

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[0029]

Mode for Carrying Out the Invention

[0030] FIG. 1 shows a block diagram of a (partial) high-speed charge-coupled CMOS TDI imager pixel array 100 in one embodiment. The pixel array 100 is partial in that its column slice 102 is shown, and the pixel array 100 may include additional columns. The column slice 102 includes a plurality (M) of TDI (pixel) registers 104 (e.g., pixel registers) including individual TDI (pixel) registers (e.g., 1041, 1042,... 104N,... and 104M), a plurality of N TDI registers 106 includes a subset of the TDI registers 1041, 1042,... and 104N, where N is less than or equal to M, and a plurality of N output registers 108 includes output registers (e.g., 1081, 1082,... and 108N).

[0031] Multiple M TDI registers 104 are coupled to multiple N output registers 108 that receive signal charges from multiple N TDI registers 106. Each output register 108 has a global signal reset functionality 300 and N parallel conversion functionality 400, as described later in Figures 3 and 4. To place all reset, charge transfer, and charge sensing functions in one location, the output registers 108 support nondestructive readout with reset functionality. The individual output registers are linked one after the other from beginning to end, and when a readout is performed, the respective signal charges are transferred so that they are received at the beginning (for example, to the end to fill the registers) for further transfer within the multiple output registers.

[0032] According to one embodiment, in contrast to the conventional read operation described above, high-speed parallel operation based on multiple TDI stages is achieved as follows.

[0033] Multiple (N) output registers 108 are reset globally and in parallel (for example, via function 300 according to one embodiment) and are ready to receive charges transferred from multiple (N) TDI pixel registers 106.

[0034] Charges accumulated in multiple (N) TDI registers 106 (for example, out of a total of multiple (M) TDI registers 104) are transferred along the linked N output registers 108, from the beginning to the end of the N output registers 108.

[0035] Each of the signal charges in each of the N output registers 108 is converted in parallel to a signal voltage (for example, via function 400 according to one embodiment).

[0036] Furthermore, via function 400, each of the analog signal voltages is converted to a digital value in parallel by each of the N ADCs. According to one embodiment, the A / D conversion is also performed in parallel while the next signal charge from each of the N TDI registers is processed. Each of the output registers is coupled to a parallel ADC via its respective S / H capacitor array for CDS operation. Each S / H capacitor array comprises two reference capacitors and a signal capacitor for ping-pong type S / H operation.

[0037] In each embodiment, in order to incorporate all functions, a floating gate (FG) configuration 200 for the output register and a global reset function 300 are provided, as shown in Figures 2 and 3, respectively.

[0038] In one embodiment, each output register 1081, 1082, ... 108N-1, and 108N is shown to contain each group of three-phase (e.g., Φ1, Φ2, and Φ3) charge transfer gates (e.g., 2031, 2032, ..., 203N-1, and 203N, collectively 203) and their respective floating gates (e.g., 2021, 2022, ... 202N-1, and 202N). Each group is linked to the adjacent group one after the other, and when a read operation is performed, the respective signal charges from multiple (N) TDI registers 106 are transferred from the first 108N to the last 1081 of multiple (N) output registers 108.

[0039] Figure 2 shows the channel potential diagram and the corresponding charge transfer. Each of the floating gates 2021, 2022, ... 202N-1, and 202N (collectively, multiple (N) floating gates 202) is coupled to a reference voltage (Vref) 204 via its respective precharge (PRC) gate (e.g., 2061, 2062, ... 206N-1, and 206N). Each of the PRC gates 2061, 2062, ... 206N-1, and 202N is driven by PRC 206.

[0040] The drain voltage (VDD) 210 is coupled to each source follower (e.g., 2121, 2122, ... 212N-1, and 212N). Each of the source followers 2121, 2122, ... 212N-1, and 212N is coupled to each floating gate 2021, 2022, ... 202N-1, 202N, and Vref 204 (via their respective PRC gates 2061, 2062, ... 206N-1, and 202N). Although not shown in Figure 2, and shown in Figure 4, each of the source followers 2121, 2122, ..., 212N-1, and 212N is also coupled to their respective S / H capacitor array circuits (e.g., via 2141, 2142, ..., 214N-1, and 214N) for CDS operation via their respective selector (SEL) switches (e.g., 420N).

[0041] Figure 3 is a block diagram showing the global reset structure functionality 300 of the two floating gates 202N-1 and 202N of Figure 2 in one embodiment, where only two of the floating gates 202 are shown for brevity. The reset signal 302 is coupled to the reset gates 302N-1 and 302n between the reset drain (VDD) 210 and each of the floating gates 202N-1 and 202N. Each of the floating gates 202N-1 and 202n is also shown coupled to their respective source followers 212N-1 and 212N.

[0042] Figure 4 shows a portion of the n parallel conversion functions 400 with a typical nth floating gate 202N embodiment. Figure 4 shows details of one output register of the N output registers 108, i.e., output register 108N. The S / H capacitor array circuit 402n (within the dashed contour) and the comparator 404N of the nth parallel ADC are connected to the nth output register 108N, which has the floating gate 202N. For simplicity, the components within the S / H capacitor array circuit 402N are labeled without subscripts, but it will be understood that each array circuit has its own components for parallel operation. Each of the N arrays of S / H capacitor array circuits comprises two reference capacitors and a signal capacitor for ping-pong type S / H operation. N instances of the S / H capacitor array circuit perform the following operations: each first reference capacitor of each S / H capacitor array samples its current reference voltage in parallel; each earlier-in-time signal voltage samples its signal capacitor in parallel; and each second reference capacitor provides its CDS voltage from the earlier-in-time reference voltages sampled by each capacitor, along with the earlier-in-time signal voltages sampled by the signal capacitors, in parallel to its ADC to generate its earlier-in-time digital value (described later).

[0043] The operation in Figure 4 can also be understood by referring to Figure 5, which shows the operation timing 500 in one embodiment. Figure 5 shows processing periods 502 and 504 for processing the current N TDI rows and the next N TDI rows (for two consecutive read and AD conversions, each overlapping in time, performing the current read while converting the previous read). A single line period (i.e., TDI scan rate) of a processing period (e.g., 502) is shown at 506. Figure 5 also shows AD conversion windows 508 and 510 for the previous N TDI rows and the current N TDI rows.

[0044] The dashed vertical line 512 represents the time when Vref204 at the current time was sampled by the first reference capacitor Cref1 410. The dotted vertical line 514 represents the time when the signal voltage (Vsig) at the previous time was sampled by the signal capacitor Csig418, which was ready for CDS operation. The dotted line 516 indicates the time when the next Vref210 was sampled by Cref2 412. The dashed vertical line 518 represents the time when Vsig at the current time was sampled by Csig418 for CDS operation. The dashed arrow 522 from vertical line 512 to vertical line 518 represents the CDS interval at the current time, and AD conversion 510 is performed during the period of the next time. The dotted arrow 520 ending at 514 represents the CDS interval at the previous time, and AD conversion 508 is performed at this time. The dashed arrow 524, starting at 516, represents the CDS interval at the next time point, and the AD conversion takes place over a further subsequent time period (not shown).

[0045] Referring again to Figure 4, when both S / H switches (Sample-Hold Signal (SHS) switch 406 and Sample-Hold Reset (SHR) switch 408) are closed, Vref210 is sampled to Cref1 410 when the first S / H switch (SH1 switch 412) is closed and the second S / H switch (SH2 switch 414) is open.

[0046] Next, both the SHR switch 408 and the SH1 switch 412 are opened to hold Vref210 in Cref1 410. Simultaneously, the SH2 switch 414 is closed for CDS operation with Vsig sampled by Csig 418, and the signal charge has been transferred from the previous (i.e., previous processing period) read of the nth TDI register. Then, the SHS switch 406 is opened for the next cycle.

[0047] The AD conversion of the signal voltages to the previous N TDI registers (via each of the N S / H capacitor arrays and ADCs) takes place while the signal charges accumulated in the current N TDI registers 104 are transferred to the n output registers 108. This completes one cycle 502 of the operation timing 500 shown in Figure 5.

[0048] For the next cycle 504, when both the SHS switch 406 and the SHR switch 408 are closed again, the SH2 switch 414 is closed, and the SH1 switch 412 is opened, Vref210 is sampled into Cref2 416. Then, both the SHR switch 408 and the SH2 switch 414 are opened to hold Vref in Cref2. Simultaneously, the SH1 switch 412 is closed to sample the signal charge in Cref1 410 transferred from the current N TDI registers. After that, the SHS switch 406 is opened to hold the signal voltage in Csig 418.

[0049] The AD conversion of the signal voltages for the current N TDI registers takes place while the signal charges accumulated in the next N TDI registers are transferred to the N output registers.

[0050] The detailed operation according to the embodiments shown in Figures 1 to 5 is as follows: The previous signal charges accumulated under the (N) floating gates 202 of the (N) output registers 108 are emptied to VDD 210 via their respective RSTs (e.g., the Nth RST is 302N). This operation is performed globally in parallel, as shown in Figure 3.

[0051] The channel potential of the floating gate 202 is set by Vref 204 via each PRC gate (e.g., the nth such gate is 206N, which sets the potential wells 202N) and ready to receive signal charge from (N) TDI pixel registers 106 (the nth such register is 104N). Vref 204 is sampled and held in each of the S / H capacitor array circuits (e.g., the nth such S / H capacitor array circuit is 402N).

[0052] The signal charges accumulated in multiple (N) TDI registers 106 are transferred to the ends of multiple (N) floating gates 202 by the three-phase charge transfer gate 203 of the output register 108.

[0053] The signal charge accumulated under each floating gate is converted into a signal voltage and output in parallel via the SF. The signal voltage is also sampled in parallel into each of the S / H capacitors.

[0054] Next, each of the analog signal voltages is converted in parallel to a digital value by each of the n ADCs, the nth such ADC being 404N. The AD conversion is also performed in parallel (e.g., all at once or simultaneously), during which the next N (i.e., the next N of the multiple (N) signal charges at the next time point) in the TDI register 104 is transferred to the output register 108. That is, for the first multiple (N) of each signal charge transferred at the current time point (e.g., time point T0), after being converted to their respective current voltage signals (e.g., one at a time), the next signal charge of each of the second multiple (N) is read from the multiple (N) TDI registers 104 to the multiple (N) output registers 108 immediately after the current time point (e.g., time point T1), so that each of the first multiple (N) of signal charges transferred at the current time point (e.g., time point T0) is converted to their respective current voltage signals, and then each of the next N of the second multiple (N) signal charges is read from the multiple (N) TDI registers 104 to the multiple (N) output registers 108 immediately after the current time point (e.g., time point T1). Similarly, when each of the first multiple (N) signal charges is read out at the present time, each of the multiple (N) earlier signal charges read out at an earlier time point (e.g., time point T-1) immediately preceding time point T0 is converted to its respective previous voltage signal and then to its respective previous digital value.

[0055] Figures 6A and 6B are block diagrams showing high-speed charge-coupled CMOS TDI imagers 600A and 600B configured for bidirectional operation according to their respective embodiments. Bidirectional operation responds to the scanning direction (e.g., forward and reverse) performed by the CMOS TDI imager. In the first bidirectional embodiment, a CCD pixel array 601 marked by a dashed-dotted box is shown, comprising a plurality of TDI pixel registers 602 having a plurality of upper (first) output registers 604 coupled to each end thereof and a plurality of lower (second) output registers 606.

[0056] Each output register 604 and 606 is connected to each of the multiple S / H capacitor array circuits 608 and 610, which in turn are coupled to each of the multiple column-parallel ADCs 612 and 614.

[0057] Figure 6A shows a typical column slice 616 of the CMOS TDI imager 600A, marked with a dashed line. Column slice 616 comprises a column subset of the TDI pixel register 602, column subsets of output registers 604 and 606, column subsets of S / H capacitor array circuits 608 and 610, and column subsets of column-parallel ADCs 612 and 614. The column subset of the TDI pixel register 602 is equivalent to multiple M TDI pixel registers 104. The column subsets of output registers 604 and 606 are equivalent to multiple N output registers 108.

[0058] In the second bidirectional embodiment 600B, the respective output registers 604 and 606 at each end of the TDI pixel register 602 are multiplexed to the S / H capacitor array 608 and the column-parallel ADC 612 located at one end of the TDI pixel register 602.

[0059] Figures 6A and 6B are simplified and can be implemented using the structures shown in Figures 2-4 with appropriate adaptation.

[0060] In one embodiment, during the operation of Embodiment 600A or 600B, the method described herein is performed bidirectionally, using one or the other of the first and second output registers (as multiple output registers) when reading multiple TDI pixel registers into multiple output registers and performing parallel conversion of the multiple output registers. According to one embodiment, the selection of one or the other responds to the scanning direction (performed, for example, by the CMOS TDI imager 600A or 600B). In one embodiment (e.g., 600A), output register 604, S / H capacitor array circuit 608, and column-parallel ADC 612 are used in the forward scanning direction, and output register 606, S / H capacitor array circuit 610, and column-parallel ADC 614 are used in the reverse scanning direction. In one embodiment (e.g., 600B), output registers 604 and 606 are multiplexed to the S / H capacitor array circuit 610 and column-parallel ADC 612 for the forward and reverse scanning directions, respectively.

[0061] Practical implementations may include any or all of the features described herein. These and other embodiments, features and various combinations may be expressed as methods, apparatus, systems, means and other ways of combining the features described herein for performing a function. Several embodiments have been described. Nevertheless, it will be understood that various modifications can be made without departing from the spirit and scope of the processes and techniques described herein. In addition, other steps may be provided or steps may be excluded from the described processes, and other components may be added to or removed from the described systems. Thus, other embodiments are within the scope of the claims.

[0062] Throughout this specification and in the claims, the words “comprise,” “contain,” and their variations mean “including but not limited to,” and are not intended to exclude other components, integers, or steps. Throughout this specification, the singular form includes the plural form unless the context requires otherwise. In particular, where the indefinite article is used, it should be understood that both singular and plural are intended unless this specification requires otherwise.

[0063] Features, integers, characteristics, or groups described in relation to a particular aspect, embodiment, or example of the present invention should be understood to be applicable to any other aspect, embodiment, or example, unless they are incompatible therewith. All features disclosed herein (including any appended claims, abstract, and drawings) and / or all steps of any method or process so as disclosed may be combined in any combination, except for any combination in which at least some of such features and / or steps are mutually exclusive. The present invention is not limited to the details of any example or embodiment described herein. The present invention extends to any novel one or any novel combination of features disclosed herein (including the appended claims, abstract, and drawings), or any novel one or any novel combination of any steps of any method or process disclosed. <Other> <Means> The method of technical idea 1 performs parallel conversion of the multiple output registers by reading out multiple time-delayed and integrated (TDI) pixel registers to receive the respective signal charges to multiple output registers, converting the respective signal charges in parallel to their respective signal voltages, and converting the respective signal voltages in parallel to their respective digital values. The method of technical idea 2 includes, in the method described in technical idea 1, resetting the plurality of output registers in parallel and receiving the respective signal charges. The method of technical idea 3, in the method described in technical idea 2, includes resetting the plurality of output registers in parallel by setting the plurality of output registers to zero in parallel to the reset drain voltage via a reset gate. The method of technical idea 4 is a method of any of technical ideas 1 to 3, wherein the individual output registers of the plurality of output registers are linked one after the other from beginning to end, and performing a readout includes transferring the respective signal charge to be received at the beginning for further transfer within the plurality of output registers. The method of technical idea 5, in the method of any one of technical ideas 1 to 4, comprises performing a readout by receiving the respective signal charge in each potential well under each floating gate having the respective output register. The method of technical idea 6, in the method described in technical idea 5, wherein each of the floating gates is coupled to each of the source followers (SF) to provide each of the signal voltages for conversion to each of the digital values. The method of technical idea 7 is a method of any of technical ideas 1 to 6, in which the respective signal voltages are converted by the operation of using a ping-pong type sample-and-hold (S / H) capacitor array circuit, sampling each reference voltage in parallel at the present time to each first reference capacitor of each sample-and-hold (S / H) capacitor array, sampling the earlier signal voltage in time to each signal capacitor, and providing the respective correlated double sampling (CDS) voltages from the earlier reference voltages sampled by each second reference capacitor and the earlier signal voltages sampled by the signal capacitors in parallel to each column-parallel analog-to-digital converter (ADC) to generate the earlier digital value in time. The method of technical idea 8 further includes, in the method described in technical idea 7, receiving in parallel the respective reference voltages at the next time point to each of the second reference capacitors and the current signal voltage to each of the signal capacitors, and providing in parallel to each column-parallel ADC the respective CDS voltages from the respective current reference voltages sampled at each of the first reference capacitors and the respective current signal voltages sampled at the signal capacitors to each column-parallel ADC to generate the respective current digital values. The method of technical idea 9 is that, in the method of any of technical ideas 1 to 8, the conversion of each signal voltage in parallel to its respective digital value is performed at the present time, and further in parallel with the execution of the next time point readout of each of the multiple signal charges to the multiple output registers. The method of technical idea 10 is the method of any of technical ideas 1 to 9, wherein the reading of the plurality of TDI registers in order to receive the respective signal charges is performed in parallel with the conversion from the earlier-time signal voltage to the earlier-time digital value. The method of technical idea 11 is performed by a high-speed CMOS TDI image sensor having a plurality of CCD pixels arranged in a matrix, wherein the column slices thereof include the plurality of TDI pixel registers and the plurality of output registers, in the manner of any one of technical ideas 1 to 10. The method of technical idea 12 is the method of any of technical ideas 1 to 11, wherein a first output register is coupled to one end of the TDI pixel register, a second output register is coupled to the other end of the TDI pixel register, and in response to the scanning direction, one of the first output register and the second output register is used as the plurality of output registers. The device of technical idea 13 comprises a plurality of output registers coupled to receive the respective signal charges read from a plurality of TDI pixel registers, each of the plurality of output registers comprising a circuit that provides a parallel reset function, a parallel charge detection function and a charge transfer function, and each of the plurality of output registers coupled to a column-parallel ADC to generate a respective digital value for each of the respective signal charges. In the apparatus of technical concept 14, as described in technical concept 13, each of the output registers is coupled to the ADC via its respective S / H capacitor for CDS operation. The apparatus of technical idea 15, in the apparatus described in technical idea 13 or 14, wherein the parallel charge sensing function for each of the plurality of output registers converts the respective signal charge accumulated in the group of potential wells into the respective signal voltages for the column-parallel ADC. The apparatus of technical idea 16 is configured such that, in the apparatus described in any of technical ideas 13 to 15, the column-parallel ADC reads each signal charge into the output register at the next time point while it is converting each signal charge from the current time point. The apparatus of technical concept 17, in the apparatus of technical concept 16, wherein each of the output registers is coupled to the column-parallel ADC via its respective S / H capacitor array, and each of the arrays comprises two reference capacitors and a signal capacitor for ping-pong type S / H operation. The apparatus of technical concept 18 operates collectively in such a way that, in the apparatus described in technical concept 16, each S / H capacitor array samples its respective reference voltage in parallel with the respective first reference capacitor of each S / H capacitor array at the present time, samples the earlier-in-time signal voltage in parallel with each signal capacitor, and provides the respective CDS voltages from the earlier-in-time reference voltages sampled by the respective second reference capacitors and the earlier-in-time signal voltages sampled by the signal capacitors to each ADC in parallel to generate the earlier-in-time digital value. The apparatus of technical concept 19 operates collectively such that, in the apparatus described in technical concept 18, each S / H capacitor array further operates in parallel to receive, in the following time points, the respective reference voltages to the respective second reference capacitors and the current signal voltages to the respective signal capacitors, and provides, in parallel to the respective ADCs, the respective CDS voltages from the respective current reference voltages sampled by the respective first reference capacitors and the respective current signal voltages sampled by the signal capacitors, to the respective ADCs to generate the respective current digital values. The apparatus of technical concept 20 is an apparatus described in any of technical concepts 13 to 19, comprising a CMOS TDI image sensor, wherein a plurality of CCD pixels are arranged in a matrix, and the column slices thereof are coupled to a plurality of TDI pixel registers. The apparatus of technical concept 21 is an apparatus described in any of technical concepts 13 to 19, comprising a CMOS TDI image sensor, wherein a plurality of CCD pixels are arranged in a matrix, and the column slices thereof comprise a plurality of TDI pixel registers, each of which is coupled to i) a first output register at a first end of the plurality of TDI pixel registers and ii) a second output register at a second end of the plurality of TDI pixel registers for bidirectional operation, wherein one of the first output register and the second output register is selectively defined as the plurality of output registers depending on the scanning direction. The apparatus of technical idea 22 comprises a circuit configured to perform a method described in any of technical ideas 1 to 12.

Claims

1. In a configuration comprising a plurality of time delay and integral (TDI)-charge-coupled element (CCD) pixel registers arranged in a matrix, and the same number or fewer output registers corresponding to each column slice of the TDI-CCD pixel register, The charge accumulated across each column slice of the TDI-CCD pixel register is read sequentially by the corresponding output register. Each of the aforementioned output registers receives an analog charge, which is then converted into an analog signal voltage in parallel. A method characterized by performing a parallel conversion to the digital value based on the analog charge of the output register by converting each of the converted analog signal voltages into their respective digital values ​​in parallel.

2. The method according to claim 1, characterized in that a plurality of output registers are reset and the respective analog charges are received.

3. The method according to claim 2, characterized in that resetting the multiple output registers involves setting the reset drain voltage of the multiple output registers to zero in parallel via a reset gate.

4. The individual columns of the multiple columns of output registers are linked one after another from the beginning to the end. The method according to any one of 1 to 3, characterized in that performing the read transfers the charge of each analog to be received first for further transfers in a sequence of multiple output registers.

5. The method according to any one of 1 to 4, characterized in that performing the read operation involves receiving the charge of each analog in each potential well beneath each floating gate having each of the output registers.

6. The method according to claim 5, characterized in that each of the floating gates is coupled to its respective source follower (SF) to provide its respective analog signal voltage for conversion to its respective digital value.

7. The method according to any one of 1 to 6, characterized in that converting each analog signal voltage to the digital value is done by providing each correlated double sampling (CDS) voltage in parallel to a column-parallel analog-to-digital converter (ADC).

8. The method according to any one of 1 to 7, characterized in that, at the present time which is time 1, the conversion of the analog signal voltage to a digital value based on the analog charge read from each column slice of the TDI-CCD pixel register at the previous time which is a time prior to the present time, and the reading of the analog charge from each column slice of the TDI-CCD pixel register are performed in parallel.

9. The first column of output registers is coupled to one end of the column slice of the TDI-CCD pixel registers, The second column of output registers is coupled to the other end of the column slice of the TDI-CCD pixel registers. The method according to any one of 1 to 8, characterized in that, in response to the scanning direction, it is performed by using one of the first column of output registers and the second column of output registers as the column of output registers.

10. It consists of multiple time delay and integral (TDI)-charge-coupled element (CCD) pixel registers arranged in a matrix configuration, and the same number or fewer output registers corresponding to each column slice of the TDI-CCD pixel register, A device configured such that the charge accumulated across each column slice of the TDI-CCD pixel register is sequentially received by the corresponding output register, Each of the output registers is configured to include a circuit that provides a reset function, a parallel charge detection function that converts the analog charge into an analog signal voltage, and a charge transfer function. The apparatus is characterized in that each of the output registers is coupled to a column-parallel analog-to-digital converter (ADC) to generate in parallel digital values ​​based on the analog charge of the output registers.

11. The apparatus according to claim 10, characterized in that each column of the output register is coupled to the column-parallel ADC via its respective sample-and-hold (S / H) capacitor for correlated double sampling (CDS) operation.

12. The apparatus according to claim 10 or 11, characterized in that the parallel charge sensing function of each column of the output register converts the charge of each analog accumulated in the group of potential wells into a signal voltage of each analog for the column-parallel ADC.

13. The apparatus according to any one of claims 10 to 12, characterized in that, while the column-parallel ADC converts the charge of each analog from the present time, which is the time when it is 1, the charge of each analog is read out to the output register at the next time, which is a time later than the present time.

14. Each of the aforementioned S / H capacitor arrays At the current time, each reference voltage is sampled in parallel to the respective first reference capacitor of each of the S / H capacitor arrays. The analog signal voltages at the previous point in time, which is prior to the current point in time, are sampled in parallel to the respective signal capacitors. The apparatus according to claim 13, characterized in that it collectively operates to generate the respective digital values ​​at the previous time by providing each of the column-parallel ADCs with the respective CDS voltages based on the respective reference voltages at the previous time, which are sampled by each second reference capacitor, and the respective analog signal voltages at the previous time, which are sampled by the signal capacitor.

15. Each of the S / H capacitor arrays is Furthermore, in parallel, the respective reference voltages to each of the second reference capacitors and the current analog signal voltages to each of the signal capacitors are received at the next time point. The apparatus according to claim 14, characterized in that it operates collectively to generate the respective digital values ​​at the current time by providing each of the column-parallel ADCs with the respective CDS voltages based on the reference voltage at the current time, which are sampled by each of the first reference capacitors, and the respective analog signal voltages at the current time, which are sampled by the signal capacitors.

16. The column slice comprises i) a first output register coupled to a first end of the column of TDI-CCD pixel registers, and ii) a second output register coupled to a second end of the column of TDI-CCD pixel registers for bidirectional operation. The apparatus according to any one of claims 10 to 15, characterized in that one of the first row of output registers and the second row of output registers is selectively defined as the row of output registers depending on the scanning direction.

17. An apparatus comprising a circuit configured to perform the method described in any one of claims 1 to 9.

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