Single-photon avalanche diodes and sensor arrays

Abstract

The SPAD sensor may include an active region (102) having one or more active region contacts (102a), a deep isolation region (106a) along the outer periphery of the SPAD sensor, and a contact region (204) between the active region and the deep isolation region. The size of the contact region varies along the periphery of the SPAD device, and the contact region may include one or more contact region contacts (204a). The SPAD sensor may further include a buried well region (208) between the contact region and the active region. An array of SPAD sensors is also described herein.

Description

Technical Field

[0001] The present disclosure relates to single photon avalanche diode sensors and single photon avalanche diode sensor arrays, and more particularly, although not limited thereto, to 3D stacked back-illuminated single photon avalanche diode sensors.

Background Art

[0002] The present disclosure generally provides single photon avalanche diode (SPAD) sensors with improved photon detection efficiency (PDE) and fill factor, and / or achieves a reduction in the number of required metal layers in a 3D stacked SPAD wafer.

[0003] In particular, the present disclosure generally relates to 3D stacked SPAD sensors having back-illumination (BSI) and full deep trench isolation (DTI), and / or arrays of such SPAD sensors.

[0004] Several attempts have been made to improve the PDE of SPAD devices, including the use of microlenses, charge collection type / electrical microlenses, contact area sharing, optimization of depletion layer width, use of metal mirrors, and inverse pyramid surface structures. However, many of these techniques require additional components and / or layers in the SPAD structure, complicating the device manufacturing process. Therefore, there is a need for improved SPAD devices with an improved PDE.

[0005] Therefore, an object of the present disclosure is to provide an SPAD device having an improved PDE and fill factor, and further to provide an improved SPAD array having an improved metallization layer configuration.

Summary of the Invention

[0006] Generally, aspects of the present disclosure may provide an SPAD device and / or an SPAD array that addresses the above problems.

[0007] According to one aspect of this disclosure, a single-photon avalanche diode (SPAD) sensor, An active region having one or more active region contacts, A deep (trench) isolation region along the outer circumference of the SPAD sensor, A contact region between an active region and a deep (trench) isolation region, wherein the contact region comprises one or more contact region contacts, The embedded well region between the contact region and the active region, Equipped with, The size of the contact area changes along the periphery of the SPAD device. A single-photon avalanche diode (SPAD) sensor is provided.

[0008] Deep (trench) isolation regions may be provided around the entire periphery of the SPAD device such that the isolation region surrounds the active region from the lateral direction. The terms lateral and longitudinal are used herein to refer to relative directions. In particular, longitudinal is generally used with respect to the stacking of SPAD sensors (e.g., the z-direction in Figure 1), while lateral is used with respect to any direction perpendicular to the longitudinal direction (e.g., the x-direction and y-direction in Figure 1). Thus, the phrase "surrounded from the lateral direction" can be interpreted as meaning that a feature is completely surrounded by another feature in at least the x-direction and y-direction. The active region may generally comprise a doped layer of the SPAD sensor that promotes avalanche multiplication and may also be called the avalanche multiplication region. The active area may generally refer to the area of ​​the active region where avalanche multiplication occurs, as viewed from a top view of the SPAD sensor.

[0009] The variable size of the contact area (also called the anode ring and / or cathode ring) in SPAD devices facilitates an increase in the size of the active area compared to devices with a contact area having uniform dimensions across the periphery of the device. The improved curve factor leads to an improvement in PDE. For example, a SPAD with a 12.5 μm pitch can result in a PDE increase of approximately 20% or more. For SPADs with smaller pitches, even greater relative improvements can be achieved. The curve factor will be understood as the ratio of the active area of ​​the SPAD device (e.g., shown by a dashed line across the edge of the active area 102 in Figure 1) to the total area of ​​the SPAD device. In other words, for a square SPAD device (e.g., the length of each side of the periphery is equal to the pitch), the curve factor can be calculated by the following formula.

number

[0010] Providing a deep trench isolation region surrounding the SPAD device (for example, forming the outer perimeter of the SPAD structure) can facilitate the isolation of the SPAD device. Therefore, when multiple SPAD sensors are formed in an array, the deep trench isolation region can further reduce crosstalk between adjacent devices. In such an array, adjacent devices may share a single deep trench isolation region. The deep trench isolation region can be filled or partially filled with a dielectric or metal.

[0011] Therefore, the SPAD sensors according to this disclosure may be combined with other SPAD sensors to form an array. It will be understood that some or all of the other SPAD sensors in such an array may be SPAD sensors according to this disclosure. However, this is not a requirement, and in such an array, the SPAD sensors of this disclosure may be combined with one or more other SPAD sensors that do not form part of the scope of this disclosure. Thus, in implementation form, an array of SPAD sensors comprising one or more SPAD sensors according to this disclosure is provided.

[0012] In some implementations, the SPAD device may further include a shallow trench isolation region along the outer periphery of the SPAD sensor. Similar to the deep trench isolation region, the shallow trench isolation region may surround the active region laterally. The shallow trench isolation region may be located vertically above at least a portion of the deep trench isolation region, and may, for example, be in contact with the deep trench isolation region.

[0013] In the implementation configuration, the SPAD sensor may be a back-illuminated SPAD sensor and / or may form part of a stacked 3D CMOS wafer.

[0014] In general, SPAD devices may be provided in any shape. However, in a given implementation, a SPAD device may comprise multiple corner regions and multiple edge regions extending between the corner regions. For example, a square SPAD device may comprise four corner regions and four edge regions extending between the corner regions. In such an implementation, the lateral size or width of the contact region may be greater than the lateral size of the contact region along the edge region in one or more of the corner regions.

[0015] The differentiated sizing of contact areas within the corner(s) and edge(s) regions(s) of the SPAD device facilitates a further proportional increase in the size of the active area, thereby improving the device's PDE. Various structures fall within the scope of this implementation. For example, contact areas may be located within only one or more corner regions, within some or all of the corner regions, or within only one of the corner regions. Similarly, contact area contacts may be located within only one or more corner regions.

[0016] In a further example, the contact region may include a doped region (for contact with the contact region contact) and a well region, the doped region being located above the well region. The well region may be located only within one or more corner regions, while the doped region may extend along one or more edge regions.

[0017] In some implementations, the active region may comprise a cathode region or an electrode, and the contact region may comprise an anode region or an electrode (e.g., an anode ring). In other implementations, the active region comprises an anode region or an electrode, and the contact region comprises a cathode region or an electrode (e.g., a cathode ring). Therefore, the active region contact and the contact region contact may each be provided as an anode contact or a cathode contact.

[0018] Therefore, the metal contact layer connected to the active region contact and the contact region contact may be used as an anode metal connector or a cathode metal connector, depending on the mounting configuration.

[0019] A further aspect of the present disclosure provides a SPAD array comprising a plurality of SPAD sensors, each SPAD sensor having one or more anode contacts and one or more cathode contacts, wherein each anode contact is connected to one or more anode metal connectors, and each cathode contact is connected to one or more cathode metal connectors. One or more anode metal connectors and one or more cathode metal connectors are each formed within the same metal layer.

[0020] Optionally, the SPAD array according to this disclosure may include a central hybrid bonding region. The hybrid bonding region may include at least a portion of each of the anode metal connectors or at least a portion of each of the cathode metal connectors, each of the anode metal connectors or cathode metal connectors within the hybrid bonding region providing a hybrid bonding location.

[0021] At least one of the SPAD sensors in the SPAD array may be a SPAD sensor according to this disclosure.

[0022] Advantageously, in such arrays, it is sufficient to use a single metal layer level for both anode and cathode metal connectors, while still allowing routing of the metal layer to the central hybrid junction connection area. Thus, the present disclosure provides a SPAD array with improved metal layer utilization.

[0023] To facilitate this, the SPAD array may comprise one or more N×M SPAD sub-arrays, and the contact region contacts may be provided only along the outer periphery of the N×M SPAD sub-array. Here, N and M represent the number of SPAD sensors positioned in the vertical direction of the sub-array. For example, from the top view, a 2×3 SPAD sub-array has two SPAD sensors along the first side of the outer periphery of the sub-array and three SPAD sensors along the second side of the outer periphery of the sub-array, resulting in a rectangular sub-array with a total of six SPAD sensors. As described above, in an implementation form, the contact region contacts may form an anode contact or a cathode contact.

[0024] For example, the contact region contacts may be provided only within a corner region along the outer periphery of the N×M SPAD sub-array, or only within one of the corner regions along the outer periphery of the N×M SPAD sub-array. Additionally or alternatively, in an implementation form, the contact region contacts may be provided on one or more edge regions along the outer periphery of the N×M SPAD sub-array. For example, in an array of square SPAD sensors, the sensors of the N×M sub-array may have contact region contacts in any combination of one, two, and three corner regions and zero, one, and two edge regions of the SPAD device, provided that the corner regions and edge regions are along the outer periphery of the N×M array.

[0025] In an implementation form, at least one of n and m may be equal to 2, for example, such that the SPAD sub-array is a 2×M sub-array. In the case of an array of square SPAD sensors, the use of such a 2×M sub-array may assist in the arrangement of the sub-arrays such that all SPAD sensors have at least one edge or corner region along the outer periphery of the sub-array. Preferably, both N and M may be equal to 2 such that the N×M sub-array is a 2×2 sub-array.

[0026] Here, some embodiments of the present disclosure will be described by way of example only, with reference to the accompanying drawings.

Brief Description of the Drawings

[0027] [Figure 1A] Schematically shows a view from above an exemplary SPAD device. [Figure 1B] Schematically shows a cross-sectional view from the side of an exemplary SPAD device. [Figure 2A] Schematically shows a view from above a SPAD device according to one implementation form. [Figure 2B] Schematically shows a cross-sectional view from the side of a SPAD device according to one implementation form. [Figure 3A] Schematically shows a view from above a SPAD device according to a further implementation form. [Figure 3B] Schematically shows a cross-sectional view from the side of a SPAD device according to a further implementation form. [Figure 4A] Schematically shows a view from above a SPAD device according to a further implementation form. <� [Figure 4B] Schematically shows a cross-sectional view from the side of a SPAD device according to a further implementation form. [Figure 5] Schematically shows a view from above an exemplary SPAD array. [Figure 6] Schematically shows a view from above a SPAD array according to one implementation form. [Figure 7] Schematically shows a view from above a 3×3 SPAD array according to one implementation form. [Figure 8] Schematically shows a view from above a 3×2 SPAD array according to a further implementation form. [Figure 9] Schematically shows a 3D stacked wafer according to one implementation form. <�

Modes for Carrying Out the Invention

[0028] Next, aspects of the present invention will be described with reference to exemplary embodiments. Although all of the following exemplary embodiments share similar SPAD structures, it will be understood that these are merely exemplary structures and the present invention is not intended to be limited to the structures shown in the exemplary embodiments. For example, the doping shown in the examples may be reversed (e.g., an n-type region exchanged for a p-type region, and vice versa), and / or the SPAD junction configuration may differ based on the intended purpose of the device. The following examples generally describe concentrated or enhanced SPAD devices, but other known SPAD configurations, including but not limited to diffused guard ring and merged implant guard ring configurations, may also be implemented within the scope of the present invention.

[0029] Similarly, while the SPAD structures shown below are symmetrical (e.g., having the same pitch in each of the lateral (x and y) directions), it is also within the scope of this disclosure that SPAD structures may be asymmetrical (e.g., having different pitches in the lateral (x and y) directions). This also applies to the active region of the SPAD device, which may also be formed in shapes other than those shown, such as an octagon or a circle.

[0030] It will be further understood that the layers forming the anode and cathode regions (e.g., part of the active and contact regions) may differ from the example shown, and the number of contacts within the anode and cathode regions may also differ from those shown. For example, the active and contact regions may have any number of contact points, such as one, two, three, four, five, or more than nine, sixteen, twenty-five, etc., as desired. However, in some implementations, fewer contacts within the active region may be preferable because a larger number of active region contacts may reduce the efficiency of the back-illumination design.

[0031] An exemplary BSI-type SPAD device 100 is shown in Figure 1. Figure 1 includes Figure 1A, which schematically shows a top view, and Figure 1B, which schematically shows a cross section along line 1-1 in Figure 1A. The dashed arrows in both Figure 1B and subsequent figures represent the paths of incident light. It will be understood that incident light can enter the SPAD device 100 from any angle. The SPAD device 100 comprises an active region 102, a contact region 104, also commonly referred to as an anode or cathode ring, and an isolation region 106 comprising a deep trench isolation region 106a and a shallow trench isolation region 106b. An embedded well layer or region 108, also called a deep well, is formed within the contact region 104 and may comprise, for example, a depletion region below and around the active region 102. In some implementations, the embedded well layer may be doped only by background doping of the wafer, and the depletion region may extend to a lower doped layer or substrate layer, such as the p-well region 110. An isolation region 106 is provided around the outer periphery of the SPAD device 100, thereby isolating the SPAD device 100 from other SPAD devices forming, for example, an array of SPAD devices. This isolation can reduce crosstalk between adjacent devices and / or the dark count rate of the SPAD device 100. The SPAD device 100 may share the isolation region 106 with adjacent SPAD devices. The pitch of the SPAD devices represents the repeating distance of the array of SPAD devices. For example, in an array of SPAD devices, the pitch may be the distance from the center of one SPAD device to the center of an adjacent SPAD device. Alternatively, the pitch of the SPAD devices in such an array may be, for example, the distance between the centers of the isolation regions 106 on both sides of the device.

[0032] In this example, the active region 102 comprises an n+-doped cathode region 102b and a cathode contact 102a. A doped p-well region 102c is located below the cathode region 102b, and avalanche yielding occurs near the boundary of these regions. The contact region 104 forms an anode ring by an anode contact 104a. The contact region 104 includes a p+-doped region 104b and a doped p-well region 104c. A further doped p-well region 110 forms the bottom layer or substrate of the device within the isolation region 106.

[0033] This exemplary implementation includes an anode ring, but it will be understood that the contact region 104 may instead form a cathode ring. Similarly, the active region 102 may include a cathode region or an anode region. Thus, contacts 102a and 104a may more generally be referred to as active region contacts 102a and contact region contacts 104a, and the cathode region 102b may be referred to as the active region contact region or the second contact region. This applies equally to all further implementations disclosed herein.

[0034] In the SPAD device 100, the contact region 104 has uniform dimensions around the entire circumference of the device. In other words, the widths of the p+-doped region 104b and the p-well region 104c remain substantially constant throughout the device, so that the anode contact 104a can be provided around the entire contact region 104.

[0035] As briefly explained above, Figure 1 shows a known BSI-type SPAD 100 having a deep trench isolation region 106a that laterally surrounds the active region 102. In the SPAD device 100 of Figure 1, the width of the contact region 104 is substantially uniform around the entire circumference of the device 100. This is because the width of the contact region 104 is limited by the need that it be sufficient to smooth the low ohmic contact region contact 104a across the entire outer circumference of the device 100, and because the minimum distance between the active region 102 and the contact region 104 is determined by the required lateral breakdown voltage. This lateral breakdown voltage needs to be higher than the vertical breakdown voltage for a good SPAD with a low dark count rate and depends on the distance between the n+ region and the p+ regions 102b and 104b.

[0036] Figure 2 shows an exemplary BSI-type SPAD200. Figure 2 includes Figure 2A, which schematically shows a top view, and Figure 2B, which schematically shows a cross-section along line 2-2 in Figure 2A. The SPAD device 200 shares a similar structure to the SPAD device 100, and corresponding features are given the same reference numbers.

[0037] In contrast to the SPAD device 100, the contact region 204 of the SPAD device 200 has non-uniform dimensions along the periphery of the device 200. In particular, the widths of the p+-doped region 204b and the p-well region 204c are substantially larger at the corners of the device 200 than along the edges of the device 200. In this exemplary implementation, the contact region 204 will be understood to be an anode ring. However, in alternative implementations, the contact region 204 may be a cathode ring with an n+-doped region and an n-well region instead of the p+-doped region 204b and the p-well region 204c, respectively. This applies equally to all the exemplary implementations below. Therefore, as shown in Figure 2, the width of the contact region 204 along the edge region may not be sufficient to smooth low-ohmic contact along the edge of the device, so the contact region 204 may have a contact region (e.g., anode) contact 204a only in the corner region. However, it will be understood that the SPAD device 200 does not need to be symmetrical, and one, two, or three edge regions may include contact regions 204 sufficient to facilitate such contact along these edges.

[0038] By reducing the size of the contact area 204 in the peripheral region of the SPAD device 200, it becomes easier to increase the relative size of the active area of ​​device 200 compared to device 100. As a result, the improved curve factor of the SPAD device 200 leads to an improvement in PDE.

[0039] Advantageously, since the contact region 204 surrounds the active region laterally, it is not essential that the isolation region 106 be provided within the device 200; however, it is still preferable that such an isolation region 106, particularly a deep trench isolation region 106a, be provided to help isolate the SPAD device 200 from any adjacent SPAD devices. For example, in some implementations, the inclusion of a deep trench isolation region 106a can reduce crosstalk between adjacent devices from about 10% of the measured signal to about 2.5% or less of the measured signal. The deep trench isolation region 106a may be filled or partially filled with dielectric material and / or metal. Optionally, and as described above, the isolation region 106 may further comprise a shallow trench isolation region 106b above the deep trench isolation region 106a.

[0040] Figure 3 shows a further example of the BSI type SPAD300. Figure 3 includes Figure 3A, which schematically shows a top view, and Figure 3B, which schematically shows a cross-section along line 3-3 in Figure 3A. The SPAD device 300 also shares a similar structure to the SPAD device 100, and the corresponding features are given the same reference numbers.

[0041] In the SPAD device 300, the contact region 304, which comprises a p+-doped region 304b and a p-well region 304c, is formed only in the corner regions of the device 300, such that the contact region 304 does not completely surround the active region 102 from the lateral direction. Thus, the contact region 304 may have contact region (e.g., anode) contacts 304a only within the corner regions. However, it will be understood that the SPAD device 300 does not need to be symmetrical, and one or more corners of the SPAD device 300 may not have contact regions 304, such that contact regions (and therefore contact region contacts 304a) are provided only at one, two, or three corners of the device. Similarly, some of the edge regions, such as one, two, or three of the edge regions, may have contact regions 304. The contact regions 304 in these edge regions may be sufficient to facilitate contact along these edges, or they may be provided to help isolate the device without facilitating the use of additional contacts.

[0042] Removing contact areas 304 in part or all of the edge region of the SPAD device 300 facilitates a further increase in the size of the active area of ​​device 300 compared to devices 100 and / or 200. As a result, the improved curve factor of the SPAD device 300 leads to a further improvement in PDE. However, in this implementation, it is particularly preferable to provide isolation areas 106 (at least deep trench isolation areas 106a and optionally shallow trench isolation areas 106b, etc.) around the periphery of device 300 to reduce crosstalk with any adjacent devices and facilitate electrical isolation between them.

[0043] Figure 4 shows a further example of the BSI type SPAD400. Figure 4 includes Figure 4A, which schematically shows a top view, and Figure 4B, which schematically shows a cross-section along line 4-4 in Figure 4A. The SPAD device 400 also shares a similar structure to the SPAD device 100, and the corresponding features are given the same reference numbers.

[0044] In the SPAD device 400, the contact region 404 comprises a p+-doped region 404b and a p-well region 404c. The p+-doped region 404b forms a complete ring surrounding the active region 102 from the side, while the p-well region 404c is located only within the corner region of the device 400. The SPAD device 400 does not need to be symmetrical, and it will also be understood that one, two, or three of the edge regions may have contact regions 404 comprising both the p+-doped region 404b and the p-well region 404c.

[0045] Advantageously, the structure of the contact region 404 in the SPAD device 400 facilitates an increase in the size of the active area of ​​device 400 compared to, for example, devices 100 and 200, and also improves the isolation of the SPAD device 400 compared to device 300. As a result, the structure shown in Figure 4 can provide a balance between an improved curve factor (and thus an improved PDE) and a reduced dark count rate and / or crosstalk between adjacent devices.

[0046] As stated above, the examples described herein are not intended to limit the scope of the invention, and alternative devices not shown are considered to be within the scope of the invention. For example, the doping shown in the example may be reversed so that the contact regions 204, 304, and 404 form a cathode ring instead of an anode ring (e.g., an n-type region swapped with a p-type region, and vice versa). Similarly, devices 200, 300, and 400 may be formed in other shapes, such as octagons or circles. Furthermore, it will be understood that features from the exemplary SPAD sensors may be combined as needed. For example, a single device may comprise a first edge region having a contact region as shown in Figure 2, a second edge region edge having a contact region as shown in Figure 3, and a third edge region edge having a contact region as shown in Figure 4. Any other combination is also contemplated within the scope of this disclosure.

[0047] In particular, each exemplary device may have contact area contacts 204a, 304a, 404a in some, but not all, of the corner areas, such as one, two, or three corner areas. Similarly, each exemplary device may have contact area contacts 204a, 304a, 404a in some, but not all, of the edge areas, such as one, two, or three edge areas.

[0048] An exemplary SPAD array 500 is shown in Figure 5. The SPAD array 500 may comprise a 4x4 array of SPAD devices, such as the SPAD device 100 in Figure 1. Each SPAD device in array 500 has contact area contacts 502 electrically connected to a shared first metal layer 506 (shown by cross-diagonal hatching), while a second metal layer 508 (shown by vertical / horizontal hatching) is electrically connected to the first metal layer via vias 512 (shown here by dashed rectangles surrounding each of the active area contacts 504). Each metal connection or connector portion of the second metal layer 508 comprises a hybrid contact junction 510 (shown by left-diagonal hatching). Both the contact area contacts 502 and the active area contacts 504 are shown by right-diagonal hatching. The contact area contacts 502 are shown at the corners of each SPAD device, but more generally, they may be provided around the entire perimeter of each device, as shown in Figure 1. On the other hand, the active area contact 504 is located within the active area (i.e., approximately in the center) of each SPAD device.

[0049] Such 4x4 arrays may form a subset of a larger array (e.g., 320x240). The 4x4 arrays may be replicated to achieve the required total array size. In such arrays, all SPAD cathodes must be connected to a quench circuit that forms part of the complementary metal-oxide-semiconductor (CMOS) circuitry on a 3d stacked CMOS wafer. The CMOS core voltage of advanced CMOS nodes is typically low (e.g., about 0.9V), and therefore, the quench circuit uses IO transistors capable of withstanding higher voltages (e.g., about 3.3V) to allow for higher over-bias voltages (e.g., about 3.0V). Consequently, a large gap is typically required between the CMOS core and the quench circuit IO transistors due to the different voltage domains.

[0050] Therefore, it is beneficial for quench circuits for some SPADs within the SPAD array to be located in close proximity or adjacent to one another. These clusters of SPADs may also share CMOS circuits such as time-to-digital converters (TDCs) and histogram memory. Thus, the SPAD array 500 in Figure 5 provides hybrid junction locations for all 16 SPADs of the 4x4 array within a local area. To achieve this, the first metal layer 506 and the second metal layer 508 must overlap and therefore be provided as separate layers within the 3D stacked SPAD wafer of the SPAD array 500.

[0051] In contrast, if the hybrid junction is located within the SPAD pitch of each SPAD device, the use of one or more metallization layers on the CMOS wafer may be limited. This can significantly restrict the CMOS wafer.

[0052] In some cases, it is desirable to combine SPAD devices to form an array comprising multiple SPAD devices. One such exemplary 4x4 SPAD array 500 is shown in Figure 5. As described above, the SPAD array 500 comprises a superimposed first metal layer 506 and a second metal layer 508, which are therefore provided as separate layers within the 3D stacked SPAD wafer of the SPAD array 500.

[0053] Figure 6 shows a top view of a 4×4 SPAD array 600. The SPAD array 600 may comprise one or more SPAD devices, such as those shown in Figures 2, 3, and 4, or any other suitable SPAD devices. Similar to array 500, the 4×4 array 600 may form a subset of a larger array (e.g., 320×240), and the 4×4 array 600 may be replicated to achieve the required total array size. The color coding in Figure 6 is the same as the color coding in Figure 5, with right diagonal hatching, cross diagonal hatching, and left diagonal hatching representing the anode / cathode contacts 602, the first metal layer 604, and the hybrid junction area 606, respectively.

[0054] In the SPAD array 600, each SPAD device comprises an active region contact 602a connected to an active region metal connector (also called a hybrid bonded metal connector) 604a, and a contact region contact 602b connected to a contact region metal connector 604b. The active region metal connector 604a and the contact region metal connector 604b may also be called an anode metal connector and a cathode metal connector. It will be understood that either region 604a or 604b may form an anode connector or a cathode connector depending on the configuration of the SPAD device (e.g., doping of layers).

[0055] In array 600, each SPAD device is provided with a contact area contact 602b in only a single corner region. In this way, the contact area metal connector 604b does not need to be provided around the periphery of all SPAD devices in array 600, and it is sufficient to use a single metal layer level for both the hybrid bonding metal connector 604a and the contact area metal connector 604b, while still allowing routing of the hybrid bonding metal connector 604a to the central hybrid bonding connection area with the hybrid bonding portion 606. Thus, array 600 provides a 3D stacked SPAD wafer structure with improved utilization of the metal layer.

[0056] It will be understood that the structure of Array 600 is not limited to use with SPAD devices having contact region contacts only within a single corner region, but may also be used with SPAD devices having contact region contacts within two, three, or four corner regions of the SPAD device. Similarly, such array structures may also be implemented with SPAD devices having contact region contacts along one, two, or three edge regions of the SPAD device, or along any combination of one, two, three, and four corner regions and zero, one, two, and three edge regions.

[0057] In implementations, a SPAD array may comprise multiple N×M subarrays, where N and M are integers. For example, the 4×4 array 600 shown in Figure 6 comprises multiple exemplary 2×2 subarrays 608, where N represents the number of SPAD sensors in the first (e.g., y) direction and M represents the number of SPAD sensors in the second (e.g., x) direction. N and M may be other integer values ​​and / or each may be a different integer value, and it will be understood that subarrays such as the 2×2 subarrays 608 may be used as independent 2×2 arrays. Similarly, a larger array that itself may comprise subarrays (such as the 4×4 array 600) may form subarrays of larger arrays. For example, as described above, the 4×4 array 600 may form a subset of a larger array, e.g., a 320×240 array, and the 4×4 array 600 may be replicated or combined with other suitable (sub)arrays to achieve the required total array size. Therefore, a subarray(s) can generally represent the smallest repeatable pattern(s) of SPAD sensors used to form a particular implementation of a SPAD array.

[0058] Further exemplary arrays are shown in Figures 7 and 8. Figure 7 shows a top view of an exemplary 3×3 SPAD array 700, and Figure 8 shows an exemplary 3×2 SPAD array 800. In both cases, features corresponding to those of array 600 are given similar reference numbers.

[0059] In both array 700 and array 800, the array structure allows for the use of a single metal layer 604 level for both the hybrid bond metal connector 604a and the contact area metal connector 604b, while still allowing the routing of the hybrid bond metal connector 604a to the central hybrid bond connection area with the hybrid bond portion 606. Thus, like array 600, arrays 700 and 800 provide a 3D stacked SPAD wafer structure with improved utilization of the metal layer.

[0060] In some implementations, the contact area contacts 602b may be provided only along the outer periphery of the array and / or along the outer periphery of the N×M subarray. For example, in Figure 6, the contact area contacts 602b are provided only along the outer periphery of the 2×2 subarray 608. Thus, the array and / or subarray may comprise any number of SPAD devices, but preferably the array (or subarrays forming a larger array) is an N×M array, where at least one of N and M is equal to 1 or 2, such that all SPAD sensors in the array include at least one corner or edge region along the outer periphery of the subarray.

[0061] More generally, it will be understood that SPAD subarrays or arrays can take any shape formed by SPAD sensors, including asymmetric shapes that cannot be described using the N×M grid format.

[0062] Figure 9 shows an exemplary 3D stacked CMOS wafer 900. The 3D stacked wafer 900 comprises a SPAD sensor 902 and a CMOS wafer layer 904 that forms part of the CMOS circuit. The SPAD sensor 902 and the CMOS circuit are connected by a hybrid bond 906 which includes a hybrid bond region or contact 906a, such as the hybrid bond region 606 shown in Figures 6 to 8. The 3D stacked CMOS wafer 900 further comprises an active region metal connector 910a and a contact region metal connector 910b formed from a single metal layer, which are connected to the SPAD sensor 902 by active region contacts and contact region contacts 908a and 908b, respectively.

[0063] Those skilled in the art will understand that, in the foregoing description and the attached claims, positional terms such as “above,” “alongside,” and “side” are made with reference to conceptual diagrams, such as those shown in the attached drawings. These terms are used for ease of reference and are not intended to be restrictive. Therefore, these terms should be understood to refer to the object when it is in the orientation shown in the attached drawings.

[0064] Although the present disclosure has been described above in terms of preferred embodiments, it should be understood that these embodiments are merely illustrative and the claims are not limited to these embodiments. Those skilled in the art will be able to take this disclosure into consideration and formulate modifications and alternatives that they believe will fall within the scope of the appended claims. Each feature disclosed or illustrated herein may be incorporated into any embodiment, either alone or in any suitable combination with any other feature disclosed or illustrated herein. [Explanation of Symbols]

[0065] 100 SPAD sensors 102 Active region 102a Active area contact 102b Cathode region 102c well area 104 Contact Area 104a Contact area Contact 104b Doped area 104c well area 106 Isolation Area 106a Deep trench isolation region 106b Shallow trench isolation area 108 Embedded well layer 110 well area 200 SPAD sensors 204 Contact area 204a Contact area Contact 204b Doped area 204c well area 300 SPAD Sensor 304 Contact Area 304a Contact area Contact 304b Doped area 304c well area 400 SPAD Sensor 404 Contact Area 404a Contact area Contact 404b Doped area 404c well area 500 SPAD arrays 502 Contact Area Contact 504 Active Area Contact 506 First metal layer 508 Second metal layer 510 Hybrid joint 600 SPAD arrays 602 Anode / Cathode Contact 602a Active area contact 602b Contact area Contact 604 Metal layer 604a Active Area Metal Connector 604b Metal connector with contact area 606 Hybrid joint 608 SPAD subarray 700 SPAD array 800 SPAD array 900 3D stacked wafers 902 SPAD sensor 904 CMOS wafer layer 906 Hybrid Bonding 906a Hybrid Bonding Contact 908a Active Area Contact 908b Contact area Contact 910a Active Area Metal Connector 910b Metal Contact Connector

Claims

1. A single-photon avalanche diode sensor (SPAD sensor), An active region having one or more active region contacts, A deep isolation region along the outer circumference of the SPAD sensor, A contact region between the active region and the deep isolation region, wherein the contact region comprises one or more contact region contacts, The embedded well region between the contact region and the active region, Equipped with, The size of the contact area changes along the periphery of the SPAD sensor. The SPAD sensor comprises a plurality of corner regions and a plurality of edge regions extending between the corner regions, wherein the size of the contact region is larger than the size of the contact region along the edge region in one or more of the corner regions. The contact region comprises a well region and a doped region above the well region, one or more contact regions electrically contact the doped region, the well region is located only in one or more corner regions of the corner region, and the doped region extends along the edge region. Single-photon avalanche diode sensor (SPAD sensor).

2. The SPAD sensor according to claim 1, wherein the SPAD sensor is a back-illuminated SPAD sensor.

3. The SPAD sensor according to claim 1 or 2, further comprising a shallow isolation region along the outer circumference of the SPAD sensor.

4. The SPAD sensor according to claim 3, wherein the shallow isolation region is located above the deep isolation region.

5. The SPAD sensor according to claim 1, wherein the contact area contact is located only in one or more corner areas of the corner area.

6. The SPAD sensor according to claim 1 or 2, wherein the active region comprises a cathode region and the contact region comprises an anode region.

7. The SPAD sensor according to claim 1 or 2, wherein the active region comprises an anode region and the contact region comprises a cathode region.

8. A plurality of SPAD sensors, each SPAD sensor comprising one or more anode contacts and one or more cathode contacts, wherein each of the one or more anode contacts is connected to one or more anode metal connectors, and each of the one or more cathode contacts is connected to one or more cathode metal connectors, A hybrid bonding region, wherein the hybrid bonding region includes at least a portion of each of the one or more anode metal connectors or at least a portion of each of the one or more cathode metal connectors, Equipped with, The one or more anode metal connectors and the one or more cathode metal connectors are each formed within the same metal layer. At least one of the aforementioned SPAD sensors is the SPAD sensor described in claim 1 or 2. SPAD array.

9. The SPAD array according to claim 8, wherein the deep isolation region is shared between adjacent SPAD sensors.

10. A three-dimensional stacked wafer comprising one or more SPAD sensors as described in claim 1 or 2.

11. The three-dimensional stacked wafer according to claim 10, wherein the three-dimensional stacked wafer is a three-dimensional stacked complementary metal-oxide-semiconductor (CMOS) wafer.

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