Non-volatile memory

Abstract

This nonvolatile storage device has a three-dimensional multilayer structure wherein a plurality of nonvolatile storage elements are arranged in series, and is provided with: a columnar semiconductor member that contains a metal oxide; a ferroelectric layer that contains hafnium oxide and surrounds the semiconductor member, while being in contact with the lateral surface of the semiconductor member; and a plurality of gate electrodes that face the lateral surface of the semiconductor member, with the ferroelectric layer being interposed therebetween, while being arranged in the longitudinal direction of the semiconductor member. Meanwhile, the semiconductor member continuously extends from the outer peripheral surface to the central axis.

Description

Technical Field

[0001] One embodiment of the present invention relates to a nonvolatile memory device. In particular, it relates to a nonvolatile memory device having a three-dimensional stacked structure in which a plurality of nonvolatile memory elements are arranged in series.

Background Art

[0002] In recent years, with the advancement of semiconductor systems, information communication has become necessary in various aspects of daily life. For the realization of the so-called IoT (Internet of Things), high-speed and high-capacity information communication is required between a computer (e.g., a server) and an Internet-connected device (also called an edge device). For this purpose, a nonvolatile memory as a high-speed and high-capacity storage memory is required for Internet-connected devices. Furthermore, with the miniaturization of Internet-connected devices, there is a strong demand for nonvolatile memories to have low power consumption.

[0003] Among the expanding demand for nonvolatile memories, the long-known ferroelectric memory has come into the spotlight again. For example, a ferroelectric memory using a hafnium oxide-based material has high compatibility with the CMOS process, a fast erase / program speed, and low-voltage operation with low power consumption. Therefore, recently, the development of FeFET (Ferroelectric Field Effect Transistor) using a hafnium oxide-based material as a gate insulating layer has been actively carried out (e.g., Non-Patent Document 1 and Non-Patent Document 2). Also, for further increasing the capacity of storage memories, memories with high density and low power consumption in which a plurality of FeFETs are integrated in a three-dimensional structure have been proposed (e.g., Non-Patent Document 3 and Non-Patent Document 4). In particular, the memory having a three-dimensional stacked structure described in Non-Patent Document 4 uses a hafnium oxide-based material as a gate insulating film and a semiconductor material containing a metal oxide (e.g., IGZO) as a channel layer, and thus has low power consumption and high reliability.

Prior Art Documents

Non-Patent Documents

[0004] [Non-licensed document 1] Min-Kyu Kim, Jang-Sik Lee, "Ferroelectric Analog Synaptic Transistors", [online], January 30, 2019, American Chemical Society, [February 13, 2019], インターネット<URL:https: / / pubs.acs.org / doi / abs / 10.1021 / acs.nanolett.9b00180>(2019) [Non-licensed document 2] Yuxing Li, Renrong Liang, Jiabin Wang, Ying Zhang, He Tian, ​​Houfang Liu, Songlin Li, Weiquan Mao, Yu Pang, Yutao Li, Yi Yang, Tian-Ling Ren, "A Ferroelectric Thin Film Transistor Based on Annealing-Free HfZrO Film", July 26, 2017, IEEE Journal of the Electron Devices Society, Volume 5, Pages: 378-383, (2017) [Non-licensed document 3] K. Florent, M. Pesic, A. Subirats, K. Banerjee, S. Lavizzari, A. Arreghini, L. Di Piazza, G. Potoms, F. Sebaai, SRC McMitchell, M. Popovici, G. Groeseneken, J. Van Houdt, "Vertical Ferroelectric HfO2 FET based on 3-D NAND Architecture: Towards Dense Low-Power Memory", 2018 IEEE International Electron Devices Meeting (IEDM), Page(s):2.5.1-2.5.4, (2018)

Non-licensed Document 4

[0005] As mentioned above, in recent years, three-dimensional stacked memory structures with low power consumption and high reliability are being realized by integrating ferroelectric memory at high density. However, the miniaturization of internet-connected devices is expected to continue rapidly. Therefore, there is a need to develop non-volatile memory that can operate with even lower power consumption without compromising reliability.

[0006] One of the objectives of the present invention is to provide a highly reliable non-volatile memory device. In particular, one of the objectives of the present invention is to provide a highly reliable non-volatile memory device with low power consumption. [Means for solving the problem]

[0007] A non-volatile memory device in one embodiment of the present invention is a non-volatile memory device having a three-dimensional stacked structure in which a plurality of non-volatile memory elements are arranged in series. The non-volatile memory device comprises a columnar semiconductor member containing a metal oxide, a ferroelectric layer containing hafnium oxide that is in contact with the side surface of the semiconductor member and surrounds the semiconductor member, and a plurality of gate electrodes that face the side surface of the semiconductor member via the ferroelectric layer and are arranged along the longitudinal direction of the semiconductor member, wherein the semiconductor member is a continuous member from the outer peripheral surface to the central axis. Here, "C facing B via A" is a relationship that must be satisfied by at least a part of A, at least a part of B, and at least a part of C, and is not limited to a relationship that must be satisfied by all of A, all of B, or all of C.

[0008] In the aforementioned non-volatile memory device, multiple non-volatile memory elements may share a semiconductor member. The diameter of the semiconductor member may be 20 nm or less. The metal oxide is preferably a first oxide composed of one or more metals selected from the group consisting of In, Ga, Zn, and Sn. For example, the metal oxide may be IGZO (metal oxide composed of indium, gallium, zinc, and oxygen), ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnO (Zinc Oxide), or InO (Indium Oxide). Alternatively, the metal oxide is preferably a second oxide composed of multiple metals selected from the group consisting of In, Al, and Zn. For example, it may be IAO (Indium Aluminum Oxide) or IAZO (Indium Aluminum Zinc Oxide). Furthermore, the metal oxide is preferably a third oxide consisting of In and element X (Si, Hf, Zr, Ti, Ta, W), or a metal oxide in which at least one element X is added to the first or second oxide.

[0009] The non-volatile memory device may further include a plurality of insulating layers provided between a plurality of gate electrodes.

[0010] In the non-volatile memory device, the width of each of the plurality of gate electrodes may be 1 μm or less.

[0011] In the non-volatile memory device, the thickness of the ferroelectric layer may be 5 nm or more and 20 nm or less. [Brief explanation of the drawing]

[0012] [Figure 1] This is a cross-sectional view showing the device structure of a non-volatile memory device according to one embodiment of the present invention. [Figure 2] This is a cross-sectional perspective view showing the device structure of a non-volatile memory device according to one embodiment of the present invention. [Figure 3]It is a perspective view showing the configuration of a semiconductor member and a gate insulating layer in the nonvolatile memory element shown in FIG. 2. [Figure 4] It is a diagram showing the simulation result of the Id-Vg characteristics in the nonvolatile memory element of one embodiment of the present invention. [Figure 5] It is a diagram plotting the width of the memory window and the channel length obtained from the Id-Vg characteristics of FIG. 4. [Figure 6] It is a diagram showing the relationship between the SS value and the drain current obtained from the Id-Vg characteristics of FIG. 4. [Figure 7] It is a diagram showing the distribution of polarization charges in the gate insulating layer in the nonvolatile memory element of one embodiment of the present invention. [Figure 8] It is a diagram showing the distribution of polarization charges in the gate insulating layer in the nonvolatile memory element of Comparative Example 1. [Figure 9] It is a diagram showing a simulation model of the electric field distribution inside the gate insulating layer in the nonvolatile memory element of one embodiment of the present invention. [Figure 10] It is a diagram showing the simulation result of the electric field distribution inside the gate insulating layer in the nonvolatile memory element of one embodiment of the present invention. [Figure 11] It is a diagram showing the simulation result of the Id-Vg characteristics in the nonvolatile memory element of one embodiment of the present invention. [Figure 12] It is a diagram showing the relationship between the width of the memory window and the diameter of the channel obtained from the Id-Vg characteristics shown in FIG. 11. [Figure 13] It is a diagram showing the relationship between the SS value and the drain current obtained from the Id-Vg characteristics shown in FIG. 11. [Figure 14] It is a cross-sectional view showing the element structure of the nonvolatile memory element of Comparative Example 2. [Figure 15] It is a diagram showing the simulation result of the Id-Vg characteristics of the nonvolatile memory element of Comparative Example 2. [Figure 16] It is a diagram showing the relationship between the width of the memory window and the channel length obtained from the Id-Vg characteristics shown in FIG. 15. [Figure 17]It is a diagram showing the relationship between the SS value obtained from the Id-Vg characteristics shown in FIG. 15 and the drain current. [Figure 18] It is a diagram comparing the dependence of the width of the memory window on the channel length between the non-volatile memory element of one embodiment of the present invention and the non-volatile memory element of Comparative Example 2. [Figure 19] It is a cross-sectional perspective view showing a modified example of the element structure in the non-volatile memory device of one embodiment of the present invention. [Figure 20] It is a diagram showing the relationship between the width of the memory window and the film thickness of the gate insulating layer 220 in the non-volatile memory element having the element structure shown in FIG. 19. [Figure 21] It is a cross-sectional perspective view showing a modified example of the element structure in the non-volatile memory device of one embodiment of the present invention. [Figure 22] It is a diagram showing the relationship between the width of the memory window and the film thickness of the semiconductor member in the non-volatile memory element having the element structure shown in FIG. 21. [Figure 23] It is a cross-sectional view corresponding to the element structure in the non-volatile memory element of Comparative Example 2. [Embodiments for Carrying Out the Invention]

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings and the like. However, the present invention can be implemented in various modes without departing from the gist thereof, and is not to be construed as being limited to the description of the embodiments exemplified below. For the sake of clarity in the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the actual mode, but this is merely an example and does not limit the interpretation of the present invention. In this specification and each drawing, elements having the same functions as those described with respect to the already shown drawings may be denoted by the same reference numerals, and redundant explanations may be omitted.

[0014] In the embodiments described below, the temperature conditions for the simulation are all at room temperature.

[0015] [Element Structure] The following describes a non-volatile memory device 100 according to an embodiment of the present invention.

[0016] Figure 1 is a cross-sectional view showing the device structure of a non-volatile memory device 100 according to one embodiment of the present invention. The non-volatile memory device 100 shown in Figure 1 has a three-dimensional stacked structure in which a plurality of non-volatile memory elements 20 (see Figure 2) are three-dimensionally integrated. The plurality of non-volatile memory elements 20 are arranged in series along the longitudinal direction of a columnar semiconductor member 210 that functions as a channel. In this embodiment, the non-volatile memory element 20 is an FeFET (Ferroelectric Field Effect Transistor) having a gate insulating layer made of a ferroelectric material.

[0017] A source electrode 120 is provided on the substrate 110. The substrate 110 can be a silicon substrate with an insulating surface, or a metal substrate, etc. The source electrode 120 can be a metallic material containing titanium, aluminum, tungsten, tantalum, molybdenum, copper, etc., or a compound material containing these metallic materials. When an n-type semiconductor substrate (for example, an n-type silicon substrate) is used as the source, the source electrode 120 shown in Figure 1 can be omitted.

[0018] Multiple non-volatile memory elements 20 are arranged in series between the source electrode 120 and the drain electrode 130. The semiconductor member 210 is electrically connected to the source electrode 120 and the drain electrode 130. In other words, in the non-volatile memory device 100, the multiple non-volatile memory elements 20 share the source electrode 120 and the drain electrode 130 in addition to the semiconductor member 210.

[0019] The source electrode 120 is electrically connected to the source terminal 140, which is made of a metallic material. The drain electrode 130 is electrically connected to the drain terminal 150, which is made of a metallic material. The drain terminal 150 is connected to the bit line (not shown) of the non-volatile memory device 100. In addition, each of the multiple gate electrodes 230 is electrically connected to the gate terminal 160. The multiple gate terminals 160 are connected to the word line (not shown) of the non-volatile memory device 100. The source terminal 140, drain terminal 150 and gate terminal 160 are electrically connected to the source electrode 120, drain electrode 130 and gate electrode 230, respectively, via the passivation layer 170 or contact holes provided in the insulating layer 240 provided between each gate electrode 230.

[0020] Figure 2 is a cross-sectional perspective view showing the element structure of a non-volatile memory device 100 according to one embodiment of the present invention. Specifically, Figure 2 is an enlarged view of the portion enclosed by the frame line 200 (corresponding to the three non-volatile memory elements 20) in the non-volatile memory device 100. Figure 3 is a perspective view showing the configuration of the semiconductor member 210 and the gate insulating layer 220 in the non-volatile memory element 20 shown in Figure 2.

[0021] As shown in Figure 2, the non-volatile memory element 20 of this embodiment is an FeFET composed of a semiconductor member 210, a gate insulating layer 220, and a gate electrode 230. In the non-volatile memory device 100 of this embodiment, multiple non-volatile memory elements 20 share the semiconductor member 210 and the gate insulating layer 220.

[0022] The semiconductor member 210 is a columnar member that functions as a channel of the non-volatile memory element 20. As shown in FIGS. 2 and 3, the semiconductor member 210 substantially has no hollow portion or other member inside. Here, "substantially having no hollow portion or other member inside" means that, for example, a minute hollow portion or other member may be included inside the semiconductor member 210. That is, a minute hollow portion or other member that does not significantly affect the element characteristics may exist inside the semiconductor member 210. The semiconductor member 210 is a member continuous from the outer peripheral surface to the central axis. That is, the semiconductor member 210 is continuously composed of the same material (including materials that can be regarded as substantially the same) from the outer peripheral surface to the central axis.

[0023] In the present embodiment, a metal oxide called IGZO is used as the material constituting the semiconductor member 210. IGZO is a metal oxide exhibiting semiconductor characteristics and is a compound material composed of indium, gallium, zinc, and oxygen. Specifically, IGZO is an oxide containing In, Ga, and Zn, or a mixture of such oxides. The composition of IGZO is preferably In2-xGaxO3(ZnO)m (0 < x < 2, m is a natural number of 0 or less than 6), more preferably InGaO3(ZnO)m (m is a natural number of 0 or less than 6), and most preferably InGaO3(ZnO).

[0024] In the present embodiment, the semiconductor member 210 is cylindrical. However, it is not limited to this example, and the semiconductor member 210 may be an elliptical columnar or prismatic member. In the present embodiment, the diameter (D) of the semiconductor member 210 is 8 nm. The diameter of the semiconductor member 210 may be set, for example, within a range of 30 nm or less (preferably 1 nm or more and 20 nm or less, more preferably 4 nm or more and 10 nm or less). When the semiconductor member 210 has a shape other than a cylindrical shape, the diameter or length of the semiconductor member 210 in a direction substantially orthogonal to the interface between the semiconductor member 210 and the gate insulating layer 220 may be regarded as the diameter of the semiconductor member 210 and set accordingly.

[0025] As shown in Figures 1 and 2, in this embodiment, a cylindrical semiconductor member 210 having a longitudinal direction substantially perpendicular to the substrate 110 is used. In this case, when manufacturing the non-volatile memory device 100, the semiconductor member 210 is formed by filling holes having a diameter of, for example, 30 nm or less with a metal oxide material. In this embodiment, the semiconductor member 210 is formed using the ALD (Atomic Layer Deposition) method. However, the semiconductor member 210 is not limited to this example and can also be formed using methods such as the PLD (Pulsed Laser Deposition) method, DC sputtering method, RF sputtering method, spin coating method, dip coating method, and mist CVD (Mist Chemical Vapor Deposition) method. In particular, methods using solutions, such as the spin coating method, are suitable when filling holes with a metal oxide material.

[0026] The gate insulating layer 220 corresponds to the ferroelectric layer in the non-volatile memory element 20 of this embodiment. In this embodiment, zirconium-doped hafnium oxide (hereinafter referred to as "HZO") is used as the ferroelectric material constituting the gate insulating layer 220. However, other ferroelectric layers such as silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc., doped hafnium oxide may be used as the gate insulating layer 220. In this embodiment, the gate insulating layer 220 is formed to a thickness of 10 nm using the ALD (Atomic Layer Deposition) method. However, the thickness of the gate insulating layer 220 is not limited to this example, and can be, for example, 5 nm to 22 nm (preferably 10 nm to 18 nm).

[0027] The gate insulating layer 220 is provided in contact with the side surface of the semiconductor member 210 and surrounding the semiconductor member 210. That is, as shown in Figure 3, the gate insulating layer 220 can be described as a cylindrical member having a cylindrical semiconductor member 210 with diameter (D) inside. Thus, the channel portion of this embodiment has a structure in which the space inside the cylindrical gate insulating layer 220 is occupied by the semiconductor member 210.

[0028] The gate electrode 230 functions as a gate that controls the program operation or erase operation of the non-volatile memory element 20. In this embodiment, a compound layer made of titanium nitride (TiN) is used as the gate electrode 230. However, the material of the gate electrode 230 is not limited to this, and metallic materials including tungsten, tantalum, molybdenum, aluminum, copper, etc., or compound materials containing such metallic materials can be used. The gate electrode 230 can be formed, for example, by sputtering.

[0029] For forming the gate electrode 230, techniques called the gate-first method or the gate-last method can be used. In the gate-first method, a laminate is formed by alternately stacking polysilicon layers and insulating layers such as silicon oxide on a substrate, and a channel layer is formed after creating multiple holes perpendicular to the laminate and forming a ferroelectric layer inside the holes (punch and plug). The polysilicon layer is then used as the gate electrode. In the gate-last method, first, a laminate is formed by alternately stacking dummy layers made of silicon nitride or the like and insulating layers such as silicon oxide, and a punch and plug process is performed. After that, the dummy layers are selectively removed, and a metal material such as tungsten is embedded in the space created by the removal. The metal layer made of the embedded metal material is then used as the gate electrode. Here, lithography and reactive ion etching can be used to form the holes. CVD and ALD methods can be used to fill the space with the metal material. Although the gate-last method is a complex process, it has the advantage of being able to manufacture devices with metal gates that have lower resistance than polysilicon gates.

[0030] In the non-volatile memory element 20 of this embodiment, the width of the gate electrode 230 corresponds to the channel length (L) of the non-volatile memory element 20. The width of the gate electrode 230 is the thickness of the titanium nitride layer that functions as the gate electrode 230. In this embodiment, the width of the gate electrode 230 (i.e., the channel length) is 1 μm or less (preferably 50 nm or less). As will be described later, the non-volatile memory element 20 of this embodiment can ensure a stable memory window when the channel length is 1 μm or less.

[0031] The insulating layer 240 is an insulating film that provides insulating isolation between two adjacent gate electrodes 230. As the insulating layer 240, insulating films such as silicon oxide and silicon nitride can be used. In this embodiment, the thickness of the insulating layer 240 is 10 nm to 50 nm (preferably 20 nm to 40 nm), but it is not limited to this example. The thickness of the insulating layer 240 can be appropriately determined in relation to the channel length (i.e., the width of the gate electrodes 230). However, if the insulating layer 240 is too thin, adjacent non-volatile memory elements 20 may influence each other, potentially causing malfunctions. Also, if the insulating layer 240 is too thick, the distance between channels of adjacent non-volatile memory elements 20 increases, potentially becoming an obstacle to carrier movement.

[0032] As described above, the non-volatile memory device 100 of this embodiment has a three-dimensional stacked structure in which multiple non-volatile memory elements 20 are densely integrated. Furthermore, each non-volatile memory element 20 uses a metal oxide called IGZO as its channel, thus providing high reliability. Compared to polysilicon, which is generally used as a channel in FETs, IGZO has fewer internal defects and is less likely to cause a decrease in carrier mobility. In addition, since IGZO does not form a low-dielectric interface layer (low-k layer) at the interface with the ferroelectric layer, voltage loss that occurs when voltage is supplied to the gate electrode can also be reduced. The absence of low-quality low-k layers means that degradation of device characteristics due to charge traps, etc., can also be reduced. In addition to these advantages, since IGZO has sufficient carrier mobility in its deposited state (i.e., amorphous state), there is no need to make it polycrystalline through annealing, and it is not affected by grain boundaries and crystal defects. Furthermore, a non-volatile memory element using IGZO as a channel can be operated as a junctionless FET (a transistor without a pn junction). Therefore, in FETs using IGZO as the channel, carriers move within the channel body (near the center of the channel) and are less susceptible to charge trapping near the interface layer.

[0033] For the reasons stated above, the non-volatile memory element 20 of this embodiment can achieve high reliability by using IGZO as the channel. Furthermore, as will be described later, in the non-volatile memory device 100 of this embodiment, each non-volatile memory element 20 can operate with low power consumption. Therefore, according to this embodiment, a non-volatile memory device 100 with high capacity, low power consumption, and high reliability can be obtained. The element characteristics of the non-volatile memory element 20 will be described below using simulation results.

[0034] [Element Characteristics] Figure 4 shows the simulation results of the Id-Vg characteristics in a non-volatile memory element 20 according to one embodiment of the present invention. Specifically, Figure 4 shows the dependence of the Id-Vg characteristics on the channel length in an FeFET having the structure shown in Figures 2 and 3. Figure 5 shows the relationship between the memory window width and the channel length obtained from the Id-Vg characteristics in Figure 4. Figure 6 shows the relationship between the SS value and the drain current obtained from the Id-Vg characteristics in Figure 4.

[0035] In the Id-Vg characteristics shown in Figure 4, the channel length (L) of the semiconductor member 210 was set to 10 nm, 20 nm, 50 nm, 100 nm, 200 nm, 500 nm, or 1 μm, respectively. In Figure 4, the diameter of the semiconductor member 210 and the thickness of the gate insulating layer 220 were set to 8 nm and 10 nm, respectively. The residual polarization (Pr) was 20 μC / cm². 2 The settings were as follows: The source-drain voltage (Vds) was set to 50mV, and the source-gate voltage (hereinafter referred to as "gate voltage") (Vg) was swept within the range of -5V to 5V.

[0036] According to the simulation results shown in Figure 4, a memory window of sufficient width was obtained regardless of the channel length in the range of channel length of 1 μm or less. In particular, in the range of channel length from 20 nm to 1 μm, almost identical and stable Id-Vg characteristics were obtained, and there was no significant change in the width of the memory window. In other words, from the simulation results shown in Figure 4, it was found that the non-volatile memory element 20 of this embodiment has a sufficient memory window when the channel length is from 20 nm to 1 μm, and that the width of the memory window does not change significantly.

[0037] In this regard, as shown in the graph in Figure 5, the memory window width remains stable in the range of 1.0V to 1.3V (specifically, 1.05V to 1.25V) when the channel length is between 20nm and 1μm. In other words, when the channel length is between 20nm and 1μm, the memory window width is within the range of 1.15V ± 1.0V. Thus, the non-volatile memory element 20 of this embodiment can ensure a stable memory window width in the channel length range of 20nm to 1μm, without depending on the channel length.

[0038] On the other hand, as shown in Figure 4, when the channel length was 10 nm, a memory window with a larger width was obtained compared to other channel lengths. Specifically, as shown in Figure 5, when the channel length was 10 nm, the width of the memory window was approximately 1.4 V. This is thought to be due to the coupling effect between the source-side potential and the drain-side potential in the gate insulating layer 220.

[0039] Furthermore, as shown in Figure 6, an SS value of approximately 60 mV / dec, close to the ideal value, was obtained in the channel length range of 20 nm to 1 μm. In other words, it was found that the non-volatile memory element 20 can achieve a stable memory window width and exhibit excellent cutoff characteristics in the channel length range of 20 nm to 1 μm. In contrast, a slight degradation in the SS value was observed when the channel length was 10 nm. Considering these findings, it is thought that in the case of the non-volatile memory element 20 of this embodiment, when the channel length is less than 20 nm, characteristic degradation such as the so-called short-channel effect occurs due to the coupling effect between the source-side potential and the drain-side potential.

[0040] Furthermore, as shown in Figure 4, the non-volatile memory element 20 of this embodiment achieves good switching operation at a low voltage of ±1.0V or less regardless of the channel length, within the channel length range of 1 μm or less. In particular, in the channel length range of 20 nm to 1 μm, good switching operation is achieved at a low voltage of ±0.5V or less. Thus, the non-volatile memory element 20 of this embodiment has the advantage of low power consumption because it can be operated at low voltage.

[0041] Next, Figure 7 shows the distribution of polarization charge in the gate insulating layer 220 of a non-volatile memory element 20 according to one embodiment of the present invention. Figure 8 shows the distribution of polarization charge in the gate insulating layer 220 of a non-volatile memory element 50 of Comparative Example 1. In the simulations shown in Figures 7 and 8, the gate voltage is set to -5V. The gate insulating layer (ferroelectric layer) is set as a continuum model. Figures 7 and 8 show the dielectric polarization moment of the gate insulating layer when the channel length is 50 nm, which is 0.2 μC / cm. 2 This is shown in steps. In Figures 7 and 8, the length of the longer side of the rectangle labeled "IGZO Channel" that represents the channel corresponds to the channel length.

[0042] As shown in Figure 7, the gate insulating layer 220 (the region labeled "Ferroelectric layer") in the non-volatile memory element 20 exhibits continuous spontaneous polarization reversal along the channel. That is, the gate insulating layer 220 in the non-volatile memory element 20 exhibits continuous spontaneous polarization reversal from the source to the drain. Note that in Figure 7, the signs (±) of the spontaneous polarization are reversed on the upper and lower sides of the channel, which means that the vector direction of the electric field is reversed. Furthermore, a region where no spontaneous polarization reversal occurs is observed at a distance from the channel, which is thought to be due to treating the ferroelectric layer as a continuum model.

[0043] Thus, the gate insulating layer 220 of the non-volatile memory element 20 undergoes a continuous spontaneous polarization reversal from the source side to the drain side, making it possible to control the writing operation (program operation and erase operation) effectively.

[0044] On the other hand, Figure 8 shows the simulation results for a planar FeFET using IGZO as the channel and a ferroelectric layer as the gate insulating layer. In this case, spontaneous polarization reversal of the gate insulating layer is observed on the left and right sides, but not as it approaches the center. That is, in the nonvolatile memory element of Comparative Example 1, spontaneous polarization reversal occurs in the gate insulating layer near the source and drain, but not in the parts far from the source and drain.

[0045] The reason why spontaneous polarization reversal, as shown in Figure 7, is observed in the non-volatile memory element 20 of this embodiment will be explained below.

[0046] Figure 9 shows a simulation model of the electric field distribution inside the gate insulating layer 220 in a non-volatile memory element 20 according to one embodiment of the present invention. Specifically, Figure 9 shows the electric field distribution on a plane perpendicular to the longitudinal direction in the semiconductor member 210 and the gate insulating layer 220 shown in Figure 3. Figure 10 shows the simulation results of the electric field distribution inside the gate insulating layer 220 in a non-volatile memory element 20 according to one embodiment of the present invention. Figure 10 shows the electric field distribution in a straight line passing through the center point of a cross-section perpendicular to the longitudinal direction in the semiconductor member 210 and the gate insulating layer 220 shown in Figure 3.

[0047] In Figure 9, the dotted lines schematically represent equipotential lines Va and Vb, respectively. For equipotential lines Va and Vb, it is considered that a magnitude relationship similar to ε*E1*S1=ε*E2*S2 holds approximately according to Gauss's theorem. Here, ε, E, and S represent the dielectric constant, electric field strength, and surface area, respectively. In other words, the electric field strength (strength of the electric field) inside the gate insulating layer 220 increases as it approaches the semiconductor member 210. Figure 10 shows how the electric field strength inside the gate insulating layer 220 (region labeled HZO) increases as it approaches the semiconductor member 210 (region labeled IGZO). Inside the gate insulating layer 220, a large electric field is formed near the semiconductor member 210 which functions as a channel. Therefore, as shown in Figure 7, it is considered that spontaneous polarization reversals occur continuously along the channel.

[0048] As described above, the non-volatile memory element 20 of this embodiment has a structure in which a cylindrical gate insulating layer 220 surrounds a columnar semiconductor member 210, and has the characteristic that spontaneous polarization reversal is likely to occur in the gate insulating layer 220 near the channel. In other words, in this embodiment, it is possible to improve the characteristics of program operation (especially erase operation) by utilizing the fact that the electric field near the channel is strengthened due to electric field concentration in the three-dimensional structure.

[0049] Next, the dependence of the semiconductor member 210 on the diameter in the non-volatile memory element 20 of this embodiment will be described.

[0050] Figure 11 shows the simulation results of the Id-Vg characteristics in a non-volatile memory element 20 of one embodiment of the present invention. Specifically, Figure 11 shows the dependence of the Id-Vg characteristics on the diameter of the semiconductor member 210 in an FeFET having the structure shown in Figures 2 and 3. Figure 12 shows the relationship between the memory window width and diameter obtained from the Id-Vg characteristics shown in Figure 11. Figure 13 shows the relationship between the SS value and drain current obtained from the Id-Vg characteristics shown in Figure 11.

[0051] In the Id-Vg characteristics shown in Figure 11, the diameter (D) of the semiconductor member 210 was set to 8 nm, 16 nm, or 24 nm, respectively. In Figure 11, the channel length of the semiconductor member 210 and the film thickness of the gate insulating layer 220 were set to 50 nm and 10 nm, respectively. The residual polarization (Pr) was 20 μC / cm². 2 The settings were adjusted accordingly. Additionally, the source-drain voltage (Vds) was set to 50mV, and the gate voltage (Vg) was swept within the range of -5V to 5V.

[0052] According to the simulation results shown in Figure 11, it was found that the smaller the diameter (D) of the semiconductor element 210, i.e., the channel diameter, the larger the memory window width. As shown in Figure 12, there is a linear relationship between the diameter of the semiconductor element 210 and the memory window width in the non-volatile memory element 20. Referring to the relationship shown in Figure 12, for example, if the diameter of the semiconductor element 210 is 20 nm or less, a memory window width of 0.6 V or more can be secured. Also, if the diameter of the semiconductor element 210 is 16 nm or less, a memory window width of 0.8 V or more can be secured. Furthermore, if the diameter of the semiconductor element 210 is 10 nm or less, a memory window width of 1.0 V or more can be secured.

[0053] Furthermore, as shown in Figure 13, it was found that the SS value of the non-volatile memory element 20 does not depend on the diameter of the semiconductor material 210 and falls within the range of 60 mV / dec to 65 mV / dec. It was also found that the SS value of the non-volatile memory element 20 decreases as the diameter of the semiconductor material 210 decreases. From the above, it was found that the SS value of the non-volatile memory element 20 is good regardless of the diameter of the semiconductor material 210.

[0054] As described above, the non-volatile memory element 20 of this embodiment has a structure in which the inside of the cylindrical gate insulating layer 220 is occupied by a semiconductor member 210, as shown in Figures 2 and 3. By adopting such a structure, the non-volatile memory element 20 can obtain a good memory window width and SS value, for example, in the range where the diameter (D) of the semiconductor member 210 is 20 nm or less and the channel length (L) is 1 μm or less.

[0055] [Element structure of Comparative Example 2] Figure 14 is a cross-sectional view showing the element structure of the non-volatile memory device 500 in Comparative Example 2. As shown in Figure 14, the non-volatile memory device 500 has a three-dimensional stacked structure in which a plurality of non-volatile memory elements 50 are three-dimensionally integrated. The plurality of non-volatile memory elements 50 are arranged in series along the longitudinal direction of the channel layer 510, with a cylindrical channel layer 510 that functions as a channel in common. The non-volatile memory element 50 is an FeFET composed of a channel layer 510, a gate insulating layer 520, and a gate electrode 530. The channel layer 510 and the gate insulating layer 520 are common to the plurality of non-volatile memory elements 50. The difference between the non-volatile memory element 20 of this embodiment and the non-volatile memory element 50 shown in Figure 14 is that the non-volatile memory element 50 has a cylindrical channel layer 510 and a filler member 550 made of insulating material on the inside. The filler member 550 functions as a filling member that fills the inside of the cylindrical channel layer 510. As the filler member 550, insulating materials such as silicon oxide, silicon nitride, and resin can be used. In this embodiment, a member with a diameter of 4 nm made of silicon oxide is used as the filler member 550.

[0056] Figure 15 shows the simulation results of the Id-Vg characteristics of the non-volatile memory element 50 of Comparative Example 2. Specifically, Figure 15 shows the dependence of the Id-Vg characteristics on the channel length in an FeFET having the structure shown in Figure 14. Figure 16 shows the relationship between the memory window width and the channel length, obtained from the Id-Vg characteristics shown in Figure 15. Figure 17 shows the relationship between the SS value and the drain current, obtained from the Id-Vg characteristics shown in Figure 15.

[0057] In the Id-Vg characteristics shown in Figure 15, the channel length (L) of the channel layer 510 was set to 20 nm, 50 nm, 100 nm, 200 nm, 500 nm, or 1 μm, respectively. In Figure 15, the film thickness of the channel layer 510 and the gate insulating layer 520 were set to 8 nm and 10 nm, respectively. The residual polarization (Pr) was 20 μC / cm². 2 The settings were as follows: The source-drain voltage (Vds) was set to 50mV, and the gate voltage (Vg) was swept within the range of -5V to 5V.

[0058] According to the simulation results shown in Figures 15 and 16, it was found that in the channel length range of 500 nm or less, the memory window gradually widens, and the width of the memory window increases as the channel length decreases. In particular, in the channel length range of 50 nm to 200 nm, the width of the memory window remains stable in the range of approximately 0.7 V to 0.8 V. On the other hand, when the channel length becomes 50 nm or less, the width of the memory window increases. This is thought to be due to the effect of coupling between the source side potential and the drain side potential.

[0059] Furthermore, as shown in Figure 17, the SS value of the non-volatile memory element 50 in Comparative Example 2 was found to be approximately 60 mV / dec, independent of the channel length. In contrast, a slight degradation of the SS value was observed when the channel length was 20 nm. Based on these findings, it is considered that in the case of the non-volatile memory element 50, when the channel length is less than 50 nm, characteristic degradation such as the so-called short-channel effect occurs due to the coupling effect between the source-side potential and the drain-side potential.

[0060] Figure 18 compares the dependence of the memory window width on the channel length in a non-volatile memory element 20 of one embodiment of the present invention and a non-volatile memory element 50 of Comparative Example 2. In Figure 18, the plot labeled "Embodiment" shows the memory window width of the non-volatile memory element 20 of this embodiment. The plot labeled "Comparative example" shows the memory window width of the non-volatile memory element 50 of Comparative Example 2. In "Comparative example," "D_channel_20nm" refers to a structure in which a cylindrical IGZO with a film thickness of 8 nm is provided around a filler member with a diameter of 4 nm.

[0061] As shown in Figure 18, in the range where the channel length is 1 μm or less, the memory window width of the non-volatile memory element 20 of the present invention is larger than that of the non-volatile memory element 50 of Comparative Example 2. Furthermore, while the memory window width of the non-volatile memory element 50 of Comparative Example 2 fluctuates greatly, the memory window width of the non-volatile memory element 20 of this embodiment is stable at around 1.2 V. Thus, the non-volatile memory element 20 of this embodiment can stably secure a larger memory window regardless of the channel length compared to the non-volatile memory element 50 of Comparative Example 2. In other words, the non-volatile memory element 20 of this embodiment can significantly improve the memory window compared to the non-volatile memory element 50 of Comparative Example 2.

[0062] (Variation 1) In this modified example, the relationship between the outer diameter of the semiconductor component 210 and the thickness of the gate insulating layer 220 will be explained.

[0063] Figure 19 is a cross-sectional perspective view showing a modified example of the element structure in a non-volatile memory device 100 according to one embodiment of the present invention. Specifically, Figure 19 corresponds to an enlarged view of the portion enclosed by the frame line 200 in the non-volatile memory device 100 shown in Figure 1.

[0064] In the example shown in FIG. 19, the film thickness D2 of the gate insulating layer 220 made of a ferroelectric material is larger than the outer diameter D1 of the semiconductor member 210 (that is, the diameter of the semiconductor member 210). Specifically, when the outer diameter of the semiconductor member 210 is D1 and the film thickness of the gate insulating layer 220 is D2, the relationship D1 < D2 holds. Such a relationship is derived from the simulation results described below.

[0065] FIG. 20 is a diagram showing the relationship between the width of the memory window and the film thickness of the gate insulating layer 220 (denoted as "Thzo" in FIG. 20) in the nonvolatile memory element having the element structure shown in FIG. 19. In FIG. 20, the channel length and diameter of the semiconductor member 210 are set to 50 nm and 8 nm, respectively. Also, the write voltages are 5 V, 7.5 V, and 10 V.

[0066] As shown in FIG. 20, in the range where the film thickness D2 of the gate insulating layer 220 is 10 nm or more and 18 nm or less, regardless of the write voltage, a tendency was observed that the width of the memory window gradually increases as the film thickness D2 of the gate insulating layer 220 increases. On the other hand, when the film thickness D2 of the gate insulating layer 220 exceeds 18 nm, when the write voltage is 5 V, the width of the memory window decreases, and when the write voltage is 7.5 V, almost no change was observed in the width of the memory window.

[0067] When the write voltage is 5 V, the tendency observed when the film thickness D2 of the gate insulating layer 220 exceeds 18 nm is considered to be due to the fact that the write voltage applied to the nonvolatile memory element is insufficient due to the increase in the film thickness of the gate insulating layer 220. Therefore, when the write voltage is 10 V, the width of the memory window increases even when the film thickness D2 of the gate insulating layer 220 exceeds 18 nm. That is, it is considered that the larger the write voltage, the larger the film thickness of the gate insulating layer 220 at which the memory window reaches its maximum. However, since an increase in the write voltage causes an increase in the power consumption of the nonvolatile memory device 100, it is desirable that the write voltage be 7.5 V or less.

[0068] As described above, when the writing voltage is 7.5V or less, it was confirmed that the memory window width increases linearly regardless of the writing voltage when the film thickness D2 of the gate insulating layer 220 is in the range of at least 10nm to 18nm, and that a memory window with a width of at least 1.3V can be secured. Furthermore, according to the results shown in Figure 20, if each graph is extrapolated to the range where the film thickness D2 of the gate insulating layer 220 is 10nm or less, it is expected that a memory window with a width of at least 1.3V can be secured when the film thickness D2 of the gate insulating layer 220 is at least 8nm.

[0069] These results indicate that a sufficiently wide memory window can be secured when the film thickness D2 of the gate insulating layer 220 is greater than or equal to the outer diameter D1 of the semiconductor member 210 (in this case, 8 nm). More preferably, the film thickness D2 of the gate insulating layer 220 is 1.4 times or more the outer diameter D1 of the semiconductor member 210. That is, in the example shown in Figure 20, it is desirable that the film thickness D2 of the gate insulating layer 220 be 8 nm or more (preferably 12 nm or more, and even more preferably 16 nm or more).

[0070] As described above, in the device structure shown in Figure 19, a sufficient memory window width can be secured by making the film thickness D2 of the gate insulating layer 220 equal to or greater than the outer diameter D1 of the semiconductor member 210.

[0071] The device structure shown in this modified example is particularly effective when the integration density of the memory holes (cylindrical holes with diameter D3 in Figure 19) is approximately 50 nm in diameter. As explained using Figure 12, the device structure shown in Figure 2, which has virtually no hollow parts or other components inside, allows for a better memory window width as the outer diameter of the semiconductor member 210 decreases. However, when the diameter of the memory holes is large, the outer diameter of the semiconductor member 210 inevitably increases, which is undesirable from the standpoint of securing a sufficient memory window. In contrast, the device structure of this modified example can adequately accommodate memory holes with a diameter of approximately 50 nm while securing a sufficiently wide memory window by reducing the outer diameter D1 of the semiconductor member 210 and increasing the film thickness D2 of the gate insulating layer 220. Specifically, assuming that the diameter of the memory holes is in the range of 30 nm to 60 nm, it is preferable that the outer diameter of the semiconductor member 210 is 1 nm to 12 nm and the film thickness of the gate insulating layer 220 is 15 nm to 22 nm.

[0072] (Modification 2) This modified example describes a case in which a hollow portion exists at the center of the semiconductor material, with a diameter significantly smaller than the outer diameter of the semiconductor material.

[0073] Figure 21 is a cross-sectional perspective view showing a modified example of the element structure in a non-volatile memory device 100 according to one embodiment of the present invention. Specifically, Figure 21 corresponds to an enlarged view of the portion enclosed by the frame line 200 in the non-volatile memory device 100 shown in Figure 1.

[0074] In the example shown in Figure 21, the semiconductor member 210a is cylindrical. That is, the semiconductor member 210a has a hollow portion in the center. In this modified example, the hollow portion of the semiconductor member 210a is filled with a filler member 250a made of an insulating material. However, this is not the only example, and the hollow portion of the semiconductor member 210a may be an empty void. In this modified example, the inner diameter D5 of the semiconductor member 210a (i.e., the outer diameter of the filler member 250a) is sufficiently smaller than the outer diameter D1 of the semiconductor member 210a (i.e., the diameter of the semiconductor member 210a). Specifically, the ratio of the inner diameter D5 of the semiconductor member 210a to the outer diameter D1 of the semiconductor member 210a is 15% or less (preferably 10% or less). This relationship is derived from the simulation results described next.

[0075] Figure 22 shows the relationship between the memory window width and the semiconductor material thickness D4 (labeled "Tigzo" in Figure 22) in a non-volatile memory element with the device structure shown in Figure 21. Here, the semiconductor material thickness corresponds to the distance between the filler material 250a and the gate insulating layer 220a, as shown in Figure 21 as an example. That is, in the example shown in Figure 21, the relationship D1 = 2 × D4 + D5 holds. In Figure 22, the channel length of the semiconductor material is set to 50 nm, the thickness of the gate insulating layer is set to 10 nm, and the writing voltage is set to 5 V. The outer diameter D1 of the semiconductor material (simply labeled "D" in Figure 22) is set to 8 nm, 16 nm, and 24 nm.

[0076] In each graph shown in Figure 22, the plot at the far right (the plot with the largest Tigzo) corresponds to a device structure without a hollow portion in the semiconductor material, i.e., the device structure shown in Figure 2. For example, in the graph corresponding to D1=24nm, the film thickness D4 (Tigzo) at the plot at the far right is 12nm, which corresponds to the radius of a semiconductor material without a hollow portion (D5=0). On the other hand, all plots other than the one at the far right correspond to device structures where a hollow portion exists in the semiconductor material (D5>0), as shown in Figure 21.

[0077] As shown in Figure 22, in each graph, the rate of change in the memory window width in response to changes in the semiconductor material film thickness (Tigzo) is small near the plot at the far right. For example, in the graph corresponding to D1=8nm, the memory window width (approximately 1.35V) is almost identical between the plot at the far right (Tigzo=4nm) and the adjacent plot (Tigzo=3nm). This indicates that, in the case of D1=8nm, there is almost no change between the memory window width in a device structure with a semiconductor material without a hollow portion (the device structure shown in Figure 2) and the memory window width in a device structure including a semiconductor material with a 2nm hollow portion (i.e., the device structure shown in Figure 21).

[0078] Thus, in the case of D1=8nm, it was found that even in the device structure shown in Figure 21, if the volume of the hollow portion is sufficiently small, a memory window width substantially equivalent to that of the device structure shown in Figure 2 can be secured. From this, it can be said that if a device structure includes a semiconductor material having a hollow portion with an outer diameter D5 of 2nm or less (preferably 1nm or less), a memory window width substantially equivalent to that of a device structure with a semiconductor material without a hollow portion (D5=0) can be secured. For example, in the case of D1=16nm, the memory window width when Tigzo=7nm (i.e., the outer diameter of the hollow portion is 2nm) is approximately 0.9V, which is substantially the same as the memory window width in the plot on the far right (approximately 0.85V). Also, in the case of D=24nm, the memory window width when Tigzo=11nm (i.e., the outer diameter of the hollow portion is 2nm) is approximately 0.55V, which is substantially the same as the memory window width in the plot on the far right (approximately 0.5V).

[0079] From the above results, it was found that if the ratio of the inner diameter D5 of the semiconductor member to the outer diameter D1 of the semiconductor member is 15% or less (preferably 10% or less), then even with the element structure shown in Figure 21, a memory window width substantially equivalent to that of the element structure including a semiconductor member without a hollow portion shown in Figure 2 can be achieved, and there are no practical problems.

[0080] The results described above indicate that the device structure shown in Figure 2 has a high process margin. For example, in the device structure shown in Figure 2, the semiconductor member 210 is formed by filling holes (trenches) with a diameter of about 30 to 50 nm with a metal oxide material. However, since the filling proceeds from the inner wall side of the trench, there may be cases where an unfillable void is formed near the center of the semiconductor member 210. However, even in this case, if the volume of the void is sufficiently small, it is considered that a memory window substantially equivalent to that of the case without a void can be secured.

[0081] Incidentally, in the results shown in Figure 22, for example, when D=16nm and Tigzo=4nm, the width of the memory window is approximately 1.25V. In this case, since the thickness of the gate insulating layer is 10nm, the diameter of the memory hole (a cylindrical hole with diameter D3 in Figure 23) is 36nm. Such a device structure corresponds to the device structure of Comparative Example 2 shown in Figure 14. Specifically, referring to Figure 23, the outer diameter D1 of the semiconductor member 510 is 16nm, the thickness D2 of the gate insulating layer 520 is 10nm, the diameter D3 of the memory hole is 36nm, the thickness D4 of the semiconductor member 510 is 4nm, and the outer diameter D5 of the filler member 550 is 8nm.

[0082] In contrast, in Figure 19, the device structure in which the film thickness of the semiconductor member 210 (corresponding to half the outer diameter D1 of the semiconductor member 210) and the diameter D3 of the memory hole are the same as the device structure shown in Figure 23 has an outer diameter D1 of the semiconductor member 210 of 8 nm, a film thickness D2 of the gate insulating layer 220 of 14 nm, and a memory hole diameter D3 of 36 nm. According to the results shown in Figure 20, the memory window width of such a device structure is approximately 1.45 V. In other words, it is larger than the memory window width (approximately 1.25 V) in the device structure shown in Figure 23.

[0083] From the above, when comparing under the same conditions the ratio of the total thickness of the semiconductor material to the diameter D3 of the memory hole (which is D1 in the case of the device structure shown in Figure 19, and twice D4 in the case of the device structure shown in Figure 23), it can be said that the memory window width is larger for the device structure shown in Figure 19 compared to the device structure shown in Figure 23.

[0084] Based on the non-volatile memory device which is an embodiment of the present invention, any additions, deletions, or design modifications of components, or additions, omissions, or changes in conditions of processes, made by those skilled in the art, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0085] Furthermore, any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0086] 10...Non-volatile memory element, 110...Substrate, 120...Source electrode, 130...Drain electrode, 140...Source terminal, 150...Drain terminal, 160...Gate terminal, 170...Passivation layer, 210...Semiconductor material, 220...Gate insulating layer, 230...Gate electrode, 240...Insulating layer

Claims

1. A non-volatile memory device having a three-dimensional stacked structure in which multiple non-volatile memory elements are arranged in series, A columnar semiconductor member containing a metal oxide, A ferroelectric layer containing hafnium oxide, which surrounds the semiconductor member and is in contact with the side surface of the semiconductor member, A plurality of gate electrodes are arranged facing the side surface of the semiconductor member via the ferroelectric layer and along the longitudinal direction of the semiconductor member, A plurality of insulating layers are provided between each of the plurality of gate electrodes, Equipped with, The plurality of non-volatile memory elements share the semiconductor member, The semiconductor member is a continuous member from the outer surface to the central axis. A non-volatile memory device in which the thickness of the ferroelectric layer is greater than the outer diameter of the semiconductor member.

2. The non-volatile memory device according to claim 1, wherein the outer diameter of the semiconductor member is 20 nm or less.

3. The non-volatile memory device according to claim 1 or 2, wherein the metal oxide is IGZO, ITO, IZO, or ITZO.

4. The non-volatile memory device according to any one of claims 1 to 3, wherein the width of each of the plurality of gate electrodes is 1 μm or less.

5. The non-volatile memory device according to claim 1, wherein the thickness of the ferroelectric layer is 5 nm or more and 20 nm or less.

6. A non-volatile memory device having a three-dimensional stacked structure in which multiple non-volatile memory elements are arranged in series, A cylindrical semiconductor component containing a metal oxide, A ferroelectric layer containing hafnium oxide, which surrounds the semiconductor member and is in contact with the side surface of the semiconductor member, A plurality of gate electrodes are arranged facing the side surface of the semiconductor member via the ferroelectric layer and along the longitudinal direction of the semiconductor member, A plurality of insulating layers are provided between each of the plurality of gate electrodes, Equipped with, The plurality of non-volatile memory elements share the semiconductor member, The semiconductor member has a hollow portion in the center, A non-volatile memory device in which the ratio of the inner diameter of the semiconductor member to the outer diameter of the semiconductor member is 15% or less.

7. The non-volatile memory device according to claim 6, wherein the outer diameter of the semiconductor member is 20 nm or less.

8. The non-volatile memory device according to claim 6 or 7, wherein the metal oxide is IGZO, ITO, IZO, or ITZO.

9. The non-volatile memory device according to any one of claims 6 to 8, wherein the width of each of the plurality of gate electrodes is 1 μm or less.

10. The non-volatile memory device according to any one of claims 6 to 9, wherein the thickness of the ferroelectric layer is 5 nm or more and 20 nm or less.

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