GaN trench MOSFET and its manufacturing method

Abstract

The present invention discloses a GaN trench MOSFET and a method for manufacturing the same. The GaN trench MOSFET according to the present invention is characterized in that there is an n-GaN region containing both Mg and donor impurities at a location reaching the n - -GaN drift layer from the bottom of the trench. The n-GaN region is formed in the Mg-doped p-GaN at the bottom of the trench by using ion implantation several times. Also, the side surfaces that have been ion-implanted are removed by dry etching several times to form an electron channel at the interface between the p-GaN and the oxide film layer.

Description

[Technical Field]

[0001] (Cross-references to related fields) This application claims priority to U.S. Application No. 63 / 389,363, titled "GaN TRENCH MOSFET AND FABRICATION METHOD," filed on 14 July 2022 by Tadao Hashimoto. The aforementioned application is incorporated by reference to it in its entirety, as presented below.

[0002] This application is related to the following patent application.

[0003] PCT patent application US2005 / 024239 (attorneys docket number 30794.0129-WO-01(2005-339-1)) filed on July 8, 2005, by Kenji Fujito, Tadao Hashimoto, and Shuji Nakamura, entitled "METHOD FOR GROWING GROUP III NITRIDE CRYSTALS IN SUPERCRITICAL AMMONIA USING AN AUTOCLAVE,"

[0004] Under Section 119(c) of the United States Patent Act, Tadao Hashimoto, Makoto Saito, and Shuji Nakamura filed a provisional U.S. patent application No. 60 / 790,310 (attorney docket number 30794,179-US-P1 (2006-204)) on April 7, 2006, entitled "METHOD FOR GROWING LARGE SURFACE AREA GALLIUM NITRIDE CRYSTALS IN SUPERCRITICAL AMMONIA AND LARGE SURFACE AREA GALLIUM NITRIDE CRYSTALS," and a patent application filed on April 6, 2007, entitled "METHOD FOR GROWING LARGE SURFACE AREA GALLIUM NITRIDE CRYSTALS IN SUPERCRITICAL AMMONIA AND LARGE SURFACE U.S. Patent Application No. 11 / 784,339, titled "AREA GALLIUM NITRIDE CRYSTALS" (attorney docket number 30794,179-US-U1 (2006-204)),

[0005] U.S. Patent Application No. 60 / 973,602, titled "GALLIUM NITRIDE BULK CRYSTALS AND THEIR GROWTH METHOD" (attorney docket number 30794.244-US-P1 (2007-809-1)), filed on September 19, 2007, by Tadao Hashimoto and Shuji Nakamura.

[0006] U.S. Patent Application No. 11 / 977,661 (attorneys docket number 30794.253-US-U1 (2007-774-2)) entitled "METHOD FOR GROWING GROUP III-NITRIDE CRYSTALS IN A MIXTURE OF SUPERCRITICAL AMMONIA AND NITROGEN, AND GROUP III-NITRIDE CRYSTALS GROWN THEREBY" filed on October 25, 2007 by Tadao Hashimoto,

[0007] U.S. Patent Application No. 12 / 392,960 (attorney docket number SIXPOI-003US) entitled "METHOD FOR PRODUCING GROUP III-NITRIDE WAFERSAND GROUP III-NITRIDE WAFERS" filed on February 25, 2009 by Tadao Hashimoto, Edward Letts, and Masanori Ikari,

[0008] U.S. Patent Application No. 12 / 455,760 (attorney docket number SIXPOI-002US) entitled "METHOD FOR PRODUCING IMPROVED CRYSTALLINITY GROUP III-NITRIDE CRYSTALS FROM INITIAL GROUP III-NITRIDE SEED BY AMMONOTHERMAL GROWTH" filed on June 4, 2009 by Edward Letts, Tadao Hashimoto, and Masanori Ikari,

[0009] U.S. Patent Application No. 12 / 455,683 (attorney docket number SIXPOI-005US), filed on June 4, 2009, by Tadao Hashimoto, Edward Letts, and Masanori Ikari, entitled "HIGH-PRESSURE VESSEL FOR GROWING GROUP III NITRIDE CRYSTALS AND METHOD OF GROWING GROUP III NITRIDE CRYSTALS USING HIGH-PRESSURE VESSEL AND GROUP III NITRIDE CRYSTAL,"

[0010] U.S. Patent Application No. 12 / 455,181 (attorney docket number SIXPOI-001US), filed on June 12, 2009, entitled "METHOD FOR TESTING III-NITRIDE WAFERS AND III-NITRIDE WAFERS WITH TEST DATA," by Tadao Hashimoto, Masanori Ikari, and Edward Letts.

[0011] U.S. Patent Application No. 12 / 580,849 (attorney docket number SIXPOI-004US), filed on October 16, 2009, by Tadao Hashimoto, Masanori Ikari, and Edward Letts, entitled "REACTOR DESIGN FOR GROWING GROUP III NITRIDE CRYSTALS AND METHOD OF GROWING GROUP III NITRIDE CRYSTALS".

[0012] U.S. Patent Application No. 13 / 781,509 (attorney docket number SIXPOI-012US), filed on February 28, 2013, by Tadao Hashimoto, entitled "COMPOSITE SUBSTRATE OF GALLIUM NITRIDE AND METAL OXIDE"

[0013] U.S. Patent Application No. 13 / 781,543 (attorney docket number SIXPOI-013US), filed on February 28, 2013, entitled "A BISMUTH-DOPED SEMI-INSULATING GROUP III NITRIDE WAFER," by Tadao Hashimoto, Edward Letts, and Sierra Hoff.

[0014] U.S. Patent Application No. 13 / 833,443 (attorney docket number SIXPOI-014US1), titled "METHOD OF GROWING GROUP III NITRIDE CRYSTALS," filed on March 15, 2013, by Tadao Hashimoto, Edward Letts, and Sierra Hoff.

[0015] U.S. Patent Application No. 13 / 834,015 (attorney docket number SIXPOI-014US2), titled "METHOD OF GROWING GROUP III NITRIDE CRYSTALS," filed on March 15, 2013, by Tadao Hashimoto, Edward Letts, and Sierra Hoff.

[0016] U.S. Patent Application No. 13 / 834,871 (attorney docket number SIXPOI-015US1), filed on March 15, 2013, entitled "GROUP III NITRIDE WAFER AND ITS PRODUCTION METHOD" by Tadao Hashimoto, Edward Letts, and Sierra Hoff.

[0017] U.S. Patent Application No. 13 / 835,636 (attorney docket number SIXPOI-015US2), filed on March 15, 2013, by Tadao Hashimoto, Edward Letts, and Sierra Hoff, entitled "GROUP III NITRIDE WAFER AND ITS PRODUCTION METHOD"

[0018] U.S. Patent Application No. 13 / 798,530 (attorney docket number SIXPOI-016US), filed on March 13, 2013, by Tadao Hashimoto, entitled "GROUP III NITRIDE WAFERS AND FABRICATION METHOD AND TESTING METHOD"

[0019] U.S. Patent Application No. 14 / 329,730 (attorney docket number SIXPOI-017US), filed on July 23, 2014, by Tadao Hashimoto, entitled "ELECTRONIC DEVICE USING GROUP III NITRIDE SEMICONDUCTOR AND ITS FABRICATION METHOD"

[0020] Related to the above. All of the above applications are invoked by reference to them as a whole, as presented below. [Background technology]

[0021] (Field of invention) This invention relates to semiconductor electronic devices primarily used in high-power and / or high-frequency electrical and electronic circuits. In particular, this invention relates to transistors using group III nitride semiconductors. (Explanation of conventional technology)

[0022] (Note: This patent application references several publications and patents, as indicated by the numbers in parentheses, e.g., [x]. A list of these publications and patents can be found in the section titled (References).)

[0023] Gallium nitride (GaN) and its related Group III nitride mixed crystals are key semiconductor materials for various electronic devices such as power switching transistors. Despite the theoretical maximum performance of GaN, estimated by Baliga's figure of merit (BFOM), being more than five times that of silicon carbide (SiC), GaN-based power switching devices are not performing to their full potential due to the difficulty of fabricating them and the lack of inexpensive, low-defect GaN substrates.

[0024] Currently, the vast majority of GaN devices are fabricated using Group III nitride thin films grown heteroepitaxially on heterosubstrates such as silicon (Si), SiC, and sapphire. Regarding GaN power devices, lateral field-effect transistors (FETs) fabricated on Si are commercially available. However, lateral devices have thin channels through which current flows, limiting the power they can achieve. Furthermore, the poor quality of GaN grown on Si makes it impossible to realize high-voltage devices exceeding 1500V.

[0025] Vertical GaN FETs fabricated on GaN substrates are ideal for applications requiring high power output and high reliability. Homoepitaxial growth on GaN substrates maintains a low dislocation density, resulting in low leakage current, high linearity, and high reliability. However, despite numerous development efforts, vertical GaN metal-oxide-semiconductor FETs (MOSFETs) have not yet reached their full potential. This is because fabricating the three-dimensional p-GaN structure necessary to prevent electric field concentration within the device is difficult.

[0026] Here, we will elaborate on the unique problems associated with these devices and their characteristics. [Overview of the project]

[0027] This invention discloses a GaN trench MOSFET and a method for manufacturing the same. The GaN trench MOSFET according to the present invention has a trench from the bottom to n - - The region up to the GaN drift layer contains an n-GaN region containing both Mg and donor impurities. By using ion implantation, an n-type region is formed at the bottom of the trench and the Mg-doped p-GaN region of the MOSFET. Furthermore, by removing a portion of the ion-implanted trench side surface by dry etching, an electron channel necessary for fabricating a GaN trench MOSFET can be formed between the Mg-doped p-GaN and the oxide film layer. [Brief explanation of the drawing]

[0028] Here, similar reference numbers refer to drawings that represent the corresponding parts throughout the entire sequence.

[0029] [Figure 1] Examples of conventional trench MOSFETs fabricated from materials other than GaN

[0030] In this drawing, the numbers indicate the following: 101 n-type substrate 102 n - Type drift layer 103 p-type region 104 Trench 104c Corner of the trench bottom 106 n-type source 107 Electronic Channels 108 gate insulating film 109 Gate Contact 110 Body Contact 111 Source Contact 112 Drain Contact 113 Deep p-type regions

[0031] Numbers 105 and 205 are not used to make it easier to compare the differences between a conventional trench MOSFET and the GaN trench MOSFET according to the present invention. Figures 3 and 4, which show the GaN trench MOSFET according to the present invention, show the structure corresponding to "5".

[0032] [Figure 2] Example of a conventional trench MOSFET fabricated with GaN

[0033] In this drawing, the numbers indicate the following: 201 n-GaN substrate 202 n - -GaN drift layer 203 p-GaN region 204 Trench 204c Corner of the bottom of the trench 206 n-GaN source 207 Electronic Channels 208 Gate Insulator 209 Gate Contact 210 Body Contact 211 Source Contact 212 Drain Contact

[0034] [Figure 3] Example of a GaN trench MOSFET according to the present invention

[0035] In this drawing, the numbers indicate the following: 1 GaN substrate 2 n - -GaN drift layer 3 Mg-doped GaN layer 4 Trench 4c Corner of the bottom of the trench 5 n-GaN region 6 n-GaN sources 7. Electron channels on p-GaN facets 8 gate insulating film 9 Gate Contact 10 Body Contact 11 Source Contact 12 Drain Contacts

[0036] [Figure 4] Figures 4A-K show an example of the fabrication procedure for a GaN trench MOSFET according to the present invention. 1 GaN substrate 2 n-GaN drift layer 3 Mg-doped GaN layer 4 Trench 4a Trench bottom 4b Trench side 4c Corner of trench bottom 5 n-GaN region 6 n-GaN source 6a Ion implantation mask for n-GaN source 7 Electron channel on p-GaN facet 8 Gate insulating film 9 Gate contact 10 Body contact 11 Source contact 12 Drain contact [Modes for carrying out the invention]

[0037] (Detailed description of the invention) (Problems that the invention aims to solve) 1. Examination of existing trench MOSFETs and their problems A. Existing MOSFETs made from semiconductors other than GaN, such as Si or SiC. Various trench MOSFETs have been fabricated using Si and SiC semiconductors. Reference 1 is a review of trench MOSFETs, and Figure 1 shows an example of a conventional trench MOSFET. Low concentration doping (i.e., n - A drift layer 102 is grown on an n-type substrate 101. During operation, a high voltage is applied to this drift layer. Due to this high voltage, the carrier density of the drift layer is 10 16 cm -3The voltage is set to a value of 1 or lower, maximizing the critical breakdown field of this layer. A p-type region 103 and a deep p-type region 113 are formed on the drift layer by ion implanting electron acceptors several times. In the case of Si and SiC, a p-type region can be easily formed by ion implanting acceptors into the drift layer 102. Subsequently, an n-type source 106 is formed by ion implanting donors onto the surface. A trench 104 is formed by etching the p-type material, after which a gate insulating film (usually silicon dioxide) and gate metal are deposited. The p-body contact 110, source contact 111, and drain contact 112 are formed using conventional semiconductor metal deposition techniques. The p-body contact 110 and source contact 111 are short-circuited to fix the potential of the p-type region and the deep p-type region to the source potential.

[0038] One of the key technologies for achieving high breakdown voltages in conventional MOSFETs is the deep p-type region. Without the deep p-type region, the electric field concentrates at the corner of the trench bottom, causing physical breakdown at the corner 104c of the trench bottom and irreparably damaging the trench. To prevent this problem, the deep p-type region extends to the substrate 101. The breakdown that occurs at the interface between the deep p-type region and the drift layer is not physical collapse but electron avalanche collapse, so the dielectric breakdown does not cause irreparable damage. In other words, the device that has recovered from electron avalanche collapse can be used again. B. Conventional MOSFETs using GaN semiconductors

[0039] GaN is a wide-bandgap semiconductor, and its material properties surpass those of SiC. Therefore, much research has been conducted to develop GaN trench MOSFETs. However, because it is difficult to obtain p-GaN by ion implantation of an acceptor (usually Mg), the reported devices, as shown in references 2 and 3, lack the deep p-type region described above. Figure 2 shows an example of a conventional GaN trench MOSFET. GaN trench MOSFETs typically have n-type regions on a GaN substrate. -- The -GaN drift layer 202 is grown, and a GaN layer doped with an acceptor is grown on the drift layer 202, followed by a p-type activation heat treatment (usually about 800 °C) for fabrication. Then, the trench 204 is formed by dry etching. As shown in FIG. 2, the bottom of the etched trench reaches the n - -GaN drift layer 202. In FIG. 2, it can be seen that the gate insulating film 208 and the gate contact 209 are located at a position lower than the interface between the p-GaN region and the n - -GaN drift layer 202. Since there is no deep p-type region in the GaN trench MOSFET, the breakdown of the device physically occurs at the corner 204c at the bottom of the trench, resulting in a non-reparable breakdown of the device.

[0040] As an attempt to fabricate a deep p-type region, research has been conducted on ion-implanting an acceptor (such as Mg) into GaN to make it p-type. It has been reported that p-GaN can be obtained by heat treatment at high pressure (about 1 GPa) and high temperature (1000 °C or higher) after Mg ion implantation, but the high-temperature and high-pressure heat treatment is not suitable for mass production.

[0041] Another possible method for fabricating a deep p-type region is to - etch the n-GaN drift layer and selectively grow p-GaN. However, silicon impurities usually accumulate at the regrowth interface, resulting in a problem of high leakage current under high-voltage bias. (Means for Solving the Problem) 2. The Present Invention

[0042] To realize a practical GaN trench MOSFET having a deep p-type region, the present invention provides a new structure and fabrication procedure described below. FIG. 3 is an example of the GaN trench MOSFET of the present invention. The device has an n - -GaN drift layer 2 grown on a GaN substrate 1. Similar to the conventional MOSFET, the electron density of the n - -GaN is 10 16 cm -3 below or less, preferably 2×10 16 cm-3 More preferably 8x10 15 cm -3 The following is stated: The p-type Mg-doped GaN layer 3 is n - -Although located above the GaN drift layer, it is separated by the n-GaN region 5 below the trench 4. One of the important steps in this invention is the formation of the n-GaN region 5. The n-GaN region 5 is formed by ion implanting a donor into a portion of the Mg-doped GaN layer 3. The carrier concentration of the n-GaN region 5 is n - -The value is close to the carrier concentration of the GaN drift layer, n - - The carrier concentration of the GaN drift layer is within + / - 50% of the carrier concentration difference. Preferably 10 16 cm -3 It is below [number] units.

[0043] As shown in Figure 3, in the final device, the n-GaN region 5 is almost below the trench, n - - It extends vertically to the GaN drift layer 2. The n-GaN region 5 also extends laterally from the trench side, and the edge of the n-GaN region contacts the electron channel 7 on the p-GaN facet, thereby collecting electrons passing through the electron channel 7 on the p-GaN facet below the gate insulating film. In this structure, n - - The interface between the p-GaN formed from the GaN drift layer 2 and the Mg-doped GaN layer 3 is closer to the substrate 1 than the interface with the n-GaN region 5 and the edge of the electron channel on the p-GaN facet. Therefore, electric field concentration does not occur at the corner 4c of the trench bottom. Dielectric breakdown occurs between the p-GaN and n formed from the Mg-doped GaN layer 3. - - This occurs at the interface of the GaN drift layer and manifests as electron avalanche decay rather than physical destruction.

[0044] To form electron channels 7 on p-GaN facets formed from the Mg-doped GaN layer 3, the p-GaN facets are formed by dry etching. The p-GaN facets are preferably (101), (201), or (102) planes in crystallographic orientation. The (101), (201), and (102) planes are at angles of approximately 62°, 75°, and 43° from the c-plane, respectively. These crystallographic planes are stable, making it difficult for surface states to form during the deposition of the insulating film layer. The fabrication procedure will be described in detail later.

[0045] Figure 4 shows an example of the fabrication procedure for the GaN trench MOSFET of the present invention. The fabrication is first carried out on an n-GaN substrate 1. - The process begins with growing the n-GaN drift layer 2 (Figure 4A). While n-GaN substrates fabricated by any method can be used, it is preferable to use a GaN substrate with a low dislocation density. GaN substrates fabricated by the ammonothermal method typically have a density of 2 x 10⁻¹⁶. 5 cm -2 It has a dislocation density of 5x10 or less, which is about an order of magnitude lower than that of GaN substrates fabricated by vapor phase growth. 5 cm -2 It is preferable to use a substrate with a dislocation density of less than n. - - The GaN drift layer is preferably grown using metal-organic vapor deposition (MOCVD) because MOCVD allows for the growth of GaN layers with low impurity concentrations at a practical rate (approximately 5 microns / hour).

[0046] After growing the drift layer, Mg-doped GaN layer 3 is grown. The growth of Mg-doped GaN layer 3 is n - - To prevent the accumulation of silicon impurities at the interface between the GaN drift layer 2 and the Mg-doped GaN layer 3, n - -It is preferable to grow the GaN drift layer 2 without interruption immediately after growth (Figure 4B). After growth, the wafer is heat-treated at approximately 800°C to activate the Mg impurities. Through this activation heat treatment, the Mg-doped GaN layer 3 becomes p-type GaN.

[0047] After growth, the wafer is removed from the growth apparatus and a trench 4 is formed by etching using an appropriate mask. The etching mask can be a photoresist, a metal layer, or a dielectric layer. Dry etching is preferable to create trenches with nearly vertical sides. A trench bottom 4a and trench side 4b are formed in the trench 4 (Figure 4C). Etching is performed on the bottom surface n - It is important to stop before reaching the interface between the p-GaN formed from the -GaN drift layer 2 and the Mn-doped GaN layer 3. Furthermore, in order to convert most of this region into n-GaN during ion implantation of the p-GaN at the bottom surface 4a of the trench 4 after trench formation, the bottom surface 4a of the trench is n - It is important to place the -GaN drift layer 2 and the Mn-doped GaN layer 3 in a location close enough to the interface of the p-GaN. In practice, it is desirable to make the thickness of this region from the bottom of the trench to the drift layer less than 1 micron, preferably less than 0.5 microns, and more preferably about 0.2 microns or less.

[0048] Subsequently, donor impurities are ion-implanted into the wafer. Any donor impurities such as Si, O, and Ge can be used, but Si is the most common donor for GaN, so it is preferable to use Si. The doping concentration is such that the region below the bottom of the trench becomes n-GaN, and its electron density is n - - A value close to the electron density of the GaN drift layer, n - -Adjust the concentration so that it falls within a difference of + / - 50% in the electron density of the GaN drift layer. As explained above, the electron concentration is 10 16 cm -3 One or less, preferably 2x10 16 cm -3 Less than 8x10 15 cm -3 It is desirable to keep it below a certain value. This converts the region below the bottom of the trench to n-GaN (n-GaN region 5). Then, all regions near the exposed surface (trench side and n-GaN source region) become n-type as shown in Figure 4D.

[0049] To increase the electron concentration and form the n-GaN source 6, it is preferable to protect the trench with a mask 6a and perform further donor ion implantation into the n-GaN source region 6 (Figure 4E). After ion implantation, the mask 6a is removed.

[0050] To remove the n-GaN region formed on the trench side surface and expose the p-GaN, the n-GaN region is removed by dry etching as shown in Figure 4F. The angle of the facets is precisely controlled to expose the p-GaN facets while retaining a portion of the n-GaN region below the trench bottom. Details of the technique for controlling the angle are well known and are described in Reference 6, which is included throughout this specification. It is preferable to perform dry etching using a photoresist mask to control the facet angle. The surface on the p-GaN facet becomes an electron channel 7.

[0051] When the electron channel 7 is exposed, a gate insulating film 8 is deposited as shown in Figure 4G. The gate insulating film pattern can be created using conventional semiconductor manufacturing processes. As is well known in the prior art, an appropriate gate insulating film material is selected to minimize the interfacial energy levels. Aluminum nitride, aluminum oxide, silicon nitride, or silicon oxide are preferred, but novel insulating materials may be used to reduce and minimize surface energy levels.

[0052] Using a conventional semiconductor process, the gate contact 9 is deposited on the gate insulating film 8 (Figure 4H), forming a p-type body contact 10 (Figure 4I), and then the source contact 11 (Figure 4J) and drain contact 12 (Figure 4K) are formed. (Modes for carrying out the invention) Example 1

[0053] GaN bulk crystals are grown by near-equilibrium ammonothermal method. GaN bulk crystals are grown on the c-plane of GaN seed crystals. Bulk GaN is sliced, ground, lapped, polished, and chemically mechanically polished to obtain a dislocation density of 2x10⁻¹⁶. 5 cm -3, carrier concentration 2x10 18 cm -3 A c-plane 2" GaN substrate with an off-angle of 0.04° in the m-axis direction and 0.00° in the a-axis direction is fabricated.

[0054] 10 micron thick n - - A GaN drift layer and a 0.9 micron thick Mg-doped GaN layer are grown using the MOCVD method with trimethylgallium and ammonia. - - To dope the GaN drift layer with a low concentration of Si, SiH4 gas diluted with hydrogen is introduced during the growth of the drift layer. - - The electron density of the GaN drift layer is 1x10⁻¹⁶ 16 cm -3 To grow the Mg-doped GaN layer, biscyclopentadienylmagnesium (CpMg), transported by hydrogen gas, is introduced into an MOCVD reactor. After MOCVD growth, the wafer is removed from the MOCVD reactor and heat-treated at 800°C in a nitrogen atmosphere to activate the Mg dopant. Through this activation heat treatment, the Mg-doped GaN layer is converted into a p-GaN layer. The Mg concentration of the p-GaN layer is 2 x 10⁻¹⁶. 18 cm -3 That is the case.

[0055] The wafer undergoes a photolithography process, followed by dry etching to form trenches on the wafer. A commonly known method involves inductively coupled plasma (ICP) etching using Cl2 gas, with photoresist acting as a mask to obtain trenches with vertical sides. Viewed from above, the trenches are hexagonal, with the distance between opposite vertices approximately 1 micron. The trench edges align with the m-plane of GaN. The trench depth is approximately 0.7 microns. Dry etching is performed using n - -The process ends before the GaN drift layer 2 is exposed, and the trench bottom and n - - A p-GaN region of approximately 0.2 microns is left sandwiched between the GaN drift layer and the p-GaN layer interface.

[0056] Si ion implantation was performed on the wafer without masking, and the trench bottom surface and n - - The p-GaN region sandwiched at the interface between the GaN drift layer and the p-GaN layer is converted. After ion implantation, the wafer is heat-treated at 800°C in nitrogen gas to activate the Si. As a result, the electron density in this region is approximately 1 x 10⁻¹⁶. 16 cm -3 n - - This matches the electron density of the GaN drift layer. The electron density in this region is n - - It is preferable to control the electron density of the GaN drift layer to within + / - 50%.

[0057] To increase the electron density in the source region, the trench bottom and sides are covered with a dielectric mask, and then additional Si ion implantation is performed. The electron density in the n-GaN source region is approximately 5 x 10⁻¹⁶. 18 cm -3 After ion implantation, the dielectric mask is removed by wet etching or the like.

[0058] To expose the p-GaN facets that form the electron channels, inductively coupled plasma (ICP) etching is performed using a photoresist mask. In this case, different types and thicknesses of photoresist are used to expose the (101) plane of p-GaN. The angle of the facets is approximately 62° from the (002) plane of the reference plane. Detailed methods for adjusting the facet angles are described in reference 6. In this way, a portion of the n-GaN on the side surface of the trench is removed, and the p-GaN facets are exposed. Subsequently, an alumina layer and an SiO2 layer are deposited as gate dielectric films, and Ti / Al is deposited as gate contacts. The gate contacts are patterned using conventional semiconductor processes.

[0059] Similarly, using conventional semiconductor processes, body contacts are formed on the p-GaN layer by dry etching n-GaN and pattern deposition of Ni / Au. Finally, Ti / Al source contacts and Ti / Al drain contacts are formed to complete the GaN MOSFET structure.

[0060] The completed GaN MOSFET structure has a deep p-type region. The breakdown voltage exceeds 1000V, and the trench bottom is p-GaN and n - -Failure occurs in locations other than trenches because it is further from the substrate than the interface of the GaN drift layer. The device according to the present invention uses p-GaN and n - -The dielectric breakdown occurring at the interface of the GaN drift layer is an electron avalanche collapse, not a physically destructive mode, so the device will not be destroyed in an irreparable (physical) way. By preventing the physical destruction at the bottom of the trench that occurs in conventional devices shown in Figure 2, the device according to the present invention is more reliable. In addition, the device structure according to the present invention prevents electric field concentration at the corners of the trench bottom, enabling a higher breakdown voltage than conventional devices. (Possible modifications)

[0061] In preferred embodiments, the use of a GaN substrate fabricated by an ammonothermal process is described, but GaN substrates manufactured by other methods such as the HVPE method may also be used.

[0062] In preferred embodiments, MOCVD is used for growing the layer structure, but other methods such as HVPE or molecular beam epitaxy may be used.

[0063] In preferred embodiments, ICP etching is used to form trenches, but other dry etching methods such as reactive etching (RIE) may be used.

[0064] The preferred embodiments of the present invention described above are presented for illustrative and explanatory purposes only. They are not intended to define the invention in minute detail or to limit it to the disclosed forms. Many modifications and changes are possible, provided that the essential points taught by the above embodiments are captured. The essential points of the present invention are not limited by this detailed description but are defined by the supplementary claims. (References)

[0065] The following references are incorporated herein by reference.

[0066] [1] RKWilliams, et al., “The Trench Power MOSFET: Part I - History, Technology, and Prospects,” IEEE Transactions, on Electron Devices Vol. 64 (2017) 674.

[0067] [2] T.Oka, et al., “1.8mΩcm 2 vertical GaN-based trench metal-oxide-semiconductor field-effect transistors on a free-standing GaN substrate for 1.2-kV-class operation,” Applied Physics Express 8 (2015) 054101.

[0068] [3] R.Li, et al., “600V / 1.7mΩcm 2 Normally-Off GaN Vertical Trench Metal-Oxide-Semiconductor Field-Effect Transistor,” IEEE Electron Devices 37 (2016) 1466.

[0069] [4] H. Sakurai, et al., “Highly effective activation of Mg-implanted p-type GaN by ultra-high-pressure annealing,” Appl. Phys. Lett. 115 (2019) 142104.

[0070] [5] A. Uedono, et al., “Effects of ultra-high-pressure annealing on characteristics of vacancies in Mg-implanted GaN studies using monoenergitic positron beam,” Sci. Rep. 10 (2020) 17349. https: / / doi.org / 10.1038 / s41598-020-74362-9.

[0071] [6] H. Hahn, et al., “Influence of mask material and process parameters on etch angle in a chlorine-based GaN dry etch,” J. Vac. Sci. Technol. A30 (2012) 051302.

[0072] These references are incorporated as a whole by reference, as if they were fully described herein, and in particular the method for fabricating GaN trench MOSFETs, the activation of Mg ion-implanted p-GaN, and the method for fabricating inclined walls by etching through the selection of mask material and process conditions are incorporated into the specification.

Claims

1. Fabricated on an n-type GaN substrate, a) n in contact with the interface of the n-type GaN substrate (1) － Type GaN drift layer (2), b) A p-type GaN layer (3) with Mg added, which is in contact with the interface of the drift layer. c) A trench (4) having an inclined surface (7) formed in the p-type GaN layer to which the Mg has been added, d) The n-type GaN region (5) located below the bottom surface of the trench, e) An n-type GaN source (6) located above the Mg-added GaN layer (3) and outside the region of the trench (4), The n-type GaN region (5) contains both Mg and donor impurities, A GaN trench MOSFET (Figure 3) characterized in that the inclined surface formed on the Mg-doped p-type GaN layer is a plane selected from the (101), (201), or (102) crystal planes.

2. The GaN trench MOSFET according to claim 1, wherein the n-type GaN region extends from the bottom of the trench to the drift layer.

3. The GaN trench MOSFET according to claim 1 or 2, characterized in that the n-type GaN region extends laterally from below the trench and from the bottom surface of the trench, so that the interface between the drift layer and the Mg-doped p-type GaN layer is closer to the substrate than the interface between the n-type GaN region and the Mg-doped p-type GaN layer.

4. The electron density of the n-type GaN region is n － The GaN trench MOSFET according to claim 1 or 2, characterized in that the difference in electron density of the type GaN drift layer is within + / - 50%.

5. The GaN trench MOSFET according to claim 1 or 2, characterized in that the trench has a plurality of inclined surfaces of the p-type GaN layer, and each of the surfaces is selected from the (101), (201), or (102) planes.

6. The GaN trench MOSFET according to claim 1 or 2, characterized in that the trench is hexagonal.

7. In the method for manufacturing a GaN trench MOSFET (a) When the MOSFET is placed vertically, n is on an n-type GaN substrate and under p-type GaN with Mg added. － A step of forming a trench in p-type GaN to which Mg has been added, having a structure with a drift layer of type GaN. (b) A step of converting the region between the trench bottom and the drift layer of the Mg-doped p-type GaN to an n-type conductive type by donor ion implantation. (c) A step of etching a part of the side surface of the trench to expose the inclined surface of the Mg-doped p-type GaN, and (d) A step of forming a source region of n-type GaN outside the trench region. A method for manufacturing a GaN trench MOSFET, characterized by having the following features.

8. The method for producing a GaN trench MOSFET according to claim 7, characterized in that Si is used in the donor ion implantation.

9. The method for manufacturing a GaN trench MOSFET according to claim 7 or 8, characterized in that the angle between the side surface of the trench and the n-type GaN substrate is steeper than the angle between the inclined surface of the Mg-doped p-type GaN and the n-type GaN substrate.

10. The method for manufacturing a GaN trench MOSFET according to claim 7 or 8, characterized in that the inclined surface of the Mg-doped p-type GaN is a surface selected from the (101), (201), or (102) surfaces.

11. The aforementioned n － The electron density of the drift layer of type GaN is 2 x 10⁻¹⁰ １６ cm －３ Even smaller, the electron density in the region between the trench bottom of the Mg-doped p-type GaN layer and the drift layer is 2 x 10 １６ cm －３ A method for manufacturing a GaN trench MOSFET according to claim 7 or 8, characterized by being smaller.

12. The dislocation density of the n-type GaN substrate is 2x10 ５ cm －２ The method for manufacturing a GaN trench MOSFET according to claim 7 or 8, characterized in that the dislocation density is less than this value.

13. The method for manufacturing a GaN trench MOSFET according to claim 7 or 8, characterized in that the trench is hexagonal.

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