Semiconductor equipment

Abstract

The present invention achieves high-speed switching operations of a power transistor. In the present disclosure, a portion of wire connections that are provided to various connection sites of a power semiconductor device is or are replaced with a flip-chip connection or connections using bump electrodes, and a capacitor is positioned adjacent to a driver chip in which a gate driver is formed.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device using a wide bandgap semiconductor material having a larger bandgap than silicon.

Background Art

[0002] Japanese Unexamined Patent Application Publication No. 2016-92100 (Patent Document 1) describes a technique related to a semiconductor device (power module) in which a signal output terminal of a control element is bump-connected face-down to a gate electrode pad of a semiconductor switching element mounted on a frame with the element surface facing up and an internal lead of a conversion substrate.

[0003] Japanese Unexamined Patent Application Publication No. 2011-23654 (Patent Document 2) describes a technique related to a power module in which a drive signal of a drive IC is flip-chip connected to a signal pad of a power element mounted on a heat sink with the element surface facing up.

[0004] Japanese Patent Application Publication No. 2005-510878 (Patent Document 3) describes a technique related to a multi-chip module in which a first bump electrode of a flip chip (gate drive circuit) is bump-connected to a gate contact and a source connection of a power transistor die mounted on a base portion of a lead frame with the element surface facing up.

[0005] Japanese Unexamined Patent Application Publication No. 2010-040814 (Patent Document 4) describes a technique related to a power transistor in which a gate electrode, a source electrode, and a drain electrode are formed on the same surface of a semiconductor chip.

[0006] Non-Patent Document 1 describes a technique of connecting between an output terminal pad of a CMOS gate driver chip and a gate terminal pad of a power transistor with a bonding wire.

Prior Art Documents

Patent Documents

[0007] [Patent Document 1] Japanese Patent Publication No. 2016-92100 [Patent Document 2] Japanese Patent Publication No. 2011-23654 [Patent Document 3] Special Publication No. 2005-510878 [Patent Document 4] Japanese Patent Publication No. 2010-040814 [Non-patent literature]

[0008] [Non-Patent Document 1] A. Yao et al., IEICE Electronics Express, Vol.18, No.14, (2021), Pages 20210234 [Overview of the project] [Problems that the invention aims to solve]

[0009] For example, power transistors using wide-bandgap semiconductor materials (hereinafter referred to as WG semiconductor materials), such as silicon carbide (SiC), which have a larger bandgap than silicon, can achieve lower losses and faster switching operation compared to power transistors using silicon. For this reason, power transistors using WG semiconductor materials are expected to be the next generation of power transistors.

[0010] In this regard, in order to maximize the high-speed switching characteristics of power transistors using WG semiconductor materials and improve circuit characteristics, it is desirable to reduce the parasitic inductance of the gate drive circuit that limits the switching speed. [Means for solving the problem]

[0011] A semiconductor device in one embodiment includes a main chip having a first surface and a first back surface, on which a power transistor having a gate, source, and drain is formed; a driver chip having a second surface and a second back surface, on which a drive circuit for driving the power transistor is formed; a wiring component having an upper surface and a lower surface, electrically connected to the driver chip; and a capacitor mounted on the wiring component.

[0012] Here, the first surface is provided with a gate pad connected to the gate of the power transistor and a source pad connected to the source, and the second surface is provided with a signal input pad, a signal output pad, a first power supply pad, and a second power supply pad for the drive circuit. The wiring components include input wiring connected to the signal input pad, first power supply wiring connected to the first power supply pad, and second power supply wiring connected to the second power supply pad.

[0013] The first power wiring has a first end close to the connection area with the first power pad, and a first other end which is the opposite end of the first end; the second power wiring has a second end close to the connection area with the second power pad, and a second other end which is the opposite end of the second end.

[0014] In this configuration, the driver chip is flip-chip connected to the main chip and wiring components such that the second surface is partially opposite the first surface and wiring components, the signal output pad is electrically connected to the gate pad, the signal input pad is electrically connected to the input wiring, the first power pad is electrically connected to the first power wiring, and the second power pad is electrically connected to the second power wiring. The capacitor is provided to be electrically connected to both the first and second power wirings and is positioned closer to the first end than the other end and closer to the second end than the other end.

[0015] A semiconductor device in one embodiment includes a main chip having a first surface and a first back surface on which a power transistor is formed, and a driver chip having a second surface and a second back surface on which a drive circuit for driving the power transistor is formed.

[0016] Here, on the first surface, a gate pad and a source pad of the power transistor are provided, and on the second surface, a signal input pad of the drive circuit, a first power supply pad for applying a first potential to the drive circuit, and a second power supply pad for applying a second potential lower than the first potential to the drive circuit are provided. On the second back surface, a signal output pad of the drive circuit connected to the gate pad is provided.

[0017] At this time, the driver chip is arranged on the main chip such that the second back surface is arranged opposite to the first surface and the signal output pad is electrically connected to the gate pad, and the capacitor is provided on the second surface so as to be electrically connected to both the first power supply pad and the second power supply pad.

Advantages of the Invention

[0018] According to one embodiment, the parasitic inductance of the gate drive circuit can be reduced. As a result, a high-speed switching operation of the power transistor becomes possible.

Brief Description of the Drawings

[0019] [Figure 1] It is a circuit diagram for explaining the circuit configuration of a power semiconductor device in the related art. [Figure 2] It is a diagram for explaining the basic idea. [Figure 3] It is a diagram for explaining the improvement points of the basic idea. [Figure 4] It is a diagram for explaining further improvement points of the basic idea. [Figure 5] It is a diagram showing the layout of the main chip. [Figure 6] It is a diagram showing the layout of the driver chip. [Figure 7] It is a diagram showing the layout of the wiring board. [Figure 8] It is a plan view showing the mounting configuration of the power semiconductor device in Embodiment 1. [Figure 9]This is a cross-sectional view taken along line AA in Figure 8. [Figure 10] This is a plan view showing a power semiconductor device in a modified example. [Figure 11] This graph shows the relationship between the drain-source voltage and time when a power transistor is turned on. [Figure 12] This diagram illustrates the overview of the power semiconductor device in embodiment 2. [Figure 13] This is a diagram showing the layout of the driver chip. [Figure 14] This is a plan view showing the implementation configuration of the power semiconductor device in embodiment 2. [Figure 15] This is a cross-sectional view taken along line AA in Figure 14. [Modes for carrying out the invention]

[0020] In all the drawings illustrating the embodiments, the same reference numeral is used for identical components, and repeated explanations of them are omitted. Hatching may be used even in plan views to improve clarity.

[0021] Furthermore, in this specification, words may be abbreviated to improve readability. For example, a power transistor (Tr) may be written as "Tr," and a gate driver (GD) may be written as "GD."

[0022] <Advantages of wide-bandgap semiconductors> Power semiconductor devices are required to have high voltage resistance, low on-resistance, and low switching losses, among other things. Currently, the mainstream power semiconductor devices are field-effect transistors (FETs) formed on semiconductor substrates mainly composed of silicon, but these power semiconductor devices are approaching their theoretical performance limits.

[0023] In this regard, semiconductor devices containing FETs formed on semiconductor substrates mainly composed of WG semiconductor material (hereinafter referred to as WG power semiconductor devices) are attracting attention.

[0024] This is because a large band gap means that the dielectric breakdown strength is high, making it easier to achieve high voltage resistance.

[0025] Furthermore, if the semiconductor material itself has high dielectric breakdown strength, the dielectric strength can be maintained even if the drift layer that maintains the dielectric strength is thin. For example, by thinning the drift layer and increasing the impurity concentration, the on-resistance of the WG power semiconductor device can be reduced.

[0026] In other words, WG power semiconductor devices excel in their ability to achieve both improved voltage withstand capability and reduced on-resistance, which are typically in a trade-off relationship. Furthermore, WG power semiconductor devices, possessing these advantages, also offer the benefit of high-temperature operation and high-speed switching due to their larger bandgap.

[0027] The technical concept in this embodiment relates to a WG power semiconductor device using WG semiconductor materials. Examples of WG semiconductor materials include compound semiconductors such as silicon carbide (SiC) and gallium nitride (GaN).

[0028] However, the technical concepts in this embodiment are not limited to these and can be broadly applied to WG power semiconductor devices using WG semiconductor materials.

[0029] In the following, we will explain using silicon carbide-based WG semiconductor devices (hereinafter referred to as SiC power semiconductor devices) as an example.

[0030] Because silicon carbide has a dielectric breakdown field strength approximately one order of magnitude greater than that of silicon, the on-resistance (device resistance) can theoretically be reduced by more than three orders of magnitude by making the drift layer, which is necessary to ensure voltage resistance, approximately one order of magnitude thinner and increasing the impurity concentration by approximately two orders of magnitude. Furthermore, because its bandgap is approximately three times larger than that of silicon, high-temperature operation and high-speed switching operation are possible, and SiC power semiconductor devices are expected to achieve performance exceeding that of silicon power semiconductor devices. In particular, this embodiment focuses on the high-speed switching characteristics among the excellent characteristics of SiC power semiconductor devices. In this case, in order to maximize the high-speed switching characteristics of the SiC power semiconductor device and improve the circuit characteristics, it is necessary to reduce the parasitic inductance that limits the switching speed.

[0031] In this specification, a SiC power semiconductor device is used as an example of a WG semiconductor device, and hereafter, a SiC power semiconductor device will simply be referred to as a power semiconductor device. The power semiconductor device referred to in this specification includes a power transistor and a gate driver, and it is assumed that both the power transistor and the gate driver use silicon carbide as the semiconductor material. Furthermore, while a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is assumed as the power transistor in this description, the technical concept in this embodiment is not limited to this and can also be applied to embodiments in which the power transistor is composed of an IGBT (Insulated Gate Bipolar Transistor).

[0032] <Explanation of related technologies> In this specification, "related technology" refers to technology that is not publicly known but has a problem identified by the present inventor, and is a technology that forms the basis of this disclosure.

[0033] Figure 1 is a circuit diagram illustrating the circuit configuration of a power semiconductor device in the related technology.

[0034] In Figure 1, the power semiconductor device includes a power transistor Tr and a gate driver GD. The "Tr" has a gate electrode G, a source S, and a drain D.

[0035] The power transistor Tr is formed inside the main chip, which is a silicon carbide semiconductor chip. The main chip has a first surface and a first back surface. For example, the first surface has a gate pad electrically connected to the gate electrode G of "Tr" and a source pad electrically connected to the source S of "Tr". On the other hand, the drain electrode of "Tr" is formed on the first back surface. Although the gate pad, source pad, and drain electrode are not shown in the circuit diagrams Figures 1 to 4, the layout of the gate pad and source pad formed on the first surface of the main chip is shown, for example, in Figure 5, which will be described later. The embodiment of the power semiconductor device including the main chip on which the gate pad and source pad are formed will be explained using Figure 8, which will be described later.

[0036] Here, in the circuit diagrams Figures 1 to 4, the term "gate electrode G" of the power transistor Tr is used to include not only the gate electrode of "Tr" formed inside the main chip, but also the gate pad formed on the first surface of the main chip. In other words, in the explanation of the circuit diagrams Figures 1 to 4, when we say "gate electrode G," we mean to include not only the gate electrode of "Tr" but also the gate pad.

[0037] Furthermore, in the circuit diagrams Figures 1 to 4, the term "source S" of the power transistor Tr is used to include not only the source of the "Tr" formed inside the main chip, but also the source pad formed on the first surface of the main chip. In other words, in the explanation of the circuit diagrams Figures 1 to 4, when we say "source S", we mean to include not only the source electrode of the "Tr" but also the source pad. In addition, in the circuit diagrams Figures 1 to 4, the term "drain D" of the "Tr" is used to mean the drain electrode formed on the first back surface of the main chip.

[0038] Next, source S is electrically connected to power source PS, while drain D is electrically connected to power drain PD.

[0039] Here, the term "power source PS" as used herein refers to a source terminal, which is an external connection terminal connected to the source pad (source S) of the main chip by a bonding wire (hereinafter referred to as "wire"). This power source PS is composed of, for example, leads and may also be referred to as a power source terminal.

[0040] Furthermore, as used herein, "power drain PD" refers to a drain terminal, which is an external connection terminal drawn out from the chip mounting section on which the main chip is mounted. In other words, a power drain PD refers to a drain terminal connected to the drain electrode (drain D) of the main chip via the chip mounting section. This power drain PD is composed of, for example, leads and may also be called a power drain terminal.

[0041] Thus, in this specification, we distinguish between source S and power source PS, and between drain D and power drain PD. Referring to Figure 1 with this in mind, we see that a wire WS is interposed between source S and power source PS, resulting in the parasitic inductance present in the wire WS. In other words, in related technologies, a parasitic inductance caused by the wire WS exists between source S and power source PS. On the other hand, since there is no wire interposed between drain D and power drain PD, the parasitic inductance present in the wire is not shown.

[0042] Next, the gate driver GD is a drive circuit that drives the power transistor Tr, and is formed inside the driver chip, which is a silicon carbide semiconductor chip. The driver chip has a second surface and a second back surface. For example, the second surface has an input pad to which an input signal can be input, an output pad electrically connected to the gate pad, a first power supply pad to which a first potential can be applied, and a second power supply pad to which a second potential smaller than the first potential can be applied.

[0043] Although the input pads, output pads, first power supply pad, and second power supply pad are not shown in the circuit diagrams Figures 1 to 4, the layout of the input pads, output pads, first power supply pad, and second power supply pad formed on the second surface of the driver chip is shown, for example, in Figure 6, which will be described later. The embodiment of the power semiconductor device including the driver chip on which these pads are formed will be explained using Figure 8, which will be described later.

[0044] As shown in Figure 1, the gate electrode G is electrically connected to the output pad of the gate driver GD via wire W. As a result, in related technologies, a parasitic inductance exists between the output pad of the gate driver GD and the gate electrode G due to wire W.

[0045] Next, the power semiconductor device has a wiring board that is electrically connected to a driver chip. This wiring board has an upper surface and a lower surface, and the upper surface has an input wiring WL3 that is electrically connected to an input pad, a first power wiring WL1 that is electrically connected to a first power pad, and a second power wiring WL2 that is electrically connected to a second power pad.

[0046] As shown in Figure 1, the first power pad of the gate driver GD is connected to the first power wiring WL1 via wire W1A to supply power potential to the gate driver GD. The first power wiring WL1 is then electrically connected to the first power terminal TE1 via wire W1B. Therefore, in related technologies, parasitic inductance exists between the first power terminal TE1 and the first power pad of the gate driver GD due to wires W1A and W1B. Note that the power potential referred to here is the first potential, which is, for example, 25V.

[0047] Similarly, to supply a reference potential (ground potential, earth potential) to the gate driver GD, the second power pad of "GD" is connected to the second power wiring WL2 via wire W2A. The second power wiring WL2 is then electrically connected to the second power terminal TE2 via wire W2B. Therefore, in the related technology, parasitic inductance due to wires W2A and W2B exists between the second power terminal TE2 and the second power pad of the gate driver GD. Note that the reference potential referred to here is a second potential smaller than the first potential, for example, 0V.

[0048] Furthermore, in order to input the input signal to the gate driver GD, the input pad of "GD" is connected to the input wiring WL3 via wire W3A. Then, the input wiring WL3 is electrically connected to the input terminal TE3 via wire W3B. Therefore, in the related technology, parasitic inductance exists between the input terminal TE3 and the input pad of the gate driver GD due to wires W3A and W3B.

[0049] Furthermore, the power semiconductor device in the related technology is configured so that a power supply E can be connected between the first power supply terminal TE1 and the second power supply terminal TE2. In addition, the second power supply terminal TE2 is configured to be electrically connected to the power source PS.

[0050] As described above, the power semiconductor device in the related technology is configured accordingly.

[0051] Next, the gate driver GD is configured to include, for example, a CMOS drive circuit (CMOS inverter). Specifically, the CMOS drive circuit has a p-channel field-effect transistor (hereinafter referred to as pFET) and an n-channel field-effect transistor (hereinafter referred to as nFET) connected in series between the power supply potential and the reference potential. The gate electrodes of the pFET and the nFET are electrically connected to each other, and the input signal is input to the gate electrodes that are electrically connected to each other. On the other hand, the connection node between the pFET and the nFET becomes the output from the gate driver GD.

[0052] In a gate driver GD configured in this way, when a high-level signal is input, the nFET turns on while the pFET turns off. As a result, the gate driver GD outputs a reference potential via the on-up nFET, and this reference potential (0V) is applied to the gate electrode G of the power transistor Tr. This turns off "Tr".

[0053] In contrast, when a low-level signal is input to the gate driver GD, the nFET turns off while the pFET turns on. As a result, the power supply potential is output from the gate driver GD via the on-up pFET, and the power supply potential (25V) is applied to the gate electrode G of the power transistor Tr. This turns on "Tr".

[0054] In this way, it can be seen that the on / off state of the power transistor Tr can be controlled by the gate driver GD.

[0055] <Consideration of improvements> As shown in Figure 1, the related technology has wires at various connection points. As a result, the parasitic inductance caused by the wires at various connection points increases in the related technology. An increase in parasitic inductance means that the switching speed of the power transistor Tr decreases. In other words, in order to maximize the high-speed switching characteristics of the power transistor and improve the circuit characteristics, it is important to reduce the parasitic inductance that limits the switching speed, and the related technology has room for improvement from this perspective. That is to say, it is desirable to reduce the parasitic inductance that limits the switching speed in the related technology.

[0056] For example, if we focus on the connection between a power transistor Tr and a gate driver GD, a wire W is provided between the gate electrode G of "Tr" and the output pad of the gate driver GD, and the effect of parasitic inductance caused by this wire W becomes significant. This is because, for example, a large current of about 1A or more flows between the output pad of "GD" and the gate electrode G of "Tr," resulting in a large current flowing through wire W and thus a large effect of parasitic inductance.

[0057] Therefore, this embodiment incorporates measures to overcome the areas for improvement present in the related technologies described above. The technical concept behind these measures will be explained below.

[0058] <Basic Concept in the Embodiment> The basic concept of this embodiment is to replace some of the wire connections provided at various connection points of the power semiconductor device with flip-chip connections using bump electrodes, and to place a capacitor between the power supply potential and the reference potential, close to the driver chip in which the gate driver is formed. According to this basic concept, parasitic inductance caused by the wires can be reduced, resulting in the realization of high-speed switching operation.

[0059] Specifically, Figure 2 is a diagram that explains the basic concept.

[0060] In Figure 2, the basic concept is that the gate electrode G (gate pad) of the power transistor Tr and the output pad of the gate driver GD are connected via a flip-chip connection using bump electrodes, rather than by a wire W. According to this basic concept, the parasitic inductance between the gate electrode G and the output pad of "GD" can be reduced.

[0061] In particular, Figure 2 shows that the gate electrode G and the gate driver GD are connected by a line segment without parasitic inductance, thus demonstrating that the gate electrode G and the output pad of "GD" are connected via a flip-chip connection.

[0062] Furthermore, in the basic design, the first power pad of "GD" and the first power wiring WL1 on the wiring board are connected via a flip-chip connection using bump electrodes, rather than via a wire W1A. Also, in the basic design, the second power pad of "GD" and the second power wiring WL2 on the wiring board are connected via a flip-chip connection using bump electrodes, rather than via a wire W2A, and the input pad of "GD" and the input wiring WL3 on the wiring board are connected via a flip-chip connection using bump electrodes, rather than via a wire W3A.

[0063] In Figure 2, the first power supply wiring WL1 and the gate driver GD are connected by a line segment without parasitic inductance, indicating that the first power supply wiring WL1 and the first power supply pad of "GD" are flip-chip connected. Similarly, the second power supply wiring WL2 and the gate driver GD are connected by a line segment without parasitic inductance, indicating that the second power supply wiring WL2 and the second power supply pad of "GD" are flip-chip connected. Likewise, the input wiring WL3 and the gate driver GD are connected by a line segment without parasitic inductance, indicating that the input wiring WL3 and the input pad of "GD" are flip-chip connected.

[0064] This reduces parasitic inductance between the first power pad of the gate driver GD and "WL1" on the wiring board, between the second power pad of the GD and "WL2" on the wiring board, and between the input pad of the GD and "WL3" on the wiring board, according to the basic concept.

[0065] In this way, according to the basic concept, some of the wire connections at various connection points in the power semiconductor device are replaced with flip-chip connections using bump electrodes. As a result, according to the basic concept, the parasitic inductance that limits the switching speed of the power transistor (Tr) can be reduced, thereby enabling high-speed switching operation of the "Tr".

[0066] As shown in Figure 2, even in the basic design, wire W1B, which is provided between the first power supply wiring WL1 and the first power supply terminal TE1, wire W2B, which is provided between the second power supply wiring WL2 and the second power supply terminal TE2, and wire W3B, which is provided between the input wiring WL3 and the input terminal TE3, remain. Therefore, if a power supply E located outside the power semiconductor device is connected between "TE1" and "TE2", the parasitic inductance caused by wires W1B and W2B may affect the high-speed switching operation of the power transistor Tr.

[0067] Therefore, in the basic design, for example, as shown in Figure 2, capacitor CP1 is placed between the power supply potential and the reference potential, close to the driver chip on which the gate driver GD is formed. In other words, in the basic design, capacitor CP1 is connected between the first power supply wiring WL1 and the second power supply wiring WL2 so as to be closer to the driver chip on which the "GD" is formed than to the first power supply terminal TE1 and the second power supply terminal TE2. As a result, according to the basic design, even though wires W1B and W2B remain, the influence of parasitic inductance caused by wires W1B and W2B can be reduced.

[0068] The reason for this is explained below.

[0069] As shown in Figure 2, capacitor CP1, located between the first power supply wiring WL1 and the second power supply wiring WL2, is connected in parallel with power supply E located outside the power semiconductor device. This means that the voltage across both electrodes of capacitor CP1 is equal to the voltage of power supply E. In other words, capacitor CP1 functions as a power supply equivalent to power supply E.

[0070] As a result, as shown in Figure 2, placing capacitor CP1 close to the driver chip where the gate driver GD is formed is equivalent to placing the power supply E at the location of capacitor CP1. Therefore, in this case, wires W1B and W2B are located outside capacitor CP1, which functions as a power supply. From this, according to the basic concept, the power supply potential and reference potential are supplied to the gate driver GD by capacitor CP1, and wires W1B and W2B do not exist on the "GD" side of "CP1". For this reason, according to the basic concept, the effect of parasitic inductance caused by wires W1B and W2B can be reduced.

[0071] Based on the above, according to the basic concept, the parasitic inductance that limits the switching speed of the power transistor can be effectively reduced by the synergistic effect of (1) replacing some of the wire connections with flip-chip connections using bump electrodes and (2) placing the capacitor that functions as a power supply close to the driver chip. Therefore, according to the basic concept, high-speed switching operation of the power transistor can be realized.

[0072] In other words, the basic idea is that (1) the driver chip is flip-chip connected to the main chip and the wiring board such that (1) the second surface is positioned partially opposite to the first surface and the top surface, the output pad is electrically connected to the gate pad (gate electrode G), the input pad is electrically connected to the input wiring WL3, the first power pad is electrically connected to the first power wiring WL1, and the second power pad is electrically connected to the second power wiring WL2. Furthermore, assuming that the first power supply wiring WL1 has a first end close to the connection area with the first power supply pad and a first other end far from the connection area with the first power supply pad, and that the second power supply wiring WL2 has a second end close to the connection area with the second power supply pad and a second other end far from the connection area with the second power supply pad, the basic concept is that (2) the capacitor mounted on the wiring board is provided to be electrically connected to both the first power supply wiring WL1 and the second power supply wiring WL2, and is positioned closer to the first end than the first other end and closer to the second end than the second other end.

[0073] This effectively reduces the parasitic inductance that limits the switching speed of power transistors, and therefore, according to the basic concept, enables high-speed switching operation of power transistors.

[0074] <Improvements to the basic concept> In the basic concept described above, for example, as shown in Figure 2, the source S and the power source PS are electrically connected by a wire WS. That is, in the basic concept, similar to the related technology shown in Figure 1, the source S and the power source PS are connected by a wire WS, and the power source PS is electrically connected to the second power supply terminal TE2. In this case, the parasitic inductance caused by the wire WS limits the high-speed switching operation of the power transistor Tr. This point will be explained below.

[0075] For example, in Figure 2, in the power transistor Tr, when the gate-source voltage between the source S and the gate electrode G exceeds a threshold voltage, "Tr" turns on, and current flows from the drain D towards the source S. In other words, when "Tr" turns on, current flows from the power drain PD towards the power source PS.

[0076] At this time, as shown in Figure 2, the power source PS is electrically connected to the second power supply terminal TE2 to which a reference potential (0V) is supplied, and the reference potential is applied. When "Tr" is turned on, current begins to flow from the power drain PD to the power source PS, and as a result, current gradually begins to flow from the source S to the power source PS through the wire WS. That is, current begins to flow through the wire WS that exists between the source S and the power source PS, and this causes a voltage drop (V=LdI / dt) which is the parasitic inductance caused by the wire WS multiplied by the rate of change of the current.

[0077] Here, since the power source PS is electrically connected to the second power supply terminal TE2 to which the reference potential is applied, the source S rises from the reference potential (the potential of the power source PS) by a voltage (V = LdI / dt). In other words, the potential of source S rises from the reference potential by a voltage (V = LdI / dt). This means that the gate-source voltage between source S and gate electrode G becomes smaller.

[0078] In this regard, considering that the switching speed of the power transistor Tr increases as the gate-source voltage increases, the decrease in the gate-source voltage due to the above phenomenon means that the switching speed of "Tr" decreases.

[0079] In this configuration, where source S and power source PS are connected by wire WS and a reference potential is applied to power source PS, the potential of source S rises above the reference potential due to the voltage drop caused by the parasitic inductance of wire WS. As a result, the gate-source voltage decreases, which reduces the switching speed of the transistor (Tr).

[0080] Therefore, not only in the related technologies shown in Figure 1, but also in the basic concept shown in Figure 2, a configuration is adopted in which the source S and the power source PS are connected by a wire WS, and the power source PS is connected to the second power supply terminal TE2. Thus, even in the basic concept, there is room to make improvements to improve the switching speed of the power transistor Tr. Accordingly, the following will explain the improvements to the basic concept that take this into consideration.

[0081] Figure 3 illustrates the improvements made to the basic concept.

[0082] In Figure 3, the improvement lies in electrically connecting the second power supply terminal TE2, to which the reference potential is applied, with the source S. Specifically, the source S is electrically connected to the second power supply terminal TE2 via the source wiring WLS, the second power supply wiring WL2, and wire W2B.

[0083] As a result, for example, when the power transistor Tr is turned on, current begins to flow through the wire WS located between the source S and the power source PS. However, in the improved design, the power source PS is not electrically connected to the second power supply terminal TE2; rather, the source S itself is electrically connected to the second power supply terminal TE2. Consequently, even if a voltage drop occurs due to the parasitic inductance of the wire WS, the reference potential is applied to the source S, which is electrically connected to the second power supply terminal TE2. In other words, according to the improved design, even if a voltage drop occurs due to the parasitic inductance of the wire WS, the potential of the source S is not affected by this voltage drop, and the potential rise from the reference potential is suppressed.

[0084] In this way, the improvements to the basic concept suppress the rise in the potential of source S from the reference potential due to the voltage drop caused by the parasitic inductance of wire WS. Therefore, the improvements to the basic concept effectively suppress the decrease in the gate-source voltage and the resulting decrease in the switching speed of power transistor Tr.

[0085] <Further improvements to the basic concept> The basic principles described above have room for further improvement, so I will explain this point.

[0086] For example, in Figure 3, when a reference potential (0V) is output from the gate driver GD and applied to the gate electrode G of the power transistor Tr, the gate-source voltage between the source S and gate electrode G of Tr becomes 0V, which is smaller than the threshold voltage, and Tr turns off. At this time, current flows through the gate-drain capacitance of Tr due to the voltage gradient (dV / dt) between the drain D and source S of Tr. This current induces a voltage between the gate electrode G and source S of Tr. If this voltage (gate-source voltage) exceeds the threshold voltage of Tr, Tr will turn on incorrectly. This phenomenon is called "false firing (false turn-on)".

[0087] In this regard, if the reference potential output from the gate driver GD is 0V, "false firing" is more likely to occur due to the mechanism described above. That is, even in the improved basic design shown in Figure 3, the reference potential applied to the second power supply terminal TE2 is 0V, and a configuration is adopted in which the reference potential output from the gate driver GD to the gate electrode G of the "Tr" is set to 0V in order to turn off the "Tr". Therefore, there is room to implement measures to suppress "false firing" of the "Tr". Accordingly, further improvements to the basic design will be explained below.

[0088] Figure 4 illustrates further improvements to the basic concept.

[0089] Considering the mechanism of "false firing" described above, false firing can be suppressed, for example, by setting the reference potential output from the gate driver GD to a "negative potential" instead of "0V". In other words, a further improvement to the basic concept is to set the reference potential output from the gate driver GD to the gate electrode G of the power transistor Tr to a negative potential instead of 0V in order to turn off the Tr in order to prevent false firing of the Tr.

[0090] Specifically, as shown in Figure 4, the reference potential applied to the second power supply terminal TE2 is set to a negative potential (-5V). However, in this case, the second power supply terminal TE2 is electrically connected to the source S of the "Tr", and it is necessary to apply 0V to the source S. Therefore, as a further improvement to the basic concept, as shown in Figure 4, a bias capacitor CP2 is inserted between the second power supply terminal TE2 and the source S of the "Tr". This makes it possible to realize a circuit configuration in which a negative potential is applied to the second power supply terminal TE2 while 0V is applied to the source S. In other words, the bias capacitor CP2 has the technical significance of being provided to enable the application of 0V to the source S while a negative potential is applied to the second power supply terminal TE2.

[0091] In this case, in particular, to apply 0V to source S, source S is electrically connected to Kelvin terminal TE4 via Kelvin wiring WLK and wire W4. This allows 0V to be supplied to source S by applying 0V to the Kelvin terminal TE4, which is an external connection terminal. In other words, the Kelvin terminal TE4 shown in Figure 4 has technical significance in that it is provided for applying 0V to source S from the outside when a negative potential, rather than 0V, is applied to the second power supply terminal TE2.

[0092] In this way, according to the further improved basic concept, it is possible to apply 0V to the source S of the power transistor Tr while effectively suppressing "false firing". As a result, according to the further improved basic concept, it is possible to suppress the rise in the potential of the source S due to the voltage drop caused by the parasitic inductance of the wire WS, while also suppressing "false firing". In other words, according to the further improved basic concept, it is possible to improve the reliability of the power semiconductor device by preventing "false firing" while realizing high-speed switching operation of the "Tr".

[0093] Furthermore, since a negative potential can be applied to the second power supply terminal TE2, the driving force of the drive circuit can be improved compared to the case where 0V is applied to the second power supply terminal TE2. Consequently, it becomes possible to reduce the area of ​​the driver chip on which the drive circuit is formed.

[0094] <Implementation Method 1> Below, we will explain the first embodiment of the basic concept (Figure 4) that incorporates the further improvements described above.

[0095] <<Main chip configuration>> Figure 5 shows the layout of the main chip 10. In Figure 5, the first surface of the main chip 10 is shown. Power transistors are formed on the main chip 10, and on the first surface, a gate pad GP electrically connected to the gate electrode of the power transistor and a source pad SP electrically connected to the source of the power transistor are formed. Although not shown in the figure, a drain electrode is formed on the first back surface opposite to the first surface of the main chip. Power transistors typically have a vertical transistor structure with a current path from the first surface to the first back surface in the thickness direction of the WG semiconductor substrate. The main chip 10 is constructed in this manner.

[0096] <<Driver Chip Configuration>> Figure 6 shows the layout of the driver chip 20. Figure 6 shows the second surface of the driver chip 20. The driver chip 20 has a drive circuit formed on it that drives power transistors, and the second surface has an output pad OP, an input pad IP, a first power supply pad VP1, a second power supply pad VP2, and a Kelvin pad KP. The drive circuit is typically integrated on the second surface on one side of the WG semiconductor substrate, and the CMOS drive circuit is formed by a group of lateral transistors with current paths parallel to the second surface. In this way, the driver chip 20 is constructed.

[0097] <<Wiring board configuration>> Figure 7 shows the layout of the wiring board 30. Figure 7 shows the top surface of the wiring board 30. As shown in Figure 7, the Kelvin wiring WLK, the second power supply wiring WL2, the first power supply wiring WL1, and the input wiring WL3 are arranged on the top surface of the wiring board 30 in the Y direction, and each wiring extends in the X direction. An insulating region is secured between each of the Kelvin wiring WLK, the second power supply wiring WL2, the first power supply wiring WL1, and the input wiring WL3, and each wiring is arranged with an insulating region between them. As a result, each wiring is configured not to be electrically conductive to the others. The wiring board 30 is configured in this way.

[0098] <<Power semiconductor device mounting configuration>> Next, we will describe the implementation configuration of the power semiconductor device 100.

[0099] Figure 8 is a plan view showing the mounting configuration of the power semiconductor device 100 assembled from the components shown in Figures 5 to 7.

[0100] In Figure 8, the power semiconductor device 100 has a case 50, and a substrate 52 is placed inside the case 50. On this substrate 52, a chip mounting section 53 and a substrate mounting section 54, each composed of, for example, a metal pattern, are arranged side by side in the horizontal direction. A drain terminal 53a, composed of, for example, a lead, is drawn out from the chip mounting section 53, and this drain terminal 53a is the power drain PD. On the other hand, a second power supply terminal TE2, composed of, for example, a lead, is drawn out from the substrate mounting section 54.

[0101] Next, the main chip 10 is positioned on the chip mounting section 53 with its first surface facing upwards. In other words, the main chip 10 is mounted on "53" with its first back surface facing the chip mounting section 53. A source pad SP and a gate pad GP are formed on the first surface of the main chip 10. In the vertical direction, a source terminal 55, for example consisting of leads, is positioned alongside the chip mounting section 53 on which the main chip 10 is mounted, and this source terminal 55 becomes the power source PS. At this time, the source pad SP and the source terminal 55 of the main chip 10 are connected by a wire WS.

[0102] Next, the wiring board 30 is placed on the board mounting section 54 with its top surface facing upwards. In other words, the wiring board 30 is mounted on "54" with its bottom surface facing the board mounting section 54. On the top surface of the wiring board 30, the Kelvin wiring WLK, the second power supply wiring WL2, the first power supply wiring WL1, and the input wiring WL3 are formed in a vertical line.

[0103] On the left side of the wiring board 30, the Kelvin terminal TE4, the second power terminal TE2, the first power terminal TE1, and the input terminal TE3 are arranged vertically. At this time, the input terminal TE3 and the input wiring WL3 are connected by wire W3B, while the first power terminal TE1 and the first power wiring WL1 are connected by wire W1B. In addition, the second power terminal TE2 and the second power wiring WL2 are connected by wire W2B, while the Kelvin terminal TE4 and the Kelvin wiring WLK are connected by wire W4.

[0104] In Figure 8, the wiring board 30 and each terminal TE1 to TE4 are connected by wires as an example, but it is also possible to integrally form each terminal TE1 to TE4 on each wiring WL1 to WL3 and WLK of the wiring board 30, or to connect them with a separate wiring board instead of wires.

[0105] Furthermore, while Figure 8 illustrates the use of metal bonding wires for connecting each terminal, a bonding ribbon made of a wide metal ribbon may also be used. In this disclosure, the term "wire" refers to both bonding wires and bonding ribbons.

[0106] Next, as shown in Figure 8, the driver chip 20 is flip-chip connected to the main chip 10 and the wiring board 30. Specifically, the second surface of the driver chip 20 is positioned partially opposite the first surface of the main chip 10 and the upper surface of the wiring board 30, respectively. The output pad OP is connected to the gate pad GP via the bump electrode BP, the input pad IP is connected to the input wiring WL3 via the bump electrode BP3, the first power supply pad VP1 is connected to the first power supply wiring WL1 via the bump electrode BP1, and the second power supply pad VP2 is connected to the second power supply wiring WL2 via the bump electrode BP2.

[0107] Furthermore, in embodiment 1, the Kelvin pad KP is electrically connected to both the source pad SP and the Kelvin wiring WLK. Specifically, the Kelvin pad KP is connected to the source pad SP via the bump electrode BP4A, and the Kelvin pad KP is connected to the Kelvin wiring WLK via the bump electrode BP4B. It should also be considered that the driver chip 20 may employ a multilayer metal structure.

[0108] Next, as shown in Figure 8, a capacitor CP1 is mounted on the wiring board 30. Here, for example, the first power supply wiring WL1 has a first end close to the connection area with the first power supply pad VP1 and a first other end far from the connection area with the first power supply pad VP1, and the second power supply wiring WL2 has a second end close to the connection area with the second power supply pad VP2 and a second other end far from the connection area with the second power supply pad VP2. Based on this, the capacitor CP1 mounted on the wiring board 30 is provided to be electrically connected to both the first power supply wiring WL1 and the second power supply wiring WL2, and is positioned closer to the first end than the first other end and closer to the second end than the second other end.

[0109] Furthermore, as shown in Figure 8, a bias capacitor CP2 is mounted on the wiring board 30. Here, for example, the Kelvin wiring WLK has a third end close to the connection area with the Kelvin pad KP, and a third other end far from the connection area with the Kelvin pad KP. Based on this, the bias capacitor CP2 mounted on the wiring board 30 is provided to be electrically connected to both the second power wiring WL2 and the Kelvin wiring WLK, and is positioned closer to the second end than the other second end, and closer to the third end than the other third end. In this way, the power semiconductor device 100 shown in Figure 8 is mounted.

[0110] Figure 9 is a cross-sectional view taken along line AA in Figure 8.

[0111] In Figure 9, the bottom surface of the case 50 is a base plate 51, on which a substrate 52 is placed via solder. A chip mounting section 53 and a substrate mounting section 54 are placed on the substrate 52. At this time, a drain terminal 53a is formed integrally with the chip mounting section 53, and a second power supply terminal TE2 is formed integrally with the substrate mounting section 54. The drain terminal 53a and the second power supply terminal TE2 are bent upward and protrude from the lid 50a that seals the case 50.

[0112] On the chip mounting section 53, for example, the main chip 10 is mounted via solder, and Figure 9 shows a wire WS connected to the source pad of the main chip 10. On the other hand, on the substrate mounting section 54, for example, the wiring board 30 is mounted via solder, and Figure 9 shows a capacitor CP1 mounted on the wiring board 30 and a wire W2B connecting the second power supply wiring formed on the wiring board 30 to the second power supply terminal TE2.

[0113] Next, in Figure 9, the driver chip 20 is flip-chip connected to both the main chip 10 and the wiring board 30. Specifically, Figure 9 shows the connection cross-section of bump electrodes BP2 and BP4A. To facilitate this flip-chip connection, the heights of the top surface of the main chip 10 and the top surface of the wiring board 30 are substantially equal.

[0114] As shown in Figure 9, the inside of the case 50 is filled with gel 56, which is an insulating material. The top of the case 50 is closed by a lid 50a, and the inside of the case 50 is sealed. In this way, the power semiconductor device 100 is mounted.

[0115] <<Characteristics of Embodiment 1>> Next, we will explain the characteristics of Embodiment Mode 1.

[0116] The first key feature is that, as shown in Figure 8, for example, the driver chip 20 is flip-chip connected to both the main chip 10 and the wiring board 30. More specifically, the first key feature lies in the connections made by the bump electrodes BP, BP1, and BP2 in Figure 8. This first feature allows for connection using bump electrodes without the need for wires, thus eliminating parasitic inductance caused by wires. Consequently, this first feature effectively reduces parasitic inductance that limits the switching speed of the power transistor, resulting in the excellent effect of enabling high-speed switching operation of the power transistor.

[0117] However, even when the first feature point is adopted, for example, as shown in Figure 8, the wiring board 30 and the external connection terminals are still connected by wires, and the high-speed switching operation of the power transistor may be restricted due to the influence of parasitic inductance caused by these wires. In this regard, the second feature point of embodiment 1 is that, as shown in Figure 8, capacitor CP1 is provided in an area on the wiring board 30 that is closer to the driver chip 20 than to the external connection terminals. Specifically, the second feature point is that capacitor CP1, which is electrically connected to both the first power supply wiring WL1 and the second power supply wiring WL2, is placed in a position closer to the driver chip 20 than to the external connection terminals (or wires). As a result, according to the second feature point, when a power supply is connected between the first power supply terminal TE1 and the second power supply terminal TE2, capacitor CP1 is connected in parallel with this power supply, and as a result, the voltage applied across capacitor CP1 becomes equivalent to the voltage applied from the power supply between "TE1" and "TE2". In other words, according to the second feature, it becomes possible to make capacitor CP1 function as if it were a power supply, and capacitor CP1 can supply power supply potential (25V) and reference potential (0V) to the driver chip 20.

[0118] In this case, the wire is located outside of the capacitor CP1, which functions as a power source. Therefore, according to the second feature point, where the capacitor CP1 supplies the power potential (first potential) and the reference potential (second potential) to the driver chip 20, the effect of parasitic inductance caused by the wire can be reduced. Thus, the combination of the first and second feature points described above can reduce the effect of parasitic inductance caused by the wire to almost zero, making this combination extremely useful from the standpoint of realizing high-speed switching operation of the power transistor.

[0119] Next, the third characteristic feature of embodiment 1 is that, for example, as shown in Figure 8, the source pad SP and the Kelvin terminal TE4 are electrically connected. According to this third characteristic feature, it becomes possible to apply a fixed reference potential (0V) from the Kelvin terminal TE4 to the source pad SP (source S). Therefore, according to this third characteristic feature, even when the power transistor is turned on and current begins to flow from the drain to the source, the influence of the voltage drop caused by the wire WS interposed between the source pad SP and the source terminal 55 (power source PS) is suppressed, and as a result, the so-called "potential rise phenomenon" of the source pad SP (source S) can be suppressed. According to this third characteristic feature, since the obstacle to the high-speed switching operation of the power transistor caused by the "potential rise phenomenon" is removed, even higher-speed switching operation becomes possible.

[0120] Next, the fourth characteristic feature of embodiment 1 is that a bias capacitor CP2 is provided between the second power supply wiring WL2 and the Kelvin wiring WLK, as shown in Figure 8, for example. As a result, according to the fourth characteristic feature, a negative potential (e.g., -5V) can be supplied to the driver chip 20 via the second power supply wiring WL2 from the second power supply terminal TE2 while 0V is applied to the source pad SP from the Kelvin terminal TE4.

[0121] In this case, a negative potential is supplied to the CMOS drive circuit formed on the driver chip 20. As a result, for example, when a high-level signal is input to the driver chip 20 and the nFET constituting the CMOS drive circuit is turned on, the driver chip 20 can supply a negative potential to the gate electrode of the power transistor. This allows the power transistor to be turned off by supplying a negative potential to the gate electrode rather than supplying 0V to the gate electrode from the driver chip 20, thus making it less likely to cause so-called "false firing." As a result, according to the fourth feature point, the reliability of the power semiconductor device can be improved.

[0122] Based on the above, according to Embodiment 1, since it possesses the first to fourth feature points described above, it is possible not only to realize high-speed switching operation of the power semiconductor device but also to improve the reliability of the power semiconductor device. In other words, Embodiment 1 is excellent in that it can simultaneously achieve performance improvement in the form of realizing high-speed switching operation and reliability improvement in the form of suppressing "false firing".

[0123] Furthermore, the fifth characteristic feature of Embodiment 1 is that, in addition to using a silicon carbide semiconductor chip as the main chip 10, a silicon carbide semiconductor chip is also used as the driver chip 20. In this case, the high-temperature characteristics of "20" can be improved, so malfunctions due to the influence of heat from the main chip 10 can be sufficiently suppressed without adopting a configuration in which a heat sink is provided on the driver chip 20. In particular, Embodiment 1 has great technical significance in that by using a silicon carbide semiconductor chip as the driver chip 20, it is not necessary to adopt a configuration in which a heat sink is provided on "20".

[0124] For example, if the configuration of embodiment 1 is adopted assuming that a silicon chip is used as the driver chip 20, a heat sink must be provided on the top (back) surface of "20". In this case, the top surface of the driver chip 20 must be as parallel as possible to the surface of the main chip 10 and the top surface of the wiring board 30. This is because if the driver chip 20 is tilted, it will be difficult to provide a heat sink on the top surface of "20".

[0125] In this regard, for example, referring to Figure 8, two bump electrodes are arranged in the right-hand region of the driver chip 20, while four bump electrodes are arranged in the left-hand region of the "20" region. In this case, since the number of bump electrodes differs between the left and right regions, it is difficult to make the top surface of "20" horizontal. Therefore, when a silicon chip that requires a heat sink is used as the driver chip 20, the configuration of the above-described embodiment 1 (see Figure 8) is difficult to realize.

[0126] In contrast, when a silicon carbide semiconductor chip is used as the driver chip 20, there is no need to provide a heat sink on the top surface of "20," and therefore the top surface of "20" does not need to be horizontal. In other words, it is not a problem if the number of bump electrodes differs in the left and right regions of the driver chip 20. Therefore, when a silicon carbide semiconductor chip is used as the driver chip 20, it is easy to realize the configuration of the embodiment 1 described above, and in this case, a remarkable effect can be obtained from the combination of the first to fourth feature points described above. That is, the configuration of the embodiment 1 is extremely useful when applied when the driver chip 20 is made from a silicon carbide semiconductor chip (or a WG semiconductor material chip).

[0127] Some of the features described above can also be rephrased as follows. The first feature can be explained by the layout of the first group of pads (GP, SP) arranged along one side of the main chip 10, the second group of pads (OP, KP) arranged along one side of the driver chip 20, the third group of pads (IP, VP1, VP2, KP) arranged along the other side of the driver chip, and the wiring group of the wiring board (WL3, WL1, WL2, WLK). This layout facilitates bump connection of the driver chip 20 to the main chip 10 and the wiring board 30. Furthermore, the second and fourth features can be explained by the arrangement order of the third group of pads (IP→VP1→VP2→KP) and the corresponding arrangement order of the wiring group (WL3→WL1→WL2→WLK), which enables the placement and mounting of capacitors CP1 and CP2 at the minimum distance.

[0128] <Variation> Next, we will describe a modified example of Embodiment 1.

[0129] Figure 10 shows the power semiconductor device 100A in this modified example.

[0130] In Figure 10, in this modified example, the source pad SP and the Kelvin wiring WLK are connected by a wire WK. In the embodiment 1 described above, as shown in Figure 8, a configuration is adopted in which the source pad SP and the Kelvin wiring WLK are electrically connected via a Kelvin pad KP formed on the driver chip 20.

[0131] In contrast, in the modified example shown in Figure 10, the source pad SP and the Kelvin wiring WLK are electrically connected by a wire WK that is separate from the driver chip 20. Thus, a wire WK may be used to connect the source pad SP and the Kelvin wiring WLK.

[0132] <<Verification of effectiveness>> Next, we will explain how the flip-chip connection of the main chip and driver chip according to Embodiment 1 can improve the switching speed of the power transistors. In particular, we will focus on the switching speed when turning on the power transistors.

[0133] Figure 11 is a graph showing the relationship between drain-source voltage and time when a power transistor is turned on. In Figure 11, the horizontal axis represents time, and the vertical axis represents drain-source voltage. The transition portion of the vertical axis from 540V to 60V is inserted as an enlarged view. Of the two graphs, the solid line represents the experimental example, and the dotted line represents the comparative example. The switching characteristics in Figure 11 were measured using a double-pulse test.

[0134] The experimental example was measured using a simplified module similar to the structure shown in Figure 10, with the main chip and driver chip connected by bump electrodes. The comparative example was measured using a simplified module similar to that described in Non-Patent Document 1 (Fig. 1(b)), with the main chip and driver chip connected by bonding wires. In each case, a custom-made SiC MOSFET (power transistor) was used for the main chip, and a custom-made SiC-CMOS drive circuit (gate driver) was used for the driver chip.

[0135] The maximum source-drain voltage of the power transistor was 600V, and the driver chip was supplied with a reference potential of 0V and a power supply potential of 35V.

[0136] Here, switching time is defined as the time required for the drain-source voltage (Vds) of a power transistor to change from 90% to 10% of its drain-source voltage (Vds) when the transistor is off, with Vds being 100%. For example, if the drain-source voltage (Vds) when the transistor is off is 600V, the time it takes to transition from 540V to 60V is defined as the switching time. For example, a short time for the drain-source voltage of a power transistor to reach 10% (60V) means that the switching speed is fast.

[0137] Therefore, looking at the two graphs shown in the enlarged view of Figure 11 from this perspective, it can be seen that in the experimental example (solid line), the drain-source voltage of the power transistor decreases to 10% (60V) faster than in the comparative example (dotted line). The switching time of the comparative example was approximately 5.5 ns, while that of the experimental example was approximately 4.8 ns, meaning the switching time was reduced by more than 10%. In other words, the results shown in Figure 11 indicate that the experimental example has a faster switching speed than the comparative example, and this supports the idea that the flip-chip connection of embodiment 1 can improve the switching speed.

[0138] <Manifestation Method 2> The basic concept described above is to reduce parasitic inductance caused by wires. However, parasitic inductance also exists in the wiring formed on the circuit board. Therefore, in embodiment 2, while adhering to the basic concept of reducing parasitic inductance caused by wires, a configuration is described in which the circuit board is removed between the driver chip and the capacitor of the power semiconductor device in order to further reduce parasitic inductance.

[0139] <<Overview>> Figure 12 is a diagram illustrating the overview of the power semiconductor device 200 in embodiment 2.

[0140] In Figure 12, gate pads GP and source pads SP are formed on the first surface of the main chip 10 on which the power transistors are formed. In the power semiconductor device 200, a driver chip 20A is mounted on the main chip 10. The configuration of the main chip 10 is the same as that described in Embodiment 1 shown in Figure 5.

[0141] Specifically, the driver chip 20A has a second surface and a second back surface, and is mounted on the main chip 10 with the second back surface facing the first surface of the main chip 10. At this time, bump electrodes BPA and BPB are interposed between the driver chip 20A and the main chip 10.

[0142] Next, as shown in Figure 12, an input pad IP, a first power pad VP1, a second power pad VP2, and a surface Kelvin pad KP1 are formed on the second surface of the driver chip 20A. Each of these pads is configured to be connectable to a wire, for example. For example, Figure 12 shows a configuration in which the input pad IP is connected to wire W1, the first power pad VP1 is connected to wire W2, the second power pad VP2 is connected to wire W3, and the surface Kelvin pad KP1 is connected to wire W4.

[0143] Furthermore, capacitor CP1 and bias capacitor CP2 are mounted on the second surface of the driver chip 20A. In particular, capacitor CP1 is provided on the second surface to be electrically connected to both the first power pad VP1 and the second power pad VP2. On the other hand, bias capacitor CP2 is provided on the second surface to be electrically connected to both the second power pad VP2 and the surface Kelvin pad KP1.

[0144] The power semiconductor device 200 is configured as described above.

[0145] <<Driver Chip Configuration>> Figure 13 shows the layout of the driver chip 20A. In particular, Figures 13(a) and (b) show the layout of the second front surface and the second back surface, respectively.

[0146] As shown in Figure 13(a), the second surface of the driver chip 20A has an input pad IP, a first power supply pad VP1, a second power supply pad VP2, and a surface Kelvin pad KP1. On the other hand, as shown in Figure 13(b), the second back surface of the driver chip 20A has an output pad OP and a back surface Kelvin pad KP2. The drive circuit of the driver chip 20A is formed, for example, on the back surface shown in Figure 13(b). This allows the output of the drive circuit to be connected to the gate of the power transistor in the shortest possible distance. In this case, the drive circuit is connected to the input pad IP, the first power supply pad VP1, and the second power supply pad VP2 by, for example, an electrode that penetrates both the front and back surfaces of the driver chip. Preferably, the drive circuit of the driver chip 20A is a SiC-CMOS drive circuit.

[0147] Here, the output pad OP and the gate pad GP (see Figure 12) are connected by a bump electrode BPA. On the other hand, the back surface Kelvin pad KP2 and the source pad (see Figure 12) are connected by a bump electrode BPB. Furthermore, the front surface Kelvin pad KP1 formed on the second surface and the back surface Kelvin pad KP2 formed on the second back surface are electrically connected, for example, by an electrode that penetrates both the front and back surfaces of the driver chip 20A.

[0148] <<Power semiconductor device mounting configuration>> Next, we will describe the implementation configuration of the power semiconductor device 200.

[0149] Figure 14 is a plan view showing the mounting configuration of the power semiconductor device 200.

[0150] In Figure 14, a substrate 52 is placed inside the case 50, and a chip mounting section 53, for example, made of a metal pattern, is placed on this substrate 52. A drain terminal 53a is integrally formed with the chip mounting section 53 and functions as a power drain PD. On the other hand, a source terminal 55 is provided separately from the chip mounting section 53 and functions as a power source PS.

[0151] Next, a main chip 10 is mounted on the chip mounting section 53. A gate pad GP and a source pad SP are formed on the first surface of the main chip 10. A driver chip 20A is mounted on the main chip 10. The driver chip 20A has a second surface, on which an input pad IP, a first power pad VP1, a second power pad VP2, and a surface Kelvin pad KP1 are formed. A capacitor CP1 is mounted on the second surface to connect to both the first power pad VP1 and the second power pad VP2. A bias capacitor CP2 is mounted on the second surface to connect to both the second power pad VP2 and the surface Kelvin pad KP1.

[0152] Next, the input terminal TE3, the first power terminal TE1, the second power terminal TE2, and the Kelvin terminal TE4 are located away from the chip mounting section 53. TE3 and IP are connected by wire W1, TE1 and VP1 by wire W2, TE2 and VP2 by wire W3, and TE4 and KP1 by wire W4. The source terminal 55 and source pad SP are connected by wire WS. In this manner, the power semiconductor device 200 is mounted.

[0153] In Figure 14, each pad IP, VP1, VP2, and KP1 is connected to each terminal TE1 to TE4 with a wire as an example, but it is also possible to connect them using a circuit board instead of wires.

[0154] Figure 15 is a cross-sectional view taken along line AA in Figure 14.

[0155] In Figure 15, the bottom surface of the case 50 is a base plate 51, on which a substrate 52 is placed via solder. A chip mounting section 53 is placed on the substrate 52. At this time, a drain terminal 53a is formed integrally with the chip mounting section 53. In addition, a Kelvin terminal TE4 is formed separately from the chip mounting section 53. The drain terminal 53a and the Kelvin terminal TE4 are bent upward and protrude from the lid 50a that seals the case 50.

[0156] A main chip 10 is mounted on the chip mounting section 53, for example, via solder, and Figure 15 shows a wire WS connected to the source pad of the main chip 10.

[0157] Next, in Figure 15, the driver chip 20A is flip-chip connected to the main chip 10. Specifically, Figure 15 shows a cross-section where the main chip 10 and the driver chip 20 are connected by a bump electrode BPB. In addition, in the cross-section shown in Figure 15, the driver chip 20A and the Kelvin terminal TE4 are connected by wire W4, and a bias capacitor CP2 is mounted on the driver chip 20.

[0158] The inside of the case 50 is filled with an insulating material, gel 56. The top of the case 50 is sealed by a lid 50a, making the inside of the case 50 airtight. In this way, the power semiconductor device 200 is mounted.

[0159] For example, capacitors CP1 and CP2 can be fabricated from semiconductor capacitors (silicon capacitors or silicon carbide capacitors) and connected using a flip-chip connection via bump electrodes. Furthermore, the bias capacitor CP2, the surface Kelvin pad KP1, the back Kelvin pad KP2, and the Kelvin terminal TE4 can be omitted as optional components.

[0160] <<Characteristics specific to manifestation mode 2>> Next, we will explain the characteristics of Embodiment 2. The characteristics common to Embodiment 1 are also carried over to Embodiment 2.

[0161] A unique feature of embodiment 2 is, for example, the absence of a wiring board between the driver chip 20A and capacitors CP1 and CP2 of the power semiconductor device 20, as shown in Figures 14 and 15. As a result, according to this feature, since the wiring present on the wiring board is not included in the components, parasitic inductance caused by the wiring can be eliminated. Consequently, according to this feature, not only is the parasitic inductance caused by the wires reduced, but the parasitic inductance of the wiring formed on the wiring board between the driver chip 20A and capacitors CP1 and CP2 is also reduced, enabling high-speed switching operation of the power transistor.

[0162] Furthermore, according to the features, by eliminating the wiring board, the power semiconductor device 200 can be miniaturized, and the number of components constituting "200" can be reduced, resulting in a reduction in the manufacturing cost of "200".

[0163] Although the present inventors have described the invention in detail based on its embodiments, it goes without saying that this disclosure is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of the invention.

[0164] In the above embodiment, a power MOSFET was used as an example of a power transistor, but the technical concept in the above embodiment is not limited to this and can be broadly applied when using IGBTs. In this case, the following terms will be reinterpreted.

[0165] "Source" → "Emitter" "Source pad" → "Emitter pad" "Source terminal" → "Emitter terminal" "Power source" → "Power emitter" "Drain" → "Collector" "Drain electrode" → "Collector electrode" "Drain terminal" → "Collector terminal" "Power drain" → "Power collector" Furthermore, in the above embodiment, a vertical power MOSFET, in which the source is on the first surface (front) of the semiconductor substrate and the drain is on the second surface (back), was used as an example of a power transistor. However, a horizontal power transistor may also be used. For example, a GaN-HEMT in which the source and drain are provided on one surface of the semiconductor substrate can be used as a power transistor. For GaN-HEMT chips, refer to, for example, Patent Document 4. Note that in a horizontal power MOSFET, the source pad and drain pad are provided on the same surface of the semiconductor substrate, so in the power semiconductor device shown in Figures 8 and 9, the drain pad is also connected to the drain terminal of the module by a wire.

[0166] Furthermore, the wiring board 30 used in the above-described embodiment 1 can also be replaced by a group of terminals extending each of the terminals TE1 to TE4 shown in Figure 8 to the position of the driver chip 20. In this case, the group of terminals (TE1 to TE4) will also serve as the wirings WL1 to WL3 and WLK of the wiring board, and will be connected to the pads IP, VP1, VP2, and KP of the driver chip 20 via bump electrodes. That is, each of the terminals in the group of terminals (TE1 to TE4) will function as each of the wirings WL1 to WL3 and WLK. This eliminates the need for the wiring board 30 and also eliminates the need for wire connections to each terminal. In this case, the capacitor CP1 will be mounted between terminals TE1 and TE2, close to the driver chip 20. Similarly, the bias capacitor CP2 will be mounted between terminals TE2 and TE4. In this case, the cross-sectional structure of the terminals TE1 to TE4 should be such that the upper surface (upper end) of the terminal group is substantially at the same height as the surface of the main chip 10, as can be understood from Figure 9, in order to facilitate bump connection to the driver chip 20. For this purpose, a chip-embedded power module structure may be used, for example, in which a part of the substrate 52 or the like is excavated to mount the main chip 10. When referring collectively to the wiring board 30 or the terminal groups TE1 to TE4 that replace the wiring board 30, they will be called "wiring components." Wiring components may also be something like a lead frame. [Explanation of Symbols]

[0167] 10 Main chips 20 driver chips 20A driver chip 30 Wiring boards 50 cases 51 Base Plate 52 circuit board 52 53 Chip mounting section 53a Drain terminal 54. Circuit board mounting section 55 Source terminal 56 Gel 100 Power Semiconductor Devices 100A Power Semiconductor Equipment 200 Power Semiconductor Equipment BP bump electrode BPA bump electrode BPB Bump Electrode BP1 Bump electrode BP2 bump electrode BP3 Bump electrode BP4A bump electrode BP4B bump electrode CP1 Capacitor CP2 bias capacitor D Drain E power supply G Terminal GD Gate Driver GP Gate Pad IP Input Pad KP Kelvin Pad KP1 Surface Kelvin Pad KP2 Backside Kelvin Pad OP Output Pad PD Power Drain PS Power Source S Sauce SP Source Pad TE1 1st power supply terminal TE2 Second power terminal TE3 Input Terminal TE4 Kelvin terminal Tr Power Transistor VP1 First Power Pad VP2 Second Power Pad W Bonding Wire (Wire) WK Bonding Wire (Wire) WLK Kelvin Wiring WLS Source Wiring WL1 First power wiring WL2 2nd power supply wiring WL3 Input Wiring WS Bonding Wire (Wire) W1A Bonding Wire (Wire) W1B Bonding Wire (Wire) W2A Bonding Wire (Wire) W2B Bonding Wire (Wire) W3A Bonding Wire (Wire) W3B Bonding Wire (Wire) W4 Bonding Wire (Wire)

Claims

1. A main chip having a first surface and a first back surface, on which a power transistor having a gate, source, and drain is formed, A driver chip having a second surface and a second back surface, on which a drive circuit for driving the power transistor is formed, The driver chip and the wiring components electrically connected, The capacitor mounted on the aforementioned wiring component, A semiconductor device equipped with, The first surface is provided with a gate pad connected to the gate of the power transistor and a source pad connected to the source. The second surface is provided with a signal input pad, a signal output pad, a first power supply pad, and a second power supply pad for the drive circuit. The wiring component includes an input wire connected to the signal input pad, a first power supply wire connected to the first power supply pad, and a second power supply wire connected to the second power supply pad. The first power wiring has a first end close to the connection area with the first power pad, and a first other end which is the opposite end of the first end. The second power wiring has a second end close to the connection area with the second power pad, and a second other end which is the opposite end of the second end. The driver chip is flip-chip connected to the main chip and the wiring components such that the second surface is partially facing the first surface and the wiring components, the signal output pad is electrically connected to the gate pad, the signal input pad is electrically connected to the input wiring, the first power pad is electrically connected to the first power wiring, and the second power pad is electrically connected to the second power wiring. A semiconductor device wherein the capacitor is provided to be electrically connected to both the first power supply wiring and the second power supply wiring, and is positioned closer to the first end than the other end of the first power supply wiring and closer to the second end than the other end of the second power supply wiring.

2. In the semiconductor device described in claim 1, The aforementioned capacitor is a semiconductor device that functions as a power source.

3. In the semiconductor device described in claim 1, The aforementioned semiconductor device is The power source terminal electrically connected to the source pad, A power drain terminal electrically connected to the drain, The input terminals electrically connected to the aforementioned input wiring, A first power terminal electrically connected to the first power wiring, The second power terminal is electrically connected to the second power wiring, A semiconductor device having the following features.

4. In the semiconductor device described in claim 3, The source pad and the power source terminal are connected by a bonding wire. The first power supply wiring and the first power supply terminal are connected by a first bonding wire. A semiconductor device wherein the second power supply wiring and the second power supply terminal are connected by a second bonding wire.

5. In a semiconductor device according to any one of claims 1 to 4, The aforementioned power transistor is a SiC power transistor using silicon carbide, The aforementioned drive circuit is a SiC-CMOS drive circuit using silicon carbide, and is a semiconductor device.

6. In a semiconductor device according to any one of claims 1 to 4, A semiconductor device in which the driver chip is flip-chip connected to the main chip and the wiring component such that the second power pad is electrically connected to the source pad.

7. In a semiconductor device according to any one of claims 1 to 4, A Kelvin pad is formed on the second surface, which is electrically connected to the source pad. The wiring component has a Kelvin wiring that is electrically connected to the Kelvin pad. The driver chip is flip-chip connected to the main chip and the wiring component so that the Kelvin pad is electrically connected to both the source pad and the Kelvin wiring. The Kelvin wiring has a third end close to the connection area with the Kelvin pad, and a third other end which is the opposite end of the third end. The aforementioned semiconductor device is A bias capacitor is provided to be electrically connected to both the second power supply wiring and the Kelvin wiring, and is positioned closer to the second end than the other end of the second, and closer to the third end than the other end of the third, The Kelvin terminal electrically connected to the aforementioned Kelvin wiring, A semiconductor device having the following features.

8. In the semiconductor device according to claim 7, The Kelvin terminal is configured to allow the application of 0V to a semiconductor device.

9. In the semiconductor device according to claim 7, A semiconductor device in which the Kelvin wiring and the Kelvin terminal are connected by a third bonding wire.

10. A main chip having a first surface and a first back surface, on which power transistors are formed, A driver chip having a second surface and a second back surface, on which a drive circuit for driving the power transistor is formed, The capacitor mounted on the aforementioned driver chip, A semiconductor device equipped with, The first surface is provided with the gate pad and source pad of the power transistor. The second surface is provided with a signal input pad for the drive circuit, a first power supply pad for applying a first potential to the drive circuit, and a second power supply pad for applying a second potential with a voltage lower than the first potential to the drive circuit. On the second back surface, a signal output pad of the drive circuit connected to the gate pad is provided. The driver chip is positioned on the main chip such that the second back surface is facing the first front surface and the signal output pad is electrically connected to the gate pad. A semiconductor device wherein the capacitor is provided on the second surface so as to be electrically connected to both the first power pad and the second power pad.

11. In the semiconductor device according to claim 10, The semiconductor device further comprises a bias capacitor mounted on the driver chip, The second surface is further provided with a surface Kelvin pad. The second back surface is further provided with a back surface Kelvin pad connected to the source pad and the front surface Kelvin pad, The bias capacitor is provided on the second surface so as to be electrically connected to both the second power supply pad and the surface Kelvin pad. The driver chip is positioned on the main chip such that the second back surface is positioned opposite the first front surface and the back surface Kelvin pad is electrically connected to the source pad. A semiconductor device wherein each of the signal input pad, the first power pad, the second power pad, and the surface Kelvin pad, which are formed on the second surface, is configured to be connectable to a bonding wire.

12. In the semiconductor device according to claim 10 or 11, The aforementioned power transistor is a SiC power transistor using silicon carbide, The aforementioned drive circuit is a SiC-CMOS drive circuit using silicon carbide, and is a semiconductor device.

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