Semiconductor equipment

Abstract

To provide a technique capable of reducing the size of a semiconductor device.SOLUTION: A semiconductor device includes a second semiconductor switching element having a rectangular shape with its long sides facing the first semiconductor switching element in a plan view and an area in a plan view smaller than that of the first semiconductor switching element, and made of a wide band gap semiconductor, and a plurality of first wires connecting the first semiconductor switching element and the second semiconductor switching element, each having a diameter of 40 μm or less and made of silver or gold.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] In recent years, a technique of connecting between an emitter terminal of an IGBT (Insulated Gate Bipolar Transistor) and a source terminal of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a wire has been proposed (for example, Patent Document 1). Note that between power chips such as IGBT and MOSFET, from the viewpoint of current density, it is generally connected with a thick wire having a diameter of 200 to 400 μm and made of aluminum.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, for example, in the wedge bonding method generally used for bonding thick wires, a bonding area on the order of mm is required. Thus, since the bonding area of the thick wire is relatively large, there is a problem that the size of the semiconductor device cannot be reduced.

[0005] ] Therefore, the present disclosure has been made in view of the above problems, and an object thereof is to provide a technique capable of reducing the size of a semiconductor device.

Means for Solving the Problems

[0006] The semiconductor device according to this disclosure comprises a first semiconductor switching element made of silicon, a second semiconductor switching element having a rectangular shape in plan view with its longer side facing the first semiconductor switching element, a smaller area in plan view than the first semiconductor switching element, and made of a wide bandgap semiconductor, and a plurality of first wires connecting the first semiconductor switching element and the second semiconductor switching element, with a diameter of 40 μm or less and made of silver or gold. , a control chip for controlling the first semiconductor switching element and the second semiconductor switching element, and a fourth wire connecting each of the first semiconductor switching element and the second semiconductor switching element to the control chip, and extending perpendicular to the direction in which the first semiconductor switching element and the second semiconductor switching element are arranged. It is equipped with. [Effects of the Invention]

[0007] According to this disclosure, the second semiconductor switching element has a rectangular shape in plan view, with its longer side facing the first semiconductor switching element. Furthermore, multiple chip wires, each with a diameter of 40 μm or less and made of silver or gold, connect the first and second semiconductor switching elements. This configuration allows for a reduction in the size of the semiconductor device. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view showing the configuration of the semiconductor device according to this embodiment 1. [Figure 2] This is an enlarged plan view showing a part of the configuration of the semiconductor device according to this embodiment 1. [Figure 3] This is an enlarged plan view showing a part of the configuration of the semiconductor device according to Modification Example 1. [Figure 4] This is a side view showing a part of the configuration of a semiconductor device according to Modification 2. [Figure 5] This is an enlarged plan view showing a part of the configuration of the semiconductor device according to Modification 3. [Figure 6] This is an enlarged plan view showing a part of the configuration of the semiconductor device according to Modification 3. [Figure 7] This is an enlarged plan view showing a part of the configuration of the semiconductor device according to Modification 3. [Figure 8] This is an enlarged plan view showing a part of the configuration of the semiconductor device according to Modification 3. [Figure 9] This is an enlarged plan view showing a part of the configuration of the semiconductor device according to Modification 4. [Modes for carrying out the invention]

[0009] The embodiments will be described below with reference to the attached drawings. The features described in each of the embodiments below are illustrative, and not all features are necessarily required. In addition, in the descriptions below, the same or similar reference numerals are used for similar components in multiple embodiments, and the different components are mainly described. Also, in the descriptions below, specific positions and directions such as "top," "bottom," "left," "right," "front," or "back" do not necessarily have to coincide with the positions and directions in actual implementation.

[0010] <Embodiment 1> Figure 1 is a plan view showing the configuration of a semiconductor device according to this embodiment 1, and Figure 2 is an enlarged plan view showing a part of the configuration of Figure 1. The semiconductor device in Figure 1 comprises a first semiconductor switching element 1, a second semiconductor switching element 2, a plurality of chip wires 3, lead frames 4a, 4b, 4c, lead wires 5, gate wires 6, a control chip 7, and a sealing resin 8.

[0011] The first semiconductor switching element 1 is made of silicon. The second semiconductor switching element 2 has a smaller area in a plan view than the first semiconductor switching element 1 and is made of a wide-bandgap semiconductor. Wide-bandgap semiconductors include, for example, silicon carbide (SiC), gallium nitride (GaN), and diamond. The second semiconductor switching element 2, made of a wide-bandgap semiconductor, can operate more stably at high temperatures and high voltages, and can achieve faster switching speeds than the first semiconductor switching element 1, which is made of silicon.

[0012] Hereinafter, an example will be described in which the first semiconductor switching element 1 is an IGBT (Insulated Gate Bipolar Transistor), and the second semiconductor switching element 2 is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). However, the first semiconductor switching element 1 and the second semiconductor switching element 2 may be, for example, MOSFET (Metal Oxide Semiconductor Field Effect Transistor), IGBT, RC-IGBT (Reverse Conducting - IGBT), and the like.

[0013] In FIG. 2, a gate pad 1a and an emitter terminal are provided on the front side of the first semiconductor switching element 1, and a collector terminal is provided on the back side. In FIG. 2, a gate pad 2a and a source terminal are provided on the front side of the second semiconductor switching element 2, and a drain terminal is provided on the back side.

[0014] A plurality of chip wires 3, which are a plurality of first wires, connect the emitter terminal of the first semiconductor switching element 1 and the source terminal of the second semiconductor switching element 2. The diameter of each of the plurality of chip wires 3 is 40 μm or less, and each of the plurality of chip wires 3 is composed of silver or gold.

[0015] Since such chip wires 3 are relatively thin, for bonding the chip wires 3, for example, a ball bonding method can be used instead of a wedge bonding method. Thereby, the bonding area of the chip wires 3 can be reduced to the order of μm, and the design constraints due to the bonding area can be relaxed.

[0016] In the following description, the chip wires 3 are appropriately compared with thick wires. The diameter of the thick wire is thicker than the diameter of the chip wires 3, for example, 200 μm or more and 400 μm or less, and the thick wire is composed of, for example, aluminum.

[0017] By increasing the number of chip wires 3, the total current density of the plurality of chip wires 3 can be made equal to the current density of the thick wire. On the other hand, even when the number of chip wires 3 is increased, since the bonding area of each chip wire 3 is very small, the total bonding area of the plurality of chip wires 3 can be made smaller than the bonding area of the thick wire.

[0018] As described above, according to the configuration according to the first embodiment in which the first semiconductor switching element 1 and the second semiconductor switching element 2 are connected by a plurality of chip wires 3, the size of the semiconductor device can be reduced.

[0019] Also, in the first embodiment, as shown in FIGS. 1 and 2, the second semiconductor switching element 2 has a rectangular shape in a plan view in which the long side faces the first semiconductor switching element 1. The long side of the second semiconductor switching element 2 and the side of the first semiconductor switching element 1 facing the long side may be parallel or substantially parallel. According to such a configuration, a plurality of chip wires 3 can be arranged along the longitudinal direction of the second semiconductor switching element 2. As a result, the length of the plurality of chip wires 3 can be shortened, so that the size of the semiconductor device can be reduced.

[0020] Also, in the first embodiment, in a plan view, the longitudinal direction of the second semiconductor switching element 2 is perpendicular to the extending direction of the plurality of chip wires 3. According to such a configuration, the length of the plurality of chip wires 3 can be further shortened, so that the size of the semiconductor device can be further reduced. However, the longitudinal direction of the second semiconductor switching element 2 does not have to be perpendicular to the extending direction of the plurality of chip wires 3, and may be, for example, substantially perpendicular.

[0021] Lead frames 4a and 4b are each mounted with a first semiconductor switching element 1 and a second semiconductor switching element 2. Each of lead frames 4a and 4b is electrically connected to the collector terminal of the mounted first semiconductor switching element 1 and to the drain terminal of the mounted second semiconductor switching element 2. Lead frame 4c is not mounted with the first semiconductor switching element 1 and the second semiconductor switching element 2.

[0022] The lead wire 5 connects the first semiconductor switching element 1 mounted on the lead frame 4a to the lead frame 4b. The lead wire 5 also connects the first semiconductor switching element 1 mounted on the lead frame 4b to the lead frame 4c. In this embodiment 1, the lead wire 5 is a thick wire. The front surface of the first semiconductor switching element 1 is relatively large, providing sufficient space to accommodate the bonding area of ​​the thick wire. Therefore, even with a thick lead wire 5, the size of the semiconductor device does not substantially increase.

[0023] The gate wire 6 connects the gate pad 1a of the first semiconductor switching element 1 and the gate pad 2a of the second semiconductor switching element 2 to the control chip 7.

[0024] The control chip 7 controls the first semiconductor switching element 1 and the second semiconductor switching element 2 by controlling the gate voltages of the first semiconductor switching element 1 and the second semiconductor switching element 2 via the gate wire 6. In this embodiment 1, in a plan view, the control chip 7 is provided on the opposite side of the second semiconductor switching element 2 from the first semiconductor switching element 1, and the second semiconductor switching element 2 is provided between the control chip 7 and the first semiconductor switching element 1.

[0025] The control chip 7 on the right side of Figure 1 is an HVIC (High Voltage IC) that controls the current between lead frame 4a and lead frame 4b by controlling the gate voltages of three sets of first semiconductor switching elements 1 and second semiconductor switching elements 2 from the right. The control chip 7 on the left side of Figure 1 is an LVIC (Low Voltage IC) that controls the current between lead frame 4b and lead frame 4c by controlling the gate voltages of three sets of first semiconductor switching elements 1 and second semiconductor switching elements 2 from the left.

[0026] In the example shown in Figure 1, there were two control chips 7, but there may be only one. Also, in the example shown in Figure 1, there were six pairs of first semiconductor switching elements 1 and second semiconductor switching elements 2, but this is not the only option.

[0027] The sealing resin 8 covers the first semiconductor switching element 1, the second semiconductor switching element 2, and the control chip 7. The sealing resin 8 is formed by injecting the uncured resin into the mold through the mold gate. Figure 1 shows that the sealing resin 8 has a resin gate mark 8a, which is a trace of the gate, but the resin gate mark 8a is not essential in this embodiment 1.

[0028] <Summary of Embodiment 1> In the semiconductor device according to this embodiment 1 described above, the second semiconductor switching element 2 has a rectangular shape in plan view, with its longer side facing the first semiconductor switching element 1. Furthermore, multiple chip wires 3, each with a diameter of 40 μm or less and made of silver or gold, connect the first semiconductor switching element 1 and the second semiconductor switching element 2. This configuration allows for a reduction in the size of the semiconductor device.

[0029] Furthermore, in this embodiment 1, in a plan view, the control chip 7 is located on the opposite side of the second semiconductor switching element 2 from the first semiconductor switching element 1. With this configuration, the connection portions between the lead frames 4a, 4b, 4c and the lead wires 5 can be located on the opposite side of the first semiconductor switching element 1 from the control chip 7 and the second semiconductor switching element 2. As a result, the main current flows through the first semiconductor switching element 1 and the lead wires 5, reducing the current flowing through the second semiconductor switching element 2. This makes it possible to reduce the number of chip wires 3, which is expected to reduce manufacturing costs.

[0030] <Example 1> As shown in Figure 3, the connection points between the multiple chip wires 3 and the first semiconductor switching element 1 and the second semiconductor switching element 2 may be arranged alternately (i.e., in a staggered pattern) along the arrangement direction of the multiple chip wires 3. With this configuration, the number of multiple chip wires 3 per unit area can be increased, so the total number of multiple chip wires 3 can be increased or the total bonding area of ​​the multiple chip wires 3 can be reduced. Since the same current is divided and flows through the multiple chip wires 3, there is no practical problem even if the chip wires 3 come into contact with each other.

[0031] <Modification 2> Figure 4 is a side view of a part of the configuration of the semiconductor device according to this modified example 2, as seen from the resin gate trace 8a side in Figure 1. As shown in Figure 4, the height of the loops of the multiple chip wires 3 may increase in order from the distance from the resin gate trace 8a.

[0032] With this configuration, the flow of resin injected from the mold gate during the formation of the sealing resin 8 can be suppressed as it passes through the multiple chip wires 3. Therefore, by providing a component with weak mechanical strength on the side opposite the mold gate with respect to the multiple chip wires 3, defects in the component due to resin flow can be suppressed. In the example in Figure 4, this component is a relatively long gate wire 6 connecting the first semiconductor switching element 1 and the control chip 7, and the above configuration can suppress the breakage of this gate wire 6.

[0033] <Variation 3> In the configuration shown in Figure 1 of Embodiment 1, the lead wire 5 was a thick wire, but it is not limited to this. As shown in Figure 5, the second wire, the lead wire 5, may have a diameter of 40 μm or less, similar to the multiple tip wires 3, and may be a wire made of silver or gold.

[0034] In other words, the lead wire 5 connecting the first semiconductor switching element 1 mounted on the first lead frame, lead frame 4a, to the second lead frame, lead frame 4b, may be a wire with a diameter of 40 μm or less. Similarly, the lead wire 5 connecting the first semiconductor switching element 1 mounted on the first lead frame, lead frame 4b, to the second lead frame, lead frame 4c, may also be a wire with a diameter of 40 μm or less.

[0035] This configuration allows for a reduction in the bonding area of ​​the lead wire 5, thereby reducing the size of the semiconductor device. Furthermore, using the same wire for both the chip wire 3 and the lead wire 5 improves manufacturability.

[0036] Furthermore, as shown in Figures 6 to 8, a third wire, a thick wire 9, with a larger diameter than the chip wire 3, may be provided. As shown in Figure 6, the thick wire 9 may work in cooperation with the lead wire 5 in Figure 5 to connect the first semiconductor switching element 1 mounted on the lead frames 4a and 4b to the lead frames 4b and 4c, respectively. As shown in Figure 7, the thick wire 9 may work in cooperation with the chip wire 3 in Figure 5 to connect the first semiconductor switching element 1 to the second semiconductor switching element 2. As shown in Figure 8, the thick wire 9 may connect the first semiconductor switching element 1 mounted on the lead frames 4a and 4b to the lead frames 4b and 4c, respectively, and also connect the first semiconductor switching element 1 to the second semiconductor switching element 2.

[0037] This configuration allows for the use of thick wires 9 that are less prone to breakage, thereby increasing the reliability of the semiconductor device. Furthermore, it ensures sufficient current density in each path.

[0038] <Modification 4> As shown in Figure 9, the gate wire 6, which is the fourth wire connecting each of the first semiconductor switching element 1 and the second semiconductor switching element 2 to the control chip 7, may extend in a direction perpendicular to the direction in which the first semiconductor switching element 1 and the second semiconductor switching element 2 are arranged. With this configuration, the length of the gate wire 6 can be shortened, thereby suppressing breakage of the gate wire 6 during resin injection of the sealing resin 8.

[0039] The details of the embodiment can be modified or omitted as appropriate.

[0040] The various aspects of this disclosure are summarized below as an appendix.

[0041] (Note 1) A first semiconductor switching element made of silicon, A second semiconductor switching element has a rectangular shape in plan view, with its longer side facing the first semiconductor switching element, and has a smaller area in plan view than the first semiconductor switching element, and is made of a wide-bandgap semiconductor. A plurality of first wires, each with a diameter of 40 μm or less and made of silver or gold, connect the first semiconductor switching element and the second semiconductor switching element. A semiconductor device equipped with the following features.

[0042] (Note 2) The semiconductor device according to Appendix 1, wherein, in a plan view, the longitudinal direction of the second semiconductor switching element is perpendicular to the extending direction of the plurality of first wires.

[0043] (Note 3) The semiconductor device according to Appendix 1 or Appendix 2, wherein the connection points of the plurality of first wires with the first semiconductor switching element and the second semiconductor switching element are arranged alternately along the arrangement direction of the plurality of first wires.

[0044] (Note 4) A control chip for controlling the first semiconductor switching element and the second semiconductor switching element, The resin gate marks are present, and the sealing resin covers the first semiconductor switching element, the second semiconductor switching element, and the control chip. Furthermore, The semiconductor device according to any one of the appendices 1 to 3, wherein the height of the loops of the plurality of first wires increases in order from the distance from the resin gate trace.

[0045] (Note 5) The system further comprises a control chip for controlling the first semiconductor switching element and the second semiconductor switching element, In a plan view, the control chip is provided on the opposite side of the second semiconductor switching element from the first semiconductor switching element, as described in any one of the appendices 1 to 3.

[0046] (Note 6) A first lead frame on which the first semiconductor switching element and the second semiconductor switching element are mounted, The second lead frame, A plurality of second wires, each with a diameter of 40 μm or less, connect the first semiconductor switching element mounted on the first lead frame to the second lead frame. A semiconductor device further comprising any one of the appendices 1 to 5.

[0047] (Note 7) A first lead frame on which the first semiconductor switching element and the second semiconductor switching element are mounted, The second lead frame, A third wire, having a diameter larger than the first wire, connects at least one of the following: the space between the first semiconductor switching element mounted on the first lead frame and the second lead frame, and the space between the first semiconductor switching element and the second semiconductor switching element. A semiconductor device further comprising any one of the appendices 1 to 5.

[0048] (Note 8) A control chip for controlling the first semiconductor switching element and the second semiconductor switching element, A fourth wire connects the first semiconductor switching element and the second semiconductor switching element to the control chip, and extends perpendicular to the direction in which the first semiconductor switching element and the second semiconductor switching element are arranged. A semiconductor device as described in any one of the appendices 1 to 3, further comprising the above. [Explanation of symbols]

[0049] 1. First semiconductor switching element, 2. Second semiconductor switching element, 3. Chip wire, 4a, 4b, 4c. Lead frame, 5. Lead wire, 6. Gate wire, 7. Control chip, 8. Encapsulation resin, 8a. Resin gate mark, 9. Thick wire.

Claims

1. A first semiconductor switching element made of silicon, A second semiconductor switching element has a rectangular shape in plan view, with its longer side facing the first semiconductor switching element, and has a smaller area in plan view than the first semiconductor switching element, and is made of a wide-bandgap semiconductor. A plurality of first wires, each with a diameter of 40 μm or less and made of silver or gold, connect the first semiconductor switching element and the second semiconductor switching element. A control chip for controlling the first semiconductor switching element and the second semiconductor switching element, A fourth wire connects the first semiconductor switching element and the second semiconductor switching element to the control chip, and extends perpendicular to the direction in which the first semiconductor switching element and the second semiconductor switching element are arranged. A semiconductor device equipped with the following features.

2. A semiconductor device according to claim 1, A semiconductor device in which, in a plan view, the longitudinal direction of the second semiconductor switching element is perpendicular to the extending direction of the plurality of first wires.

3. A semiconductor device according to claim 1 or claim 2, A semiconductor device in which the connection points of the plurality of first wires with the first semiconductor switching element and the second semiconductor switching element are arranged alternately along the arrangement direction of the plurality of first wires.

4. A semiconductor device according to claim 1 or claim 2, The resin gate marks are present, and the sealing resin covers the first semiconductor switching element, the second semiconductor switching element, and the control chip. Furthermore, A semiconductor device in which the heights of the loops of the plurality of first wires increase in order from the distance from the resin gate mark.

5. A semiconductor device according to claim 1 or claim 2, A first lead frame on which the first semiconductor switching element and the second semiconductor switching element are mounted, The second lead frame and A plurality of second wires, each with a diameter of 40 μm or less, connect the first semiconductor switching element mounted on the first lead frame to the second lead frame. A semiconductor device that further enhances these features.

6. A semiconductor device according to claim 1 or claim 2, A first lead frame on which the first semiconductor switching element and the second semiconductor switching element are mounted, The second lead frame and A third wire, having a diameter larger than the first wire, connects at least one of the following: the space between the first semiconductor switching element mounted on the first lead frame and the second lead frame, and the space between the first semiconductor switching element and the second semiconductor switching element. A semiconductor device that further enhances these features.

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