Semiconductor devices and methods

Abstract

The present disclosure relates to a semiconductor device including a substrate including a first wide bandgap semiconductor material and a first region of a first conductivity type and a second region of a second conductivity type disposed above the substrate, the first region and the second region including a second wide bandgap semiconductor material, the first region and the second region forming a Zener PN diode configured as an antifuse. A corresponding method for manufacturing the semiconductor device is also provided.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. This disclosure further relates to a method for manufacturing such semiconductor devices. [Background Art]

[0002] An anti-fuse is a semiconductor electrical device that has a high resistance in its initial state. After a special process called programming, the anti-fuse becomes a low resistance and performs a function opposite to that of a fuse. Anti-fuses are widely used in integrated circuits as programmable logic devices (for design customization), one-time programmable read-only memories (OTP), trimming of analog component values, adjustment of voltage reference circuits, or die and chip serial code identification (traceability).

[0003] One of the most efficient and cost-effective anti-fuses developed with silicon-based technology is the Zener type anti-fuse, also called Zener zap. Zener type anti-fuses exist in bipolar technology, complementary metal oxide semiconductor (CMOS), bipolar CMOS (Bi-CMOS), mixed signal, and smart power technology.

[0004] A Zener device, or generally a PN junction or Zener diode, is formed by at least two semiconductor elements (different doping elements) of opposite conductivity types. One element is of the N type, i.e., doped so that the element can provide an excess of negative charges (electrons), while the other element is of the P type, doped so that the element can provide an excess of positive charges (holes).

[0005] A Zener-type antifuse is programmed by applying either a high voltage or a high current to a Zener diode for a short period of time. The voltage or current spike generates enough energy to overheat the structure, permanently damaging it and thereby short-circuiting it. Programming with a current spike (or voltage spike) is called Zener zapping. Zener zapping is schematically shown in Figure 1.

[0006] Wide-bandgap (WBG) technology is a new technology being developed to replace silicon technology. Compared to silicon, the superior material properties of wide-bandgap (WBG) technology make it more suitable for a variety of applications and fields, such as power applications. Zener-type antifuses are not currently used in WBG semiconductor technology for several reasons, including the following:

[0007] a) Maturity. WBG technology is still under research and development and, with the exception of gallium nitride (GaN), for example, is not yet ready to be incorporated into existing technologies.

[0008] b) Many topologies used in WBG are vertical, which can make it difficult to integrate devices.

[0009] Currently, there are no known implementations of Zener-type antifuses in WBG technology. In recent years, academia and industry have focused on integrating basic elements and circuits around power GaN high electron mobility transistors (HEMTs).

[0010] A natural solution that industry might adopt is to co-integrate GaN HEMT power devices with silicon-based antifuses. However, this means encapsulating two different dies from two different technologies within a single package. This solution may require a complex packaging scheme, particularly regarding the placement and routing / connection of the different dies. In addition, the reliability of the entire co-package system may not be guaranteed, and the use of two dies can result in a larger resulting chip area. [Overview of the Initiative] [Means for solving the problem]

[0011] This disclosure aims to improve the above-mentioned solution by monolithically incorporating a Zener-type antifuse into WBG technology.

[0012] This is achieved by the solution provided in the independent claim. A valid implementation is defined in the dependent claim.

[0013] According to a first embodiment, a semiconductor device is provided comprising a substrate containing a first wide-bandgap semiconductor material, and a first region of a first conductivity type and a second region of a second conductivity type disposed above the substrate, the first region of the first conductivity type and the second region of the second conductivity type each containing a second WBG semiconductor material, wherein the first region and the second region form a Zener PN diode configured as an antifuse.

[0014] WBG semiconductor materials include materials with a band gap in the range of 2 eV or more.

[0015] According to the first embodiment, a Zener-type antifuse can be monolithically incorporated into WBG technology.

[0016] In one implementation of the first embodiment, the first and second regions are arranged in a horizontal configuration with respect to their arrangement above the substrate, with the first region positioned above the substrate and the second region positioned above the substrate, adjacent to the first region. Alternatively, the first and second regions are arranged in a vertical configuration with respect to their arrangement above the substrate, with the second region positioned above the first region and the first region positioned above the substrate.

[0017] This offers the advantage that Zener-type antifuses can be easily incorporated into both horizontal and vertical WBG technologies.

[0018] In one implementation of the first embodiment, the first region and the second region are separated by a certain distance. Alternatively, the first region and the second region are adjacent. Alternatively, the first region and the second region partially overlap.

[0019] This offers the advantage that the efficiency of the programming or zapping process can be optimized with respect to time, applied voltage, applied current, and / or dissipated energy.

[0020] In one implementation of the first embodiment, the first region has a first shape including a first lateral projection. The first lateral projection has a tip shape, a truncated tip shape, or another polygonal shape, or the first shape includes a cylindrical shape, or a cylindrical shape having the first lateral projection, and the first lateral projection has a tip shape, a truncated tip shape, or another polygonal shape. Furthermore, the second region has a second shape including a second lateral projection. The second lateral projection has a tip shape, a truncated tip shape, or another polygonal shape, or the second shape includes a cylindrical shape, or a cylindrical shape having the second lateral projection, and the lateral projection has a tip shape, a truncated tip shape, or another polygonal shape.

[0021] This enables further optimization of the efficiency of the programming or zapping process with respect to time, the applied voltage, the applied current, and / or the dissipated energy.

[0022] In one implementation of the first aspect, the semiconductor device further includes a first metal gate in electrical contact with the first region and a second metal gate in electrical contact with the second region.

[0023] This results in the formation of a metal filament between the first region of the first conductivity type and the second region of the second conductivity type, causing an electrical short circuit, thereby providing the advantage that programming of a Zener PN junction configured as an anti-fuse may be possible.

[0024] In one implementation of the first aspect, the semiconductor device further includes a semiconductor layer including a third wide-bandgap semiconductor material. The semiconductor layer is disposed between the substrate and the first region and the second region, respectively.

[0025] This results in the formation of a channel below the semiconductor layer in the regions under the first region and the second region, thereby providing the advantage that implementation of a Zener-type anti-fuse in HEMT technology may be possible.

[0026] In one implementation of the first aspect, the semiconductor device further includes a semiconductor layer including a third wide-bandgap semiconductor material, the semiconductor layer is disposed above the first region and the second region, or the second region is disposed above the first region and the semiconductor layer is disposed above the second region.

[0027] This results in the formation of a channel in the region above the first region and the second region, thereby providing the advantage that implementation of a Zener-type anti-fuse in vertical HEMT technology may be possible.

[0028] In one implementation of the first aspect, the first metal gate and the second metal gate contact the first region and the second region through a semiconductor layer. Alternatively, the second metal gate contacts the second region through a semiconductor layer.

[0029] In one implementation of the first aspect, the semiconductor device includes at least one additional first region of a first conductivity type and at least one additional second region of a second conductivity type disposed above the semiconductor layer, where the at least one additional first region and the at least one additional second region include a second wide-bandgap semiconductor material, at least one additional first metal gate in electrical contact with the at least one additional first region, and at least one additional second metal gate in electrical contact with the at least one additional second region, and at least one additional semiconductor layer including a third wide-bandgap semiconductor material and disposed above the at least one additional first region and the at least one additional second region, where the at least one additional first metal gate and the at least one additional second metal gate contact the at least one additional first region and the at least one additional second region through the at least one additional semiconductor layer, and the at least one additional first region and the at least one additional second region form at least one additional Zener PN diode configured as an anti-fuse.

[0030] Thereby, the advantage is obtained that a multi-stack of Zener-type anti-fuses in WBG technology can be created.

[0031] In one implementation of the first aspect, the first region and the second region are disposed within an N-well structure or a P-well structure formed in a substrate. Alternatively, the first region is disposed within a first well structure, the second region is disposed within a second well structure, and the first well structure and the second well structure include an N-well structure or a P-well structure formed in a substrate.

[0032] This offers the advantage that Zener-type antifuses can be incorporated into WBG (Wide Bandgap) and ultra-wide bandgap (UWBG) technologies.

[0033] In this disclosure, UWBG semiconductor materials include semiconductor materials having a bandgap greater than 4 eV.

[0034] In one implementation of the first embodiment, the semiconductor device further includes a first region, an additional or alternative second region, and at least one structure of thermal insulating material that partially or completely contacts the substrate, wherein the at least one structure of thermal insulating material includes silicon dioxide (SiO2), or a nitride compound comprising any one of silicon nitride (Si3N4), aluminum gallium nitride (AlGaN), or aluminum nitride (AlN).

[0035] This results in a thermal increase during the zapping process, such as overheating, which has the advantage of facilitating the programming of the Zener PN diode configured as an antifuse.

[0036] In one implementation of the first embodiment, the semiconductor device further includes an intermediate region of a third conductivity type disposed between a first region and a second region, the intermediate region comprising a second wide-bandgap semiconductor material, and the intermediate region being a P-type region, an N-type region, or an undoped region.

[0037] This offers the advantage of further simplifying the programming or zapping process for Zener PN diodes configured as antifuses.

[0038] In one implementation of the first embodiment, the second wide-bandgap semiconductor material includes GaN.

[0039] In one implementation of the first embodiment, the third wide-bandgap material includes AlGaN.

[0040] In one implementation of the first embodiment, the first metal gate is in partial or total contact with the first region. Alternatively, the first metal gate extends partially or total within the first region. The second metal gate is in partial or total contact with the second region, or the second metal gate extends partially or total within the second region.

[0041] In one implementation of the first embodiment, the first metal gate and the second metal gate include a metal stack containing aluminum, titanium, copper, gold, or another metallic element, or one of Ni / Au, Ni / Ag, Pd / Au, Cr / Au, Pt / Au, Ti / Pt / Au, Ni / Si, W / Si, Ti / Al, Ti / Al / Ti, or TiN / Al / TiN.

[0042] In one implementation of the first embodiment, the first wide-bandgap semiconductor material comprises silicon carbide (SiC) or gallium oxide (Ga2O3). Alternatively, the first wide-bandgap semiconductor material comprises a heteroepitaxial bulk material, the heteroepitaxial bulk material comprising gallium nitride (GaN) on silicon (Si), GaN on SiC, GaN on diamond, or a wide-bandgap semiconductor on an insulating material.

[0043] A second aspect provides a method for manufacturing a semiconductor device. The method includes the steps of: preparing a substrate containing a first wide-bandgap semiconductor material; and forming a first region of a first conductivity type and a second region of a second conductivity type, which are disposed on the substrate, wherein the first region and the second region contain a second wide-bandgap semiconductor material, and the first region and the second region form a Zener PN diode configured as an antifuse.

[0044] Wide-bandgap semiconductor materials include materials with a bandgap exceeding 2 eV.

[0045] This offers the advantage of providing a Zener-type antifuse that can be monolithically integrated into WBG technology.

[0046] In one implementation of the second embodiment, the first and second regions are arranged in a horizontal configuration with respect to their arrangement above the substrate, with the first region positioned above the substrate and the second region positioned above the substrate, adjacent to the first region. Alternatively, the first and second regions are arranged in a vertical configuration with respect to their arrangement above the substrate, with the second region positioned above the first region and the first region positioned above the substrate.

[0047] This offers the advantage that Zener-type antifuses can be easily incorporated into both horizontal and vertical WBG technologies.

[0048] In one implementation of the second aspect, the first region and the second region are separated by a certain distance. Alternatively, the first region and the second region are adjacent. Alternatively, the first region and the second region partially overlap.

[0049] This offers the advantage that the efficiency of the programming or zapping process can be optimized with respect to time, applied voltage, applied current, and / or dissipated energy.

[0050] In one implementation of the second embodiment, the first region has a first shape including a first lateral projection. The first lateral projection has a tip shape, a truncated tip shape, or another polygonal shape, or the first shape includes a cylindrical shape, or a cylindrical shape having the first lateral projection, and the first lateral projection has a tip shape, a truncated tip shape, or another polygonal shape. Furthermore, the second region has a second shape including a second lateral projection. The second lateral projection has a tip shape, a truncated tip shape, or another polygonal shape, or the second shape includes a cylindrical shape, or a cylindrical shape having the second lateral projection, and the lateral projection has a tip shape, a truncated tip shape, or another polygonal shape.

[0051] This allows for further optimization of the efficiency of the programming or zapping process with respect to time, applied voltage, applied current, and / or dissipated energy.

[0052] In one implementation of the second embodiment, the method further includes the step of forming a first metal gate that electrically contacts a first region and a second metal gate that electrically contacts a second region.

[0053] This results in the formation of a metal filament between the first region of the first conductivity type and the second region of the second conductivity type, causing an electrical short circuit, which has the advantage of potentially enabling the programming of the Zener PN junction configured as an antifuse.

[0054] In one implementation form of the second embodiment, the method further includes a semiconductor layer comprising a third wide-bandgap semiconductor material disposed between the substrate and the first region and the second region, respectively.

[0055] This creates channels beneath the semiconductor layers in the regions below the first and second regions, which has the advantage of enabling the implementation of Zener-type antifuses in HEMT technology.

[0056] In one implementation of the second embodiment, the method further includes the step of forming a semiconductor layer comprising a third wide-bandgap semiconductor material, wherein the semiconductor layer is located above the first and second regions, or the second region is located above the first region and the semiconductor layer is located above the second region.

[0057] This creates a channel in the region above the first and second regions, which has the advantage of enabling the implementation of a Zener-type antifuse in vertical HEMT technology.

[0058] In one implementation of the second embodiment, the first metal gate and the second metal gate contact the first region and the second region via a semiconductor layer. Alternatively, the second metal gate contacts the second region via a semiconductor layer.

[0059] In one implementation embodiment of the second aspect, the method comprises the steps of forming at least one additional first region of a first conductivity type and at least one additional second region of a second conductivity type, which are disposed above a semiconductor layer, wherein the at least one additional first region and at least one additional second region include a second wide-bandgap semiconductor material; forming at least one additional first metal gate electrically in contact with the at least one additional first region and at least one additional second metal gate electrically in contact with the at least one additional second region; and forming a third wide-bandgap The method further includes the step of forming at least one additional semiconductor layer comprising a cap semiconductor material and positioned above at least one additional first region and at least one additional second region, wherein at least one additional first metal gate and at least one additional second metal gate are in contact with at least one additional first region and at least one additional second region via at least one additional semiconductor layer, and the at least one additional first region and at least one additional second region form at least one additional Zener PN diode configured as an antifuse.

[0060] This offers the advantage of being able to create a multi-stack of Zener-type antifuses in WBG technology.

[0061] In one implementation of the second embodiment, the first region and the second region are located within an N-well or P-well structure formed in the substrate. Alternatively, the first region is located within a first well structure, and the second region is located within a second well structure, wherein the first and second well structures include an N-well or P-well structure formed in the substrate.

[0062] This offers the advantage that Zener-type antifuses can be incorporated into WBG and UWBG technologies.

[0063] In this disclosure, UWBG semiconductor materials include semiconductor materials having a bandgap greater than 4 eV.

[0064] In one implementation of the second embodiment, the method further comprises the steps of forming a first region, an additional or alternative second region, and at least one structure of thermal insulating material that is in partial or complete contact with the substrate, wherein the at least one structure of thermal insulating material comprises SiO2, or a nitride compound comprising one of Si3N4, AlGaN, or AlN.

[0065] This results in a thermal increase during the zapping process, such as overheating, which has the advantage of facilitating the programming of the Zener PN diode configured as an antifuse.

[0066] In one implementation of the second embodiment, the method further includes an intermediate region of a third conductivity type disposed between a first region and a second region, the intermediate region comprising a second wide-bandgap semiconductor material, and the intermediate region being a P-type region, an N-type region, or an undoped region.

[0067] This offers the advantage of further simplifying the programming or zapping process for Zener PN diodes configured as antifuses.

[0068] In one implementation of the second embodiment, the second wide-bandgap semiconductor material includes GaN.

[0069] In one implementation of the second embodiment, the third wide-bandgap material includes AlGaN.

[0070] In one implementation of the second embodiment, the first metal gate is in partial or total contact with the first region. Alternatively, the first metal gate extends partially or total within the first region. The second metal gate is in partial or total contact with the second region, or the second metal gate extends partially or total within the second region.

[0071] In one implementation of the first embodiment, the first metal gate and the second metal gate include a metal stack containing aluminum, titanium, copper, gold, or another metallic element, or one of Ni / Au, Ni / Ag, Pd / Au, Cr / Au, Pt / Au, Ti / Pt / Au, Ni / Si, W / Si, Ti / Al, Ti / Al / Ti, or TiN / Al / TiN.

[0072] In one implementation of the second embodiment, the first wide-bandgap semiconductor material comprises SiC or Ga2O3. Alternatively, the first wide-bandgap semiconductor material comprises a heteroepitaxial bulk material, the heteroepitaxial bulk material comprising GaN on Si, or GaN on SiC, or GaN on diamond, or a wide-bandgap semiconductor on an insulating material.

[0073] The method and its implementation according to the second embodiment provide the same advantages and effects as those described above for the device and its respective implementation according to the first embodiment.

[0074] The above-described aspects and implementations of this disclosure will be described in the following description in relation to the attached drawings. [Brief explanation of the drawing]

[0075] [Figure 1] This is a schematic diagram illustrating the Zener zapping process. [Figure 2] This is a schematic diagram of the semiconductor device disclosed herein. [Figure 3a] These are top views of examples of the first and second shapes according to this disclosure. [Figure 3b] These are top views of examples of the first and second shapes according to this disclosure. [Figure 3c] These are top views of examples of the first and second shapes according to this disclosure. [Figure 3d] These are top views of examples of the first and second shapes according to this disclosure. [Figure 4] This is a schematic diagram of the semiconductor device disclosed herein. [Figure 5a] This is a schematic diagram of an example of a metal gate in a semiconductor device according to this disclosure. [Figure 5b] This is a schematic diagram of an example of a metal gate in a semiconductor device according to this disclosure. [Figure 5c] This is a schematic diagram of an example of a metal gate in a semiconductor device according to this disclosure. [Figure 6a] This is a schematic diagram of an example of a metal gate in a semiconductor device according to this disclosure. [Figure 6b] This is a schematic diagram of an example of a metal gate in a semiconductor device according to this disclosure. [Figure 7] This is a schematic diagram of the semiconductor device disclosed herein. [Figure 8a] This is a schematic diagram of the semiconductor device disclosed herein. [Figure 8b] This is a schematic diagram of the semiconductor device disclosed herein. [Figure 8c] This is a schematic diagram of the semiconductor device disclosed herein. [Figure 9a] This is a schematic diagram of the semiconductor device disclosed herein. [Figure 9b] This is a schematic diagram of the semiconductor device disclosed herein. [Figure 10] This is a schematic diagram of the semiconductor device disclosed herein. [Figure 11] This is a schematic diagram of the semiconductor device disclosed herein. [Figure 12] This is a schematic diagram of the semiconductor device disclosed herein. [Figure 13] This figure shows a method for manufacturing semiconductor devices according to this disclosure. [Modes for carrying out the invention]

[0076] Figure 2 shows a schematic diagram of a semiconductor device 10 according to an exemplary embodiment of the present disclosure. The semiconductor device 10 includes a substrate 12, a first region 14a of a first conductivity type, and a second region 14b of a second conductivity type 14b. The first region 14a and the second region 14b are located above the substrate 12.

[0077] The substrate 12 comprises a first WBG semiconductor material comprising SiC or Ga2O3. Alternatively, the first WBG semiconductor material comprises a heteroepitaxial bulk material. The heteroepitaxial bulk material comprises GaN on silicon (Si), GaN on SiC, GaN on diamond, or a WBG semiconductor on an insulating material. The substrate 12 may include a base structure having one or more layers formed by an epitaxial growth process on top.

[0078] The first region 14a and the second region 14b contain a second WBG semiconductor material. The second WBG semiconductor material contains GaN.

[0079] For example, conventional semiconductors such as silicon have a band gap in the range of 0.6 to 1.5 eV, while WBG materials have a band gap in the range of over 2 eV. This larger band gap allows WBG semiconductor-based devices to operate at higher voltages, frequencies, and temperatures than devices based on conventional semiconductor materials.

[0080] In this disclosure, WBG semiconductor materials include semiconductor materials having a bandgap in the range of 2 eV or more.

[0081] For example, the bandgap value of GaN is 3.44 eV.

[0082] The first region 14a of the first conductivity type may be a P-type region or an N-type region. Conversely, the second region 14b of the second conductivity type may be an N-type region or a P-type region. In this way, the first region 14a and the second region 14b form a Zener PN diode configured as an antifuse.

[0083] Generally, semiconductor devices 10 can be manufactured by standard mask / injection processes, controlled continuous epitaxial growth and continuous epitaxy, and etching techniques.

[0084] The first region 14a of the first conductivity type and the second region 14b of the second conductivity type can be fabricated by conventional techniques for WBG technology, for example, from undoped GaN by implantation, in-situ or ex-situ dopant integration of dopants during epitaxial growth, metal-organic chemical vapor deposition (MOCVD) growth, molecular beam epitaxy (MBE), delta doping, or other deposition / doping techniques.

[0085] Alternatively, the first region 14a of the first conductivity type and the second region 14b of the second conductivity type may be created by continuous epitaxial growth combined with selective etching and regrowth, thereby allowing for fine-tuning of the dopant profile in each region 14a and 14b.

[0086] The chemical species used to dope the first region 14a and the second region 14b may be, for example, magnesium, iron, or silicon, but are not limited to these.

[0087] The design of a Zener-type antifuse relies on creating a deliberate abrupt change in geometric layout in two regions 14a and 14b with different conductivity types to enhance the electric field and cause premature failure of the PN diode. The selection of geometric shape and doping level may be done to optimize the efficiency of the programming process with respect to time, applied voltage, applied current, and / or dissipated energy.

[0088] In this manner, in the present disclosure, the first region 14a of the first conductivity type has a first shape, and the second region 14b of the second conductivity type has a second shape, thereby optimizing the efficiency of the programming or zapping process.

[0089] Figures 3a to 3d show top views of various examples of the first shape of the first region 14a and the second shape of the second region 14b. The first region 14a may have a first shape including a first lateral projection. The first lateral projection may have a tip shape (see Figure 3a), a truncated tip shape (see Figure 3b), or another polygonal shape. Alternatively, the first shape may include a cylindrical shape (e.g., a circular shape shown in the top view of Figure 3c), or a cylindrical shape having the first lateral projection, the first lateral projection having a tip shape, a truncated tip shape, or another polygonal shape (see Figures 3c and 3d).

[0090] The second region 14b may have a second shape including a second lateral projection. The second lateral projection may have a tip shape (see Figure 3a), a truncated tip shape (see Figure 3b), or another polygonal shape, or the second shape may be cylindrical (see Figure 3c), or include a cylindrical shape with a second lateral projection, the lateral projection having a tip shape, a truncated tip shape, or another polygonal shape (see Figures 3c and 3d).

[0091] The first shape of the first region 14a and the second shape of the second region 14b may be identical or they may be different from each other.

[0092] Furthermore, the first region 14a and the second region 14b may be separated by a distance D shown in the first column (left to right) of Figures 3a and 3b. Alternatively, the first region 14a and the second region 14b may be adjacent. Alternatively, the first region 14a and the second region 14b may partially overlap, for example, as shown in the fourth column of Figures 3a and 3b.

[0093] The first lateral projection of the first region 14a and the second lateral projection of the second region 14b can be aligned, for example, as shown in the first, second, and fourth columns of Figures 3a and 3b.

[0094] For example, as shown in Figure 3a, a layout in which the first shape of the first region 14a has a first lateral projection with a tip shape, and the second shape of the second region 14a has a second lateral projection with a tip shape, may enable the most energy-efficient programming process, and these regions may be separated by a certain distance, adjacent, or partially overlapping.

[0095] For example, in a layout as shown in Figure 3b, where the first shape of the first region 14a has a first lateral projection having a truncated tip shape or another polygonal shape, and the second shape of the second region 14a has a second lateral projection having a truncated tip shape or another polygonal shape, the energy required to program the Zener antifuse can be adjusted to meet specific technical requirements.

[0096] The fabrication of the first region 14a and the second region 14b, as well as the first shape of the first region 14a and the second shape of the second region 14b, can be controlled by a combination of epitaxy, etching, and injection processes.

[0097] To achieve an efficient zapping process, the thickness of the first region 14a and the thickness of the second region 14b can be adjusted.

[0098] In the embodiment shown in Figure 2, the first region 14a and the second region 14b are arranged in a horizontal configuration with respect to their placement above the substrate 12. As a result, the first region 14a is positioned above the substrate 12, and the second region 14b is positioned above the substrate 12, next to the first region 14a.

[0099] In the exemplary embodiment shown in Figure 4, the semiconductor device 10 further includes an intermediate region 16 of a third conductivity type located between the first region 14a and the second region 14b. The intermediate region 16 comprises a second wide-bandgap semiconductor material, and the intermediate region 16 is either a P-type region or an N-type region. Alternatively, the intermediate region 16 is an undoped region.

[0100] To achieve an efficient zapping process, the thicknesses of the first region 14a, the second region 14b, and the intermediate region 16 can be adjusted. Furthermore, the intermediate region 16 for the third conductivity type, like the first region 14a and the second region 14b, can be fabricated by conventional techniques for WBG technology.

[0101] In this embodiment, the semiconductor device 10 further includes semiconductor layers 20 disposed between the substrate 12 and a first region 14a and a second region 14b, respectively. The semiconductor layer 20 includes a third WBG semiconductor material. For example, the third WBG semiconductor material includes AlGaN and has a bandgap value of about 6 eV.

[0102] In this embodiment, the semiconductor layer 20 provides a two-dimensional electron gas (2DEG) at the AlGaN / GaN interface below the first region 14a and the second region 14b, for example, below a Zener PN diode configured as an antifuse, and the two-dimensional electron gas (2DEG) can be adjusted by further insulating injection.

[0103] The first region 14a of the first conductivity type, the second region 14b of the second conductivity type, and the intermediate region 16 of the third conductivity type can be grown epitaxially on the semiconductor layer 20. Alternatively, the first region 14a of the first conductivity type, the second region 14b of the second conductivity type, and the intermediate region 16 of the third conductivity type may be grown on a region that does not contain the semiconductor layer 20, for example, after partial or total etching of the semiconductor layer 20.

[0104] The semiconductor device 10 may further include a first metal gate 18a that can electrically contact a first region 14a, and a second metal gate 18b that can electrically contact a second region 14b. The first metal gate 18a and the second metal gate 18b may contain aluminum, titanium, copper, gold, or another metallic element. Alternatively, the first metal gate 18a and the second metal gate 18b may contain a metal stack containing any one of Ni / Au, Ni / Ag, Pd / Au, Cr / Au, Pt / Au, Ti / Pt / Au, Ni / Si, W / Si, Ti / Al, Ti / Al / Ti, or TiN / Al / TiN. However, other suitable combinations of materials may also be possible.

[0105] The first metal gate 18a may be in partial or total contact with the first region 14a. Alternatively, the first metal gate 18a may extend partially or total into the first region 14a. The second metal gate 18b may be in partial or total contact with the second region 14b. Alternatively, the second metal gate 18b may extend partially or total into the second region 14b.

[0106] Optionally, the first metal gate 18a or the second metal gate 18b may be in partial or complete contact with the intermediate region 16.

[0107] Figures 5a to 5c show schematic diagrams of examples of metal gates within a semiconductor device 10, and for clarity only the second region 14b of the second conductivity type, the second metal gate 18b, a portion of the semiconductor layer 20 below the second region 14b, and a portion of the substrate 12 below the semiconductor layer 20 are shown. In the examples shown in Figures 5a and 5c, the second metal gate 18b is in partial contact with the second region 14b, whereas the example in Figure 5b shows the second metal gate 18b in full contact with the second region 14b.

[0108] Figures 6a and 6b show schematic diagrams of examples of metal gates in a semiconductor device 10. For clarity, only the second region 14b of the second conductivity type, the second metal gate 18b, a portion of the semiconductor layer 20 below the second region 14b, and a portion of the substrate 12 below the semiconductor layer 20 are shown. In the example shown in Figure 6a, the second metal gate 18b extends partially into the second region 14b, for example, a portion of the width of the second metal gate 18b extends into the second region 14b. In the example shown in Figure 6b, the second metal gate 18b extends entirely into the second region 14b, for example, the entire width of the second metal gate 18b extends into the second region 14b.

[0109] The first metal gate 18a and the second metal gate 18b can be fabricated by standard deposition / sputtering / filling / etching of a metallic element on the surface of the first region 14a and the second region 14b, respectively. The first metal gate 18a and the second metal gate 18b can be easily fabricated, for example, during wafer manufacturing. Alternatively, the first metal gate 18a and the second metal gate 18b can be fabricated by metal deposition / sputtering / filling of the wafer backside etching region. Alternatively, the first metal gate 18a and the second metal gate 18b can be fabricated by a combination of both fabrication techniques.

[0110] Electrical isolation (insulation) may be provided between the first metal gate 18a and the second metal gate 18b. This can be achieved by providing a certain distance between the first metal gate 18a and the second metal gate 18b, which are filled with dielectric material.

[0111] The semiconductor device 10 in the embodiment shown in Figure 4 can be a HEMT device incorporating a Zener-type antifuse, and therefore, conventional fabrication techniques of HEMT technology can be used to manufacture the semiconductor device 10.

[0112] Since no changes from standard HEMT techniques and process flows are required, the embodiment shown in Figure 4 may enable a relatively simple implementation of a Zener-type antifuse. Furthermore, since the first region 14a of the first conductivity type and the second region 14b of the second conductivity type can be formed by a regular mask / injection process of undoped GaN material, the embodiment of the disclosure provides a cost-effective implementation of the semiconductor device 10. Alternatively, since the first region 14a of the first conductivity type and the second region 14b of the second conductivity type can be created by continuous epitaxial growth combined with selective etching and regrowth, the embodiment of the disclosure may achieve optimal performance of a Zener PN diode configured as an antifuse, although this example may increase manufacturing costs and complexity.

[0113] In exemplary embodiments, the first region 14a of the first conductivity type and the second region 14b of the second conductivity type are arranged in a vertical configuration with respect to their arrangement above the substrate 12. The vertical configuration may include a fully vertical configuration or a semi-vertical configuration.

[0114] Figure 7 shows a schematic diagram of a semiconductor device 10 in which a first region 14a of a first conductivity type and a second region 14b of a second conductivity type are arranged in a perfectly vertical configuration. In this embodiment, the second region 14b is located above the first region 14a, and the first region 14a is located above the substrate 12. The semiconductor device 10 may further include an intermediate region 16 of a third conductivity type located between the first region 14a and the second region 14b, and a semiconductor layer 20 located between the substrate 12 and the first region 14a and the second region 14b.

[0115] As in the above exemplary embodiments and examples, the substrate 12 comprises a first WBG semiconductor material, the first region 14a of the first conductivity type, the second region 14b of the second conductivity type, and the intermediate region 16 comprises a second WBG semiconductor material, and the semiconductor layer 20 comprises a third WBG semiconductor material.

[0116] In the exemplary embodiment shown in Figure 7, the semiconductor device 10 further includes a first metal gate 18a that is in electrical contact with a first region 14a, and a second metal gate 18b that is in electrical contact with a second region 14b.

[0117] The first metal gate 18a may be in partial or total contact with the first region 14a, or may extend partially or total within the first region 14a. As in the examples shown in Figures 5a to 5c, or Figures 6a to 6b, the second metal gate 18b may be in partial or total contact with the second region 14b, or may extend partially or total within the second region 14b. The first metal gate 18a or the second metal gate 18b may partially extend into the intermediate region 16. The first metal gate 18a and the second metal gate 18b contain the same materials as disclosed in the earlier embodiments and examples.

[0118] In this embodiment, the fabrication of the first region 14a and the second region 14b, as well as the first shape of the first region 14a and the second shape of the second region 14b, is achieved by etching of the first region 14a, the second region 14b, and / or the intermediate region 16, including, for example, mask bevel etching, thereby generating sharp corners in the first region 14a, the second region 14b, and / or the intermediate region 16, respectively, and enabling the realization of desired first and second shapes that can improve the zapping process.

[0119] Alternatively, after growing the first region 14a, the wafer can be removed from the MOCVD reactor and mask etching can be performed. The wafer can then be returned to the MOCVD reactor to grow the intermediate region 16, and optionally the wafer can then be removed from the MOCVD reactor and another mask etching can be performed. The wafer can then be returned to the MOCVD reactor to grow the second region 14b, and the wafer can then be removed from the MOCVD reactor and mask etching can be performed. Sharp corners are formed in the etched regions of the first region 14a and the second region 14b, thereby realizing desired first and second shapes that can improve the zapping process.

[0120] The semiconductor device 10 in the embodiment shown in Figure 7 can be a HEMT device incorporating a Zener-type antifuse, and therefore, conventional fabrication techniques of HEMT technology can be used to manufacture the semiconductor device 10.

[0121] The embodiment in Figure 7 enables a combination of layer growth in the MOCVD reactor, which may reduce manufacturing costs. Furthermore, the vertical configuration allows the embodiment in Figure 7 to incorporate a Zener PN diode configured as an antifuse into HEMT devices having both horizontal topology, e.g., GaN HEMTs, and vertical topology, e.g., GaN-on-GaN, SiC, or Ga2O3-based HEMTs.

[0122] In the exemplary embodiments shown in Figures 8a to 8c, the first region 14a of the first conductivity type and the second region 14b of the second conductivity type are arranged in a semi-vertical configuration. In the semi-vertical configuration, the second region 14b of the second conductivity type may be formed above the first region 14a, and the first region 14a may include one or more recesses. Additionally or alternatively, the second region 14b may include one or more recesses. Additionally or alternatively, the semiconductor device 10 may include an intermediate region 16 of a third conductivity type located between the first region 14a and the second region 14b, and the intermediate region 16 may or may not include one or more recesses.

[0123] In these embodiments, when the first region 14a is formed, one or more portions thereof may be etched. Thus, at least a sloped portion 28a may be formed between at least one etched (recessed) portion of the first region 14a and the unetched portion of the first region 14a. Thus, by etching one or more portions of the second region 14b, at least a sloped portion 28b may be formed between the recesses of the second region 14b and the unetched portions of the second region 14b. Additionally or alternatively, by etching a portion of the intermediate region 16, at least a third sloped portion 28c may be formed between the recesses and non-recesses of the intermediate region 16.

[0124] This allows for the formation of a first shape in the first region 14a and a second shape in the second region 14, including a tip shape, a truncated tip shape, or another polygonal shape, in order to achieve an efficient zapping process.

[0125] In the exemplary embodiment shown in Figure 8a, the first region 14a, the second region 14b, and the intermediate region 16 each include a recess, forming inclined portions 28a, 28b, and 28c, respectively. The inclined portions 28a, 28b, and 28c may be identical or different from each other.

[0126] In the exemplary embodiment shown in Figure 8b, the first region 14a includes two recesses, thereby forming two inclined portions 28a-1 and 28a-2, while the second region 14b and the intermediate region 16 include one recess, thereby forming inclined portions 28b and 28c, respectively. Therefore, the first shape of the first region 14a and the second shape of the second region 14b are different from each other. The inclined portions 28a-1, 28a-2, 28b, and 28c may be identical or different from each other.

[0127] In the exemplary embodiment of Figure 8c, the first region 14a includes two recesses, thereby forming two inclined portions 28a-1 and 28a-2; the second region 14b includes one recess, thereby forming an inclined portion 28b; and the intermediate region 16 is not recessed. Thus, the first shape of the first region 14a and the second shape of the second region 14b are different from each other, and the intermediate region 16 may have a shape that can further improve the zapping process. The inclined portions 28a-1, 28a-2, and 28b may be identical or different from each other.

[0128] In the embodiment shown in Figure 9a, the first region 14a and the second region 14b are arranged in a horizontal configuration with respect to their arrangement above the substrate 12, and the semiconductor layer 20 is positioned above the first region 14a and the second region 14b. In this mounting configuration, the first metal gate 18a and the second metal gate 18b contact the first region 14a and the second region 14b, respectively, via the semiconductor layer 20. The semiconductor device 10 may also include an intermediate region 16 of a third conductivity type positioned between the first region 14a and the second region 14b.

[0129] As described in previous embodiments and examples, the substrate 12 includes a first WBG semiconductor material, the first region 14a of the first conductivity type, the second region 14b of the second conductivity type, and the intermediate region 16 of the third conductivity type include a second WBG semiconductor material, and the semiconductor layer 20 includes a third WBG semiconductor material.

[0130] The first metal gate 18a may be in partial or total contact with the first region 14a, or may extend partially or total within the first region 14a. As in the examples shown in Figures 5a to 5c, or Figures 6a to 6b, the second metal gate 18b may be in partial or total contact with the second region 14b, or may extend partially or total within the second region 14b. The first metal gate 18a or the second metal gate 18b may partially extend into the intermediate region 16. The first metal gate 18a and the second metal gate 18b contain the same materials as disclosed in the earlier embodiments and examples.

[0131] In this embodiment, the semiconductor device 10 may further include isolation injection to remove the 2DEG formed beneath the semiconductor layer 20, thereby avoiding an electrical short circuit between the first region 14a and the second region 14b.

[0132] In the exemplary embodiment shown in Figure 9b, the first region 14a of the first conductivity type and the second region 14b of the second conductivity type are arranged in a fully vertical configuration above the substrate 12, with the second region 14b positioned above the first region 14a and the semiconductor layer 20 positioned above the second region 14b. Optionally, the first region 14a and the second region 14b of the second conductivity type may be arranged in a semi-vertical configuration.

[0133] In this embodiment, the first metal gate 18a is in electrical contact with the first region 14a, and the second metal gate is in contact with the second region via the semiconductor layer 20. The semiconductor device 10 may include an intermediate region 16 having a third conductivity type, located between the first region 14a and the second region 14b.

[0134] As described in previous embodiments and examples, the substrate 12 includes a first WBG semiconductor material, the first region 14a of the first conductivity type, the second region 14b of the second conductivity type, and the intermediate region 16 of the third conductivity type include a second WBG semiconductor material, and the semiconductor layer 20 includes a third WBG semiconductor material.

[0135] The first metal gate 18a may be in partial or total contact with the first region 14a, or may extend partially or total into the first region 14a. As in the examples shown in Figures 5a to 5c, or Figures 6a to 6b, the second metal gate 18b may be in partial or total contact with the second region 14b, or may extend partially or total into the second region 14b. The first metal gate 18a or the second metal gate 18b may partially extend into the intermediate region 16. The first metal gate 18a and the second metal gate 18b contain the same materials as disclosed in the earlier embodiments and examples.

[0136] In the exemplary embodiment shown in Figure 10, the first region 14a of the first conductivity type and the second region 14b of the second conductivity type are arranged in a horizontal configuration with respect to their arrangement above the substrate 12. The semiconductor device 10 may include an intermediate region 16 of the third conductivity type, located between the first region 14a and the second region 14b. The semiconductor device 10 further includes a semiconductor layer 20 located above the first region 14a and the second region 14b, with a first metal gate 18a and a second metal gate 18b contacting the first region 14a and the second region 14b, respectively, via the semiconductor layer 20.

[0137] As described in previous embodiments and examples, the substrate 12 includes a first WBG semiconductor material, the first region 14a of the first conductivity type, the second region 14b of the second conductivity type, and the intermediate region 16 of the third conductivity type include a second WBG semiconductor material, and the semiconductor layer 20 includes a third WBG semiconductor material.

[0138] The first metal gate 18a may be in partial or total contact with the first region 14a, or may extend partially or total within the first region 14a. As in the examples shown in Figures 5a to 5c, or Figures 6a to 6b, the second metal gate 18b may be in partial or total contact with the second region 14b, or may extend partially or total within the second region 14b. The first metal gate 18a or the second metal gate 18b may partially extend into the intermediate region 16. The first metal gate 18a and the second metal gate 18b contain the same materials as disclosed in the earlier embodiments and examples.

[0139] In this embodiment, the semiconductor device 10 further includes at least one additional first region 14a-1, 14a-2 of a first conductivity type and at least one additional second region 14b-1, 14b-2 of a second conductivity type, disposed above the semiconductor layer 20. The semiconductor device 10 further includes at least one additional first metal gate 18b-1, 18b-2 that are electrically in contact with the at least one additional first region 14a-1, 14a-2, respectively, and at least one additional second metal gate 18b-1, 18b-2 that are electrically in contact with the at least one additional second region 14b-1, 14b-2, respectively. Furthermore, the semiconductor device 10 includes at least one additional semiconductor layer 20-1, 20-2 disposed above the at least one additional first region 14a-1, 14a-2 and the at least one additional second region 14b-1, 14b-2, respectively.

[0140] At least one additional first metal gate 18a-1, 18a-2 and at least one additional second metal gate 18b-1, 18b-2 contact at least one additional first region 14a-1, 14a-2 and at least one additional second region 14b-1, 14b-2, respectively, via at least one additional semiconductor layer 20-1, 20-2.

[0141] As described in previous embodiments and examples, at least one additional first region 14a-1, 14b-2 of the first conductivity type and at least one additional second region 14b-1, 14b-2 of the first conductivity type comprise a second WBG semiconductor material, and at least one additional semiconductor layer 20-1, 20-2 comprises a third WBG semiconductor material.

[0142] In this embodiment, at least one additional first region 14a-1 and at least one additional second region 14b-1 form at least one additional Zener PN diode configured as an antifuse. Another additional first region 14b-1 and another additional second region 14b-2 form yet another additional Zener PN diode configured as an antifuse.

[0143] The semiconductor device 10 may further include at least one additional intermediate region 16-1, 16-2 of a third conductivity type, positioned between at least one additional first region 14a-1, 14a-2 of a first conductivity type and at least one additional second region 14b-1, 14b-2 of a first conductivity type. The at least one additional intermediate region 16-1, 16b-2 of the third conductivity type comprises a second WBG semiconductor material.

[0144] At least one additional first metal gate 18a-1, 18a-2 may be in partial or total contact with at least one additional first region 14a-1, 14a-2, or the first metal gates 18a-1, 18a-2 may extend partially or total into at least one additional first region 14a-1, 14a-2. As in the examples shown in Figures 5a to 5c or Figures 6a to 6b, the second metal gates 18b-1, 18b-2 may be in partial or total contact with at least one additional second region 14b-1, 14b-2, or the second metal gates 18b-1, 18b-2 may extend partially or total into at least one additional first region 14b-1, 14b-2. At least one additional first metal gate 18a-1, 18a-2, or at least one additional second metal gate 18b-1, 18b-2, may each partially extend into at least one additional intermediate region 16-1, 16-2. The at least one additional first metal gate 18a-1, 18a-2 and the at least one additional second metal gate 18b-1, 18b-2 may comprise the same materials as those disclosed in the prior embodiments and examples.

[0145] This embodiment makes it possible to create a multi-stack of antifuse in which multiple levels can be created between semiconductor layer 20 and at least one additional semiconductor layer 20-1, and between the additional semiconductor layer 20-1 and another additional semiconductor layer 20-2.

[0146] In this embodiment, the semiconductor device 10 may further include a network of metal interconnects, such as vias or plugs, that contact the first region 14a and at least one additional first region 14a-1, and the first region 14b and at least one additional second region 14b-1. Similarly, if further additional first regions are formed, the network of metal interconnects may further contact an additional first region 14a-1 and another additional second region 14a-2, and further contact an additional second region 14b-1 and another additional second region 14b-2.

[0147] In one embodiment shown in Figure 11, the semiconductor device 10 further includes at least one structure 22a, 22b of thermal insulating material that partially or completely contacts a first region 14a and / or a second region 14b and / or a substrate 12. The at least one structure 22a, 22b of thermal insulating material includes SiO2 or a nitride compound comprising one of Si3N4 or AlGaN or AlN.

[0148] Alternatively, at least one structure 22a, 22b of the thermal insulating material may be in partial or complete contact with the semiconductor layer 20. Alternatively, at least one structure 22a, 22b of the thermal insulating material may be in partial or complete contact with the substrate 12 and / or the semiconductor layer 20. Alternatively, at least one structure 22a, 22b of the thermal insulating material may not be in contact with the first region 14a and / or the second region 14b.

[0149] In particular, this embodiment may cause a thermal increase, such as overheating, during the zapping process, which can facilitate the programming of the antifuse.

[0150] Figure 12 shows a schematic diagram of a semiconductor device 10 according to another exemplary embodiment. In this embodiment, the first region 14a of the first conductivity type and the second region 14b of the second conductivity type are located within an N-well structure 24 or P-well structure 24 formed in the substrate 12. Alternatively, the first region 14a is located within a first well structure 26a and the second region 14b is located within a second well structure 26b, where the first well structure 26a and the second well structure 26b include an N-well structure or P-well structure formed in the substrate 12.

[0151] As an addition or alternative, the first region 14a is located within a first well structure 26a, and the second region 14b is located within a second well structure 26b, wherein the first well structure 26a and the second well structure 26b include an N-well structure or P-well structure located within an N-well or P-well structure 24 formed within the substrate 12.

[0152] The N-well or P-well structure 24, the first well structure 26a, and the second well structure 26b can be formed by injection. Alternatively, the N-well or P-well structure 24, the first well structure 26a, and the second well structure 26b can be formed by etching and epitaxial regrowth.

[0153] In this embodiment, the substrate 12 may include a first WBG semiconductor material or a UWBG semiconductor material. The first WBG semiconductor material and UWBG semiconductor material may include, for example, GaN, SiC, and Ga2O3. The first WBG semiconductor material or UWBG semiconductor material may include a heteroepitaxial bulk material that includes GaN on Si, or GaN on SiC, or GaN on diamond, or a WBG semiconductor material semiconductor on an insulating material, or a UWBG semiconductor material on an insulating material.

[0154] In this disclosure, UWBG semiconductor materials include semiconductor materials having a bandgap greater than 4 eV.

[0155] In this embodiment, the first region 14a of the first conductivity type, the second region 14b of the second conductivity type, and the intermediate region 16 of the third conductivity type may include a second WBG semiconductor material or an UWBG semiconductor material. The first WBG semiconductor material and the UWBG semiconductor material may include GaN, SiC, or Ga2O3. For example, the band gap value of Ga2O3 is 4.8 eV.

[0156] The chemical species used to dope the first region 14a and the second region 14b may, but are not limited to, magnesium, iron, or silicon when the second WBG semiconductor material contains GaN. Alternatively, when the second WBG semiconductor material contains SiC, the dopant may, for example, phosphorus, boron, aluminum, or nitrogen. Alternatively, when the second WBG semiconductor material contains Ga2O3, the dopant may, for example, Si, tin, germanium, nitrogen, magnesium, or iron.

[0157] The semiconductor device 10 may further include a semiconductor layer 20 comprising a third WBG semiconductor material, as described in the previous embodiments and examples.

[0158] In this embodiment, the semiconductor device 10 may further include a first metal gate 18a that is in electrical contact with the first region 14a, and a second metal gate 18b that is in electrical contact with the second region 14b.

[0159] The first metal gate 18a may be in partial or total contact with the first region 14a, or may extend partially or total within the first region 14a. As in the examples shown in Figures 5a to 5c, or Figures 6a to 6b, the second metal gate 18b may be in partial or total contact with the second region 14b, or may extend partially or total within the second region 14b. The first metal gate 18a or the second metal gate 18b may partially extend into the intermediate region 16. The first metal gate 18a and the second metal gate 18b contain the same materials as disclosed in the earlier embodiments and examples.

[0160] The semiconductor device 10 may further include at least one structure 22a, 22b of a thermal insulating material that is in partial or complete contact with the first region 14a and / or the second region 14b and / or the substrate 12. The at least one structure 22a, 22b of the thermal insulating material may include silicon dioxide SiO2, or a nitride compound containing any one of Si3N4, AlGaN, or AlN.

[0161] Alternatively, at least one structure 22a, 22b of the thermal insulating material may be in partial or complete contact with the semiconductor layer 20. Alternatively, at least one structure 22a, 22b of the thermal insulating material may be in partial or complete contact with the substrate 12 and / or the semiconductor layer 20. Alternatively, at least one structure 22a, 22b of the thermal insulating material may not be in contact with the first region 14a and / or the second region 14b.

[0162] In particular, the semiconductor device 10 of the embodiment shown in Figure 12 may be used in general WBG and UWBG techniques, and therefore, standard fabrication techniques of WBG and UWBG techniques may be used to fabricate the semiconductor device 10. The semiconductor device 10 according to the exemplary embodiments of this disclosure offers several advantages.

[0163] The semiconductor device 10 provides a cost-effective solution for implementing Zener PN diodes configured as antifuses in WBG power semiconductor technology.

[0164] The semiconductor device 10 makes it possible to perform trimming in WBG technology (currently only practical with silicon technology).

[0165] The semiconductor device 10 enables adjustment of the voltage reference circuit in the WBG (which is mainly used in integrated circuit design).

[0166] The semiconductor device 10 enables the implementation of serial code identification of the die / chip in the WBG device.

[0167] The semiconductor device 10 provides a Zener PN diode configured as a "one-time programmable" antifuse, as it does not need to be reconfigured each time the power supply is interrupted, applied, or disconnected.

[0168] The semiconductor device 10 is less susceptible to the influence of alpha particles.

[0169] Figure 13 shows steps of a method 30 for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0170] In the first step S32, the substrate 12 is prepared. The substrate 12 comprises a first WBG semiconductor material comprising SiC or Ga2O3. Alternatively, the first WBG semiconductor material comprises a heteroepitaxial bulk material comprising GaN on Si, or GaN on SiC, or GaN on diamond, or a WBG semiconductor on an insulating material. The substrate 12 may include a base structure having one or more layers formed by an epitaxial growth process on top.

[0171] In the second step S34, a first region 14a of a first conductivity type and a second region 14b of a second conductivity type are formed, which are located above the substrate 12. The first region 14a and the second region 14b contain a second WBG semiconductor material. For example, the second WBG semiconductor material contains GaN.

[0172] The first region 14a of the first conductivity type may be a P-type region or an N-type region. Conversely, the second region 14b of the second conductivity type may be an N-type region or a P-type region. In this way, the first region 14a and the second region 14b form a Zener PN diode configured as an antifuse.

[0173] Generally, semiconductor devices 10 can be manufactured by standard mask / injection processes, controlled continuous epitaxial growth and continuous epitaxy, and etching techniques.

[0174] Method 30 may further include forming an intermediate region 16 of a third conductivity type which may be located between the first region 14a and the second region 14b. The intermediate region 16 may contain a second WBG semiconductor material and may be a P-type region, an N-type region, or an undoped region.

[0175] The first region 14a and the second region 14b may be arranged in a horizontal configuration with respect to their arrangement above the substrate 12, with the first region 14a being positioned above the substrate 12 and the second region 14b being positioned above the substrate 12, next to the first region 14a.

[0176] Alternatively, the first region 14a and the second region 14b may be arranged in a vertical configuration with respect to their arrangement above the substrate 12.

[0177] Vertical configurations can include fully vertical or semi-vertical configurations.

[0178] In a fully vertical configuration, the second region 14b may be positioned above the first region 14a, and the first region 14a may be positioned above the substrate 12.

[0179] In a semi-vertical configuration, the second region 14b of the second conductivity type may be formed above the first region 14a, and the first region 14a may include one or more recesses. Additionally or alternatively, the second region 14b may include one or more recesses. Additionally or alternatively, the semiconductor device 10 may include an intermediate region 16 of a third conductivity type located between the first region 14a and the second region 14b, and the intermediate region 16 may or may not include one or more recesses.

[0180] The first region 14a and the second region 14b may be separated by a certain distance, or they may be adjacent, or they may partially overlap.

[0181] The first region 14a may have a first shape, the first shape may include a first lateral projection, the first lateral projection may have a tip shape, a truncated tip shape, or another polygonal shape, or the first shape may include a cylindrical shape, or a cylindrical shape having a first lateral projection, and the first lateral projection may have a tip shape, a truncated tip shape, or another polygonal shape. The second region 14b may have a second shape, the second shape may include a second lateral projection, the second lateral projection may have a tip shape, a truncated tip shape, or another polygonal shape, or the second shape may include a cylindrical shape, or a cylindrical shape having a second lateral projection, and the lateral projection may have a tip shape, a truncated tip shape, or another polygonal shape.

[0182] Method 30 may further include the step of forming a semiconductor layer 20, which may include a third WBG semiconductor material and may be placed between the substrate 12 and a first region 14a and a second region 14b, respectively. For example, the third WBG semiconductor material may include AlGaN.

[0183] Method 30 may further include the step of forming a semiconductor layer 20 comprising a third WBG semiconductor material, the semiconductor layer 20 being located above the first region 14a and the second region 14b. Alternatively, the second region 14b may be located above the first region 14a, and the semiconductor layer 20 may be located above the second region 14b.

[0184] Method 30 may further include the step of forming a first metal gate 18a that is in electrical contact with a first region 14a and a second metal gate 18b that is in electrical contact with a second region 14b.

[0185] The first metal gate 18a and the second metal gate 18b may contact the first region 14a and the second region 14b via the semiconductor layer 20. Alternatively, the second metal gate 18b may contact the second region 14b via the semiconductor layer 20.

[0186] The first metal gate 18a may be in partial or total contact with the first region 14a, or may extend partially or total into the first region 14a. The second metal gate 18b may be in partial or total contact with the second region 14b, or may extend partially or total into the second region 14b.

[0187] The first metal gate 18a and the second metal gate 18b may contain a metal stack containing aluminum, titanium, copper, gold, or another metallic element, or one of the following: Ni / Au, Ni / Ag, Pd / Au, Cr / Au, Pt / Au, Ti / Pt / Au, Ni / Si, W / Si, Ti / Al, Ti / Al / Ti, or TiN / Al / TiN. However, other suitable combinations of materials may also be possible.

[0188] Method 30 may further include the steps of forming at least one additional first region 14a-1, 14a-2 of a first conductivity type and at least one additional second region 14b-1, 14b-2 of a second conductivity type, which may be positioned above the semiconductor layer 20; forming at least one additional first metal gate 18a-1, 18a-2 that is in electrical contact with the at least one additional first region 14a-1, 14a-2 and at least one additional second metal gate 18b-1, 18b-2 that is in electrical contact with the at least one additional second region 14b-1, 14b-2; and forming at least one additional semiconductor layer 20-1, 20-2, which may be positioned above the at least one additional first region 14a-1, 14a-2 and at least one additional second region 14b-1, 14b-2.

[0189] At least one additional first metal gate 18a-1, 18a-2 and at least one additional second metal gate 18b-1, 18b-2 may contact at least one additional first region 14a-1, 14a-2 and at least one additional second region 14b-1, 14b-2 via at least one additional semiconductor layer 20-1, 20-2.

[0190] At least one additional first region 14a-1, 14a-2 and at least one additional second region 14b-1, 14b-2 may contain a second wide-bandgap semiconductor material, while at least one additional semiconductor layer 20-1, 20-2 may contain a third wide-bandgap semiconductor material.

[0191] Furthermore, at least one additional first region 14a-1, 14a-2 and at least one additional second region 14b-1, 14b-2 form at least one additional Zener PN diode configured as an antifuse.

[0192] The method may further include the step of forming a first region 14a and a second region 14b which may be located within an N-well structure 24 or a P-well structure 24 formed within the substrate 12. Alternatively, the first region 14a may be located within a first well structure 26a, and the second region 14b may be located within a second well structure 26b, where the first well structure 26a and the second well structure 26a may include an N-well structure or a P-well structure formed within the substrate 12.

[0193] Method 30 may further include the step of forming at least one structure 22a, 22b of a thermal insulating material that can be in partial or complete contact with the first region 14a and / or the second region 14b and / or the substrate 12. The at least one structure 22a, 22b of the thermal insulating material may include SiO2 or a nitride compound comprising any one of Si3N4 or AlGaN or AlN.

[0194] Examples of fabrication techniques that can be used to form the first region 14a and first shape of the first conductivity type, the second region 14b and second shape of the second conductivity type, the intermediate region 16 of the third conductivity type, the first metal gate 18a, and the second metal gate 18b are the same as those disclosed above in various embodiments and examples of the semiconductor device 10.

[0195] This disclosure is described in relation to various exemplary embodiments and implementations. However, from the examination of the drawings, this disclosure, and the independent claims, other modifications can be understood and derived by those skilled in the art and those practicing the claimed matters. In the wording of the claims and specification, the words “comprising” do not exclude other elements or steps, and the indefinite articles “a” or “an” do not exclude plurals. A single element or other unit may perform the function of several entities or items described in the claims. The mere fact that certain means are described in different dependent claims does not imply that combinations of these means cannot be used in advantageous embodiments. [Explanation of symbols]

[0196] 10 Semiconductor devices 12 circuit boards 14a First area 14b Second area 14a-1 Additional first area 14a-2 Additional first area 14b-1 Additional second area 14b-2 Additional second area 16 Intermediate area 16-1 Additional Intermediate Areas 16-2 Additional Intermediate Areas 18a First metal gate 18b Second metal gate 18a-1 Additional first metal gate 18a-2 Additional first metal gate 18b-1 Additional second metal gate 18b-2 Additional second metal gate 20 Semiconductor Layers 20-1 Additional semiconductor layer 20-2 Additional semiconductor layer 22a At least one structure 22b At least one structure 24 N-well structure, P-well structure 26a First well structure 26b Second well structure 28a Slope 28b Slope 28c Slope 28a-1 Slope section 28a-2 Slope section 30 ways S32 First Step S34 Second Step

Claims

1. A substrate (12) containing a first wide-bandgap semiconductor material, A first region (14a) of a first conductivity type and a second region (14b) of a second conductivity type are disposed above the substrate (12), wherein the first region (14a) and the second region (14b) each contain a second wide-bandgap semiconductor material, Includes, The first region (14a) and the second region (14b) form a Zener PN diode configured as an antifuse. The semiconductor layer (20) further includes a third wide-bandgap semiconductor material, The semiconductor layer (20) is positioned above the first region (14a) and the second region (14b), or The second region (14b) is positioned above the first region (14a), and the semiconductor layer (20) is positioned above the second region (14b). Semiconductor device (10).

2. The first region (14a) and the second region (14b) are arranged in a horizontal configuration with respect to their arrangement above the substrate (12), with the first region (14a) positioned above the substrate (12) and the second region (14b) positioned above the substrate (12) next to the first region (14a), or The first region (14a) and the second region (14b) are arranged in a vertical configuration with respect to their arrangement above the substrate (12), the second region (14b) is positioned above the first region (14a), and the first region (14a) is positioned above the substrate (12), The semiconductor device (10) according to claim 1.

3. The first region (14a) and the second region (14b) are separated by a certain distance, or the first region (14a) and the second region (14b) are adjacent, or the first region (14a) and the second region (14b) partially overlap. The semiconductor device (10) according to claim 1 or 2.

4. The first region (14a) has a first shape, the first shape includes a first lateral projection, the first lateral projection has a tip shape, a truncated tip shape, or another polygonal shape, or the first shape is cylindrical, or includes a cylindrical shape having a first lateral projection, the first lateral projection has a tip shape, a truncated tip shape, or another polygonal shape, The second region (14b) has a second shape, the second shape includes a second lateral projection, the second lateral projection has a tip shape, a truncated tip shape, or another polygonal shape, or the second shape is cylindrical, or includes a cylindrical shape having a second lateral projection, the lateral projection has a tip shape, a truncated tip shape, or another polygonal shape. The semiconductor device (10) according to claim 1.

5. Further comprising a first metal gate (18a) that is in electrical contact with the first region (14a), and a second metal gate (18b) that is in electrical contact with the second region (14b), The semiconductor device (10) according to claim 1.

6. A substrate (12) comprising a first wide-bandgap semiconductor material, A first region (14a) of a first conductivity type and a second region (14b) of a second conductivity type are disposed above the substrate (12), wherein the first region (14a) and the second region (14b) each contain a second wide-bandgap semiconductor material, Includes, The first region (14a) and the second region (14b) form a Zener PN diode configured as an antifuse. The semiconductor layer (20) further comprises a third wide-bandgap semiconductor material, disposed between the substrate (12) and the first region (14a) and the second region (14b), respectively. Semiconductor device (10).

7. The first metal gate (18a) and the second metal gate (18b) contact the first region (14a) and the second region (14b) via the semiconductor layer (20), or The second metal gate (18b) contacts the second region (14b) via the semiconductor layer (20). The semiconductor device (10) according to claim 5.

8. Displaced above the semiconductor layer (20) are at least one additional first region (14a-1, 14a-2) of the first conductivity type and at least one additional second region (14b-1, 14b-2) of the second conductivity type, wherein the at least one additional first region (14a-1, 14a-2) and the at least one additional second region (14b-1, 14b-2) include the second wide-bandgap semiconductor material, At least one additional first metal gate (18a-1, 18a-2) electrically contacting the at least one additional first region (14a-1, 14a-2), and at least one additional second metal gate (18b-1, 18b-2) electrically contacting the at least one additional second region (14b-1, 14b-2), The third wide-bandgap semiconductor material comprises at least one additional semiconductor layer (20-1, 20-2) disposed above the at least one additional first region (14a-1, 14a-2) and the at least one additional second region (14b-1, 14b-2), It further includes, The at least one additional first metal gate (18a-1, 18a-2) and the at least one additional second metal gate (18b-1, 18b-2) contact the at least one additional first region (14a-1, 14a-2) and the at least one additional second region (14b-1, 14b-2) via the at least one additional semiconductor layer (20-1, 20-2), The at least one additional first region (14a-1, 14a-2) and the at least one additional second region (14b-1, 14b-2) form at least one additional Zener PN diode configured as an antifuse. The semiconductor device (10) according to claim 7.

9. The first region (14a) and the second region (14b) are located within an N-well structure (24) or P-well structure (24) formed within the substrate (12), or The first region (14a) is located within a first well structure (26a), and the second region (14b) is located within a second well structure (26b), and the first well structure (26a) and the second well structure (26a) include an N-well structure or a P-well structure formed within the substrate (12). The semiconductor device (10) according to claim 1.

10. The present invention further includes at least one structure (22a, 22b) of a thermal insulating material that is in partial or complete contact with the first region (14a) and / or the second region (14b) and / or the substrate (12), At least one structure (22a, 22b) of the thermal insulating material is silicon dioxide SiO ２ , or silicon nitride Si ３ N ４ or a nitride compound containing one of the following: aluminum gallium nitride (AlGaN) or aluminum nitride (AlN), The semiconductor device (10) according to claim 9.

11. Further comprising a third conductivity type intermediate region (16) disposed between the first region (14a) and the second region (14b), The intermediate region (16) includes the second wide-bandgap semiconductor material, and the intermediate region (16) is a P-type region, an N-type region, or an undoped region. The semiconductor device (10) according to claim 1.

12. The second wide-bandgap semiconductor material includes gallium nitride (GaN), The semiconductor device (10) according to claim 1.

13. The third wide-bandgap semiconductor material includes aluminum gallium nitride (AlGaN), The semiconductor device (10) according to claim 1 or 6.

14. The first metal gate (18a) is in partial or total contact with the first region (14a), or the first metal gate (18a) extends partially or total into the first region (14a), The second metal gate (18b) is in partial or total contact with the second region (14b), or the second metal gate (18b) extends partially or total into the second region (14b), The semiconductor device (10) according to claim 5.

15. The first metal gate (18a) and the second metal gate (18b) include a metal stack containing aluminum, titanium, copper, gold, or another metallic element, or one of Ni / Au, Ni / Ag, Pd / Au, Cr / Au, Pt / Au, Ti / Pt / Au, Ni / Si, W / Si, Ti / Al, Ti / Al / Ti, TiN / Al / TiN, The semiconductor device (10) according to claim 5.

16. The first wide-bandgap semiconductor material is silicon carbide (SiC) or gallium oxide (Ga) ２ O ３ Includes or, The first wide-bandgap semiconductor material includes a heteroepitaxial bulk material, and the heteroepitaxial bulk material includes gallium nitride GaN on silicon Si, or GaN on SiC, or GaN on diamond, or a wide-bandgap semiconductor on an insulating material. The device according to claim 1.

17. A method (30) for manufacturing a semiconductor device (10), wherein the method is The steps include preparing a substrate (12) containing a first wide-bandgap semiconductor material, A step of forming a first region (14a) of a first conductivity type and a second region (14b) of a second conductivity type, which are disposed above the substrate (12), wherein the first region (14a) and the second region (14b) include a second wide-bandgap semiconductor material. Includes, The first region (14a) and the second region (14b) form a Zener PN diode configured as an antifuse. Forming a semiconductor layer (20) containing a third wide-bandgap semiconductor material above the first region (14a) and the second region (14b), or A method further comprising forming the second region (14b) above the first region (14a) and forming the semiconductor layer (20) above the second region (14b).

18. A method (30) for manufacturing a semiconductor device (10), wherein the method is: The steps include preparing a substrate (12) containing a first wide-bandgap semiconductor material, A step of forming a first region (14a) of a first conductivity type and a second region (14b) of a second conductivity type, which are disposed above the substrate (12), wherein the first region (14a) and the second region (14b) include a second wide-bandgap semiconductor material. Includes, The first region (14a) and the second region (14b) form a Zener PN diode configured as an antifuse. A method further comprising arranging a semiconductor layer (20) containing a third wide-bandgap semiconductor material between the substrate (12) and the first region (14a) and the second region (14b), respectively.

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