Semiconductor equipment

Abstract

To provide a semiconductor device having improved avalanche resistance.SOLUTION: A semiconductor device comprises; a silicon carbide layer having a first surface and a second surface; and a first-conductivity-type first silicon carbide region which includes a first region, and second and third regions positioned between the first region and the first surface, wherein the first-conductivity-type impurity concentration in the second region is equal to or higher than that of the first region, and the first-conductivity-type impurity concentration in the third region is higher than that of the second region. The semiconductor device further comprises: a second-conductivity-type second silicon carbide region which is positioned between the first silicon carbide region and the first surface, and includes a fourth region in contact with the second region and a fifth region in contact with the third region and having a second-conductivity-type impurity concentration higher than that of the fourth region; a first-conductivity-type third silicon carbide region between the second silicon carbide region and the first surface; a first gate electrode which is opposite to the second silicon carbide region; a first gate insulation layer; a first electrode including a first portion in contact with the second silicon carbide region and the third silicon carbide region; and a second electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] Silicon carbide is expected to be a promising material for next-generation semiconductor devices. Compared to silicon, silicon carbide has superior physical properties, including a bandgap approximately three times larger, a breakdown field strength approximately ten times greater, and a thermal conductivity approximately three times higher. By utilizing these properties, it is possible to realize, for example, metal oxide semiconductor field effect transistors (MOSFETs) that are capable of high voltage resistance, low loss, and high-temperature operation.

[0003] For MOSFETs using silicon carbide, improvement in avalanche withstand capability is desired. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2019-165245 [Overview of the project] [Problems that the invention aims to solve]

[0005] The problem that this invention aims to solve is to provide a semiconductor device with improved avalanche withstand capability. [Means for solving the problem]

[0006] The semiconductor device of the embodiment includes: a silicon carbide layer having a first surface and a second surface facing the first surface; a first silicon carbide region of a first conductivity type provided in the silicon carbide layer, comprising a first region, a second region and a third region, the second region located between the first region and the first surface, the third region located between the first region and the first surface, the first conductivity type impurity concentration in the second region being equal to or higher than the first conductivity type impurity concentration in the first region, and the first conductivity type impurity concentration in the third region being higher than that in the second region; and a second silicon carbide region of a second conductivity type provided in the silicon carbide layer and located between the first silicon carbide region and the first surface, comprising a fourth region and a fifth region, the fourth region being in contact with the second region. And, before A second silicon carbide region, wherein the concentration of the second conductivity type impurity in the fifth region is higher than the concentration of the second conductivity type impurity in the fourth region; a third silicon carbide region of the first conductivity type, provided within the silicon carbide layer and located between the second silicon carbide region and the first surface; a first gate electrode, provided on the side of the first surface relative to the silicon carbide layer, extending in a first direction parallel to the first surface, and facing the second silicon carbide region on the first surface; and a second direction, provided on the side of the first surface relative to the silicon carbide layer, extending in the first direction, parallel to the first surface and perpendicular to the first direction relative to the first gate electrode. The device comprises: a second gate electrode facing the second silicon carbide region on the first surface; a first gate insulating layer provided between the second silicon carbide region and the first gate electrode; a second gate insulating layer provided between the second silicon carbide region and the second gate electrode; a first electrode provided on the side facing the first surface with respect to the silicon carbide layer, the first electrode including a first portion provided between the first gate electrode and the second gate electrode and in contact with the second silicon carbide region and the third silicon carbide region; and a second electrode provided on the side facing the second surface with respect to the silicon carbide layer. The first silicon carbide region further includes a sixth region and a seventh region, the sixth region is located between the first region and the first surface, the seventh region is located between the first region and the first surface, the first conductivity type impurity concentration in the sixth region is equal to or higher than the first conductivity type impurity concentration in the first region, the first conductivity type impurity concentration in the seventh region is higher than that of the second region, the sixth region is located between the third region and the seventh region, the second silicon carbide region further includes an eighth region and a ninth region, the eighth region is in contact with the sixth region, the ninth region is in contact with the seventh region, the second conductivity type impurity concentration in the ninth region is higher than that of the second conductivity type impurity concentration in the eighth region, and the eighth region is located between the fifth region and the ninth region. . [Brief explanation of the drawing]

[0007] [Figure 1]Schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 2] Schematic top view of the semiconductor device according to the first embodiment. [Figure 3] Schematic top view of the semiconductor device according to the first embodiment. [Figure 4] Schematic cross-sectional view of the semiconductor device of the comparative example. [Figure 5] Schematic cross-sectional view of the semiconductor device of the modified example of the first embodiment. [Figure 6] Schematic cross-sectional view of the semiconductor device according to the second embodiment. [Figure 7] Schematic cross-sectional view of the semiconductor device according to the second embodiment. [Figure 8] Schematic top view of the semiconductor device according to the second embodiment. [Figure 9] Schematic top view of the semiconductor device according to the second embodiment. [Figure 10] Equivalent circuit diagram of the semiconductor device according to the second embodiment.

Mode for Carrying Out the Invention

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described may be omitted as appropriate.

[0009] Also, in the following description, n + , - ,

[0008] , ++ , + , + , - , , <00001​​​​​​​​​​​​​​​​​​​​​​​​The concentration of p-type impurities is relatively higher than that of p, - This indicates that the concentration of p-type impurities is relatively lower than that of p. + shape, n - The shape is simply the n-shape, p + shape, p - The shape is sometimes simply described as "p-shape."

[0010] Impurity concentration can be measured, for example, by Secondary Ion Mass Spectrometry (SIMS). The relative levels of impurity concentration can also be determined, for example, from the carrier concentration obtained by Scanning Capacitance Microscopy (SCM). Furthermore, distances such as the width and depth of impurity regions can be determined, for example, by SIMS. Also, distances such as the width and depth of impurity regions can be determined, for example, from SCM images or Scanning Electron Microscope (SEM) images. In addition, the thickness of the insulating layer can be measured, for example, on images from SIMS, SEM, or Transmission Electron Microscope (TEM).

[0011] In this specification, "p-type impurity concentration" in the p-type silicon carbide region refers to the net p-type impurity concentration obtained by subtracting the n-type impurity concentration in that region from the p-type impurity concentration in that region. Similarly, "n-type impurity concentration" in the n-type silicon carbide region refers to the net n-type impurity concentration obtained by subtracting the p-type impurity concentration in that region from the n-type impurity concentration in that region.

[0012] Furthermore, unless otherwise stated in the specification, the impurity concentration in a particular region shall be represented by the impurity concentration in the central part of that region.

[0013] (First embodiment) The semiconductor device of the first embodiment includes a silicon carbide layer having a first surface and a second surface facing the first surface, and a first silicon carbide region of a first conductivity type provided within the silicon carbide layer, comprising a first region, a second region and a third region, the second region located between the first region and the first surface, the third region located between the first region and the first surface, the first conductivity type impurity concentration of the second region being equal to or higher than the first conductivity type impurity concentration of the first region, and the first conductivity type impurity of the third region A first silicon carbide region having a higher concentration of conductive impurities than the second region, and a second silicon carbide region of second conductivity type located within the silicon carbide layer and between the first silicon carbide region and the first surface, comprising a fourth region and a fifth region, the fourth region being in contact with the second region, the fifth region being in contact with the third region, and the concentration of second conductive impurities in the fifth region being higher than the concentration of second conductive impurities in the fourth region, and a second silicon carbide region located within the silicon carbide layer and between the second silicon carbide region and the first surface. A third silicon carbide region of a first conductive type located between the first plane and the first plane, a first gate electrode provided on the side of the first plane relative to the silicon carbide layer, extending in a first direction parallel to the first plane, and facing the second silicon carbide region on the first plane, a second gate electrode provided on the side of the first plane relative to the silicon carbide layer, extending in a first direction, provided in a second direction parallel to the first plane and perpendicular to the first direction relative to the first gate electrode, and facing the second silicon carbide region on the first plane, and the second The device comprises a first gate insulating layer provided between a silicon carbide region and a first gate electrode, a second gate insulating layer provided between a second silicon carbide region and a second gate electrode, a first electrode provided on the side facing the first surface with respect to the silicon carbide layer, the first electrode including a portion provided between the first gate electrode and the second gate electrode and in contact with the second silicon carbide region and the third silicon carbide region, and a second electrode provided on the side facing the second surface with respect to the silicon carbide layer.

[0014] The semiconductor device of the first embodiment is a planar gate type vertical MOSFET 100 using silicon carbide. The MOSFET 100 of the first embodiment is a Double Implantation MOSFET (DIMOSFET) in which the body region and source region are formed by ion implantation, for example.

[0015] The following explanation will use the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. MOSFET100 is a vertical n-channel MOSFET that uses electrons as carriers.

[0016] Figure 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment. Figures 2 and 3 are schematic top views of a semiconductor device according to the first embodiment. Figure 2 is a schematic diagram showing the pattern of the gate electrode and impurity region on the upper surface of the silicon carbide layer. Figure 3 is a schematic diagram showing the pattern of the impurity region on the upper surface of the silicon carbide layer, with the gate electrode removed from Figure 2. Figure 1 is a cross-sectional view AA' of Figures 2 and 3.

[0017] The MOSFET 100 comprises a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a first gate insulating layer 16a, a second gate insulating layer 16b, a third gate insulating layer 16c, a first gate electrode 18a, a second gate electrode 18b, a third gate electrode 18c, and an interlayer insulating layer 20. The source electrode 12 includes a contact electrode portion 12x (first portion).

[0018] Within the silicon carbide layer 10, n + Drain region 22 of type n, drift region 24 (first silicon carbide region) of type n, body region 26 (second silicon carbide region) of type p, n ++ A source region 30 (third silicon carbide region) is provided.

[0019] The n-shaped drift region 24 is n - The lower region of the n-type is 24x (first region), the first low-concentration n-region of the n-type is 24y1 (second region), the second low-concentration n-region of the n-type is 24y2 (sixth region), the third low-concentration n-region of the n-type is 24y3, n + The first high-concentration n region of type 24z1 (third region), n + It includes the second high-concentration n region 24z2 (the seventh region) of the type.

[0020] The p-type body region 26 consists of the first low-concentration p-region 26x1 (fourth region) of the p-type, the second low-concentration p-region 26x2 (eighth region) of the p-type, the third low-concentration p-region 26x3, and p + The first high-concentration p region of type 26y1 (the fifth region), p + The second high-concentration p region of type 26y2 (the ninth region), p ++ It includes the type contact region 26z (the 10th region).

[0021] The silicon carbide layer 10 is provided between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 is single-crystal SiC. For example, the silicon carbide layer 10 is 4H-SiC.

[0022] The silicon carbide layer 10 comprises a first surface ("F1" in Figure 1) and a second surface ("F2" in Figure 1). Hereinafter, the first surface F1 may be referred to as the front surface and the second surface F2 as the back surface. The first surface F1 is located on the source electrode 12 side of the silicon carbide layer 10. The second surface F2 is located on the drain electrode 14 side of the silicon carbide layer 10. The first surface F1 and the second surface F2 face each other. Hereinafter, "depth" refers to the depth in the direction toward the second surface with respect to the first surface.

[0023] The first and second directions are parallel to the first face F1. The second direction is perpendicular to the first direction. The direction from the first face F1 to the second face F2 is the third direction. The third direction is perpendicular to the first and second directions.

[0024] The first surface F1 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (0001) surface. The second surface F2 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (000-1) surface. The (0001) surface is referred to as the silicon surface. The (000-1) surface is referred to as the carbon surface.

[0025] n + The drain region 22 is provided on the back side of the silicon carbide layer 10. The drain region 22 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drain region 22 is, for example, 1 × 10⁻⁶ 18 cm-3 The above 1 x 10 21 cm -3 The following applies:

[0026] The n-shaped drift region 24 is provided between the drain region 22 and the first surface F1. The n-shaped drift region 24 is provided between the source electrode 12 and the drain electrode 14.

[0027] The n-type drift region 24 is provided on the drain region 22. The drift region 24 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drift region 24 is lower than the concentration of n-type impurities in the drain region 22. The thickness of the drift region 24 is, for example, 3 μm to 150 μm.

[0028] The drift region 24 is n - The lower region of the n-type is 24x (first region), the first low-concentration n-region of the n-type is 24y1 (second region), the second low-concentration n-region of the n-type is 24y2 (sixth region), the third low-concentration n-region of the n-type is 24y3, n + The first high-concentration n region of type 24z1 (third region), n + It includes the second high-concentration n region 24z2 (the seventh region) of the type.

[0029] n - The lower region 24x of the shape is provided on the side of the second surface F2 of the drift region 24. The lower region 24x is in contact with the drain region 22.

[0030] The lower region 24x contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the lower region 24x is, for example, 4 × 10⁻⁶. 14 cm -3 The above 1 x 10 17 cm -3 The following applies:

[0031] The first low-density n-region 24y1, the second low-density n-region 24y2, and the third low-density n-region 24y3 of the n-type are located between the lower region 24x and the first surface F1. The first low-density n-region 24y1, the second low-density n-region 24y2, and the third low-density n-region 24y3 are located between the lower region 24x and the body region 26. The first low-density n-region 24y1, the second low-density n-region 24y2, and the third low-density n-region 24y3 are tangent to the body region 26. The first low-density n-region 24y1, the second low-density n-region 24y2, and the third low-density n-region 24y3 extend in the first direction.

[0032] The first low-concentration n-region 24y1, the second low-concentration n-region 24y2, and the third low-concentration n-region 24y3 contain, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration in the first low-concentration n-region 24y1, the second low-concentration n-region 24y2, and the third low-concentration n-region 24y3 is equal to or higher than the n-type impurity concentration in the lower region 24x. The n-type impurity concentration in the first low-concentration n-region 24y1, the second low-concentration n-region 24y2, and the third low-concentration n-region 24y3 is, for example, 4 × 10⁻⁶. 14 cm -3 The above 2 x 10 17 cm -3 The following applies:

[0033] n + The first high-concentration n region of type 24z1, n + The second high-density n-region 24z2 of the type is located between the lower region 24x and the first surface F1. The first high-density n-region 24z1 and the second high-density n-region 24z2 are located between the lower region 24x and the body region 26. The first high-density n-region 24z1 and the second high-density n-region 24z2 are tangent to the body region 26. The first high-density n-region 24z1 and the second high-density n-region 24z2 extend, for example, in the first direction.

[0034] The first high-concentration n-region 24z1 is located between the first low-concentration n-region 24y1 and the second low-concentration n-region 24y2. The second high-concentration n-region 24z2 is located between the second low-concentration n-region 24y2 and the third low-concentration n-region 24y3.

[0035] The first high-concentration n-region 24z1 and the second high-concentration n-region 24z2 contain, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration in the first high-concentration n-region 24z1 and the second high-concentration n-region 24z2 is higher than the n-type impurity concentration in the first low-concentration n-region 24y1, the second low-concentration n-region 24y2, and the third low-concentration n-region 24y3.

[0036] The n-type impurity concentrations in the first high-concentration n-region 24z1 and the second high-concentration n-region 24z2 are, for example, 1.5 to 10 times the n-type impurity concentrations in the first low-concentration n-region 24y1, the second low-concentration n-region 24y2, and the third low-concentration n-region 24y3. The n-type impurity concentrations in the first high-concentration n-region 24z1 and the second high-concentration n-region 24z2 are, for example, 1 × 10⁻⁶ 15 cm -3 The above 2 x 10 17 cm -3 The following applies:

[0037] The p-shaped body region 26 is provided between the drift region 24 and the first surface F1. The body region 26 extends in the first direction. The body region 26 functions as the channel region of the MOSFET 100.

[0038] A portion of the body region 26 is in contact with the first surface F1. A portion of the body region 26 faces the first gate electrode 18a, the second gate electrode 18b, and the third gate electrode 18c. A portion of the body region 26 becomes the channel region of the MOSFET 100.

[0039] The body region 26 contains, for example, aluminum (Al) as a p-type impurity. The depth of the body region 26 is, for example, between 500 nm and 900 nm. The body region 26 is electrically connected to the source electrode 12. The body region 26 is fixed at the potential of the source electrode 12.

[0040] Body region 26 consists of a first low-concentration p region 26x1 (fourth region) of the p type, a second low-concentration p region 26x2 (eighth region) of the p type, a third low-concentration p region 26x3 of the p type, and p + The first high-concentration p region of type 26y1 (the fifth region), p +The second high-concentration p region of type 26y2 (the ninth region), p ++ It includes the type contact region 26z (the 10th region).

[0041] The first low-concentration p-region 26x1 is in contact with the first low-concentration n-region 24y1. The first low-concentration p-region 26x1 is located in a third direction relative to the first low-concentration n-region 24y1.

[0042] The second low-concentration p region 26x2 is in contact with the second low-concentration n region 24y2. The second low-concentration p region 26x2 is located in a third direction relative to the second low-concentration n region 24y2.

[0043] The third low-concentration p region 26x3 is in contact with the third low-concentration n region 24y3. The third low-concentration p region 26x3 is located in the third direction of the third low-concentration n region 24y3.

[0044] The first low-concentration p-region 26x1, the second low-concentration p-region 26x2, and the third low-concentration p-region 26x3 of the p-type contain, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the first low-concentration p-region 26x1, the second low-concentration p-region 26x2, and the third low-concentration p-region 26x3 of the p-type is, for example, 5 × 10⁻⁶ 16 cm -3 The above 5 x 10 19 cm -3 The following applies:

[0045] The first high-concentration p-region 26y1 is in contact with the first high-concentration n-region 24z1. The first high-concentration p-region 26y1 is located in a third direction relative to the first high-concentration n-region 24z1. The first high-concentration p-region 26y1 is located between the first low-concentration p-region 26x1 and the second low-concentration p-region 26x2.

[0046] The first high-concentration p-region 26y1 is located, for example, in a third direction of the contact electrode portion 12x. The first high-concentration p-region 26y1 is located, for example, directly below the contact electrode portion 12x.

[0047] The first high-concentration p region 26y1 is located, for example, in a third direction of the contact region 26z. The first high-concentration p region 26y1 is located, for example, directly below the contact region 26z. The first high-concentration p region 26y1 is in contact with the contact region 26z.

[0048] The second high-concentration p region 26y2 is in contact with the second high-concentration n region 24z2. The second high-concentration p region 26y2 is located in a third direction relative to the second high-concentration n region 24z2. The second high-concentration p region 26y2 is located between the second low-concentration p region 26x2 and the third low-concentration p region 26x3.

[0049] The second high-concentration p-region 26y2 is located, for example, in a third direction of the contact electrode portion 12x. The second high-concentration p-region 26y2 is located, for example, directly below the contact electrode portion 12x.

[0050] The second high-concentration p region 26y2 is located, for example, in a third direction of the contact region 26z. The second high-concentration p region 26y2 is located, for example, directly below the contact region 26z. The second high-concentration p region 26y2 is in contact with the contact region 26z.

[0051] The first high-concentration p-region 26y1 and the second high-concentration p-region 26y2 contain, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentrations in the first high-concentration p-region 26y1 and the second high-concentration p-region 26y2 are higher than the p-type impurity concentrations in the first low-concentration p-region 26x1, the second low-concentration p-region 26x2, and the third low-concentration p-region 26x3.

[0052] The p-type impurity concentrations in the first high-concentration p-region 26y1 and the second high-concentration p-region 26y2 are, for example, 1.5 to 10 times the p-type impurity concentrations in the first low-concentration p-region 26x1, the second low-concentration p-region 26x2, and the third low-concentration p-region 26x3. The p-type impurity concentrations in the first high-concentration p-region 26y1 and the second high-concentration p-region 26y2 are, for example, 5 × 10 16 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0053] p ++ The contact region 26z of the type is located between the first high-concentration p region 26y1 and the first surface F1. The contact region 26z is located between the first high-concentration p region 26y1 and the source electrode 12. The contact region 26z is located between the first high-concentration p region 26y1 and the contact electrode portion 12x of the source electrode 12. The contact region 26z is located in a third direction of the first high-concentration p region 26y1. The contact region 26z is in contact with the first high-concentration p region 26y1.

[0054] The contact region 26z is located between the second high-concentration p region 26y2 and the first surface F1. The contact region 26z is located between the second high-concentration p region 26y2 and the source electrode 12. The contact region 26z is located between the second high-concentration p region 26y2 and the contact electrode portion 12x of the source electrode 12. The contact region 26z is located in a third direction of the second high-concentration p region 26y2. The contact region 26z is in contact with the second high-concentration p region 26y2.

[0055] The contact region 26z is in contact with the source electrode 12. The contact region 26z is electrically connected to the source electrode 12. The contact between the contact region 26z and the source electrode 12 is, for example, an ohmic contact. The contact region 26z is fixed at the potential of the source electrode 12.

[0056] The contact region 26z is in contact with the contact electrode portion 12x of the source electrode 12. The depth of the contact region 26z is, for example, between 200 nm and 500 nm.

[0057] The contact region 26z contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in contact region 26z is higher than that of the first high-concentration p-region 26y1 and the second high-concentration p-region 26y2. The concentration of p-type impurities in contact region 26z is, for example, 1 × 10⁻⁶. 19 cm -3 The above 5 x 10 21 cm-3 The following applies:

[0058] n + The source region 30 of the shape is provided between the body region 26 and the first surface F1. The source region 30 is provided, for example, between the first low-density p region 26x1 and the first surface F1. The source region 30 is provided, for example, between the first high-density p region 26y1 and the first surface F1.

[0059] The source region 30 is provided, for example, between a third low-concentration p region 26x3 and a first surface F1. The source region 30 is provided, for example, between a second high-concentration p region 26y2 and a first surface F1.

[0060] Source region 30 contains, for example, phosphorus (P) or nitrogen (N) as n-type impurities. The concentration of n-type impurities in source region 30 is higher than the concentration of n-type impurities in drift region 24.

[0061] The concentration of n-type impurities in source region 30 is, for example, 1 × 10⁻⁶. 19 cm -3 The above 5 x 10 21 cm -3 The following conditions apply: The depth of the source region 30 is shallower than the depth of the body region 26. The depth of the source region 30 is, for example, between 80 nm and 200 nm.

[0062] The source region 30 is in contact with the source electrode 12. The source region 30 is electrically connected to the source electrode 12. The contact between the source region 30 and the source electrode 12 is, for example, an ohmic contact. The source region 30 is fixed at the potential of the source electrode 12. The source region 30 is in contact with the contact electrode portion 12x of the source electrode 12.

[0063] The first gate electrode 18a is provided on the side of the first surface F1 with respect to the silicon carbide layer 10. The first gate electrode 18a extends in the first direction. The first gate electrode 18a faces the body region 26 on the first surface F1.

[0064] The second gate electrode 18b is provided on the side of the first surface F1 relative to the silicon carbide layer 10. The second gate electrode 18b extends in a first direction. The second gate electrode 18b is provided in a second direction relative to the first gate electrode 18a. The second gate electrode 18b faces the body region 26 on the first surface F1.

[0065] The third gate electrode 18c is provided on the side of the first surface F1 relative to the silicon carbide layer 10. The third gate electrode 18c extends in a first direction. The third gate electrode 18c is provided in a second direction relative to the second gate electrode 18b. The second gate electrode 18b is provided between the first gate electrode 18a and the third gate electrode 18c. The third gate electrode 18c faces the body region 26 on the first surface F1.

[0066] The first gate electrode 18a, the second gate electrode 18b, and the third gate electrode 18c are conductive layers. The first gate electrode 18a, the second gate electrode 18b, and the third gate electrode 18c are, for example, polycrystalline silicon containing p-type or n-type impurities.

[0067] A first gate insulating layer 16a is provided between the first gate electrode 18a and the body region 26. A second gate insulating layer 16b is provided between the second gate electrode 18b and the body region 26. A third gate insulating layer 16c is provided between the third gate electrode 18c and the body region 26.

[0068] The first gate insulating layer 16a, the second gate insulating layer 16b, and the third gate insulating layer 16c include, for example, silicon oxide. The first gate insulating layer 16a, the second gate insulating layer 16b, and the third gate insulating layer 16c include, for example, silicon oxide layers. It is also possible to apply, for example, a high dielectric constant insulating material to the first gate insulating layer 16a, the second gate insulating layer 16b, and the third gate insulating layer 16c. Furthermore, it is also possible to apply, for example, a laminated structure of a silicon oxide layer and a high dielectric constant insulating layer to the first gate insulating layer 16a, the second gate insulating layer 16b, and the third gate insulating layer 16c.

[0069] The thicknesses of the first gate insulating layer 16a, the second gate insulating layer 16b, and the third gate insulating layer 16c are, for example, between 30 nm and 100 nm.

[0070] The interlayer insulating layer 20 is provided on the first gate electrode 18a, the second gate electrode 18b, and the third gate electrode 18c. The interlayer insulating layer 20 is provided between the first gate electrode 18a and the source electrode 12, between the second gate electrode 18b and the source electrode 12, and between the third gate electrode 18c and the source electrode 12.

[0071] The interlayer insulating layer 20 electrically isolates the first gate electrode 18a from the source electrode 12, the second gate electrode 18b from the source electrode 12, and the third gate electrode 18c from the source electrode 12. The interlayer insulating layer 20 includes, for example, silicon oxide. The interlayer insulating layer 20 is, for example, a silicon oxide layer.

[0072] The source electrode 12 is provided on the side of the first surface F1 relative to the silicon carbide layer 10. The source electrode 12 is in contact with the silicon carbide layer 10. The source electrode 12 is in contact with the contact region 26z and the source region 30.

[0073] The source electrode 12 includes a contact electrode portion 12x. The contact electrode portion 12x is located between the first gate electrode 18a and the second gate electrode 18b. The contact electrode portion 12x is in contact with the contact region 26z and the source region 30.

[0074] The source electrode 12 contains a metal. The source electrode 12 has, for example, a laminated structure of a barrier metal film and a metal film.

[0075] The barrier metal film includes, for example, titanium (Ti), tungsten (W), or tantalum (Ta). The barrier metal film is, for example, a titanium film, a titanium nitride film, a tungsten nitride film, or a tantalum nitride film.

[0076] The metal film includes, for example, aluminum (Al). The metal film is, for example, an aluminum film.

[0077] The contact electrode portion 12x of the source electrode 12 includes, for example, a metal silicide layer. The metal silicide layer is in contact with, for example, the contact region 26z. The metal silicide layer is in contact with, for example, the source region 30.

[0078] The metal silicide layer includes, for example, nickel (Ni), titanium (Ti), or cobalt (Co). The metal silicide layer is, for example, a nickel silicide layer, a titanium silicide layer, or a cobalt silicide layer.

[0079] The drain electrode 14 is provided on the second surface F2 side of the silicon carbide layer 10. The drain electrode 14 is provided on the second surface F2 of the silicon carbide layer 10. The drain electrode 14 is in contact with the second surface F2.

[0080] The drain electrode 14 includes, for example, a metal or a metal-semiconductor compound. The drain electrode 14 includes, for example, a nickel silicide layer, a titanium layer, a nickel layer, a silver layer, or a gold layer.

[0081] The drain electrode 14 is electrically connected to the drain region 22. The drain electrode 14 is, for example, in contact with the drain region 22.

[0082] Next, the operation and effects of the MOSFET 100 of the first embodiment will be described.

[0083] Figure 4 is a schematic cross-sectional view of a comparative example semiconductor device. Figure 4 corresponds to Figure 1 of the first embodiment.

[0084] The semiconductor device in the comparative example is a planar gate type vertical MOSFET 900 using silicon carbide.

[0085] The MOSFET900 has an n-type drift region 24, n + The first high-concentration n region of type 24z1, n +It differs from the MOSFET 100 of the first embodiment in that it does not include the second high-concentration n region 24z2 of the p type. Also, the MOSFET 900 has a p-type body region 26, + Type 1 high-concentration p region 26y1, p + It differs from the MOSFET 100 of the first embodiment in that it does not include the second high-concentration p-region 26y2 of the type.

[0086] When a reverse bias voltage exceeding the breakdown voltage is applied to a MOSFET, avalanche breakdown occurs at the pn junction, and an avalanche current flows. This avalanche current can cause the MOSFET to burn out, for example, due to an increase in its temperature. The current or energy that a MOSFET can tolerate when avalanche breakdown occurs is called the avalanche withstand voltage.

[0087] In the MOSFET900, for example, if the breakdown voltage of the pn junction between the p-type body region 26 and the n-type drift region 24 in the cell becomes too high, the reverse bias voltage at which avalanche breakdown occurs will increase, potentially reducing the avalanche withstand capability. In particular, if avalanche breakdown occurs in the pn junction of the termination region (not shown) surrounding the cell of the MOSFET900 before the cell, the avalanche withstand capability will decrease. This is because the area of ​​the termination region is smaller than the area of ​​the cell, thus limiting the current that the MOSFET900 can supply.

[0088] In the MOSFET 100 of the first embodiment, the n-type drift region 24 is n + The first high-concentration n region of type 24z1, n + It includes a second high-concentration n region 24z2 of type p. Also, the p-type body region 26 is p + Type 1 high-concentration p region 26y1, p + It includes the second high-concentration p-region 26y2 of the type.

[0089] MOSFET100 is n + The first high-concentration n region of type 24z1 and p + A pn junction is formed in the first high-concentration p region 26y1 of the type, and n +The second high-concentration n region of type 24z2 and p + The MOSFET 100 features a pn junction formed in the second high-concentration p region 26y2 of the type. By partially incorporating a pn junction with a high impurity concentration in the cell portion, avalanche breakdown is more likely to occur in the cell portion. Therefore, the avalanche withstand capability of the MOSFET 100 is improved.

[0090] From the viewpoint of improving avalanche resistance, it is preferable to provide two pn junctions for one contact electrode portion 12x: a pn junction formed by a first high-concentration n region 24z1 and a first high-concentration p region 26y1, and a pn junction formed by a second high-concentration n region 24z2 and a second high-concentration p region 26y2. By providing two pn junctions, the paths of the avalanche current flowing into one contact electrode portion 12x are dispersed, and the heat generation of the contact electrode portion 12x is suppressed. Therefore, the avalanche resistance is improved.

[0091] From the viewpoint of improving avalanche tolerance, it is preferable that the first high-concentration p region 26y1 is located in the third direction of the contact region 26z. In other words, it is preferable that the first high-concentration p region 26y1 is located directly below the contact region 26z. Furthermore, it is preferable that the first high-concentration p region 26y1 is in contact with the contact region 26z. With the above configuration, the electrical resistance of the path through which the avalanche current flows is reduced. Therefore, heat generation in the contact electrode portion 12x is suppressed, and the avalanche tolerance is improved.

[0092] Similarly, from the viewpoint of improving avalanche tolerance, the second high-concentration p-region 26y2 is preferably located in the third direction of the contact region 26z. In other words, the second high-concentration p-region 26y2 is preferably located directly below the contact region 26z. Furthermore, the second high-concentration p-region 26y2 is preferably in contact with the contact region 26z. With the above configuration, the electrical resistance of the path through which the avalanche current flows is reduced. Therefore, heat generation in the contact electrode portion 12x is suppressed, and the avalanche tolerance is improved.

[0093] From the viewpoint of improving avalanche tolerance, the p-type impurity concentrations in the first high-concentration p-region 26y1 and the second high-concentration p-region 26y2 are preferably 1.5 times or more, and more preferably 2 times or more, the p-type impurity concentrations in the first low-concentration p-region 26x1, the second low-concentration p-region 26x2, and the third low-concentration p-region 26x3.

[0094] (modified version) Figure 5 is a schematic cross-sectional view of a modified semiconductor device of the first embodiment. Figure 5 corresponds to Figure 1 of the first embodiment.

[0095] The modified semiconductor device is a planar gate type vertical MOSFET 101 using silicon carbide.

[0096] MOSFET101 has an n-type drift region 24, and a second low-concentration n-type region 24y2, n + MOSFET 900 differs from the MOSFET 100 of the first embodiment in that it does not include the second high-concentration n region 24z2 of the p type. Furthermore, the p-type body region 26 of MOSFET 900 is a second low-concentration p region 26x2 of the p type, p + It differs from the MOSFET 100 of the first embodiment in that it does not include the second high-concentration p-region 26y2 of the type.

[0097] Similar to the MOSFET 100 in the first embodiment, the avalanche withstand capability of MOSFET 101 is improved.

[0098] As described above, according to the first embodiment and its modifications, a MOSFET with improved avalanche withstand capability can be realized.

[0099] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the first silicon carbide region further includes an eleventh region in contact with the first surface, the first electrode further includes a second portion in contact with the eleventh region, the second portion is provided between the first gate electrode and the second gate electrode, and the second portion is located in a first direction relative to the first portion. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0100] The semiconductor device of the second embodiment is a planar gate type vertical MOSFET 200 using silicon carbide. The MOSFET 200 of the second embodiment is a DIMOSFET. Furthermore, the MOSFET 200 of the second embodiment is equipped with a Schottky Barrier Diode (SBD) as an internal diode.

[0101] The following explanation will use the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. MOSFET200 is a vertical n-channel MOSFET that uses electrons as carriers.

[0102] Figures 6 and 7 are schematic cross-sectional views of the semiconductor device according to the second embodiment. Figures 8 and 9 are schematic top views of the semiconductor device according to the second embodiment. Figure 8 is a schematic diagram showing the pattern of the gate electrode and impurity region on the upper surface of the silicon carbide layer. Figure 9 is a schematic diagram showing the pattern of the impurity region on the upper surface of the silicon carbide layer, with the gate electrode removed from Figure 8. Figure 6 is a cross-sectional view of BB' in Figures 8 and 9. Figure 7 is a cross-sectional view of BB' in Figures 8 and 9.

[0103] The MOSFET 200 comprises a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a first gate insulating layer 16a, a second gate insulating layer 16b, a third gate insulating layer 16c, a first gate electrode 18a, a second gate electrode 18b, a third gate electrode 18c, and an interlayer insulating layer 20. The source electrode 12 includes a contact electrode portion 12x (first portion) and a diode electrode portion 12y (second portion).

[0104] Within the silicon carbide layer 10, n + Drain region 22 of type n, drift region 24 (first silicon carbide region) of type n, body region 26 (second silicon carbide region) of type p, n ++ A source region 30 (third silicon carbide region) is provided.

[0105] The n-shaped drift region 24 is n -The lower region 24x (first region) of the shape, the first low-concentration n region 24y1 of n-type (second region), the second low-concentration n region 24y2 of n-type (sixth region), the third low-concentration n region 24y3 of n-type, n + the first high-concentration n region 24z1 of n-type (third region), n + the second high-concentration n region 24z2 of n-type (seventh region), and the JBS region 24s (eleventh region).

[0106] The p-type body region 26 includes a first low-concentration p region 26x1 of p-type (fourth region), a second low-concentration p region 26x2 of p-type (eighth region), a third low-concentration p region 26x3 of p-type, p + the first high-concentration p region 26y1 of p-type (fifth region), p + the second high-concentration p region 26y2 of p-type (ninth region), p ++ and the contact region 26z of p-type (tenth region).

[0107] The source electrode 12 includes a contact electrode portion 12x and a diode electrode portion 12y. The contact electrode portion 12x and the diode electrode portion 12y are provided between the first gate electrode 18a and the second gate electrode 18b. The contact electrode portion 12x and the diode electrode portion 12y are provided between the second gate electrode 18b and the third gate electrode 18c.

[0108] The diode electrode portion 12y is located in the first direction of the contact electrode portion 12x.

[0109] n - The n-type drift region 24 includes the JBS region 24s. The JBS region 24s is in contact with the first surface F1. The JBS region 24s is surrounded by the body region 26.

[0110] The JBS region 24s is in contact with the diode electrode portion 12y of the source electrode 12. The JBS region 24s functions as the cathode region of the SBD.

[0111] In the drift region 24 surrounding the JBS region 24s, n + the first high-concentration n region 24z1 of n-type, n+ There is no second high-concentration n region 24z2 of this type. Also, in the body region 26 surrounding the JBS region 24s, there is no p + type first high-concentration p region 26y1 and no p + type second high-concentration p region 26y2 of this type.

[0112] Next, the operation and effects of the MOSFET 200 of the second embodiment will be described.

[0113] FIG. 10 is an equivalent circuit diagram of the semiconductor device of the second embodiment. In the MOSFET 200, a pn diode and an SBD are connected as built-in diodes in parallel with the transistor between the source electrode 12 and the drain electrode 14. The body region 26 is the anode region of the pn junction diode, and the drift region 24 is the cathode region of the pn junction diode. Also, the source electrode 12 is the anode electrode of the SBD, and the JBS region 24s is the cathode region of the SBD.

[0114] For example, consider the case where the MOSFET 200 is used as a switching element connected to an inductive load. When the MOSFET 200 is off, a voltage that is positive with respect to the drain electrode 14 may be applied to the source electrode 12 due to the inductive current caused by the inductive load. In this case, a forward current flows through the built-in diode. This state is also referred to as a reverse conduction state.

[0115] If the MOSFET does not include an SBD, a forward current flows through the pn junction diode. The pn junction diode operates in a bipolar manner. When a reflux current is passed through the pn junction diode operating in a bipolar manner, stacking defects grow in the silicon carbide layer due to the recombination energy of carriers. When stacking defects grow in the silicon carbide layer, there arises a problem that the on-resistance of the MOSFET increases. The increase in the on-resistance of the MOSFET leads to a decrease in the reliability of the MOSFET.

[0116] The MOSFET200 is equipped with an SBD. The forward voltage (Vf) at which forward current begins to flow through the SBD is lower than the forward voltage (Vf) of the pn junction diode. Therefore, forward current flows through the SBD before it flows through the pn junction diode.

[0117] The forward voltage (Vf) of an SBD is, for example, between 1.0V and less than 2.0V. The forward voltage (Vf) of a pn junction diode is, for example, between 2.0V and 3.0V.

[0118] The SBD operates unipolar. Therefore, even when forward current flows, stacking faults do not grow in the silicon carbide layer 10 due to carrier recombination energy. Consequently, the increase in the on-resistance of the MOSFET 200 is suppressed. Thus, the reliability of the MOSFET 200 is improved.

[0119] Furthermore, MOSFET200 is similar to MOSFET100 in the first embodiment, n + The first high-concentration n region of type 24z1 and p + A pn junction is formed in the first high-concentration p region 26y1 of the type, and n + The second high-concentration n region of type 24z2 and p + It features a pn junction formed in the second high-concentration p region 26y2 of the type. Therefore, the avalanche withstand capability of MOSFET 200 is improved by a similar mechanism as in MOSFET 100.

[0120] Furthermore, in MOSFET200, the drift region 24 surrounding the JBS region 24s is n + The first high-concentration n region of type 24z1, n + The second high-concentration n region 24z2 of type is absent. Also, the body region 26 surrounding the JBS region 24s contains p + The first high-concentration p-region of type 26y1, p + The second high-concentration p-region 26y2 of type is absent.

[0121] Therefore, avalanche breakdown occurs near the JBS region 24s, and the flow of avalanche current is suppressed. Thus, the degradation of the Schottky junction characteristics of the SBD due to heat generation can be suppressed.

[0122] In the first and second embodiments, the case of 4H-SiC as the crystal structure of SiC was described as an example, but the present invention can also be applied to devices using SiC with other crystal structures such as 6H-SiC and 3C-SiC. Furthermore, it is possible to apply a plane other than the (0001) plane to the surface of the silicon carbide layer 10.

[0123] In the first and second embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type was described as an example, but it is also possible to have the first conductivity type be p-type and the second conductivity type be n-type.

[0124] In the first and second embodiments, aluminum (Al) was exemplified as a p-type impurity, but boron (B) can also be used. Similarly, nitrogen (N) and phosphorus (P) were exemplified as n-type impurities, but arsenic (As), antimony (Sb), etc., can also be applied.

[0125] Furthermore, the present invention can also be applied to Insulated Gate Bipolar Transistors (IGBTs).

[0126] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0127] 10. Silicon carbide layer 12 Source electrode (first electrode) 12x Contact electrode portion (first portion) 12y diode electrode portion (second portion) 14. Drain electrode (second electrode) 16a First gate insulating layer 16b Second gate insulating layer 16c Third gate insulating layer 18a First gate electrode 18b Second gate electrode 18th Third gate electrode 24. Drift region (first silicon carbide region) 24x Lower region (first region) 24y1 First low-concentration n region (second region) 24y2 Second low-concentration n region (sixth region) 24z1 First high-concentration n region (third region) 24z2 Second high-concentration n region (seventh region) 24s JBS area (11th area) 26 Body region (second silicon carbide region) 26x1 First low-concentration p-region (fourth region) 26x2 Second low-concentration p-region (8th region) 26y1 First high-concentration p-region (fifth region) 26y2 Second high-concentration p-region (9th region) 26z Contact area (10th area) 30. Source region (third silicon carbide region) 100 MOSFETs (Semiconductor Devices) 200 MOSFETs (Semiconductor Equipment) F1 First Side F2 Second side

Claims

1. A silicon carbide layer having a first surface and a second surface facing the first surface, A first silicon carbide region of a first conductivity type provided within the silicon carbide layer, comprising a first region, a second region and a third region, wherein the second region is located between the first region and the first surface, the third region is located between the first region and the first surface, the concentration of the first conductivity type impurity in the second region is equal to or higher than the concentration of the first conductivity type impurity in the first region, and the concentration of the first conductivity type impurity in the third region is higher than that in the second region, and A second silicon carbide region of a second conductivity type, provided within the silicon carbide layer and located between the first silicon carbide region and the first surface, comprising a fourth region and a fifth region, wherein the fourth region is in contact with the second region, and the concentration of the second conductivity type impurity in the fifth region is higher than the concentration of the second conductivity type impurity in the fourth region, and A third silicon carbide region of first conductivity type is provided within the silicon carbide layer and is located between the second silicon carbide region and the first surface, A first gate electrode is provided on the side of the first surface with respect to the silicon carbide layer, extending in a first direction parallel to the first surface, and facing the second silicon carbide region on the first surface, A second gate electrode is provided on the first surface side with respect to the silicon carbide layer, extending in the first direction, and provided in a second direction parallel to the first surface and perpendicular to the first direction with respect to the first gate electrode, and facing the second silicon carbide region on the first surface, A first gate insulating layer is provided between the second silicon carbide region and the first gate electrode, A second gate insulating layer is provided between the second silicon carbide region and the second gate electrode, A first electrode provided on the first surface side of the silicon carbide layer, comprising a first electrode provided between the first gate electrode and the second gate electrode, and including a first portion in contact with the second silicon carbide region and the third silicon carbide region, A second electrode provided on the second surface side of the silicon carbide layer, Equipped with, The first silicon carbide region further includes a sixth region and a seventh region, the sixth region being located between the first region and the first surface, the seventh region being located between the first region and the first surface, the first conductivity type impurity concentration in the sixth region being equal to or higher than the first conductivity type impurity concentration in the first region, the first conductivity type impurity concentration in the seventh region being higher than that in the second region, and the sixth region being located between the third region and the seventh region. The second silicon carbide region further includes an eighth region and a ninth region, the eighth region being in contact with the sixth region, the ninth region being in contact with the seventh region, the second conductivity type impurity concentration in the ninth region being higher than the second conductivity type impurity concentration in the eighth region, and the eighth region being located between the fifth region and the ninth region.

2. A silicon carbide layer having a first surface and a second surface facing the first surface, A first silicon carbide region of a first conductivity type provided within the silicon carbide layer, comprising a first region, a second region and a third region, wherein the second region is located between the first region and the first surface, the third region is located between the first region and the first surface, the concentration of the first conductivity type impurity in the second region is equal to or higher than the concentration of the first conductivity type impurity in the first region, and the concentration of the first conductivity type impurity in the third region is higher than that in the second region, and A second silicon carbide region of a second conductivity type, provided within the silicon carbide layer and located between the first silicon carbide region and the first surface, comprising a fourth region and a fifth region, wherein the fourth region is in contact with the second region, and the concentration of the second conductivity type impurity in the fifth region is higher than the concentration of the second conductivity type impurity in the fourth region, and A third silicon carbide region of first conductivity type is provided within the silicon carbide layer and is located between the second silicon carbide region and the first surface, A first gate electrode is provided on the side of the first surface with respect to the silicon carbide layer, extending in a first direction parallel to the first surface, and facing the second silicon carbide region on the first surface, A second gate electrode is provided on the first surface side with respect to the silicon carbide layer, extending in the first direction, and provided in a second direction parallel to the first surface and perpendicular to the first direction with respect to the first gate electrode, and facing the second silicon carbide region on the first surface, A first gate insulating layer is provided between the second silicon carbide region and the first gate electrode, A second gate insulating layer is provided between the second silicon carbide region and the second gate electrode, A first electrode provided on the first surface side of the silicon carbide layer, comprising a first electrode provided between the first gate electrode and the second gate electrode, and including a first portion in contact with the second silicon carbide region and the third silicon carbide region, A second electrode provided on the second surface side of the silicon carbide layer, Equipped with, The concentration of the first conductivity type impurity in the second region is higher than the concentration of the first conductivity type impurity in the first region. A semiconductor device wherein the concentration of the second conductivity type impurity in the fifth region is 1.5 times or more and 10 times or less the concentration of the second conductivity type impurity in the fourth region.

3. The semiconductor device according to claim 1, wherein the concentration of the second conductivity type impurity in the fifth region is 1.5 times or more and 10 times or less the concentration of the second conductivity type impurity in the fourth region.

4. The semiconductor device according to any one of claims 1 to 3, wherein the fifth region is located relative to the first portion in a direction from the first surface toward the second surface.

5. The fifth region is located in a third direction from the first surface toward the second surface relative to the first portion, The semiconductor device according to claim 1, wherein the ninth region is located in the third direction relative to the first portion.

6. A silicon carbide layer having a first surface and a second surface facing the first surface, A first silicon carbide region of a first conductivity type provided within the silicon carbide layer, comprising a first region, a second region and a third region, wherein the second region is located between the first region and the first surface, the third region is located between the first region and the first surface, the concentration of the first conductivity type impurity in the second region is equal to or higher than the concentration of the first conductivity type impurity in the first region, and the concentration of the first conductivity type impurity in the third region is higher than that in the second region, and A second silicon carbide region of a second conductivity type, provided within the silicon carbide layer and located between the first silicon carbide region and the first surface, comprising a fourth region and a fifth region, wherein the fourth region is in contact with the second region, and the concentration of the second conductivity type impurity in the fifth region is higher than the concentration of the second conductivity type impurity in the fourth region, and A third silicon carbide region of first conductivity type is provided within the silicon carbide layer and is located between the second silicon carbide region and the first surface, A first gate electrode is provided on the side of the first surface with respect to the silicon carbide layer, extending in a first direction parallel to the first surface, and facing the second silicon carbide region on the first surface, A second gate electrode is provided on the first surface side with respect to the silicon carbide layer, extending in the first direction, and provided in a second direction parallel to the first surface and perpendicular to the first direction with respect to the first gate electrode, and facing the second silicon carbide region on the first surface, A first gate insulating layer is provided between the second silicon carbide region and the first gate electrode, A second gate insulating layer is provided between the second silicon carbide region and the second gate electrode, A first electrode provided on the first surface side of the silicon carbide layer, comprising a first electrode provided between the first gate electrode and the second gate electrode, and including a first portion in contact with the second silicon carbide region and the third silicon carbide region, A second electrode provided on the second surface side of the silicon carbide layer, Equipped with, The second silicon carbide region further includes a tenth region, the tenth region being located between the fifth region and the first portion, and the concentration of the second conductivity type impurity in the tenth region is higher than the concentration of the second conductivity type impurity in the fifth region. The first silicon carbide region further includes an eleventh region in contact with the first surface, The first electrode further includes a second portion that is in contact with the eleventh region, A semiconductor device wherein the second portion is provided between the first gate electrode and the second gate electrode, and the second portion is positioned in the first direction relative to the first portion.

7. The first silicon carbide region further includes an eleventh region in contact with the first surface, The semiconductor device according to any one of claims 1 to 5, wherein the first electrode further includes a second portion in contact with the eleventh region.

8. The semiconductor device according to claim 7, wherein the second portion is provided between the first gate electrode and the second gate electrode, and the second portion is positioned in the first direction of the first portion.

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