Semiconductor equipment

Abstract

To provide a technique for improving a tolerance dose when an IGBT structure is turned off in a semiconductor device comprising a semiconductor substrate including an IGBT region and a diode region.SOLUTION: A semiconductor device 1 comprises: a plurality of first trench gates 50 positioned in an IGBT region 20A; a plurality of first dummy trenches 60 positioned in a diode region 20B; and a plurality of second dummy trenches 70 positioned in a boundary 20C between the IGBT region and the diode region. The plurality of second dummy trenches is disposed while being spaced apart from each other in a direction of connecting the IGBT region with the diode region. The plurality of second dummy trenches includes a deep portion 76, which is formed deeper than the plurality of trench gates and the plurality of first dummy trenches, at least in a part thereof.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the same.

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate having an IGBT (insulated gate bipolar transistor) region and a diode region. In this semiconductor device, an upper electrode is provided so as to cover the upper surface of the semiconductor substrate, and a lower electrode is provided so as to cover the lower surface of the semiconductor substrate. In the IGBT region, an IGBT structure is provided such that the upper electrode becomes an emitter electrode and the lower electrode becomes a collector electrode. In the diode region, a diode structure is provided such that the upper electrode becomes an anode electrode and the lower electrode becomes a cathode electrode. The diode structure is connected in anti-parallel to the IGBT structure and can operate as a free-wheeling diode.

[0003] Also, in the semiconductor device of Patent Document 1, a plurality of trench gates are provided in the IGBT region, and a plurality of dummy trenches are provided in the diode region. Further, in the semiconductor device of Patent Document 1, a single boundary trench is provided at the boundary between the IGBT region and the diode region and is formed deeper than the plurality of trench gates and the plurality of dummy trenches. The boundary trench is provided to suppress the inflow of carriers from the IGBT region toward the diode region. Thereby, in the semiconductor device of Patent Document 1, it is said that the withstand capacity during the recovery operation of the diode structure increases.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In this type of semiconductor device, there is also a need for techniques to improve the withstand capability when the IGBT structure turns off. This specification provides techniques to improve the withstand capability when the IGBT structure turns off. [Means for solving the problem]

[0006] A semiconductor device disclosed herein may include a semiconductor substrate (10) including an IGBT region (20A) and a diode region (20B), a lower electrode (44) provided on the lower surface (10b) of the semiconductor substrate, an upper electrode (42) provided on the upper surface (10a) of the semiconductor substrate, a plurality of trench gates (50) extending inward from the upper surface of the semiconductor substrate located in the IGBT region, a plurality of first dummy trenches (60) extending inward from the upper surface of the semiconductor substrate located in the diode region, and a plurality of second dummy trenches (70) extending inward from the upper surface of the semiconductor substrate located at the boundary (20C) between the IGBT region and the diode region. Each of the plurality of second dummy trenches may be spaced apart from one another along the direction connecting the IGBT region and the diode region. Each of the plurality of second dummy trenches may have a deep portion (76) formed deeper than the plurality of trench gates and the plurality of first dummy trenches, at least in part thereof. With this semiconductor device, when the IGBT structure turns off, at least part of the second dummy trench is formed deeply, so avalanche preferentially occurs at the bottom of the second dummy trench, and the occurrence of avalanche at the bottom of the trench gate can be suppressed. As a result, the withstand capability when the IGBT structure turns off is improved in this semiconductor device.

[0007] This specification may also disclose a method for manufacturing the semiconductor device described above. This manufacturing method may include a trench forming step of forming a plurality of trenches extending from the upper surface toward the depths of the semiconductor substrate, wherein the trench width of at least a portion of the trenches corresponding to the plurality of second dummy trenches is greater than the trench width of the trenches corresponding to the plurality of trench gates and the plurality of first dummy trenches. According to this manufacturing method, trenches corresponding to each of the plurality of trench gates, the plurality of first dummy trenches and the plurality of second dummy trenches can be formed simultaneously. [Brief explanation of the drawing]

[0008] [Figure 1] This diagram schematically shows the planar layout of the IGBT region and diode region of a semiconductor device. [Figure 2] This is a cross-sectional view of a key part illustrating the features of one embodiment of a semiconductor device, and schematically shows the cross-sectional view of the key part corresponding to line II-II in Figure 1. [Figure 3] This figure illustrates one method for realizing one embodiment of a semiconductor device, and schematically shows a perspective view of the main part of the semiconductor device with the upper electrodes removed. [Figure 4] This figure illustrates one method for realizing one embodiment of a semiconductor device, and schematically shows a perspective view of the main part of the semiconductor device with the upper electrodes removed. [Figure 5] This figure illustrates one method for realizing one embodiment of a semiconductor device, and schematically shows a perspective view of the main part of the semiconductor device with the upper electrodes removed. [Figure 6] This is a cross-sectional view of a key part illustrating another embodiment of the semiconductor device, schematically showing the cross-sectional view of the key part corresponding to line II-II in Figure 1. [Figure 7] This is a cross-sectional view of a key part illustrating another embodiment of the semiconductor device, schematically showing the cross-sectional view of the key part corresponding to line II-II in Figure 1. [Figure 8]This is a cross-sectional view of a key part illustrating another embodiment of the semiconductor device, schematically showing the cross-sectional view of the key part corresponding to line II-II in Figure 1. [Modes for carrying out the invention]

[0009] The embodiments will be described below with reference to the drawings. Components common to all embodiments are denoted by the same reference numerals, and their descriptions are omitted. Furthermore, for the purpose of clarity in the illustration, only some of the components that are repeatedly arranged may be denoted by reference numerals.

[0010] As shown in Figure 1, the semiconductor device 1 includes a semiconductor substrate 10. The semiconductor substrate 10 is not particularly limited, but may be, for example, a silicon carbide (SiC) substrate. In the following, the thickness direction of the semiconductor substrate 10 will be referred to as the z direction, the direction parallel to the upper surface of the semiconductor substrate 10 will be referred to as the x direction, and the direction parallel to the upper surface of the semiconductor substrate 10 and perpendicular to the x direction will be referred to as the y direction.

[0011] As shown in Figure 1, the semiconductor substrate 10 is not particularly limited, but may include, for example, two device regions 20 and a termination region 30 arranged around the device regions 20. Each of the device regions 20 is divided into an IGBT region 20A and a diode region 20B. A structure for forming an IGBT is provided within the IGBT region 20A, and a structure for forming a diode is provided within the diode region 20B. In each of the device regions 20, the IGBT region 20A and the diode region 20B are arranged alternately along the y-direction. Hereinafter, the direction connecting the IGBT region 20A and the diode region 20B, in which the IGBT region 20A and the diode region 20B are arranged alternately, will also be called the IGBT-diode direction.

[0012] As shown in Figure 2, the semiconductor device 1 comprises an upper electrode 42, a lower electrode 44, a plurality of trench gates 50 provided in the IGBT region 20A, a plurality of first dummy trenches 60 provided in the diode region 20B, and a plurality of second dummy trenches 70 provided in the boundary region 20C. The upper electrode 42 is provided to cover the upper surface 10a of the semiconductor substrate 10. The lower electrode 44 is provided to cover the lower surface 10b of the semiconductor substrate 10. In this way, the semiconductor device 1 is configured as a vertical device. The upper electrode 42 functions as the emitter electrode of the IGBT structure and also functions as the anode electrode of the diode structure. The lower electrode 44 functions as the collector electrode of the IGBT structure and also functions as the cathode electrode of the diode structure.

[0013] The semiconductor substrate 10 of the semiconductor device 1 is p + A collector area 11 of type n + A cathode region 12 of type n, an n-type region 13, a p-type region 14, and n + The emitter region 15 of type and p + It includes a type of contact area 16.

[0014] The collector region 11 is located in the IGBT region 20A of the semiconductor substrate 10 and is positioned to be exposed on the lower surface 10b of the semiconductor substrate 10. The collector region 11 is in ohmic contact with the lower electrode 44. The cathode region 12 is located in the diode region 20B of the semiconductor substrate 10 and is positioned to be exposed on the lower surface 10b of the semiconductor substrate 10. The cathode region 12 is in ohmic contact with the lower electrode 44. Thus, the collector region 11 is located across the entire IGBT region 20A and the cathode region 12 is located across the entire diode region 20B at the position exposed on the lower surface 10b of the semiconductor substrate 10. In other words, the semiconductor substrate 10 is divided into the IGBT region 20A where the collector region 11 is located and the diode region 20B where the cathode region 12 is located.

[0015] The n-type region 13 is provided in both the IGBT region 20A and the diode region 20B. In the IGBT region 20A, the n-type region 13 is disposed between the collector region 11 and the p-type region 14 and functions as the drift region of the IGBT structure. In the diode region 20B, the n-type region 13 is provided between the cathode region 12 and the p-type region 14 and functions as the low-concentration region of the diode structure.

[0016] The p-type region 14 is provided in both the IGBT region 20A and the diode region 20B. In the IGBT region 20A, the p-type region 14 is disposed on the n-type region 13 and functions as the body region of the IGBT structure. In the diode region 20B, the p-type region 14 is disposed on the n-type region 13 and functions as the anode region of the diode structure.

[0017] The emitter region 15 is provided in the IGBT region 20A and is dispersedly arranged at a position exposed to the upper surface 10a of the semiconductor substrate 10. The emitter region 15 is in ohmic contact with the upper electrode 42. The emitter region 15 is in contact with the side surface of the trench gate 50 and is separated from the n-type region 13 by the p-type region 14. The portion of the p-type region 14 that separates the n-type region 13 and the emitter region 15 and is in contact with the side surface of the trench gate 50 functions as a channel.

[0018] The contact region 16 is provided in both the IGBT region 20A and the diode region 20B and is dispersedly arranged at a position exposed to the upper surface 10a of the semiconductor substrate 10. The contact region 16 is in ohmic contact with the upper electrode 42. The p-type region 14 is electrically connected to the upper electrode 42 through the contact region 16.

[0019] The plurality of trench gates 50 are provided in the upper layer portion of the semiconductor substrate 10 located in the IGBT region 20A. Each of the plurality of trench gates 50 extends in the x direction and is arranged at intervals in the y direction when the semiconductor substrate 10 is viewed in plan. Thus, the plurality of trench gates 50 are arranged in a stripe shape. Each of the plurality of trench gates 50 is formed so as to penetrate the p-type region 14 from the upper surface 10a of the semiconductor substrate 10 and reach the n-type region 13. Each of the plurality of trench gates 50 includes a gate insulating film 52 and a gate electrode 54 insulated from the semiconductor substrate 10 by the gate insulating film 52. The gate electrode 54 of each of the plurality of trench gates 50 is insulated from the upper electrode 42 by an interlayer insulating film.

[0020] The plurality of first dummy trenches 60 are provided in the upper layer portion of the semiconductor substrate 10 located in the diode region 20B. Each of the plurality of first dummy trenches 60 extends in the x direction and is arranged at intervals in the y direction when the semiconductor substrate 10 is viewed in plan. Thus, the plurality of first dummy trenches 60 are arranged in a stripe shape. Each of the plurality of first dummy trenches 60 is formed so as to penetrate the p-type region 14 from the upper surface 10a of the semiconductor substrate 10 and reach the n-type region 13. Each of the plurality of first dummy trenches 60 includes a dummy insulating film 62 and a dummy electrode 64 insulated from the semiconductor substrate 10 by the dummy insulating film 62. The dummy electrode 64 of each of the plurality of first dummy trenches 60 is electrically connected to the upper electrode 42.

[0021] Multiple second dummy trenches 70 are provided in the upper layer of the semiconductor substrate 10 located at the boundary 20C between the IGBT region 20A and the diode region 20B. Here, the boundary 20C is defined as an area extending a predetermined distance from the boundary between the IGBT region 20A and the diode region 20B (i.e., the boundary between the collector region 11 and the cathode region 12) toward each of the IGBT region 20A and the diode region 20B along the IGBT-diode direction (y-direction in this example). The predetermined distance is half the film thickness of the n-type region 13 measured along the thickness direction of the semiconductor substrate 10. Therefore, the width of the boundary 20C measured along the IGBT-diode direction is equal to the film thickness of the n-type region 13. Multiple second dummy trenches 70 only need to be located in at least a portion of this boundary 20C. In this example, multiple second dummy trenches 70 are located in both the IGBT region 20A and the diode region 20B within the boundary 20C.

[0022] Each of the multiple second dummy trenches 70 extends in the x-direction and is arranged at intervals from one another in the y-direction when the semiconductor substrate 10 is viewed from above. Thus, the multiple second dummy trenches 70 are arranged in a stripe pattern. Each of the multiple second dummy trenches 70 is formed to penetrate the p-type region 14 from the upper surface 10a of the semiconductor substrate 10 and reach the n-type region 13. Each of the multiple second dummy trenches 70 comprises a dummy insulating film 72 and a dummy electrode 74 that is insulated from the semiconductor substrate 10 by the dummy insulating film 72. Each dummy electrode 74 of the multiple second dummy trenches 70 is electrically connected to the upper electrode 42.

[0023] Each of the multiple second dummy trenches 70 has at least a portion of a deep section 76 that is formed deeper than the multiple trench gates 50 and the multiple first dummy trenches 60. As will be described later, each of the multiple second dummy trenches 70 may be configured to be deeper than the multiple trench gates 50 and the multiple first dummy trenches 60 as a whole, or at least a portion of it may be configured to be deeper than the multiple trench gates 50 and the multiple first dummy trenches 60. In the example where the entire second dummy trench 70 is configured to be deeper than the multiple trench gates 50 and the multiple first dummy trenches 60, it can be said that the entire second dummy trench 70 is composed of the deep section 76.

[0024] Multiple second dummy trenches 70 may be formed in a separate process from the multiple trench gates 50 and the multiple first dummy trenches 60. However, manufacturing costs can be reduced by forming the multiple second dummy trenches 70 in the same process as the multiple trench gates 50 and the multiple first dummy trenches 60. Referring to Figures 3 to 5, a configuration of multiple second dummy trenches 70 suitable for reducing manufacturing costs will be described.

[0025] In the example shown in Figure 3, the overall trench width 70W of the second dummy trench 70 is greater than the trench width 50W of the trench gate 50. Note that the trench width of the first dummy trench 60 is the same as the trench width 50W of the trench gate 50. Therefore, the trench width 70W of the second dummy trench 70 is greater than the trench width of the first dummy trench 60. Here, trench width refers to the width of the trench in the shorter direction (y-direction in this example).

[0026] When forming trenches in a semiconductor substrate 10, etching gas can easily enter trenches with larger trench widths, increasing the etching rate. Therefore, by forming multiple trenches with different widths in a single etching pass using a single photomask, it is possible to create trenches of different depths. Accordingly, the manufacturing method of the semiconductor device 1 shown in Figure 3 includes a trench formation step that includes the steps of depositing a photomask on the semiconductor substrate 10 and forming multiple trenches in the upper layer of the semiconductor substrate 10 exposed from the opening of the photomask by dry etching. The photomask is patterned such that the trench width of the trenches corresponding to the multiple second dummy trenches 70 is larger than the trench width of the trenches corresponding to the multiple trench gates 50 and the multiple first dummy trenches 60. This makes it possible to make the depth of the trenches corresponding to the multiple second dummy trenches 70 greater than the depth of the trenches corresponding to the multiple trench gates 50 and the multiple first dummy trenches 60 in a single etching pass using a single photomask.

[0027] In the example shown in Figure 3, each of the multiple second dummy trenches 70 was formed so that the trench width at any position along its longitudinal direction was greater than the trench width of each of the multiple trench gates 50 and the multiple first dummy trenches 60. As a result, each of the multiple second dummy trenches 70 was configured so that its entirety was deeper than the multiple trench gates 50 and the multiple first dummy trenches 60. Alternatively, in the example shown in Figure 4, each of the multiple second dummy trenches 70 is formed so that the trench width at some positions along its longitudinal direction is greater than the trench width of each of the multiple trench gates 50 and the multiple first dummy trenches 60. As a result, each of the multiple second dummy trenches 70 is configured so that the portion corresponding to some position along its longitudinal direction is deeper than the multiple trench gates 50 and the multiple first dummy trenches 60. In the example shown in Figure 4, a deep portion 76 is formed in part of each of the multiple second dummy trenches 70, and these deep portions 76 are distributed within the boundary portion 20C. In the example shown in Figure 4, a single etching using a single photomask can make the trench depth corresponding to the deep portion 76 greater than the trench depth corresponding to the multiple trench gates 50 and the multiple first dummy trenches 60.

[0028] In the example shown in Figure 5, multiple connected dummy trenches 80 are provided between adjacent second dummy trenches 70 in the IGBT-diode direction. Each of the multiple connected dummy trenches 80 extends in the y-direction and is arranged with a distance between them in the x-direction when the semiconductor substrate 10 is viewed from above. Each of the multiple connected dummy trenches 80 is formed to penetrate the p-type region 14 from the top surface of the semiconductor substrate 10 and reach the n-type region 13. Each of the multiple connected dummy trenches 80 includes a dummy insulating film 82 and a dummy electrode 84 that is insulated from the semiconductor substrate 10 by the dummy insulating film 82. Each dummy electrode 84 of the multiple connected dummy trenches 80 is electrically connected to the upper electrode 42.

[0029] Each of the multiple connected dummy trenches 80 is connected at both ends to each of the adjacent second dummy trenches 70. Deep sections 76 are formed where the connected dummy trenches 80 are connected to the second dummy trenches 70, and these deep sections 76 are distributed within the boundary section 20C. In the example of Figure 5, trenches corresponding to each of the multiple trench gates 50, multiple first dummy trenches 60, multiple second dummy trenches 70, and multiple connected dummy trenches 80 are simultaneously formed by a single etching using a single photomask. In the section where the connected dummy trenches 80 are connected to the second dummy trenches 70, the effective trench width of the trench is increased. Therefore, in the example of Figure 5, the depth of the trench corresponding to the deep section 76 can be made greater than the depth of the trench corresponding to the multiple trench gates 50 and multiple first dummy trenches 60 by a single etching using a single photomask.

[0030] Next, the operation of the semiconductor device 1 will be described. In the mode in which the IGBT structure is operating, a voltage is applied between the lower electrode 44 and the upper electrode 42 such that the lower electrode 44 is at a higher potential than the upper electrode 42. In this mode in which the IGBT structure is operating, when the voltage between the gate electrode 54 and the upper electrode 42 becomes higher than the threshold voltage, a channel is formed in the p-type region 14 in contact with the side surface of the trench gate 50, and electron carriers are injected from the emitter region 15 to the n-type region 13 through this channel. On the other hand, hole carriers are injected from the collector region 11 to the n-type region 13. This turns on the IGBT structure. When the voltage between the gate electrode 54 and the upper electrode 42 becomes lower than the threshold voltage, the channel on the side surface of the trench gate 50 disappears, and the IGBT structure in the IGBT region 20A is turned off. In this way, in the mode in which the IGBT structure is operating, the on and off of the IGBT structure is controlled according to the potential of the gate electrode 54 of the trench gate 50.

[0031] In the mode in which the diode structure operates, a voltage is applied between the lower electrode 44 and the upper electrode 42 such that the upper electrode 42 is at a higher potential than the lower electrode 44. In this mode in which the diode structure operates, the gate electrode 54 is set to the potential of the upper electrode 42, and the channels on the sides of the trench gate 50 disappear. In this mode in which the diode structure operates, since the upper electrode 42 is at a higher potential than the lower electrode 44, a freewheeling current flows through the pn diode, which is composed of a p-type region 14, an n-type region 13, and a cathode region 12.

[0032] In the operating mode of the IGBT structure described above, when the IGBT structure turns off, hole carriers remaining in the n-type region 13 become high-energy due to the high voltage of the inductive load, which can cause avalanche during the process of the hole carriers being discharged to the upper electrode 42. In the semiconductor device 1, since at least a portion of the second dummy trench 70 is formed deeply, avalanche preferentially occurs at the bottom of the second dummy trench 70, and the occurrence of avalanche at the bottom of the trench gate 50 can be suppressed. In particular, in the semiconductor device 1, multiple second dummy trenches are arranged at intervals along the IGBT-diode direction at the boundary 20C. Therefore, in the semiconductor device 1, the second dummy trench 70 is reliably positioned in the path through which hole carriers remaining near the boundary between the IGBT region 20A and the diode region 20B are discharged. As a result, in the semiconductor device 1, avalanche can be preferentially generated at the boundary 20C, and the occurrence of avalanche at the bottom of the trench gate 50 can be suppressed. As a result, the destruction of the trench gate 50 by avalanche is suppressed, and the withstand capability of the IGBT structure when it turns off in the semiconductor device 1 is improved.

[0033] The following describes semiconductor devices of other embodiments. These semiconductor devices can also have the same effects and advantages as semiconductor device 1 described above.

[0034] In the semiconductor device 2 shown in Figure 6, the second dummy trench 70 is unevenly distributed in the IGBT region 20A of the boundary region 20C, and the first dummy trench 60 is provided in the diode region 20B of the boundary region 20C.

[0035] In the semiconductor device 3 shown in Figure 7, the second dummy trench 70 is unevenly distributed in the diode region 20B of the boundary region 20C, and the trench gate 50 is provided in the IGBT region 20A of the boundary region 20C.

[0036] As shown in the examples in Figures 6 and 7, it is not necessary for only the second dummy trench 70 to be provided in the boundary portion 20C; a trench gate 50 and a first dummy trench 60 may also be provided in the boundary portion 20C as needed. If multiple second dummy trenches 70 are provided in at least a portion of the boundary portion 20C, the same effects and advantages as those of the semiconductor device 1 described above can be achieved.

[0037] Furthermore, the multiple second dummy trenches 70 may be positioned between the trench gate 50 and the first dummy trench 60, or they may not be positioned between the trench gate 50 and the first dummy trench 60. For example, as shown in Figure 8, the first dummy trench 60 may be provided in the IGBT region 20A adjacent to the boundary 20C.

[0038] The features of the technology disclosed herein are summarized below. Note that the technical elements described below are independent elements that exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

[0039] (Feature 1) A semiconductor substrate (10) including an IGBT region (20A) and a diode region (20B), The lower electrode (44) is provided on the lower surface (10b) of the semiconductor substrate, The upper electrode (42) provided on the upper surface (10a) of the semiconductor substrate, A plurality of trench gates (50) extending from the upper surface toward the deeper part of the semiconductor substrate located in the IGBT region, A plurality of first dummy trenches (60) extending from the upper surface toward the depths of the semiconductor substrate located in the diode region, The semiconductor substrate is located at the boundary (20C) between the IGBT region and the diode region and comprises a plurality of second dummy trenches (70) extending from the upper surface toward the deeper part of the semiconductor substrate. Each of the plurality of second dummy trenches is spaced apart from one another along the direction connecting the IGBT region and the diode region. A semiconductor device wherein each of the plurality of second dummy trenches has a deep portion (76) formed to be deeper than the plurality of trench gates and the plurality of first dummy trenches, at least in part thereof.

[0040] (Feature 2) The semiconductor device according to feature 1, wherein the plurality of second dummy trenches are provided between the plurality of trench gates and the plurality of first dummy trenches.

[0041] (Feature 3) Some of the multiple second dummy trenches are located in the IGBT region within the boundary, The semiconductor device according to feature 1 or 2, wherein the other second dummy trenches among the plurality of second dummy trenches are located in the diode region of the boundary portion.

[0042] (Feature 4) The semiconductor device according to any one of features 1 to 3, wherein each of the plurality of second dummy trenches is configured such that the whole is deeper than the plurality of trench gates and the plurality of first dummy trenches.

[0043] (Feature 5) The semiconductor device according to any one of features 1 to 3, wherein each of the plurality of second dummy trenches is configured such that a portion of it is deeper than the plurality of trench gates and the plurality of first dummy trenches.

[0044] (Feature 6) The semiconductor device according to any one of claims 1 to 5, wherein the deep portion of each of the plurality of second dummy trenches has a trench width wider than the trench width of the plurality of trench gates and the plurality of first dummy trenches.

[0045] (Feature 7) It further includes a connecting dummy trench (80) extending between adjacent second dummy trenches, The semiconductor device according to feature 5, wherein the deep portion of each of the plurality of second dummy trenches is located in a portion that connects to the connecting dummy trench.

[0046] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of symbols]

[0047] 1,2,3: Semiconductor device, 10: Semiconductor substrate, 20A: IGBT region, 20B: Diode region, 20C: Boundary region, 50: Trench gate, 60: First dummy trench, 70: Second dummy trench, 80: Connecting dummy trench

Claims

1. A semiconductor substrate (10) including an IGBT region (20A) and a diode region (20B), The lower electrode (44) is provided on the lower surface (10b) of the semiconductor substrate, The upper electrode (42) provided on the upper surface (10a) of the semiconductor substrate, A plurality of trench gates (50) extending from the upper surface toward the deeper part of the semiconductor substrate located in the IGBT region, A plurality of first dummy trenches (60) extending from the upper surface toward the depths of the semiconductor substrate located in the diode region, The semiconductor substrate is located at the boundary (20C) between the IGBT region and the diode region and comprises a plurality of second dummy trenches (70) extending from the upper surface toward the deeper part of the semiconductor substrate. Each of the plurality of second dummy trenches is spaced apart from each other along the direction connecting the IGBT region and the diode region. Each of the plurality of second dummy trenches has, at least a portion thereof, a deep portion (76) formed to be deeper than the plurality of trench gates and the plurality of first dummy trenches. Some of the aforementioned plurality of second dummy trenches are located in the IGBT region within the boundary area. A semiconductor device in which, among the plurality of second dummy trenches, the other second dummy trenches are located in the diode region of the boundary.

2. The semiconductor device according to claim 1, wherein the plurality of second dummy trenches are provided between the plurality of trench gates and the plurality of first dummy trenches.

3. The semiconductor device according to claim 1, wherein each of the plurality of second dummy trenches is configured such that its entirety is deeper than the plurality of trench gates and the plurality of first dummy trenches.

4. The semiconductor device according to claim 1, wherein each of the plurality of second dummy trenches is configured such that a portion of it is deeper than the plurality of trench gates and the plurality of first dummy trenches.

5. The semiconductor device according to any one of claims 1 to 4, wherein each of the plurality of second dummy trenches has a trench width wider than the trench width of the plurality of trench gates and the plurality of first dummy trenches.

6. It further includes a connecting dummy trench (80) extending between adjacent second dummy trenches, The semiconductor device according to claim 4, wherein the deep portion of each of the plurality of second dummy trenches is located in a portion that connects to the connecting dummy trench.

7. A semiconductor substrate (10) including an IGBT region (20A) and a diode region (20B), The lower electrode (44) is provided on the lower surface (10b) of the semiconductor substrate, The upper electrode (42) provided on the upper surface (10a) of the semiconductor substrate, A plurality of trench gates (50) extending from the upper surface toward the deeper part of the semiconductor substrate located in the IGBT region, A plurality of first dummy trenches (60) extending from the upper surface toward the depths of the semiconductor substrate located in the diode region, A plurality of second dummy trenches (70) extending from the upper surface toward the depths of the semiconductor substrate located at the boundary (20C) between the IGBT region and the diode region, It includes a connecting dummy trench (80) extending between adjacent second dummy trenches, Each of the plurality of second dummy trenches is spaced apart from each other along the direction connecting the IGBT region and the diode region. Each of the plurality of second dummy trenches has a deep portion (76) in which a part of it is formed to be deeper than the plurality of trench gates and the plurality of first dummy trenches. A semiconductor device wherein the deep portion of each of the plurality of second dummy trenches is located in a portion that connects to the connecting dummy trench.

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