Silicon carbide semiconductor equipment

Abstract

To provide a silicon carbide semiconductor device that makes it possible to easily connect n-type regions and p-type regions adjacent in the depth direction.SOLUTION: A drift layer 2 is formed by sequentially stacking first to third partial parallel pn layers 51 to 53. The first and third partial parallel pn layers 51 and 53 are trench-buried parallel pn layers. The second partial parallel pn layer 52 is a multi-stage epitaxial parallel pn layer, and its thickness t2 is thin, about 0.65 μm±0.05 μm. The n-type regions 62 and 67 of the first and third partial parallel pn layers 51 and 53 are connected to each other, and the p-type regions 63 and 68 of the first and third partial parallel pn layers 51 and 53 are connected to each other, and the n-type regions 64 of the second partial parallel pn layer 52 are connected to each other, and the p-type regions of the second partial parallel pn layer 52 are connected to each other. The stripe shape of the n-type regions 62 and 67 and the p-type regions 63 and 68 of the first and third partial parallel pn layers 51 and 53 intersects with the stripe shape of the n-type region 64 and the p-type region of the second partial parallel pn layer 52 at an angle of 45 degrees or more.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This invention relates to a silicon carbide semiconductor device. [Background technology]

[0002] Conventionally, superjunction semiconductor devices equipped with a superjunction (SJ) structure have been known, in which the drift layer is a parallel pn layer formed by alternately arranging n-type regions and p-type regions with increased impurity concentrations adjacent to each other in a direction parallel to the main surface of the semiconductor substrate. To form the drift layer of the SJ structure, multi-epitaxial or trench-embedded epitaxial methods are used.

[0003] In forming an SJ structure, the multi-stage epitaxial method involves gradually thickening an n-type epitaxial layer through multiple stages of epitaxial growth until it reaches a predetermined thickness, and repeatedly performing ion implantation to selectively form p-type regions after each stage of epitaxial growth. In the trench-filled epitaxial method, a trench is formed in an n-type epitaxial layer that has reached a predetermined thickness through a single stage of epitaxial growth, and the inside of the trench is filled with a p-type epitaxial layer.

[0004] In high-voltage superjunction semiconductor devices using silicon carbide (SiC) as the semiconductor material, the thickness of the drift layer needs to be increased. For this reason, it is easier to manufacture the device using a trench-embedded epitaxial method, in which the epitaxial layer that will serve as the drift layer is grown to the desired thickness in a single stage of epitaxial growth, and then the trench is filled with epitaxial growth after the trench is formed, rather than using a multi-stage epitaxial method in which the epitaxial layer that will serve as the drift layer is gradually thickened to the desired thickness by multiple stages of epitaxial growth.

[0005] In the trench-embedded epitaxial method, a trench is formed in the n-type epitaxial layer that serves as the drift layer, and a p-type epitaxial layer is embedded inside the trench to create an SJ structure. The thicker the drift layer, the deeper the trench needs to be formed, making it difficult to form the trench by etching (hereinafter referred to as trench etching) and to completely fill the inside of the trench with the epitaxial layer.

[0006] The reason why trench etching becomes more difficult with thicker drift layers is that trench etching is anisotropic dry etching. As the trench depth increases, it becomes more difficult to form a good trench shape with side walls approximately perpendicular to the main surface of the semiconductor substrate using dry etching, and the trench width tends to be wider near the top of the opening and narrower near the bottom (bottom of the opening). In addition, the roughness (differences in height of unevenness) of the trench side walls tends to increase.

[0007] In addition, the oxide film (SiO2 film) used as a trench etching mask needs to be formed with sufficient thickness so that it does not disappear during dry etching. This makes the formation of the oxide film used as a trench etching mask, and the dry etching process to selectively remove the oxide film and open up the area corresponding to the trench formation region, difficult. Furthermore, there are problems such as increased stress on the semiconductor substrate due to the oxide film.

[0008] Furthermore, the deeper the trench, the higher the aspect ratio of the trench (= trench depth / trench width), which increases the epitaxial growth time. In addition, the epitaxial layers that grow epitaxially on both side walls of the trench connect near the top of the trench opening, blocking the top of the trench opening and preventing the epitaxial layer from being embedded, making it easy for voids (cavities) to form inside the trench.

[0009] For these reasons, in high-voltage superjunction semiconductor devices using silicon carbide as a semiconductor material, it is difficult to make almost the entire drift layer a SJ structure in the depth direction (hereinafter referred to as a full SJ structure). Therefore, it has been more practical to make only the portion of the drift layer on the front side of the semiconductor substrate a SJ structure (hereinafter referred to as a partial SJ structure). The structure of a conventional superjunction semiconductor device with a partial SJ structure will now be described. Figure 22 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device.

[0010] The conventional silicon carbide semiconductor device 110 shown in Figure 22 is a planar gate superjunction MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a planar gate structure and a drift layer 102 with a partial SJ structure on a semiconductor substrate 120 made of silicon carbide. The semiconductor substrate 120 is n + It is formed by sequentially stacking epitaxial layers 122 to 124 on a mold starting substrate 121. + The starting substrate 121 is n + This is the type drain region 101.

[0011] The epitaxial layers 122 and 123 constitute the drift layer 102 with a partial SJ structure. - The type epitaxial layer 122 is the drain-side portion of the drift layer 102 and occupies more than half of the thickness of the drift layer 102. - The type epitaxial layer 122 is a normal n structure, not an SJ structure. - This is the drift region 102a. When an SJ structure is formed using the trench-embedded epitaxial method, the trench depth of the SJ structure is limited to 20 μm to 25 μm, although this is related to the trench width and the embedding during epitaxial growth.

[0012] Thus, because there is a limit to the trench depth of the SJ structure using the trench-embedded epitaxial method, if the thickness of the drift layer 102 is 65 μm, then if the SJ structure trench is 20 μm to 25 μm deep, then a normal n without an SJ structure will be limited. -The thickness of the type drift region 102a is about 40 to 45 μm. The epitaxial layer 123 is a parallel pn layer 105 in which the n-type region 103 and the p-type region 104 are alternately repeated adjacent to each other in a direction parallel to the main surface of the semiconductor substrate 120, and is a portion on the source side of the drift layer 102.

[0013] Inside the n-type epitaxial layer 124, a p-type base region 106 is selectively provided adjacent to the p-type region 104 in the depth direction. The portion of the n-type epitaxial layer 124 excluding the p-type base region 106 is the JFET (Junction FET) region 109. Reference numerals 107, 108, 111 to 115 are n + type source region, p + type contact region, gate insulating film, gate electrode, interlayer insulating film, source electrode and drain electrode.

[0014] As a method for forming a conventional SJ structure, a p-type epitaxial layer is epitaxially grown by introducing a gas containing a p-type dopant and an n-type dopant having a different atomic position from the p-type dopant to be incorporated, so that the aspect ratio formed in the n-type epitaxial layer is high (3 or more and 15 or less). A method of embedding a p-type epitaxial layer having a uniform carrier concentration distribution without voids inside the trench has been proposed (see, for example, Patent Document 1 below).

Prior Art Documents

Patent Documents

[0015]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0016] In superjunction semiconductor devices, the on-resistance reduction effect of the SJ structure increases with higher voltage ratings, but achieving high voltage ratings requires increasing the thickness of the drift layer. However, as mentioned above, increasing the thickness of the drift layer makes it difficult to make it a full SJ structure. Furthermore, if the drift layer is made a partial SJ structure, the on-resistance reduction effect of the SJ structure is lower compared to a full SJ structure. For example, in a 6.5kV class superjunction semiconductor device, the thickness of the drift layer is about 65μm, so if the drift layer is to be made a full SJ structure, the following specific problems arise.

[0017] When creating a full SJ structure from a drift layer of the above thickness using a multi-stage epitaxial method, dozens of stages of epitaxial growth are required to reach the desired thickness of the epitaxial layer that will become the drift layer. Even if the total number of epitaxial growth stages is reduced by increasing the thickness of each stage of epitaxial growth, and ion implantation is performed repeatedly after each stage of epitaxial growth using an ion implanter capable of achieving high acceleration energies of several MeV, it is not practical to form a full SJ structure using a multi-stage epitaxial method.

[0018] On the other hand, when creating a full SJ structure for a drift layer of the above thickness using the trench-embedded epitaxial method, it is extremely difficult to create a full SJ structure for the drift layer because it requires the formation of a trench with a high aspect ratio at a depth of about 60 μm, and extremely difficult epitaxial growth to completely fill the inside of the trench with the epitaxial layer. For this reason, in order to perform trench etching and epitaxial growth without problems, the width of the trench must inevitably be increased.

[0019] When the trench width is increased, the rate at which the epitaxial layer is embedded into the trench decreases, requiring a longer time to form the SJ structure. Furthermore, if the trench is too wide, the epitaxial layer can only be formed along the inner wall of the trench, making it impossible to completely fill the inside of the trench with the epitaxial layer, thus increasing the challenges of the epitaxial layer embedding technique. In addition, as the trench width increases, the repeating pitch between the n-type and p-type regions of the parallel pn layer widens, reducing the on-resistance reduction effect of the SJ structure.

[0020] Thus, whether using the multi-stage epitaxial method or the trench-embedded epitaxial method, the formation of the SJ structure becomes difficult, and the characteristics of the superjunction semiconductor device also deteriorate.

[0021] The objective of this invention is to provide a silicon carbide semiconductor device that enables easy connection of adjacent n-type regions and p-type regions in the depth direction. [Means for solving the problem]

[0022] Furthermore, in order to solve the above-mentioned problems and achieve the objectives of the present invention, the silicon carbide semiconductor device according to this invention comprises an epitaxial layer made of silicon carbide, including a main surface, on which a drift layer and an element structure are provided on the drift layer. The element structure has a p-type base region, a trench provided on the main surface, and a first p-type semiconductor region with a higher impurity concentration than the base region, provided between the base region and the drift layer and facing the bottom surface of the trench in the depth direction. The drift layer has a first p-type region of parallel pn layers formed inside the drift layer. The first semiconductor region is terminated inside the first p-type region. [Effects of the Invention]

[0023] The silicon carbide semiconductor device according to the present invention has the effect of making it possible to easily connect adjacent n-type regions and p-type regions in the depth direction. [Brief explanation of the drawing]

[0024] [Figure 1] This is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. [Figure 2] This is a cross-sectional view showing the cross-sectional structure along the cutting line A-A' in Figure 1. [Figure 3] Figure 2 is a plan view showing an example of the layout of the drift layer of the SJ structure as seen from the front side of the semiconductor substrate. [Figure 4] Figure 2 is a plan view showing an example of the layout of the drift layer of the SJ structure as seen from the front side of the semiconductor substrate. [Figure 5] This is a flowchart illustrating the manufacturing method of a silicon carbide semiconductor device according to Embodiment 1. [Figure 6] This is a cross-sectional view showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 7] This is a cross-sectional view showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 8] This is a cross-sectional view showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 9] This is a cross-sectional view showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 10] This is a cross-sectional view showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 11] This is a cross-sectional view showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 12] This is a cross-sectional view showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 13] This is a cross-sectional view showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 14] This is a cross-sectional view showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 15]This is a cross-sectional view showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 16] This is a cross-sectional view showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 17] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 2. [Figure 18] This is a cross-sectional view showing the silicon carbide semiconductor device according to Embodiment 2 in the process of manufacturing. [Figure 19] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 3. [Figure 20] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 4. [Figure 21] This is a characteristic diagram showing the doping concentration in the ion implantation region of a multi-stage epitaxially parallel pn layer. [Figure 22] This is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. [Modes for carrying out the invention]

[0025] Preferred embodiments of the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. In the following description of embodiments and accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted. In Miller index notation, "-" indicates a bar attached to the exponent immediately following it, and placing "-" before an exponent indicates a negative exponent.

[0026] (Embodiment 1) The structure of the silicon carbide semiconductor device according to Embodiment 1 will be described using a trench gate superjunction MOSFET as an example. Figure 1 is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. Figure 2 is a cross-sectional view showing the cross-sectional structure along the cutting line A-A' in Figure 1. Figure 2 shows the distance from the outermost unit cell (chip edge side) of the multiple unit cells (constituent units of the element) arranged in the active region 10 to the chip edge (edge ​​of the semiconductor substrate 40).

[0027] Figures 3 and 4 are plan views showing an example of the layout of the drift layer 2 of the superjunction (SJ) structure in Figure 2 as seen from the front side of the semiconductor substrate. Figures 3 and 4 (a) to (c) show the layout of the SJ structure at the cutting lines B-B', C-C', and D-D' in Figure 2, respectively. In Figure 3, the number of p-type regions 63, 65, and 68 of the first to third partially parallel pn layers 51 to 53 is simplified and shown with fewer numbers than in Figure 2, the n-type regions 62, 64, and 67 are shown with dot hatching, and the p-type region 65 is shown with diagonal hatching (the same applies to Figure 4).

[0028] The silicon carbide semiconductor device 50 according to Embodiment 1 shown in Figure 1 is a superjunction MOSFET comprising an active region 10, an intermediate region 20, and an edge termination region 30 on a semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC), with substantially the entire drift layer 2 having an SJ structure (full SJ structure) in the depth direction Z from the active region 10 to the edge termination region 30. A full SJ structure of the drift layer 2 means that an SJ structure is formed on the source side of the drift layer 2 with a thickness t5 that is, for example, 80% or more of the total thickness t4 of the drift layer 2.

[0029] A semiconductor element having a predetermined element structure is placed in the active region 10. The active region 10 is the region through which the main current flows when the semiconductor element is in the ON state. The intermediate region 20 is the region between the active region 10 and the edge termination region 30, and is adjacent to the active region 10, surrounding it. The edge termination region 30 is the region between the intermediate region 20 and the edge of the semiconductor substrate 40, and surrounds the active region 10 via the intermediate region 20, mitigating the electric field on the front side of the semiconductor substrate 40 and maintaining the breakdown voltage. Breakdown voltage is the limit voltage at which the semiconductor device will not malfunction or be destroyed.

[0030] In the edge termination region 30, a breakdown voltage structure such as a junction termination extension (JTE) structure 34, a field limiting ring (FLR), or a field plate (FP) is arranged on the front side of the semiconductor substrate 40. Alternatively, one of the JTE structures may be a breakdown voltage structure with a spatial modulation structure, where multiple p-type high-concentration impurity regions and p-type low-concentration impurity regions are alternately combined while varying their widths. Figure 2 illustrates the case where the JTE structure 34 is arranged on the front side of the semiconductor substrate 40 in the edge termination region 30.

[0031] In the active region 10, a vertical MOSFET with a general trench gate structure is arranged as a semiconductor element having a predetermined element structure. The trench gate structure consists of a p-type base region 4 provided on the front side of the semiconductor substrate 40, n + Type source area 5, p ++ It consists of a type contact region 6, a gate trench 7, a gate insulating film 8, and a gate electrode (conductive layer) 9. The semiconductor substrate 40 is made of silicon carbide n + The material is formed by sequentially depositing a drift layer 2, an n-type current diffusion region 3, and p-type base region 4, respectively, epitaxial layers 42-44, on the front surface of a starting substrate 41.

[0032] With the main surface of the semiconductor substrate 40 on the side of the p-type epitaxial layer 44 as the front surface, + Main surface (n) on the mold starting substrate 41 side+ The back surface of the starting substrate 41 is considered the back surface. The crystal plane orientation of the front surface of the semiconductor substrate 40 is, for example, the (0001) plane, the so-called Si plane. + The starting substrate 41 is n + This is a type drain region 1. The gate trench 7 penetrates the p-type epitaxial layer 44 from the front surface of the semiconductor substrate 40 in the depth direction Z, and n - It reaches into the epitaxial layer 43 and extends in a stripe-like manner in the second direction Y, for example, as will be described later.

[0033] Between adjacent gate trenches 7, p-type base regions 4 and n are arranged to extend linearly in, for example, the second direction Y. + Type source region 5 and p ++ Each type contact region 6 is selectively provided. The p-type base region 4 extends outward from the active region 10 to the step 31 described later. + Type source region 5 and p ++ The p-type contact region 6 is provided between the front surface of the semiconductor substrate 40 and the p-type base region 4, in contact with the p-type base region 4, and is exposed on the front surface of the semiconductor substrate 40.

[0034] n + The type source region 5 faces the gate electrode 9 via the gate insulating film 8 on the side wall of the gate trench 7. ++ The contact area 6 is n + It is located further from the gate trench 7 than the type source region 5. The n of the p-type epitaxial layer 44 + Type source region 5 and p ++ The portion excluding the contact region 6 is the p-type base region 4. An epitaxial layer 42, which is a drift layer 2 with a full SJ structure, is provided between the p-type base region 4 and the back surface of the semiconductor substrate 40. The configuration of the drift layer 2 with a full SJ structure will be described later.

[0035] An n-type current-diffusing region 3 is provided between the p-type base region 4 and the drift layer 2, in contact with both the p-type base region 4 and the drift layer 2. The n-type current-diffusing region 3 is a so-called current-diffusing layer (CSL) that reduces the carrier spreading resistance. The n-type current-diffusing region 3 is located between adjacent gate trenches 7 and is adjacent to the gate trenches 7. The n-type current-diffusing region 3 extends from the top surface of the semiconductor substrate 40 to a position deeper than the gate trenches 7.

[0036] Inside the n-type current diffusion region 3, p + Type regions 11 to 13 are selectively provided. + The mold region (first semiconductor region) 11 faces the bottom surface of the gate trench 7 in the depth direction Z. + The p-type region 11 is located at a depth from the front surface of the semiconductor substrate 40 that is deeper than the interface between the p-type base region 4 and the n-type current diffusion region 3, and is separated from the p-type base region 4. + Type region 11 is p + It may reach a position deeper on the drain side than the type region 12. The outermost p + Type region 11 (hereinafter, the outermost p + The mold region (referred to as the third semiconductor region) 11a) extends beyond the step 31, which will be described later.

[0037] p + The type region (second semiconductor region) 12 has p between adjacent gate trenches 7. + It is located away from the mold region 11 and the gate trench 7. + The p-type region 12 is in contact with the p-type base region 4. + Type region 13 is the outermost p + It is positioned between the type region 11a and the p-type base region 4, with the outermost part being p in the depth direction Z. + It is in contact with the p-type region 11a and the p-type base region 4. + The mold region 13 extends from the outermost gate trench 7a to the step 31. + The mold regions 11 and 12 have the function of mitigating electric field concentration on the gate insulating film 8 at the bottom surface of the gate trench 7.

[0038] An interlayer insulating film 14 is provided over the entire surface of the front surface of the semiconductor substrate 40 so as to cover the gate electrode 9. The source electrode 15 is connected to the interlayer insulating film 14 through a contact hole. + Type source region 5 and p ++ The source electrode 15 makes ohmic contact with the p-type contact region 6 and is electrically connected to these regions. The source electrode 15 extends outward from the active region 10 and is electrically connected to the p-type base region 4 in the intermediate region 20.

[0039] The source electrode 15 extends from the active region 10 to the intermediate region 20 and terminates inside the gate metal wiring 22 (towards the center of the chip), which will be described later, in the intermediate region 20. A barrier metal (not shown) may be provided between the source electrode 15 and the interlayer insulating film 14. The barrier metal has the function of preventing atomic diffusion and interaction between regions facing each other across the barrier metal. The passivation film (not shown) covers the entire surface of the front surface of the semiconductor substrate 40. The portion of the source electrode 15 exposed through the opening in the passivation film becomes the source pad.

[0040] The intermediate region 20 is located outside the center of the outermost gate trench 7a in the first direction X parallel to the front surface of the semiconductor substrate 40, and in the second direction Y parallel to the front surface of the semiconductor substrate 40 and perpendicular to the first direction X. + This region extends from the part outside the edge of the mold source region 5 to the step 31. In the intermediate region 20, in the part outside the source electrode 15, an insulating layer is formed by sequentially stacking a field oxide film 36 and an interlayer insulating film 14 on the first surface 40a of the front surface of the semiconductor substrate 40, which will be described later, starting from the edge termination region 30 side.

[0041] The intermediate region 20 contains a gate runner 21 and gate metal wiring 22. The gate runner 21 is provided on the first surface 40a of the front surface of the semiconductor substrate 40 via a field oxide film 36, and is connected to the gate electrode 9 and gate pad (not shown) in parts not shown, thereby electrically connecting the gate electrode 9 and gate pad. The gate runner 21 is covered with an interlayer insulating film 14. The gate metal wiring 22 is electrically connected to the gate runner 21 via contact holes opened in the interlayer insulating film 14.

[0042] In the edge termination region 30, for example, by removing the p-type epitaxial layer 44 over the entire edge termination region 30, a step 31 is formed on the front surface of the semiconductor substrate 40, where the edge termination region 30 is lower (recessed towards the drain side) than the portion 40a on the active region 10 side (hereinafter referred to as the first surface). As a result of the formation of the step 31, the portion 40b of the front surface of the semiconductor substrate 40 outside the step 31 (hereinafter referred to as the second surface) contains n - The type epitaxial layer 43 is exposed.

[0043] On the active region 10 side of the second surface 40b of the front surface of the semiconductor substrate 40, the outermost p + The type region 11a is exposed. The portion 40c of the front surface of the semiconductor substrate 40 between the first surface 40a and the second surface 40b (the mesa edge of the step 31: hereinafter referred to as the third surface) contains the p-type base region 4 and p + The mold region 13 is exposed. Exposure on the second and third surfaces 40b and 40c of the front surface of the semiconductor substrate 40 means that it is located in the surface region of the second and third surfaces 40b and 40c of the front surface of the semiconductor substrate 40 and is in contact with the field oxide film 36 on the second and third surfaces 40b and 40c.

[0044] Furthermore, the surface area of ​​the second surface 40b on the front surface of the semiconductor substrate 40 has the outermost p + A JTE structure 34 is provided outside the mold region 11a. The JTE structure 34 is located on the outermost p +This pressure-resistant structure has multiple p-type regions (two in this case; hereafter referred to as the first and second JTE regions 32 and 33 from the active region 10 side) arranged adjacent to each other, with a lower impurity concentration than the type region 11a and the impurity concentration decreasing as they are located further outwards. The first and second JTE regions 32 and 33 are, for example, n in the depth direction Z. - It penetrates the type epitaxial layer 43 and reaches the epitaxial layer 42.

[0045] The first JTE region 32 is the outermost p + It is adjacent to the outside of the type region 11a. The second JTE region 33 is adjacent to the outside of the first JTE region 32. The first and second JTE regions 32 and 33 and the n-type region of the most source-side partial parallel pn layer (n-type region 67 of the third partial parallel pn layer 53), described later, form a pn junction, ensuring a predetermined withstand voltage at the edge termination region 30. In addition, on the surface region of the second surface 40b of the front surface of the semiconductor substrate 40, there is an n-type region that is exposed at the edge of the semiconductor substrate 40, away from the JTE structure 34. + A type stopper region 35 is selectively provided.

[0046] Although not shown in the diagram, a region (hereinafter referred to as a spatial modulation region) may be provided between adjacent first and second JTE regions 32 and 33 of the JTE structure 34, where a p-type region with the same impurity concentration as the inner first JTE region 32 and a p-type region with the same impurity concentration as the outer second JTE region 33 are arranged alternately and repeatedly adjacent to each other in a concentric circle surrounding the active region 10. For example, when the withstand voltage is 1.7kV or higher, it is preferable to provide a spatial modulation region in the JTE structure 34.

[0047] JTE structure 34 and n on the second surface 40b of the front surface of the semiconductor substrate 40 + In the portion excluding the type stopper area 35, n - The type epitaxial layer 43 is exposed. The second and third surfaces 40b and 40c of the front surface of the semiconductor substrate 40 are covered with an insulating layer formed by sequentially laminating a field oxide film 36 and an interlayer insulating film 14. The field oxide film 36 extends on the first surface 40a of the front surface of the semiconductor substrate 40 in the intermediate region 20. The back surface (n +A drain electrode 16 is provided across the entire surface of the back surface of the mold starting substrate 41.

[0048] Next, we will describe the configuration of the drift layer 2 (epitaxial layer 42) with a full SJ structure. The drift layer 2 with a full SJ structure is n + The structure consists of three or more parallel pn layers (hereinafter referred to as partial parallel pn layers) stacked continuously on the front surface of the mold starting substrate 41 so that the total thickness t4 of the drift layer 2 is equal to three or more layers. Each partial parallel pn layer is arranged in the same pattern, continuously from the active region 10 to the edge of the chip.

[0049] Each partially parallel pn layer constituting the drift layer 2 has either a full SJ structure formed by a trench-embedded epitaxial method or a full SJ structure formed using a multi-stage epitaxial method. A full SJ structure is a structure in which an SJ structure, in which n-type regions and p-type regions are alternately and repeatedly arranged adjacent to each other in a direction parallel to the surface of the semiconductor substrate 40, extends in the depth direction Z over approximately the entire total thickness t4 of the drift layer 2.

[0050] A partially parallel pn layer formed by the trench-embedded epitaxial method (hereinafter referred to as a trench-embedded parallel pn layer) is formed by creating a trench (hereinafter referred to as an SJ trench) that penetrates the n-type epitaxial layer in the depth direction Z of a thick n-type epitaxial layer formed in one stage (one epitaxial growth), and then filling the inside of the SJ trench with a p-type epitaxial layer.

[0051] A partially parallel pn layer formed using a multi-stage epitaxial method (hereinafter referred to as a multi-stage epitaxial parallel pn layer) is formed by selectively creating p-type regions that penetrate the n-type epitaxial layer in the depth direction Z of a thin n-type epitaxial layer formed by a single-stage epitaxial growth by ion implantation. Crystal defects are introduced into the multi-stage epitaxial parallel pn layer by ion implantation.

[0052] These trench-embedded parallel pn layers and multi-stage epitaxial parallel pn layers are alternately stacked in layers of three or more (three layers in Figure 2: the first to third partial parallel pn layers 51 to 53 described later) to form a drift layer 2 with a full SJ structure. Multi-stage epitaxial parallel pn layers (partial parallel pn layers) are placed adjacent to each other between trench-embedded parallel pn layers (partial parallel pn layers) in the depth direction Z. Both the source side and the drain side of each partial parallel pn layer are trench-embedded parallel pn layers.

[0053] By including a multi-stage epitaxial parallel pn layer in part of the drift layer 2, the minority carrier (hole) lifetime of the drift layer 2 is shortened compared to cases where the drift layer 2 is composed only of trench-embedded parallel pn layers without crystal defects, or when silicon (Si) without introduced crystal defects is used as the semiconductor material. As a result, p ++ Type 6 contact area, p-type base area 4 and p + Type region 11, n-type current diffusion region 3, n-type region of a partially parallel pn layer, n-type drift region 2a and n + The parasitic diode (body diode) formed by the drain region 1 and the pn junction acts as a soft recovery, which reduces the noise during the reverse recovery of the parasitic diode.

[0054] The n-type and p-type regions of the partially parallel pn layers are arranged in stripes extending parallel to the front surface of the semiconductor substrate 40. The stripe shapes of the n-type and p-type regions of the trench-embedded parallel pn layers and the stripe shapes of the n-type and p-type regions of the multi-stage epitaxial parallel pn layers extend in different directions and are not parallel when viewed from the front surface of the semiconductor substrate 40 (in a plan view), but intersect at an angle of, for example, 45 degrees or more, and preferably are orthogonal. This allows adjacent n-type and p-type regions of trench-embedded parallel pn layers in the depth direction Z to be connected via the n-type and p-type regions of the multi-stage epitaxial parallel pn layers, respectively, even if the positions of the n-type and p-type regions are misaligned.

[0055] In both the trench-embedded parallel pn layer and the multi-stage epitaxial parallel pn layer, adjacent n-type and p-type regions in a direction parallel to the front surface of the semiconductor substrate 40 have equal width and are generally charge-balanced. The n-type and p-type regions of the multi-stage epitaxial parallel pn layer have approximately the same impurity concentration as the n-type and p-type regions of the trench-embedded parallel pn layer, respectively. Approximately the same impurity concentration means that the impurity concentration is the same within a range that includes the error that can be tolerated due to process variations. The interface between the trench-embedded parallel pn layer and the multi-stage epitaxial parallel pn layer is a flat surface approximately parallel to the front surface of the semiconductor substrate 40.

[0056] The thickness of the trench-embedded parallel pn layer is sufficiently greater than the thickness of the multi-stage epitaxial parallel pn layer, and the trench-embedded parallel pn layer occupies most of the drift layer 2. For a full SJ structure, the drift layer 2 only needs to have three or more odd-numbered partial parallel pn layers stacked to satisfy the above conditions, and the more stages of partial parallel pn layers there are, the more stages of trench-embedded parallel pn layers that make up the drift layer 2. The more stages of trench-embedded parallel pn layers there are, the thinner the thickness that each trench-embedded parallel pn layer can be relative to the total thickness t4 of the drift layer 2.

[0057] The thinner the trench-embedded parallel pn layer, the shallower the SJ trench can be. This makes trench etching for forming SJ trenches in the trench-embedded parallel pn layer and embedding epitaxial layers into the SJ trenches easier. Therefore, even if the width of the SJ trench is narrowed, the depth of the SJ trench can be made shallower, thus avoiding the process challenges mentioned above when silicon carbide is used as a semiconductor material and enabling the formation of a full SJ structure.

[0058] Hereafter, if the drift layer 2 with a full SJ structure is composed of three partially parallel pn layers, the drift layer 2 with a full SJ structure has the first and third trench-embedded parallel pn layers (first and third partially parallel pn layers 51 and 53) and the second multi-stage epitaxially parallel pn layer (second partially parallel pn layer 52) positioned between these trench-embedded parallel pn layers.

[0059] The first partially parallel pn layer 51 is a trench-embedded parallel pn layer. The first partially parallel pn layer 51 is made up of n-type regions 62 and p-type regions 63 arranged alternately and repeatedly adjacent to each other in the first direction X. The n-type regions 62 and p-type regions 63 extend linearly in the silicon carbide <11-20> direction, parallel to the second direction Y (Figure 3(a)). As a result, the pn junction surface between the p-type region 63 and the n-type region 62 is a substantially flat surface parallel to the {1-100} plane where a well-crystallinity epitaxial layer initially grows, and is substantially perpendicular to the front surface of the semiconductor substrate 40.

[0060] The first partially parallel pn layer 51 has SJ trenches 61 that penetrate the n-type epitaxial layers constituting the first partially parallel pn layer 51. The aspect ratio of the SJ trenches 61 (= depth of SJ trenches 61 / width of SJ trenches 61) is, for example, between 5 and 15. The n-type region 62 is the portion of the n-type epitaxial layers constituting the first partially parallel pn layer 51 that remains after the formation of the SJ trenches 61. The p-type region 63 is a p-type epitaxial layer embedded inside the SJ trenches 61.

[0061] In the first partially parallel pn layer 51, an n-type region 62 is arranged along the chip edge at the outermost edge of the semiconductor substrate 40. The annular portion of the n-type region 62 along the chip edge, as viewed from the front side of the semiconductor substrate 40, surrounds the central portion of the semiconductor substrate 40 and connects all the linear portions of the n-type region 62. The n-type region 62 and the p-type region 63 have equal width and are roughly charge-balanced. The narrower the width and repeat pitch of the n-type region 62 and the p-type region 63, the greater the on-resistance reduction effect. The drain-side portion of the first partially parallel pn layer 51 may be a normal n-type drift region 2a that does not have an SJ structure.

[0062] The second partially parallel pn layer 52 is a multi-stage epitaxially parallel pn layer and is adjacent to the source side of the first partially parallel pn layer 51. The second partially parallel pn layer 52 is made up of n-type regions 64 and p-type regions (second p-type regions) 65 arranged alternately adjacent to each other in the second direction Y. The n-type regions 64 and p-type regions 65 extend linearly in the first direction X. When viewed from the front surface of the semiconductor substrate 40, the stripe shape of the n-type regions 64 and p-type regions 65 is orthogonal to the stripe shape of the n-type regions 62 and p-type regions 63 of the first partially parallel pn layer 51 (Figure 3(b)).

[0063] The n-type region 64 is the portion of the n-type epitaxial layer constituting the second partially parallel pn layer 52 that remains after the formation of the p-type region 65. The p-type region 65 is an ion implantation region (diffusion region) selectively formed in the n-type epitaxial layer constituting the second partially parallel pn layer 52, and penetrates the n-type epitaxial layer in the depth direction Z to reach the first partially parallel pn layer 51. The n-type region 64 and the p-type region 65 have the same impurity concentration as the n-type region 62 and the p-type region 63 of the first partially parallel pn layer 51, respectively, and are in contact with the n-type region 62 and the p-type region 63, respectively.

[0064] As described above, when viewed from the front side of the semiconductor substrate 40, the stripe shape of the n-type region 62 and p-type region 63 of the first partially parallel pn layer 51 is not parallel to the stripe shape of the n-type region 64 and p-type region 65 of the second partially parallel pn layer 52. Therefore, at the interface between the first partially parallel pn layer 51 and the second partially parallel pn layer 52, the n-type region 62 and p-type region 63 of the first partially parallel pn layer 51 can be reliably brought into contact with the n-type region 64 and p-type region 65 of the second partially parallel pn layer 52, respectively.

[0065] The thickness of the second partial parallel pn layer 52 is thinner than that of the trench-embedded parallel pn layer, for example, about 0.65 μm ± 0.05 μm. By setting the second partial parallel pn layer 52 to the above thickness, when forming the third partial parallel pn layer 53 on top of the second partial parallel pn layer 52, it is possible to suppress the SJ trenches 66 of the third partial parallel pn layer 53 from penetrating the second partial parallel pn layer 52 in the depth direction Z and reaching the first partial parallel pn layer 51. If the SJ trenches 66 of the third partial parallel pn layer 53 reach the first partial parallel pn layer 51, the n-type region 64 and the p-type region 65 of the second partial parallel pn layer 52 will become charge unbalanced, which is undesirable.

[0066] Furthermore, by setting the second partially parallel pn layer 52 to the above thickness, impurities implanted using a general ion implantation apparatus can reach from the ion implantation surface (one surface) of the epitaxial layer constituting the second partially parallel pn layer 52 to the other surface. In addition, the diffusion region (in this case, the p-type region 65) formed by ion implantation can be formed to a depth that penetrates the epitaxial layer in the depth direction Z, and with a uniform doping concentration in the depth direction Z. A uniform impurity concentration means that the impurity concentration is approximately the same within a range that includes the error that can be tolerated due to process variations.

[0067] Furthermore, in the second partially parallel pn layer 52, an n-type region 64 is arranged along the chip edge at the outermost edge of the semiconductor substrate 40. The annular portion of the n-type region 64 along the chip edge, as viewed from the front side of the semiconductor substrate 40, surrounds the central portion of the semiconductor substrate 40, connects all the linear portions of the n-type region 64, and is in contact with the annular portion of the n-type region 62 of the first partially parallel pn layer 51 along the chip edge, as viewed from the front side of the semiconductor substrate 40, in the depth direction Z. The n-type region 64 and the p-type region 65 have equal widths and are roughly charge-balanced. The narrower the width and repeat pitch of the n-type region 64 and the p-type region 65, the greater the on-resistance reduction effect.

[0068] The third partially parallel pn layer 53 is a trench-embedded parallel pn layer and is adjacent to the source side of the second partially parallel pn layer 52. The third partially parallel pn layer 53 has the same layout as the n-type region 62 and p-type region 63 of the first partially parallel pn layer 51, with n-type region (first n-type region) 67 and p-type region (first p-type region) 68 arranged alternately and repeatedly adjacent to each other in the first direction X. Therefore, the stripe shape of the n-type region 67 and p-type region 68 is orthogonal to the stripe shape of the n-type region 64 and p-type region 65 of the second partially parallel pn layer 52 (Figure 3(c)).

[0069] The third partially parallel pn layer 53 has an SJ trench 66 that penetrates the n-type epitaxial layer constituting the third partially parallel pn layer 53. The bottom surface of the SJ trench 66 reaches the drain side beyond the interface between the third partially parallel pn layer 53 and the second partially parallel pn layer 52 and terminates inside the second partially parallel pn layer 52. It is preferable that the SJ trench 66 faces the SJ trench 61 of the first partially parallel pn layer 51. The aspect ratio of the SJ trench 66 (= depth of SJ trench 66 / width of SJ trench 66) is, for example, 5 or more and 15 or less.

[0070] The n-type region 67 is the portion of the n-type epitaxial layer constituting the third partially parallel pn layer 53 that remains after the formation of the SJ trench 66. The n-type region 67 is adjacent to the n-type region 64 of the second partially parallel pn layer 52 and is connected to the n-type region 62 of the first partially parallel pn layer 51 via the n-type region 64. The p-type region 68 is a p-type epitaxial layer embedded inside the SJ trench 66. The p-type region 68 is adjacent to the p-type region 65 of the second partially parallel pn layer 52 and is connected to the p-type region 63 of the first partially parallel pn layer 51 via the p-type region 65.

[0071] As described above, when viewed from the front side of the semiconductor substrate 40, the stripe shape of the n-type region 64 and p-type region 65 of the second partially parallel pn layer 52 is not parallel to the stripe shape of the n-type region 67 and p-type region 68 of the third partially parallel pn layer 53. Therefore, at the interface between the second partially parallel pn layer 52 and the third partially parallel pn layer 53, the n-type region 64 and p-type region 65 of the second partially parallel pn layer 52 can be reliably brought into contact with the n-type region 67 and p-type region 68 of the third partially parallel pn layer 53, respectively.

[0072] Furthermore, as described above, since the bottom surface of the SJ trench 66 terminates inside the second partially parallel pn layer 52, the p-type region 68 and the p-type region 65 of the second partially parallel pn layer 52 can be reliably brought into contact. The n-type region 67 and the p-type region 68 have the same impurity concentration as the n-type region 62 and the p-type region 63 of the first partially parallel pn layer 51, respectively. The n-type region 67 and the p-type region 68 have equal widths and are roughly charge-balanced. The narrower the width and repeat pitch of the n-type region 67 and the p-type region 68, the greater the on-resistance reduction effect.

[0073] In this way, the n-type region 62 of the first partially parallel pn layer 51 and the n-type region 67 of the third partially parallel pn layer 53 are connected in the depth direction Z via the n-type region 64 of the second partially parallel pn layer 52. The p-type region 63 of the first partially parallel pn layer 51 and the p-type region 68 of the third partially parallel pn layer 53 are connected in the depth direction Z via the p-type region 65 of the second partially parallel pn layer 52. These first to third partially parallel pn layers 51 to 53 are stacked in order to form a drift layer 2 with a full SJ structure.

[0074] Furthermore, as described above, the trench-embedded parallel pn layers and the multi-stage epitaxial parallel pn layers only need to be arranged so that the stripe shapes of the n-type and p-type regions are not parallel to each other, and the layout of the n-type and p-type regions of the first to third partial parallel pn layers as viewed from the front side of the semiconductor substrate 40 can be changed in various ways. In order to form the trench-embedded parallel pn layers, the degree of epitaxial growth of the p-type epitaxial layer inside the SJ trench depends on the properties of the crystal plane orientation of the side wall of the SJ trench.

[0075] For example, as shown in Figure 4, the n-type regions 62', 67' and p-type regions 63', 68' of the first and third partially parallel pn layers 51', 53' are made into stripe shapes extending in the <1-100> direction of silicon carbide, parallel to the second direction Y'. The n-type region 64' and p-type region 65' of the second partially parallel pn layer 52' ​​are made into stripe shapes extending parallel to the first direction X'. The layout of the n-type region 67' and p-type region 68' of the third partially parallel pn layer 53' is the same as that of the n-type region 62' and p-type region 63' of the first partially parallel pn layer 51', respectively.

[0076] In the first and third partially parallel pn layers 51' and 53', the pn junction surfaces between the p-type regions 63' and 68' and the n-type regions 62' and 67' have a predetermined slope with respect to the side walls of the SJ trenches 61' and 66', based on the properties of the {11-20} surfaces that form the side walls of the SJ trenches 61' and 66' when the p-type epitaxial layers that become the p-type regions 63' and 68' are embedded in the SJ trenches 61' and 66'. When the first to third partially parallel pn layers 51' to 53' shown in Figure 4 are designated as drift layer 2, the cross-sectional view in Figure 2 is obtained by changing the first and second directions X and Y to the first and second directions X' and Y'.

[0077] Next, a method for manufacturing the silicon carbide semiconductor device 50 according to Embodiment 1 will be described. Figure 5 is a flowchart showing an overview of the method for manufacturing the silicon carbide semiconductor device according to Embodiment 1. Figures 6 to 16 are cross-sectional views showing the silicon carbide semiconductor device during manufacturing according to Embodiment 1. Figures 6 to 8 and 11 to 16 are cross-sections perpendicular to the second direction Y of the active region 10 (see Figure 2), and Figures 9 and 10 are cross-sections perpendicular to the first direction X of the active region 10.

[0078] First, both sides are chemically mechanically polished (CMP). + The starting substrate (semiconductor wafer) 41 is cleaned, for example, by organic cleaning and RCA cleaning. +The starting substrate 41 may, for example, have a crystalline structure of silicon carbide with a four-layer periodic hexagonal structure (4H-SiC), and its front surface may be the (0001) plane, also known as the Si plane. + The starting substrate 41 is n + This becomes type drain region 1.

[0079] Next, as shown in Figure 6, using a chemical vapor deposition (CVD) apparatus, n + An n-type epitaxial layer 201 is epitaxially grown (formed) on the front surface of the mold starting substrate 41 as part of the epitaxial layer 42 (drift layer 2) (step S1). The thickness t1 and impurity concentration of the n-type epitaxial layer 201 are, for example, about 40 μm and 1 × 10⁻¹⁶, respectively. 16 / cm 3 It is to that extent.

[0080] Next, the epitaxial substrate (n + The epitaxial substrate (in which an n-type epitaxial layer 201 is laminated on a molded starting substrate 41) is cleaned, for example, by organic cleaning and RCA cleaning. Next, an oxide (SiO2) film 211 is formed on the surface of the n-type epitaxial layer 201 to a thickness of, for example, about 6 μm using, for example, a plasma chemical vapor deposition (PCVD) apparatus.

[0081] Next, a resist film 212 is formed on the surface of the oxide film 211 by photolithography, with openings in areas corresponding to the formation regions of the SJ trenches 61. The opening pattern of the resist film 212 is stripe-shaped, extending in the second direction Y. The opening width w11 and the remaining width w12 between adjacent openings of the stripe-shaped opening pattern of the resist film 212 are both approximately 2.5 μm.

[0082] Next, the oxide film 211 is dry-etched using the resist film 212 as a mask, leaving the oxide film 211 with the same stripe-shaped opening pattern as the resist film 212. This opens up the portion of the oxide film 211 corresponding to the formation region of the SJ trench 61 in the first partially parallel pn layer 51. Then, the resist film 212 is removed.

[0083] Next, as shown in Figure 7, the n-type epitaxial layer 201 is dry-etched using the remainder of the oxide film 211 as a mask to form SJ trenches 61 (step S2). The depth d1 of the SJ trenches 61 is, for example, about 30 μm. The portion of the n-type epitaxial layer 201 remaining between adjacent SJ trenches 61 becomes the n-type region 62 of the first partially parallel pn layer 51. Then, the remainder of the oxide film 211 is removed, for example, with hydrofluoric acid (HF).

[0084] The n-type epitaxial layer 201 is n-type, and the n-type epitaxial layer + The portion on the starting substrate 41 side becomes a normal n-type drift region 2a that is not an SJ structure. Before forming the n-type epitaxial layer 201 in the process of step S1, + Another n-type epitaxial layer (not shown) that forms an n-type buffer region may be formed on the front surface of the mold starting substrate 41. In this case, during the process in step S2, an SJ trench 61 may be formed that penetrates the n-type epitaxial layer 201 in the depth direction Z and reaches the n-type buffer region.

[0085] Next, as shown in Figure 8, the epitaxial substrate is cleaned by, for example, organic cleaning and RCA cleaning. Then, the inside of the SJ trench 61 is filled with a p-type epitaxial layer 202 that has been epitaxially grown (formed) using a CVD apparatus (step S3). In the process of step S3, an excess p-type epitaxial layer 202 is also epitaxially grown on the surface of the n-type epitaxial layer 201 so as to protrude above the SJ trench 61.

[0086] The p-type epitaxial layer 202 may be epitaxially grown by hydride vapor phase epitaxy (HVPE) using a mixed gas obtained by adding hydrogen chloride (HCl) gas, a hydrogen compound, to a source gas containing a dopant such as aluminum (Al). The impurity concentration of the p-type epitaxial layer 202 is, for example, 1 × 10⁻⁶. 16 / cm 3It is to that extent.

[0087] Next, by grinding and polishing, the excess p-type epitaxial layer 202 located above the surface of the n-type epitaxial layer 201 is removed, leaving the p-type epitaxial layer 202 only inside the SJ trench 61 (step S4). The portion of the p-type epitaxial layer 202 remaining inside the SJ trench 61 becomes the p-type region 63 of the first partially parallel pn layer 51.

[0088] Next, the surfaces of the n-type epitaxial layer 201 and the p-type epitaxial layer 202 are planarized by CMP (step S5). This forms a first partially parallel pn layer 51 (see Figure 3(a)) as the first partially parallel pn layer constituting the drift layer 2, in which the n-type epitaxial layer 201 and the p-type epitaxial layer 202 are configured as n-type region 62 and p-type region 63, respectively.

[0089] Next, as shown in Figure 9, an n-type epitaxial layer 203 is epitaxially grown (formed) on the first partially parallel pn layer 51 as part of the epitaxial layer 42 (drift layer 2) using a CVD apparatus (step S6). The thickness t2 of the n-type epitaxial layer 203 is, for example, about 0.65 μm. The impurity concentration of the n-type epitaxial layer 203 is approximately the same as the impurity concentration of the n-type epitaxial layer 201.

[0090] Next, the epitaxial substrate (n + An epitaxial substrate (in which a first partially parallel pn layer 51 and an n-type epitaxial layer 203 are sequentially laminated on a molded starting substrate 41) is cleaned, for example, by organic cleaning and RCA cleaning. Next, an oxide film 213 is formed on the surface of the n-type epitaxial layer 203 to a thickness of, for example, about 2 μm using, for example, a PCVD apparatus.

[0091] Next, a resist film 214 is formed on the surface of the oxide film 213 by photolithography, with openings in the areas corresponding to the formation regions of the p-type regions 65 of the second partially parallel pn layer 52. The opening pattern of the resist film 214 is stripe-like, extending in a first direction X perpendicular to the opening pattern of the resist film 212 used to form the first partially parallel pn layer 51, and both the opening width w13 and the remaining width w14 between adjacent openings are, for example, about 2.5 μm.

[0092] Next, as shown in Figure 10, the oxide film 213 is dry-etched using the resist film 214 as a mask, leaving the oxide film 213 with the same stripe-shaped opening pattern as the resist film 214. This opens up the portion of the oxide film 213 corresponding to the formation region of the p-type region 65 of the second partially parallel pn layer 52. Then, the resist film 214 is removed. As mentioned above, only Figures 9 and 10 show the cross-sectional shape in a cross section perpendicular to the first direction X.

[0093] Next, using the remainder of the oxide film 213 as a mask, a p-type region 65 is formed inside the n-type epitaxial layer 203 by ion implantation 215 of p-type impurities such as aluminum using a general ion implantation apparatus, penetrating the n-type epitaxial layer 203 in the depth direction Z (step S7). The ion implantation 215 may be a multi-stage ion implantation with different acceleration energies to form a box profile, for example.

[0094] The impurity concentration in the p-type region 65 is approximately the same as that in the p-type epitaxial layer 202. The portion of the n-type epitaxial layer 203 between adjacent p-type regions 65 becomes the n-type region 64 of the second partially parallel pn layer 52. As a result, the second partially parallel pn layer 52, consisting of the n-type region 64 and the p-type region 65, is formed as the second partially parallel pn layer constituting the drift layer 2 (see Figure 3(b)).

[0095] Here, we explain using the example of arranging one multi-stage epitaxial parallel pn layer (second partial parallel pn layer 52), but two or more multi-stage epitaxial parallel pn layers may be arranged consecutively. In this case, one multi-stage epitaxial partial parallel pn layer can be added each time the process from step S6 to step S7 is repeated. In Figure 5, this one iteration is shown by the arrow E2 pointing from step S7 to step S6.

[0096] Then, for example, hydrofluoric acid is used to remove the remainder of the oxide film 213. When two or more multi-stage epitaxial parallel pn layers are arranged consecutively, the p-type regions 65 of the multiple multi-stage epitaxial parallel pn layers have cross-sections that each have one peak and two bottoms with respect to the impurity concentration distribution in the depth direction Z. These p-type regions 65 of the cross-sections, each having one peak and two bottoms in the impurity concentration distribution in the depth direction Z, are connected in multiple ways in the depth direction Z, forming a periodic concentration distribution.

[0097] Furthermore, the second partially parallel pn layer 52 may be formed as follows: In the process of step S6, a low impurity concentration n that becomes the second partially parallel pn layer 52 - The type epitaxial layer is epitaxially grown. Then, in the process of step S7, in addition to ion implantation 215 for forming the p-type region 65 of the second partially parallel pn layer 52, ion implantation may also be performed for forming the n-type region (diffusion region) 64 of the second partially parallel pn layer 52.

[0098] Furthermore, since the p-type region 65 (or the p-type region 65 and the n-type region 64) is formed by ion implantation, crystal defects occur in the second partially parallel pn layer 52. In the case of silicon, these crystal defects can be recovered by annealing, but in silicon carbide, they cannot be recovered even if annealing is performed in a subsequent process, so crystal defects remain in the second partially parallel pn layer 52. These crystal defects shorten the carrier lifetime in the second partially parallel pn layer 52.

[0099] By forming a region with a short carrier lifetime in the drift layer 2 in this way, the high number of injected carriers when the parasitic diode (body diode) is turned on can be reduced. This has the effect of suppressing hard recovery caused by the extraction of hole carriers during the reverse recovery state of the parasitic diode. It is preferable to balance the charge in each partially parallel pn layer by making the amount of impurities, which is the product of the impurity concentration and area, approximately equal.

[0100] Next, the epitaxial substrate (n + The epitaxial substrate, on which first and second partially parallel pn layers 51 and 52 are sequentially stacked on a molded starting substrate 41, is cleaned, for example, by organic cleaning and RCA cleaning. Next, as shown in Figure 11, an n-type epitaxial layer 204 is epitaxially grown (formed) on the second partially parallel pn layer 52 as part of the epitaxial layer 42 (drift layer 2) using a CVD apparatus (step S8).

[0101] In step S8, the thickness t3 of the n-type epitaxial layer 204 is, for example, about 25 μm. The impurity concentration of the n-type epitaxial layer 204 is approximately the same as that of the n-type epitaxial layer 201. At this point in the process, the thickness of the epitaxial layer 42 becomes the total thickness t4 of the drift layer 2 (= about 65 μm). Here, the total thickness t4 of the drift layer 2 is an example for when the silicon carbide semiconductor device 50 has a breakdown voltage of 6.5 kV.

[0102] Next, the epitaxial substrate (n + An epitaxial substrate (in which first and second partially parallel pn layers 51 and 52 and an n-type epitaxial layer 204 are sequentially laminated on a molded starting substrate 41) is cleaned, for example, by organic cleaning and RCA cleaning. Next, an oxide film 216 is formed on the surface of the n-type epitaxial layer 204 to a thickness of, for example, about 6 μm using, for example, a PCVD apparatus.

[0103] Next, a resist film 217 is formed on the surface of the oxide film 216 by photolithography, with openings in the areas corresponding to the formation regions of the SJ trenches 66. The opening pattern of the resist film 217 is a stripe shape extending in the second direction Y, the same as the opening pattern of the resist film 212 used to form the first partially parallel pn layer 51, and both the opening width w15 and the remaining width w16 between adjacent openings are, for example, about 2.5 μm.

[0104] Next, the oxide film 216 is dry-etched using the resist film 217 as a mask, leaving the oxide film 216 with the same stripe-shaped opening pattern as the resist film 217. This opens up the portion of the oxide film 216 corresponding to the formation region of the SJ trench 66 in the third partially parallel pn layer 53. Then, the resist film 217 is removed.

[0105] Next, as shown in Figure 12, the n-type epitaxial layer 204 is dry-etched using the remainder of the oxide film 216 as a mask to form SJ trenches 66 (step S9). Here, since the SJ trenches 66 are formed with the same width as the SJ trenches 61 of the first partially parallel pn layer 51, the on-resistance reduction effect of the SJ structure can be enhanced by facing the SJ trenches 66 and SJ trenches 61 in the depth direction Z with as little misalignment as possible.

[0106] The depth d3 of the SJ trench 66 is such that it penetrates the n-type epitaxial layer 204 in the depth direction Z, reaching the second partially parallel pn layer 52, but does not penetrate the second partially parallel pn layer 52. The portion of the n-type epitaxial layer 204 remaining between adjacent SJ trenches 66 becomes the n-type region 67 of the third partially parallel pn layer 53. Then, the remainder of the oxide film 216 is removed, for example, with hydrofluoric acid.

[0107] Next, as shown in Figure 13, the epitaxial substrate is cleaned, for example, by organic cleaning and RCA cleaning. Then, the inside of the SJ trench 66 is filled with a p-type epitaxial layer 205 that has been epitaxially grown (formed) using a CVD apparatus (step S10). In the process of step S10, an excess p-type epitaxial layer 205 is also epitaxially grown on the surface of the n-type epitaxial layer 204 so as to protrude above the SJ trench 66.

[0108] The p-type epitaxial layer 205 may be epitaxially grown by the HVPE method, for example, using a mixed gas obtained by adding hydrogen chloride gas, a hydrogen compound, to a source gas containing a dopant such as aluminum, similar to the epitaxial growth of the p-type epitaxial layer 202. The impurity concentration of the p-type epitaxial layer 205 is approximately the same as the impurity concentration of the p-type epitaxial layer 202.

[0109] Next, the excess p-type epitaxial layer 205 located above the surface of the n-type epitaxial layer 204 is removed by grinding and polishing, leaving the p-type epitaxial layer 205 only inside the SJ trench 66 (step S11). The portion of the p-type epitaxial layer 205 remaining inside the SJ trench 66 becomes the p-type region 68 of the third partially parallel pn layer 53.

[0110] Next, the surfaces of the n-type epitaxial layer 204 and the p-type epitaxial layer 205 are planarized by CMP (step S12). This forms a third partially parallel pn layer 53, which is the third partially parallel pn layer constituting the drift layer 2, with the n-type epitaxial layer 204 and the p-type epitaxial layer 205 forming an n-type region 67 and a p-type region 68, respectively (see Figure 3(c)).

[0111] The first to third partially parallel pn layers 51 to 53 formed in the steps up to this point create an SJ structure with a thickness t5 of about 55 μm, and a drift layer 2 (epitaxial layer 42) with a total thickness t4 of about 65 μm is formed, having a full SJ structure with each n-type region and p-type region having a width of 2.5 μm (repeating pitch of 5.0 μm).

[0112] Here, we explain using drift layer 2, a full SJ structure composed of three partially parallel pn layers, as an example. However, to increase the number of partially parallel pn layers that make up drift layer 2, the number of partially parallel pn layers can be increased by two layers (multi-stage epitaxially parallel pn layers and trench-embedded parallel pn layers) each time the process from step S6 to step S12 described above is repeated. In Figure 5, this one repetition is shown by the arrow E1 from step S12 to step S6.

[0113] For example, if drift layer 2 is constructed with five partially parallel pn layers to form a full SJ structure, the thickness of the first, third, and fifth trench-embedded parallel pn layers is set to 18 μm, and the thickness of the second and fourth multi-stage epitaxial parallel pn layers is set to 0.65 μm. This makes it possible to form an SJ structure with the same thickness t5 as when drift layer 2 is constructed with the first to third partially parallel pn layers 51 to 53, even when drift layer 2 is constructed with five partially parallel pn layers.

[0114] Next, the device structure is formed on the drift layer 2 with a full SJ structure (step S13). Specifically, first, as shown in Figure 14, using a CVD apparatus, n - A type epitaxial layer 43 is epitaxially grown (formed) to a thickness of, for example, about 0.5 μm. Next, by photolithography and ion implantation of p-type impurities, n - In the surface region of the type epitaxial layer 43, p + Type region 11 and p + The mold region 12a and the mold region are repeatedly formed alternately, separated from each other in the first direction X.

[0115] p + Type region 11 is p + Formed at a different timing than type region 12a, p + Type region 11 is p + type area 12(p + The depth may be made deeper than the depth of the type region 12a) and terminated inside the lower third partially parallel pn layer 53. In this case, p +The width of the type region 11 is made wider than the width of the p-type region 68 of the third partial parallel pn layer 53 and narrower than the repetition pitch of the n-type region 67 and the p-type region 68. Next, by photolithography and ion implantation of n-type impurities, an n - -type region 3a is formed in the surface region of the n-type epitaxial layer 43.

[0116] Next, as shown in FIG. 15, the thickness of the n - -type epitaxial layer 43 is increased by epitaxial growth. Next, by photolithography and ion implantation of p-type impurities, a p - -type region 12b is selectively formed in the portion 43a where the thickness of the n + -type epitaxial layer 43 has been increased, and the p + -type region 12a and the p + -type region 12b adjacent to each other in the depth direction are connected to form a p + -type region 12.

[0117] Next, by photolithography and ion implantation of n-type impurities, an n-type region 3b is formed in the portion 43a where the thickness of the n - -type epitaxial layer 43 has been increased, and the n-type region 3a and the n-type region 3b adjacent to each other in the depth direction are connected to form an n-type current diffusion region 3.

[0118] Next, as shown in FIG. 16, using a CVD apparatus, a p-type epitaxial layer 44 that becomes a p-type base region 4 is epitaxially grown on the n - -type epitaxial layer 43. As a result, an epitaxial layer 42, an n + -type epitaxial layer 43, and a p-type epitaxial layer 44 are sequentially stacked on the front surface of the n - -type starting substrate 41, and a semiconductor substrate (semiconductor wafer) 40 is fabricated.

[0119] Next, the process of taking photolithography and ion implantation as a set is repeated under different conditions, and an n + -type source region 5 and a p ++The p-type contact regions 6 are selectively formed. + Type source region 5 and p ++ The portion excluding the type contact area 6 becomes the p-type base area 4.

[0120] Next, by photolithography and etching, n + A gate trench 7 is formed that penetrates the p-type source region 5 and the p-type base region 4 and reaches the n-type current diffusion region 3. The bottom surface of the gate trench 7 is, for example, p + The process may terminate within the mold region 11. Next, the diffusion region formed by ion implantation is subjected to heat treatment to activate impurities.

[0121] Next, a gate insulating film 8 is formed along the front surface of the semiconductor substrate 40 and the inner wall of the gate trench 7. Then, the polysilicon (poly-Si) layer deposited on the front surface of the semiconductor substrate 40 is etched back so as to be embedded inside the gate trench 7, leaving only the portion that will become the gate electrode 9 inside the gate trench 7. Next, an interlayer insulating film 14 is formed over the entire front surface of the semiconductor substrate 40.

[0122] Next, surface electrodes (source electrode 15 and drain electrode 16) are formed on both sides of the semiconductor substrate 40 using a general method (step S14). The intermediate region 20 and edge termination region 30 (see Figure 2), which are not shown in Figures 6-16, are formed at predetermined timings. After that, the semiconductor wafer is diced (cut) to separate it into individual chips, thereby completing the silicon carbide semiconductor device 50 shown in Figures 2 and 3.

[0123] As explained above, according to Embodiment 1, the drift layer has a structure in which trench-embedded parallel pn layers (partially parallel pn layers) and multi-stage epitaxially parallel pn layers (partially parallel pn layers) are alternately stacked in three or more layers. This makes it possible to make the majority of the total thickness of the thick drift layer required to achieve high voltage resistance an SJ structure (full SJ structure). For this reason, more than half of the drift layer is not an SJ structure, unlike a normal n -Compared to conventional structures with a partial SJ structure that results in a drift region (see Figure 22), the on-resistance can be reduced.

[0124] Furthermore, according to Embodiment 1, the total thickness of the drift layer can be easily increased by using trench-embedded parallel pn layers among the three or more partially parallel pn layers that constitute the drift layer. Also, the more trench-embedded parallel pn layers there are, the thinner the trench-embedded parallel pn layers can be, and the width of the SJ trench can be narrowed. As a result, the width of the n-type region and p-type region of the trench-embedded parallel pn layer can be narrowed, thereby increasing the on-resistance reduction effect.

[0125] Furthermore, according to Embodiment 1, when forming a trench-embedded parallel pn layer, the depth of the SJ trench can be made shallower than the total thickness of the drift layer, making both trench etching of the SJ trench and embedding of the epitaxial layer into the SJ trench easy. Therefore, manufacturing is easy and the properties can be improved. Also, according to Embodiment 1, it is useful when the withstand voltage is 1kV or more and the thickness of the drift layer is 10μm or more, and is particularly suitable for withstand voltage of 3kV or more when the thickness of the drift layer is 30μm or more.

[0126] Furthermore, according to Embodiment 1, when viewed from the front side of the semiconductor substrate, the stripe shapes of the n-type and p-type regions of the trench-embedded parallel pn layer and the stripe shapes of the n-type and p-type regions of the multi-stage epitaxial parallel pn layer extend in different directions. This makes it possible to reliably connect adjacent n-type regions and p-type regions of trench-embedded parallel pn layers in the depth direction via the n-type and p-type regions of the multi-stage epitaxial parallel pn layer, respectively.

[0127] In this way, adjacent n-type and p-type regions of partially parallel pn layers can be easily connected in the depth direction, thus eliminating the need to form alignment marks and perform alignment in the depth direction between the n-type and p-type regions of the partially parallel pn layers. Therefore, it is possible to avoid unique problems related to alignment that arise due to the characteristics of silicon carbide (such as alignment marks being filled in during epitaxial growth depending on the surface orientation).

[0128] (Embodiment 2) Next, the structure of the silicon carbide semiconductor device according to Embodiment 2 will be described. Figure 17 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 2. The difference between the silicon carbide semiconductor device 70 according to Embodiment 2 and the silicon carbide semiconductor device 50 according to Embodiment 1 (Figure 2) is that the trench gate structure is replaced with a planar gate structure. The silicon carbide semiconductor device 70 according to Embodiment 2 has a drift layer 2 (epitaxial layer 42) with a full SJ structure similar to that of Embodiment 1, and is equipped with parts of a general planar gate structure.

[0129] Specifically, in Embodiment 2, the semiconductor substrate 40' is made of n + On the front surface of the starting substrate 41, an epitaxial layer 42, which is a drift layer 2 with a full SJ structure similar to that of Embodiment 1, and an n-type epitaxial layer 43' which will become the n-type JFET region 74 are deposited in sequence. The main surface of the semiconductor substrate 40' on the n-type epitaxial layer 43' side is considered the front surface, + Main surface (n) on the mold starting substrate 41 side + The back surface of the mold starting substrate 41 is designated as the back surface.

[0130] The n-type epitaxial layer 43' is selectively provided with a p-type base region 71 that penetrates the n-type epitaxial layer 43' in the depth direction. The p-type base region 71 is adjacent to the p-type region 68 of the third partially parallel pn layer 53 in the depth direction Z. Between the front surface of the semiconductor substrate 40' and the p-type base region 71, an n-type base region is provided that is in contact with the p-type base region 71 and exposed to the front surface of the semiconductor substrate 40'. +Type source region 72 and p + Each type of contact region 73 is selectively provided.

[0131] n-type epitaxial layer 43', p-type base region 71, n + Type source region 72 and p + The portion excluding the n-type contact region 73 is the n-type JFET region 74. The n-type JFET region 74 is exposed on the front surface of the semiconductor substrate 40'. + The n-type source region 72 is provided separately from the n-type JFET region 74. + A p-type base region 71 exists between the n-type source region 72 and the n-type JFET region 74. + The contact area 73 is n + It is located further away from the n-type JFET region 74 than the n-type source region 72.

[0132] n + A gate electrode 76 is provided on the surface of the area sandwiched between the n-type source region 72 and the n-type JFET region 74, via a gate insulating film 75. An interlayer insulating film 77 is provided over the entire surface of the front surface of the semiconductor substrate 40 so as to cover the gate electrode 76. The source electrode 78 is connected via a contact hole opened in the interlayer insulating film 77. + Type source region 72 and p + It is electrically connected to the type contact region 73. The configuration of the back side of the semiconductor substrate 40' from the drift layer 2 is the same as in Embodiment 1.

[0133] The method for manufacturing the silicon carbide semiconductor device 70 according to Embodiment 2 is as follows: In step S13 of the method for manufacturing the silicon carbide semiconductor device 50 according to Embodiment 1 (see Figure 5), a planar gate structure is formed by a general method instead of a trench gate structure. Figure 18 is a cross-sectional view showing the state of the silicon carbide semiconductor device during manufacturing according to Embodiment 2. Specifically, first, the process is carried out in the same manner as in Embodiment 1, from step S1 to S12.

[0134] Next, as shown in Figure 18, in step S13, an n-type epitaxial layer 43' that will become an n-type JFET region 74 is epitaxially grown (formed) on the third partially parallel pn layer 53. + An epitaxial layer 42 and an n-type epitaxial layer 43' are sequentially stacked on the front surface of the mold starting substrate 41 to fabricate a semiconductor substrate (semiconductor wafer) 40'.

[0135] Next, the process of photolithography and ion implantation as a set is repeated under different conditions to create a p-type base region 71 and n-type epitaxial layer 43' on the surface region. + Type source region 72 and p + The n-type contact regions 73 are selectively formed. The p-type base region 71 and n-type contact region 73' of the n-type epitaxial layer 43'. + Type source region 72 and p + The portion excluding the type contact region 73 becomes the n-type JFET region 74.

[0136] Next, a gate insulating film 75 is formed on the entire surface of the front surface of the semiconductor substrate 40'. Then, a polysilicon layer is formed on the front surface of the semiconductor substrate 40' and patterned, and adjacent n-type JFET regions 74 are arranged on either side of each other. + A portion that will become the gate electrode 76 is left on the surface between the mold source regions 72. Next, an interlayer insulating film 14 is formed on the entire surface of the front surface of the semiconductor substrate 40. Then, by sequentially performing the processes from step S14 onward, the silicon carbide semiconductor device 70 shown in Figure 17 is completed.

[0137] As described above, according to Embodiment 2, even when Embodiment 1 is applied to a planar gate structure, the same effects as in Embodiment 1 can be obtained.

[0138] (Embodiment 3) Next, the structure of the silicon carbide semiconductor device according to Embodiment 3 will be described. Figure 19 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 3. The difference between the silicon carbide semiconductor device 80 according to Embodiment 3 and the silicon carbide semiconductor device 50 according to Embodiment 1 (Figure 2) is that an SJ trench 81 is formed in the p-type epitaxial layer 221 which becomes the p-type region 83 of the third partially parallel pn layer 84 (trench-embedded parallel pn layer), and an n-type epitaxial layer 222 which becomes the n-type region 82 is embedded inside the SJ trench 81.

[0139] The manufacturing method for the silicon carbide semiconductor device 80 according to Embodiment 3 is performed by reversing the conductivity type (n-type, p-type) in steps S8 to S11 of the manufacturing method for the silicon carbide semiconductor device 50 according to Embodiment 1 (see Figure 5). Specifically, first, the processes in steps S1 to S7 are performed in the same manner as in Embodiment 1. Next, in step S8, a p-type epitaxial layer 221 is epitaxially grown (formed) on the second partially parallel pn layer 52 as part of the epitaxial layer 85 (drift layer 2).

[0140] Next, in step S9, SJ trenches 81 are formed in the p-type epitaxial layer 221. The portion of the p-type epitaxial layer 221 remaining between adjacent SJ trenches 81 becomes the p-type region 83 of the third partially parallel pn layer 84. The SJ trenches 81 can be formed in the same manner as in Embodiment 1 using an oxide film mask with an opening in the portion facing the formation region of the n-type region 82. Next, in step S10, the n-type epitaxial layer 222 is embedded inside the SJ trenches 81.

[0141] In step S10, the portion of the n-type epitaxial layer 222 that was epitaxially grown remains inside the SJ trench 81, becoming the n-type region 82 of the third partially parallel pn layer 84. Next, in step S11, the excess portion of the n-type epitaxial layer 222 that was epitaxially grown outside the SJ trench 81 is removed, leaving the n-type epitaxial layer 222 only inside the SJ trench 81. Subsequently, by sequentially performing the processes from step S12 onward, the silicon carbide semiconductor device 80 shown in Figure 19 is completed.

[0142] The first partially parallel pn layer 51 (trench-embedded parallel pn layer) on the drain side is formed in the same manner as in Embodiment 1, and it cannot be formed by reversing the conductivity type as described above for the third partially parallel pn layer 84. + The entire portion between the type starting substrate 41 and the first partially parallel pn layer 51 where an SJ structure is not formed (corresponding to the n-type drift region 2a in Figure 2) becomes a p-type region, and the p-type region and n + This is because a pn junction is formed with the mold starting substrate 41.

[0143] Furthermore, exposure of the aperture pattern onto the etching mask for forming the SJ trench 81 may be performed using a rectil (not shown) that was used to expose the aperture pattern onto the resist film 212 (see Figure 6), which was used as a mask to form the aperture pattern onto the oxide film 211 (see Figures 6 and 7), which is an etching mask for forming the SJ trench 61 of the first partially parallel pn layer 51. In this case, the p-type region 83 of the third partially parallel pn layer 84 is positioned in the depth direction Z opposite to the n-type region 62 of the first partially parallel pn layer 51.

[0144] An SJ trench 81 may be formed such that the p-type region 83 of the third partially parallel pn layer 84 faces the n-type region 62 of the first partially parallel pn layer 51 in the depth direction Z. In this case, the SJ trench 81 can be formed using an etching mask (oxide film) that has an opening pattern in the resist film used as a mask to form an opening pattern in the etching mask (oxide film) for forming the SJ trench 81, with the opening pattern shifted in the first direction X by the width of the n-type region 62 (one column).

[0145] The silicon carbide semiconductor device 80 according to Embodiment 3 may be modified by applying Embodiment 2, and a planar gate structure may be used instead of a trench gate structure.

[0146] As described above, according to Embodiment 3, even when the conductivity type of the trench-embedded parallel pn layers (excluding the first partially parallel pn layer) constituting the drift layer is reversed, the same effects as in Embodiments 1 and 2 can be obtained.

[0147] (Embodiment 4) Next, the structure of the silicon carbide semiconductor device according to Embodiment 4 will be described. Figure 20 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 4. The difference between the silicon carbide semiconductor device 80' according to Embodiment 4 and the silicon carbide semiconductor device 80 according to Embodiment 3 (Figure 19) is that the width w1 of the SJ trench 81' of the third partially parallel pn layer 84' (trench-embedded parallel pn layer) is widened, and the width w2 of the n-type region 82' of the third partially parallel pn layer 84' is widened compared to the width w3 of the p-type region 83'.

[0148] For each partially parallel pn layer constituting the drift layer 2, the n-type region and the p-type region should be roughly charge-balanced, and the widths of the n-type and p-type regions may be different. For example, for the third partially parallel pn layer 84', the width w2 of the n-type region 82' and the width w3 of the p-type region 83' may be approximately 3.0 μm and 1.5 μm, respectively. In this case, the thickness t3' of the third partially parallel pn layer 84' can be increased, and the depth d3' of the SJ trench 81' can be increased. The depth d3' of the SJ trench 81' is, for example, approximately 35 μm.

[0149] Even if the depth d3' of the SJ trench 81' is increased, widening the width w1 of the SJ trench 81' makes it easier to form an SJ trench 81' with a good trench shape in the p-type epitaxial layer 221', which becomes the p-type region 83' of the third partially parallel pn layer 84', where the sidewalls are approximately perpendicular to the main surface of the semiconductor substrate 40. In addition, widening the width w1 of the SJ trench 81' makes it easier to avoid problems that arise when embedding the n-type epitaxial layer 222', which becomes the n-type region 82' of the third partially parallel pn layer 84', inside the SJ trench 81'.

[0150] The problem that arises when embedding the n-type epitaxial layer 222' into the SJ trench 81' is that the n-type epitaxial layers 222' that have grown epitaxially on both side walls of the SJ trench 81' connect near the top of the opening of the SJ trench 81', blocking the top of the opening and preventing the embedding of the n-type epitaxial layer 222'. By making it easier to avoid this problem, the n-type epitaxial layer 222' can be more easily embedded inside the SJ trench 81', and the on-resistance reduction effect of the SJ structure is enhanced.

[0151] The n-type region 82' and p-type region 83' of the third partially parallel pn layer 84' are roughly charge-balanced. For this reason, the p-type impurity concentration in the p-type region 83' is higher than that in the n-type region 82'. When differentiating the p-type impurity concentration in the p-type region for each partially parallel pn layer constituting the drift layer 2, it is preferable to make the p-type impurity concentration highest in the p-type region of the partially parallel pn layer closest to the source, and lower the p-type impurity concentration in the p-type region of the partially parallel pn layers located closer to the drain.

[0152] Therefore, it is preferable that the p-type impurity concentrations in the p-type regions 62 and 65 of the first and second partially parallel pn layers 51 and 52 be less than or equal to the p-type impurity concentration in the p-type region 83' of the third partially parallel pn layer 84'. By making the p-type impurity concentration highest in the p-type region 83' of the third partially parallel pn layer 84', which is closest to the source, and lowering the p-type impurity concentration in the p-type regions of the first and second partially parallel pn layers 51 and 52, which are located closer to the drain, the on-resistance reduction effect of the SJ structure can be enhanced when the p-type impurity concentrations in the p-type regions differ for each partially parallel pn layer.

[0153] The method for manufacturing the silicon carbide semiconductor device 80' according to Embodiment 4 is obtained by increasing the thickness t3' of the p-type epitaxial layer 221', which is part of the epitaxial layer 85' (drift layer 2), increasing the depth d3' of the SJ trench 81' formed in the p-type epitaxial layer 221', and widening the width w1 of the SJ trench 81', as described in the method for manufacturing the silicon carbide semiconductor device 80 according to Embodiment 3.

[0154] Embodiment 2 may be applied to the silicon carbide semiconductor device 80' according to Embodiment 4, and a planar gate structure may be used instead of a trench gate structure.

[0155] As described above, according to Embodiment 4, even when the widths of the n-type region and the p-type region differ for each partially parallel pn layer constituting the drift layer, if the n-type region and the p-type region are roughly charge-balanced for each partially parallel pn layer constituting the drift layer, the same effects as in Embodiments 1 to 3 can be obtained.

[0156] (Examples) Next, the thickness t2 of the second partially parallel pn layer 52 (multi-stage epitaxial parallel pn layer) (see Figures 2, 9, and 10) was investigated. Figure 21 is a characteristic diagram showing the doping concentration in the ion implantation region of the multi-stage epitaxial parallel pn layer. The horizontal axis of Figure 21 shows the depth from the ion implantation surface, and the vertical axis shows the aluminum doping concentration. 1 × 10⁻¹⁶ p-type region formed by ion implanting aluminum into a silicon carbide n-type epitaxial layer in multiple stages with different acceleration energies (hereinafter referred to as multi-stage ion implantation) 16 / cm 3 The box profile of the degree is shown in Figure 21.

[0157] This multi-stage ion implantation corresponds to the ion implantation 215 (see Figure 10) for forming the p-type region 65 of the second partially parallel pn layer 52. The n-type epitaxial layer that underwent multi-stage ion implantation corresponds to the n-type epitaxial layer 203 (Figures 9, 10) that constitutes the second partially parallel pn layer 52. The box profile of the p-type region shown in Figure 21 corresponds to the doping concentration distribution of the p-type region 65 of the second partially parallel pn layer 52.

[0158] Multistage ion implantation was performed in eight stages (eight times) at a temperature of 500°C, using different acceleration energies from directions perpendicular to the ion implantation surface. Although a box profile was formed by ion implantation, the impurity concentration in the depth direction Z of the semiconductor region of the box profile formed by ion implantation was not uniform compared to the semiconductor region formed by epitaxial growth, and instead exhibited a periodic concentration distribution.

[0159] Multistage ion implantation was performed using a general ion implanter under the following conditions: The acceleration energy and dose for the first stage of ion implantation were 700 keV and 2.20 × 10⁻⁶, respectively. 11 / cm 2 The acceleration energy and dose for the second stage of ion implantation are 550 keV and 8.00 × 10⁻⁶, respectively. 10 / cm 2The acceleration energy and dose for the third stage of ion implantation are 400 keV and 2.00 × 10⁻⁶, respectively. 11 / cm 2 The acceleration energy and dose for the fourth stage of ion implantation are 220 keV and 1.50 × 10⁻⁶, respectively. 11 / cm 2 That is the case.

[0160] The acceleration energy and dose for the fifth stage of ion implantation are 100 keV and 1.00 × 10⁻⁶, respectively. 11 / cm 2 The acceleration energy and dose for the sixth stage of ion implantation are 50 keV and 3.00 × 10⁻⁶, respectively. 10 / cm 2 The acceleration energy and dose for the 7th stage ion implantation are 30 keV and 2.00 × 10⁻⁶, respectively. 10 / cm 2 The acceleration energy and dose for the 8th stage ion implantation are 20 keV and 1.50 × 10⁻⁶, respectively. 11 / cm 2 That is the case.

[0161] As shown in Figure 21, the depth from the ion implantation surface to a depth of 0.65 μm is 1 × 10⁻¹⁶. 16 / cm 3 A box profile of a certain degree was observed, and it was confirmed that the doping concentration decreased as the depth from the ion implantation surface exceeded 0.65 μm (indicated by the sign F). For this reason, the thickness t2 of the second partially parallel pn layer 52 is preferably 0.65 μm or less. In addition, although a region with a low impurity concentration occurs in the surface area of ​​the ion implantation surface, the inventors have confirmed that it is removed by hydrogen etching when the upper epitaxial layer is formed.

[0162] In summary, the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of the invention. [Industrial applicability]

[0163] As described above, the silicon carbide semiconductor device according to the present invention is useful for silicon carbide semiconductor devices with a breakdown voltage of 1 kV or higher, and is particularly suitable for silicon carbide semiconductor devices with a breakdown voltage of 3.3 kV or higher. [Explanation of Symbols]

[0164] 1 n + Type drain region 2 Drift Layers 2a n-type drift region 3 n-type current diffusion region 3a,3b n-type region 4.71 p-type base region 5.72 n + Type source area 6 p ++ Type Contact Area 7,7a Gate trench 8.75 Gate Insulator 9.76 Ground Fault 10 Active area 11,11a,12,12a,12b,13 p + type area 14.77 Interlayer insulating film 15,78 Source electrodes 16 Drain electrode 20 Intermediate area 21 Gate Runner 22 Gate Metal Wiring 30 Edge Termination Region 31 steps 32 1st JTE area 33 2nd JTE area 34 JTE structure 35 n + Type stopper area 36 Field Oxide Film 40,40' Semiconductor substrate 40a The active region side of the front surface of the semiconductor substrate (first surface) 40b The portion outside the step on the front surface of the semiconductor substrate (second surface) 40c The portion between the first and second surfaces on the front surface of the semiconductor substrate (step mesa edge: third surface) 41 n+ Mold starting substrate 42,42' Epitaxial layer 43 n - Type epitaxial layer 43' n-type epitaxial layer 43a: Increased thickness of the n-type epitaxial layer 44 p-type epitaxial layer 50, 70, 80, 80' Silicon Carbide Semiconductor Device 51,51' 1st partially parallel pn layer 52,52' 2nd partially parallel pn layer 53,53',84,84' 3rd partially parallel pn layer 61,61' SJ trench of the first partially parallel pn layer 62,62' n-type region of the first partially parallel pn layer 63,63' p-type region of the first partially parallel pn layer 64,64' n-type region of the second partially parallel pn layer 65,65' p-type region of the second partially parallel pn layer 66,66',81,81' SJ trench of the third partially parallel pn layer 67,67',82,82' n-type region of the third partially parallel pn layer 68,68',83,83' p-type region of the third partially parallel pn layer 73 p + Type Contact Area 74 n-type JFET region 201,203,204,222 n-type epitaxial layers 202,205,221 p-type epitaxial layers 211,213,216 Oxide film 212,214,217 Resist film w1 Width of the SJ trench in the third part parallel pn layer w2 Width of the n-type region in the third partially parallel pn layer w3 Width of the p-type region in the third partially parallel pn layer w11, w13, w15 Aperture width of the resist film w12, w14, w16 Remaining width between adjacent apertures in the resist film X First direction parallel to the front surface of the semiconductor substrate Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction. Z-direction (depth)

Claims

1. The device comprises an epitaxial layer made of silicon carbide, which includes a main surface and is provided with a drift layer and an element structure on the drift layer. The aforementioned device structure is p-type base region, A trench provided on the main surface, It has a first p-type semiconductor region, which is provided between the base region and the drift layer and faces the bottom surface of the trench in the depth direction, and has a higher impurity concentration than the base region, The drift layer has a first p-type region of a parallel pn layer formed inside the drift layer, The first semiconductor region terminates within the first p-type region. A semiconductor chip comprising the main surface and the epitaxial layer, The aforementioned device structure is A third p-type semiconductor region is provided between the base region and the drift layer, facing the bottom surface of the trench in the depth direction and extending toward the edge side of the semiconductor chip, and having a higher impurity concentration than the base region. The silicon carbide semiconductor device is characterized in that the third semiconductor region is in contact with a plurality of the first p-type regions in the depth direction.

2. A silicon carbide epitaxial layer comprising a main surface, a drift layer and an element structure on the drift layer, The aforementioned device structure is p-type base region, A trench provided on the main surface, It has a first p-type semiconductor region, which is provided between the base region and the drift layer and faces the bottom surface of the trench in the depth direction, and has a higher impurity concentration than the base region, The drift layer has a first p-type region of a parallel pn layer formed inside the drift layer, The first semiconductor region terminates within the first p-type region. The silicon carbide semiconductor device is characterized in that the drift layer has a second p-type region that contacts the first p-type region in the depth direction.

3. comprising an n-type starting substrate made of silicon carbide, The silicon carbide semiconductor device according to claim 1 or 2, characterized in that the epitaxial layer is laminated on the (0001) side of the starting substrate.

4. The silicon carbide semiconductor device according to any one of claims 1 to 3, characterized in that the first p-type region is separated by a predetermined thickness from the bottom surface of the trench.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4, characterized in that the aspect ratio of the first p-type region is 5 or more and 15 or less.

6. The silicon carbide semiconductor device according to claim 2, characterized in that the first p-type region is terminated inside the second p-type region.

7. The silicon carbide semiconductor device according to claim 2 or 6, characterized in that the second p-type region extends in a direction different from that of the first p-type region in a plan view.

8. The silicon carbide semiconductor device according to any one of claims 1, 3, 4, or 5, characterized in that the drift layer is a full SJ structure in which the parallel pn layer has a thickness of 80% or more of the total thickness of the drift layer.

9. A silicon carbide epitaxial layer comprising a main surface, a drift layer and an element structure on the drift layer, The aforementioned device structure is p-type base region, A trench provided on the main surface, It has a first p-type semiconductor region, which is provided between the base region and the drift layer and faces the bottom surface of the trench in the depth direction, and has a higher impurity concentration than the base region, The drift layer has a first p-type region of a parallel pn layer formed inside the drift layer, The first semiconductor region terminates within the first p-type region. The drift layer is a full SJ structure in which the parallel pn layer has a thickness of 80% or more of the total thickness of the drift layer. The silicon carbide semiconductor device is characterized in that the full SJ structure has a structure in which the first p-type region and a plurality of p-type regions having the same impurity concentration as the first p-type region are connected in the depth direction.

10. The aforementioned device structure is An insulating film along the inner wall of the trench, The trench has a conductive layer embedded inside it, The drift layer has first n-type regions that are alternately arranged with the first p-type regions in a first direction parallel to the main surface to constitute the parallel pn layer. The trench extends in a stripe-like manner in a second direction parallel to the main surface and different from the first direction, The silicon carbide semiconductor device according to any one of claims 1 to 9, characterized in that the first p-type region extends in a stripe-like manner in the second direction.

11. The aforementioned device structure is The silicon carbide semiconductor device according to any one of claims 1 to 10, characterized in that a second p-type semiconductor region with a higher impurity concentration than the base region is provided between the base region and the drift layer, separated from the first semiconductor region and the trench, and in contact with the first p-type region in the depth direction.

12. A semiconductor chip comprising the main surface and the epitaxial layer, The aforementioned device structure is A third p-type semiconductor region is provided between the base region and the drift layer, facing the bottom surface of the trench in the depth direction and extending toward the edge side of the semiconductor chip, and having a higher impurity concentration than the base region. The silicon carbide semiconductor device according to any one of claims 2, 6, or 7, characterized in that the third semiconductor region is in contact with a plurality of first p-type regions in the depth direction.

13. The silicon carbide semiconductor device according to any one of claims 1 to 12, characterized in that the trench extends in the direction of the crystal plane orientation <11-20>.

14. The silicon carbide semiconductor device according to any one of claims 1 to 12, characterized in that the trench extends in the direction of the crystal plane orientation <1-100>.

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