Semiconductor chips, chip modules, and methods for manufacturing semiconductor chips (semiconductor circuit power supply)

Abstract

To provide efficient power connection, power connection routing and signal connection routing within semiconductor chips.SOLUTION: A semiconductor chip 100 has bottom external connections 110, a front side power network layer 125, a device layer 150, and a grind side power network layer 175. One or more of devices have other device power connections and one or more device ground connections. The device layer has a front side 152 and a back / grind side 154. The front side power network layer has power, ground, signal and other connections that connect to the respective device power and device ground connections through device-via connections 155. The power, ground, signal and other connections connect to the respective device power and device ground connections through a bottom 156 of the grind side power network layer. One or more first device power connections are connected to one or more of the front side power network layer connections, and one or more second device power connections are connected to one or more of the grind side power network layers.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to the power supply of semiconductor circuits. More specifically, the present invention relates to reliably and efficiently supplying power to semiconductor chip circuits and chip packages.

Background Art

[0002] In the prior art, the conventional method of supplying power and signal connections to semiconductor circuits is through connections formed in the wiring process (BEOL: Back End of the Line).

[0003] Multiple metal conduction horizontal layers are formed in BEOL. Some of these horizontal layers include horizontal connections that perform specific functions. For example, some horizontal connections distribute power to devices within the chip. Other horizontal connections can provide signals, information, data, or control, or combinations thereof, between devices. Generally, horizontal connections are wires or connections remaining within a layer in the power distribution network. For example, most horizontal connections are connections that extend within one or more of the horizontal layers within a typical semiconductor circuit chip (chip).

[0004] Other connections formed in BEOL are vertical connections such as vias. Vias, such as through-silicon vias (TSVs), pass vertically through horizontal connection layers to interconnect horizontal connections in different horizontal connection layers, or to realize other vertical through-connections, or combinations thereof.

[0005] Typically, external connections such as C4 bonds or metal pads are arranged outside the chip and are connected to / through the horizontal or vertical connections or both formed in BEOL. Therefore, one or more electrical conduction paths are formed to connect the device power supply or device signal connection or both of the devices within the chip to the external connections outside the chip.

[0006] Typically, these devices reside in the device layer within a chip. Generally, the device layer is adjacent to, but distinct from, the BEOL (Behind-the-Line) conducted horizontal layer. Devices can include active devices such as transistors, such as field-effect transistors (FETs) or bipolar junction transistors (BJTs), or passive components such as resistors, or combinations thereof. These devices are manufactured in the Front End of the Line (FEOL) process.

[0007] The connection made at BEOL is typically made on one side of the device layer, namely the BEOL metallization side or the "front side" of the chip. The side of the device layer opposite the BEOL metallization side, or the side through which the device layer passes from the front side, is called the "polished side" or "back side" of the chip. Manufacturing processes such as thinning and dicing are performed on the polished / back side so as not to interfere with the metallization on the BEOL metallization side / front side of the chip.

[0008] On the front / BEOL metallization side, the layer thickness, connection size, and connection pitch can be varied depending on the purpose of the connection.

[0009] For example, in some designs, layers that primarily contain interconnections of signals, information, or control, or a combination thereof, will have lower-pitch and finer interconnections (more tightly packed), and will be located at a lower level in the structure, closer to the devices in the device layer. Due to the lower levels of signal / data / control currents, these signal interconnections can be made finer without incurring large resistive operating losses.

[0010] Thicker / larger connections are power distribution and are generally located in the upper layers on the BEOL metallization side / front side, i.e., further away from the device layers. These power connections are larger to reduce power losses that can occur with higher current loads. These distribution layers have lower density power interconnects because the cross-section of the power interconnects is larger, or thicker, or both.

[0011] In other words, lower-level (closer to the device layer) interconnects, used to connect devices for signal / data / information / control functions, are typically finer and occur at higher densities. These thinner lines and vias have a narrower pitch and are mostly used for so-called "local interconnects."

[0012] At the upper levels (BEOL, further away from the device layer), the distance traveled by power connections increases, allowing for larger currents to flow. Generally, these upper layers contain larger power connections, and the larger the size of the connection, the greater the current that can flow. 2 R-loss is reduced. For these larger connections, reducing power loss is more important than pack density. Therefore, these upper levels are thicker and the interconnect pitch is also larger. (These large interconnects are so-called "global interconnects").

[0013] However, it should be noted that in some embodiments, one or more "embedded power rails (BPRs)" or power connections are located near or within the device layer, rather than at an upper level away from the device layer. This local placement provides power / connections close to the device layer.

[0014] In summary, the external power supply is connected to an external chip connection, such as a C4 connection or a metal / conductive pad, or a combination thereof. Power passes through the "front" of the chip (or BEOL metallization or BEOL power grid) and is distributed to the device layer. Similarly, signal, data, information, and control connections can be made from the external chip connection through the BEOL power grid to the device signal / data / information / control connections. [Overview of the Initiative] [Problems that the invention aims to solve]

[0015] However, this type of power distribution in semiconductor chips presents problems. These problems become even more severe as devices become smaller and connections and other circuits are packed more densely.

[0016] For example, large power connections occupy a significant amount of space on the front side of the chip (BEOL metallization side). This space increases the space required for signal, information, data, or control connections, or a combination thereof (typically referred to as "signal connections"). Additionally, the high density packing of devices and the high density packing of local interconnects near the devices constrains the routing of power connections. These constraints limit the routing of power connections (and in some cases, the routing of signal, data, information, and control connections), resulting in additional associated power losses, e.g., I 2 Along with R loss and wiring complexity, this leads to lower efficiency, for example, longer routing times.

[0017] Therefore, more efficient power connections or power connection routing (and signal connection routing), or a combination thereof, within semiconductor chips (chips) is required. For example, more efficient power connections within a chip reduce power loss, decrease chip heat generation, and result in more reliable chip performance and extended chip life. [Means for solving the problem]

[0018] The present invention discloses an embodiment of a semiconductor chip (chip) having one or more bottom external (power or ground) connections and one or more front side power grid layers having front side layers. One or more of the front side layers have one or more front side power connections and one or more front side ground connections. One or more of the front side power connections are connected to one or more of the respective bottom external power connections. One or more of the front side ground connections are connected to one or more of the respective bottom external ground connections.

[0019] The chip has at least one device layer. The device layer has multiple devices. One or more of the devices have one or more device power connections and one or more device ground connections. The device layer has a front side and a back polished surface side.

[0020] The front side of the device layer is mounted above the top front layer and attached to the top front layer such that one or more of the front power connections are electrically connected to one or more of the device power connections, and one or more of the front ground connections are connected to one or more of the device ground connections.

[0021] The polishing surface-side power grid layer has one or more polishing surface-side layers. The bottom polishing surface-side layer is mounted on the back polishing surface side above the back polishing surface side of the device layer, such that one or more polishing surface-side power connections are electrically connected to one or more of the device power connections, and one or more polishing surface-side ground connections are electrically connected to one or more of the device ground connections. Conduction paths are formed from the device power / ground connections through the polishing surface-side power grid layer to the top external power and ground connections at the top of the chip, respectively.

[0022] Therefore, one or more of the device power connections are connected to one of the bottom external power connections, one or more of the device power connections are connected to one of the top external power connections, and one or more of the device ground connections are connected to at least one of the bottom external ground connections and at least one of the top external ground connections. Thereby, a device layer with dual power / ground feeding / distribution is provided from both the top / back and bottom / front of the chip's device layer. In some embodiments, signal connections (connections of device signals, information, data or control, or combinations thereof) can also be routed from the device through both the front-side power grid layer and the polished-side power grid layer to the respective bottom external and top external signal connections of the chip.

[0023] Alternative embodiments having various external conduits are disclosed along with different chip embodiments and methods of making modules of one or more chips.

Brief Description of the Drawings

[0024] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings briefly described herein. The figures illustrate various stages of the apparatus, structure, and related methods of the present invention.

[0025] [Figure 1] A block diagram of a semiconductor chip (chip) comprising a front-side power / ground distribution grid, a device layer, a polished-side power / ground distribution grid, i.e., a device layer having dual power / ground / signal supply / distribution from both the top / back and bottom / front of the chip's device layer.

[0026] [Figure 2] A block diagram of a chip comprising front-side and polished-side dual power / ground / signal distribution grids having a semiconductor input power layer including power through silicon vias (PTSV).

[0027] [Figure 3]This is a block diagram of a chip that includes a semiconductor input power layer containing through-pass silicon vias (PTSVs), a cover, and a dual power / ground / signal distribution network on the front and polished sides with a heatsink.

[0028] [Figure 4] This chart shows the stages of the process for creating a chip equipped with a power / grounding distribution network on both the front and polishing surfaces, along with block diagrams of the structures created during each process stage.

[0029] [Figure 5] This is a block diagram of one embodiment of a chip that includes a front-side and polishing-side power / grounding / signal distribution network, in which an external power supply is brought from the circuit board to the polishing-side power / grounding distribution network through one or more wire joint connections.

[0030] [Figure 6A] Figure 5 is a cross-sectional elevation view of one embodiment, showing a notch in the lid for accommodating wire joint connections.

[0031] [Figure 6B] Figure 6A is a top cross-sectional view of the structure shown.

[0032] [Figure 7] This chart shows the stages of the process for creating one embodiment of a chip equipped with a power / ground / signal distribution network on the front and polished sides, mounted on a substrate, along with block diagrams of the structures created during each process stage.

[0033] [Figure 8] This figure shows a chip module comprising a chip having a dual power / ground / signal distribution network on the front and polished sides, mounted on a first substrate (which later becomes the top external power distribution conduit), and having one or more vertical / side external power distribution conduits, and a chip module comprising a chip having a dual power / ground / signal distribution network on the front and polished sides, mounted on a second substrate, and having one or more vertical / side and top external power distribution conduits.

[0034] [Figure 9A] This is a cross-sectional elevation view of a chip module in which one or more vertical / lateral external power distribution conduits enclose / surround one or more chips on three or more sides.

[0035] [Figure 9B] This is a top view of Figure 9A.

[0036] [Figure 10] This is a cross-sectional elevation view of a chip module having one or more vertical / side external power distribution conduits that are metal conductors.

[0037] [Figure 11] This is a flowchart showing the process for manufacturing and assembling chip modules. [Modes for carrying out the invention]

[0038] Embodiments of the present invention are not limited to the exemplary methods, apparatus, structures, systems, and devices disclosed herein, but are instead more broadly applicable to other alternative and broader methods, apparatus, structures, systems, and devices that will become apparent to those skilled in the art to whom this disclosure is given.

[0039] Furthermore, it should be understood that the various layers, structures, or regions, or combinations thereof, shown in the attached drawings are not drawn to scale, and one or more commonly used types of layers, structures, or regions, or combinations thereof may not be explicitly shown in the given drawings. This does not imply that layers, structures, or regions, or combinations thereof that are not explicitly shown are omitted from the actual device.

[0040] Furthermore, if a description does not necessarily focus on a particular element (such as a device or component), such elements may be omitted and excluded from the display for clarity, conciseness, or both. In addition, identical or similar reference numbers used throughout the drawings are used to indicate identical or similar features, elements, or structures, and therefore, detailed descriptions of identical or similar features, elements, or structures may not be repeated in each drawing.

[0041] The semiconductor devices, structures, and methods disclosed in accordance with embodiments of the present invention can be employed in a variety of applications, hardware, or electronic systems, or combinations thereof. Preferred hardware and systems for carrying out embodiments of the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, mobile communication devices (e.g., mobile phones and smartphones), solid-state media storage devices, expert and artificial intelligence systems, functional circuits, and neural networks. Systems and hardware incorporating the semiconductor devices and structures are intended as embodiments of the present invention.

[0042] As used herein, “height” refers to the vertical size of an element (e.g., layer, groove, hole, opening, etc.) in a section or elevation view, measured from the bottom to the top of the element, or measured relative to the surface on which the element is located, or both.

[0043] Conversely, "depth" refers to the vertical dimension of an element (e.g., a layer, groove, hole, or opening) measured from its top to its bottom surface in a cross-sectional or elevation view. Where indicated, terms such as "thickness," "thickness," or "thinness," or their derivatives, may be used instead of "height."

[0044] As used herein, “lateral,” “lateral,” “side,” and “lateral face” refer to the left or right side of an element (e.g., a layer, an opening, etc.) in a drawing, or the position of a first element relative to the side of a second element.

[0045] As used herein, “width” or “length” refers to the size of an element (e.g., a layer, groove, hole, opening, etc.) in a drawing, measured from one side to the opposite side. Where indicated, terms such as “thickness,” “slimness,” or “thinness,” or their derivatives, may be used instead of “width” or “length.”

[0046] As used herein, terms such as “top,” “bottom,” “right,” “left,” “vertical,” “horizontal,” “top,” and “bottom,” and their derivatives, refer to the disclosed structures and methods as they are oriented in the figures being depicted. For example, as used herein, “vertical” refers to a direction perpendicular to the top surface of the substrate in an elevation view, and “horizontal” refers to a direction parallel to the top surface of the substrate in an elevation view.

[0047] As used herein, unless otherwise specified, terms such as “on top of,” “covering,” “on the top of,” “located at the top,” or “located above” mean that the first element is on top of the second element, and there may be intervening elements between the first and second elements. As used herein, unless otherwise specified, terms such as “on top of,” “covering,” “on the top of,” “located above,” or “located at the top of,” or the term “displaced on top,” or the term “contact” or “direct contact” mean that the first and second elements are connected without any intervening elements present between the first and second elements, such as an intermediate conductive layer, an insulating layer, or a semiconductor layer.

[0048] It should be understood that these terms may be affected by the orientation of the described device. For example, if the device is rotated upside down, the meaning of these descriptions may change, but the descriptions remain valid as they describe the relative relationships between the features of the invention.

[0049] Disclosed are efficient and reliable semiconductor structures and circuits, semiconductor chips (chips), and chip modules for distributing power / ground / signals between one or more chips, or a combination thereof, inside or outside of them.

[0050] Embodiments of the present invention provide internal and external power distribution to the chip from two directions, namely, 1. a bottom power source from the front side of the chip via a conventional BEOL or front-side power distribution network, and 2. a top power source from the rear side or polishing side of the chip via a new polishing-side power distribution network. Distribution of grounding connections through both the front-side and polishing-side power distribution networks is also possible in some embodiments, as is signal connections.

[0051] The polishing surface-side power distribution network increases the number of power / ground connection points to the device layer, improves the efficiency of power / ground interconnection routing to the device layer (via the polishing surface), and improves power distribution I 2 This reduces R loss and frees up space for additional connections in the conventional BEOL metallization layer on the front side of the chip.

[0052] Furthermore, this dual power supply / distribution technology (power / ground distribution through both the front-side distribution network and the polished surface-side distribution network) also contributes to the connection efficiency of certain technologies using devices such as complementary field-effect transistors (CFETs). When connecting nFETs and pFETs, more efficient wiring can be achieved if connections can be made on two sides of these devices (bottom and top sides), or by connecting power from one chip side (top or bottom side) with power from the other chip side (bottom or top side), or both.

[0053] Furthermore, by connecting one or more power connections in the front-side power distribution network to one or more power connections in the polishing surface-side power distribution network, power can be supplied from both external power sources, such as a chip-top external power connection and a chip-bottom external power connection, thereby increasing the reliability of the power distribution. This can be achieved by using one or more external power distribution conduits, conductive pillars, or posts, or other connections, or a combination thereof.

[0054] A manufacturing method is disclosed that enables the construction of a power distribution network on the polishing surface side and dual power / grounding / signal connections to the chip.

[0055] Figure 1 is a block diagram of an embodiment 100 of a semiconductor chip (chip) comprising a front-side power supply / grounding distribution network 125, a device layer 150, and a polished surface-side power supply / grounding distribution network 175, i.e., a device layer 150 having dual power / grounding supply / distribution 125 / 175 from both the top / back 154 side and the bottom / front 152 side of the device layer 150 of the chip 100.

[0056] The chip 100 has one or more bottom external connections 110. In some embodiments, the bottom external connections 110 are C4 connections or metal pads, or a combination thereof (not shown). Some of the one or more bottom external connections 110 are connected to power supply or distribution connections, or both, in the front power supply / grounding distribution network 125. These bottom external connections are also referred to as bottom external power connections 110. One or more other parts of the bottom external connections 110 are connected to external ground connections, or ground connections within the front power supply / grounding distribution network 125, or a combination thereof. These bottom external connections are referred to as bottom external ground connections. In some embodiments, one or more of the bottom external connections 110 can be used as signal connections that pass through the front power supply / grounding distribution network 125 and connect to device signal connections.

[0057] The front power grid layer 125 has one or more front layers. Part of the front layers includes one or more front power connections 130. Generally, these front power connections 130 extend horizontally through the front power grid layer 125. The front power connections 130 can extend at different heights within the front power grid layer 125. For example, thicker / larger distribution connections 130 distribute power and are generally located in the upper layers of the front power grid layer 125, i.e., further away from the device layer 150. On the other hand, finer front connections 120, which are typically used for signaling, control, or data transmission, or a combination thereof, are typically found at lower levels of the front power grid layer 125, closer to the device layer 150.

[0058] Similarly, the grounding connections 120 / 130 can extend horizontally at different heights within the front power grid layer 125. A portion of the front grounding connections 120 / 130 connects to a common / grounding connection or a bottom external grounding connection 110 within the device layer 150, or a combination thereof.

[0059] One or more of the horizontal layers 120T of the front-side power grid layer 125 are the top layer 120T of the front-side power grid 125, or are close to the top layer 120T. This top front-side layer 120T is easily interfaced with the bottom surface 152 of the active layer 150.

[0060] Some embodiments of the front-side power grid layer 125 have rails 120R. Rails 120R are power connections 120R in the front-side power grid layer 125 that distribute power to the device layer 150, but rather than being at the upper level, the rail 120R connections are located in the lower level layers of the front-side power grid layer 125, closer to (or even within) the active layer 150. The “embedded power rails” included in layer 150 can also draw power from vias (e.g., device vias) 155.

[0061] In some embodiments, the front-side power grid layer 125 has one or more redistribution layers (RDLs). The RDLs are extra metal layers that facilitate access to, or connection to, some of the external connections 110, or both.

[0062] Furthermore, the front power grid layer 125 also has vertically extending vias (not shown) that make connections between horizontal layers and, if necessary, other connections.

[0063] In Figure 1, power and earth connections are indicated by the same reference numbers 120 / 120R / 120T / 130, and it should be noted that any external power and earth connections that may be connected to them, such as the C4 connection 110, are indicated by the same reference numbers without loss of generality. In some embodiments, signal connections are also designated by the same reference numbers. Those skilled in the art who have been given this disclosure will know, by convention, how to electrically isolate power connections from earth connections (and signal connections).

[0064] The device layer 150 has multiple devices 140 (including device via connections 155) or 127, typically 140. In some embodiments, the devices 140 are located on the bottom surface 152 of the device layer 150. The device vias 155 are used to connect device signals and device ground connections through the device layer 150 to the top and back / polished surface sides 154 of the device layer 150.

[0065] One or more of the devices 140 may have one or more device power connections, device signal connections, device ground connections, etc. Non-limiting examples of devices 140 include active and passive components. Non-limiting examples of active components include transistors, field-effect transistors (FETs), bipolar junction transistors (BJTs), diodes, energy sources, batteries, sensors, etc. Typically, an active device 140 has one or more device power connections and (not shown, but well known) device ground connections. Non-limiting examples of passive devices 140 include resistors, capacitors, and inductors.

[0066] The device layer has a front side 152 and a back / polished side 154. The front side 152 of the device layer is above the top surface 153 of the front power grid layer 125 and is attached to that top surface 153. One or more of the power connections 120 / 120R / 120T / 130 of the front power grid layer are electrically connected to one or more of the power connections (not shown) of the device 140, and one or more of the ground connections 120 / 120R / 120T / 130 of the front power grid layer are electrically connected to one or more of the device ground connections. In some embodiments, the device signal connections are also connected to the front signal connections in the front power grid layer 125.

[0067] The polishing surface-side power grid layer 175 is located above the back / polishing surface side 154 of the device layer 150 and has a bottom surface 156 attached to that back / polishing surface side 154. Thus, the polishing surface-side power grid layer 175 is on / attached to the back / polishing surface side 154 of the opposite device layer 150, beyond the front side 153 of the device layer 150 to which the front-side power grid layer 125 is attached.

[0068] The polishing surface side power grid layer 175 has one or more polishing surface side layers 170 / 180 / 165, including the bottom / bottom polishing surface side layer 165. The bottom polishing surface side layer 165 is located above and attached to the back / polishing surface side 154 of the device layer 150.

[0069] One or more of the polishing surface side layers 165 / 170 / 180 have one or more polishing surface side power connections, e.g., 165 / 170 / 180. As already stated, one or more of these polishing surface side layers, e.g., connections 165 / 170 / 180, function as common / ground connections (or signal connections) depending on the wiring method of the connections. One or more of the polishing surface side power connections are electrically connected to one or more of the device power connections, and one or more of the polishing surface side ground connections are connected to one or more of the device ground connections. In some embodiments, device signal connections are made.

[0070] The polishing surface-side power grid layer 175 has one or more top external connections 195. One or more of these top external connections 195 can be used as top external power connections 195. Similarly, one or more of the top external connections 195 can be used as top external ground (signal) connections 195. The designation of the top external connections 195 conforms to the type of connection made so as not to lose generality.

[0071] One or more of the top external power connections 175 are connected to one or more of the polishing-side power connections / layers 165 / 170 / 180 or the power connections of device 140, or a combination thereof. One or more of the top external ground connections 175 are connected to one or more of the polishing surface-side ground connections 165 / 170 / 180 or the ground / common connection of device 140, or a combination thereof.

[0072] Therefore, one or more of the power connections of device 140 may be connected to at least one of the bottom external power connections 110, at least one of the top external power connections 195, or to both one or more of the bottom external power connections 110 and one or more of the top external power connections 195. One or more of the device ground connections may be connected to one or more of the bottom external ground connections 110, one or more of the top external ground connections 195, or to both one or more of the bottom external ground connections and one or more of the top external ground connections.

[0073] It should be noted that in some embodiments, the top external power / ground connections 195 are electrically insulated from each other by an insulating material 190, for example, by being embedded in or surrounded by an insulating material forming the top external connection layer 190, or both. This insulating material 190 can be a polymer, a dielectric, or other electrical insulating material. In some embodiments, the insulating material 190 is thermally conductive. In some embodiments, the insulating material 190 is a dielectric such as silicon nitride (SiN), silicon dioxide (SiO2), or silicon carbonitride (SiCN) deposited by known methods.

[0074] In some embodiments, the additional layer is attached to the top external connecting layer 190, as described below.

[0075] By having power / ground connections from both the front-side power grid layer 125 and the polishing surface-side power grid layer 175, power and ground connections to, from, or a combination thereof for each device are routed and connected more efficiently, shortening connections. 2 This reduces R loss and allows for a wider connection space.

[0076] Note that vertical connections in the device layer 150 are made using device vias 155. Vias (not shown) can also be used to make vertical connections between, for example, the horizontal layers 120 / 120R / 120T / 165 / 170 / 180 in the front-side power grid layer 125 and the polishing surface-side power grid layer 175.

[0077] Furthermore, it should be noted that in some embodiments, signal, control, and data connections can pass through the front-side power grid layer 125 or the polishing surface-side power grid layer 175, or both, to connect to similar connections on the device or external connections 110 / 195, or both.

[0078] Figure 2 is a block diagram of one embodiment of a chip 200 having a semiconductor input power layer 250 including one or more power through-silicon vias (PTSVs) 292, and a dual power / grounding distribution network 125 / 175 on the front side 125 and the polished side 175.

[0079] In some embodiments, the semiconductor input power layer 250 is constructed to have one or more power vias 292 and one or more power via top conductive caps or pads 296, along with a pad 295. Layer 190A is a “mirror image” of layer 190 in that its conductive portions, e.g., pads 195 and 295, are located on opposite sides of each other and are made of a compatible conductive material, e.g., copper. Similarly, the dielectric (or electrically insulating portion of layers 190 and 190A) are located on opposite sides of each other and are made of a compatible conductive material. (Being located on opposite sides of each other means that the combination of layers 250 and 190A is positioned facing layer 190 along interface 291, and layers 190 and 190A are joined together, e.g., hybrid joined, to form layer 290 which includes fused and electrically continuous pads 195 and 295 electrically separated by a continuous and electrically joined electrical insulating material 190 / 190A).

[0080] Embodiment 200 of this chip exhibits various layer dimensions. For example, the front-side power / grounding distribution network 125 has a front-side thickness 225 between 3 micrometers (μm) and 5 μm. The active region 150 has an active region thickness 252 between 0.3 μm and 1 μm, or approximately 0.5 μm. The polishing-side power / grounding distribution network 175 has a polishing-side thickness 275 between 3 μm and 5 μm, and the top external connection layer 290 has a top external connection layer thickness 293 between 1 μm and 3 μm, typically 2 μm. The bottom external connection thickness 210 of the bottom external connection 110 is between 40 μm and 100 μm. The thickness of the semiconductor input power layer 250 is between 50 μm and 400 μm.

[0081] The semiconductor input power layer 250 is made of a non-conductive material. In some embodiments, the semiconductor input power layer 250 also has thermal conductivity. In some embodiments, the semiconductor input power layer 250 can be an undoped semiconductor material such as polymer, silicon, or amorphous silicon. Dielectric materials as described above can also be used.

[0082] The power via conductive pad 295 is positioned on the top external connection 195, and the bottom of the power via 292 is electrically connected to the top external connection 195. The power via top conductive cap or pad 296 is electrically connected to the top of the power via 292. The power via 292 enables the supply of power from an external power source of the chip 100 / 200 to the polishing surface side power / grounding distribution network 175 and the conductive layers 165 / 170 / 180 within the polishing surface side power / grounding distribution network 175.

[0083] Power vias 292, power via conductive pads 295, and power via top conductive caps / pads 296 are made of conductive material, typically a metal such as copper.

[0084] Figure 3 is a block diagram of an embodiment 300 of a chip having a dual power / grounding distribution network 125 / 175 on the front side 125 and the polished side 175, which includes a semiconductor input power layer 250 containing through-silicon power vias (TSPVs) 292, a cover 390, and a heat sink 350.

[0085] The lid 390 is made of a thermally conductive material such as copper or aluminum and structurally contains the internal components of the chip 300, functioning as a sealing layer that seals in external contaminants from the internal components of the chip 300. The lid 390 also conducts heat from the internal components of the chip 300, for example, from the device 140, through the semiconductor input power layer 250, and then to the surrounding environment, for example, through the heat sink 350.

[0086] In some embodiments, there are sealed through-holes that penetrate the lid 390, allowing for continuity of electrical contacts from internal devices 140 of the chip 300 and from external signals, ground, or power connections, or a combination thereof. For example, one or more lid conductive pads 392 on the bottom surface of the lid are positioned to electrically connect to the top of a power via 292 or a power via top conductive cap or pad 296, or both. In some embodiments, a lid via 394 is electrically connected to a lid conductive pad 392 and passes through the lid 390. Due to the electrically conductive properties of some embodiments of the lid 390, the lid conductive pads 392 and lid vias 394 are electrically insulated 352 from the lid 390 material, i.e., the lid 390 is insulated from the lid vias 394 and lid conductive pads 392 by a dielectric or insulating sleeve 352.

[0087] The electrical insulation properties of the semiconductor input power layer 250 and the top external connection layer 290 also electrically insulate the lid 390 from the polished surface side power / grounding distribution network 175 while maintaining conductivity through the lid vias 394 and lid conductive pads 392. In some embodiments, the lid 390 is attached to the semiconductor input power layer 250 using a thermal conductive material (TIM).

[0088] The heatsink 350 is thermally and mechanically attached to the surface of the lid by known methods, e.g., by a TIM such as thermal grease. In some embodiments, an opening 325 is formed through the heatsink 350 to allow external wiring / connections and other conductive paths described to connect external circuits to the lid via 394 via the heatsink 350, thereby completing the connection of power, ground, signal, control or data, or a combination thereof, to the device 140. The opening in the heatsink 350 is insulated 326 with a dielectric or other electrical insulating sleeve 326 so that the external wiring / connections do not electrically short-circuit with the heatsink 350. Other connections that allow conductive / connections to the device 140 through the heatsink 350 are also conceivable.

[0089] Figure 4 is a chart showing the steps of process 400 for making a chip, typically 100, or an embodiment 100 / 200 / 300 of a chip having a power / grounding distribution network 125 / 175 on the front side 125 and the polishing side 175, or a combination thereof. Block diagrams of the structures (structures / stages 4A, 4B, 4C, 4D, 4E, 4F, and 4G) made in the stages during process 400 are shown.

[0090] In some embodiments, process 400 begins in step 480 with structure 4A. Structure 4A has, for example, a front-side power / grounding grid 125 formed by a BEOL process, and a device layer 150 mounted on and above the front-side power / grounding grid 125. These structures are known in the art. Often, these structures 125 / 150 are fabricated on a silicon wafer or a semiconductor substrate such as a substrate 410. An etching stop layer 415, such as an oxide or nitride layer, can be placed between the wafer / substrate 410 and the device layer 150 by known processes such as FEOL and BEOL processes.

[0091] In step 482, the wafer / substrate 410 is removed 420, for example, by chemical mechanical polishing (CMP) to expose the etching stop layer 415 in structure 4B.

[0092] The construction of the polishing surface-side power / grounding distribution network 175 is facilitated by the use of a handler 425. Structure 4B is mounted to the handler 425. The handler 425 is typically a thick, strong, and rigid substrate 425, such as glass or silicon, that provides support, structure, rigidity, and mobility to structure 4B throughout some of the stages / steps (4C, 4D, and 4E) of process 400.

[0093] In step 484, after removing the etching stop layer 415, the polished surface-side power / grounding grid 175 is constructed on the device layer 150. Conductive layers 165 / 170 / 180, top external connections 195, vias, and other layers and components are formed on the polished surface-side power / grounding grid 175 using the same materials and methods as those used to form the front-side power / grounding grid 175. However, the sizing, orientation, and location of these conductive layers 165 / 170 / 180 and external contacts are dictated by design constraints on the polished surface-side power / grounding grid 175.

[0094] For example, in some embodiments, the device 140 remains on the front side 152 of the device layer, and the connection to the back / polished side 154 of the device layer 150 is made through the device via 155.

[0095] In some embodiments, the etching stop layer 415 is removed by a chemical treatment, such as reactive ion etching (RIE) using chemistry to selectively remove the material of the etching stop layer 415. Removal of the etching stop layer 415 exposes device power and ground connections, such as through-silicon vias (TSVs) (including nanoTSVs, nTSVs, and / or associated pads / connections, or nanopads having a thickness of 50-100 nanometers (nm)).

[0096] In step 486, using known methods, the top external connection layer 190 is formed on the polished surface side power / grounding distribution network 175 together with the top external connection 195 and dielectric insulating material 190 to form structure 4D.

[0097] In step 488, as described above, structure 4E is formed by forming / arranging the semiconductor input power layer 250 and the top external connection layer 290 together with power through silicon vias (PTSVs) 292 and power via top conductive caps or pads 296. Planarization or CMP is performed to flatten the surface. Known bonding techniques, such as hybrid bonding, are performed to ensure correct continuous conductivity between the external device connection 296 and between the top external connection 195.

[0098] At stage 490, the structure 4F is strong enough to be handled without the handler 425, so the handler 425 is removed. The handler 425 can be removed by reversing the mounting method, for example, by chemically dissolving the adhesive used to attach the handler. Note that if the structure is not strong enough to withstand the attachment of the external connection 110, a temporary handler (not shown) can be attached to the top surface of layer 250.

[0099] Typically, after the handler 425 is removed, the bottom external connection 110 is formed using known techniques. Examples of the external connection 110 include a C4 connection or a metal pad (not shown), or both.

[0100] In step 492, typically after the formation of the bottom external connection 110, the structure 490 is positioned on the substrate 405 and attached to the substrate 405 by, for example, soldering the C4 connection, or by other electromechanical connections to contacts (not shown) on the substrate 405, or a combination thereof. Thus, the bottom external connection 110 is physically and electrically attached to the substrate / laminated structure 405, for example, through the C4 junction.

[0101] In step 492, the cover conductive pads 392 and cover vias 394 are then aligned with the power pass-through silicon vias (PTSVs) 292, and the cover 390 is typically mounted on top of the semiconductor input power layer 250 while maintaining electrical conductivity with the device connections of the polished surface side power / grounding distribution network 175.

[0102] Furthermore, in step 492, structure 4G is formed by attaching the heat sink 350 to the top surface of the lid 390 as described above. In embodiments with an opening 325, alignment of the opening 325 of the heat sink 350 is necessary to provide a connection path to the lid via 394 or the lid conductive pad 392, or both.

[0103] It should be noted that the lid 390 is shown in the drawings as a flat layer / plate for simplicity. However, other instances of the lid 390 are also conceivable. For example, throughout this disclosure, the lid 390 may be a top layer / plate having one or more “legs” that extend downward from the top layer / plate and are attached to and thermally connected to the substrate 405. These legs provide additional heat pathways from the substrate 405 through the top surface of the lid 390 to the heat sink 350. In some embodiments, the legs (not shown) of the lid 390 may partially encompass or surround the structure 490. The lid 390 having legs is known as described above.

[0104] The substrate 405 can have a substrate thickness of 405T between 0.7 mm and 2 mm. The substrate 405 provides external ground, power, signal, data, or control connections and routing, or a combination thereof, to the chip 100 / 200 / 300. The substrate 405 provides a base mechanical support for the chip and provides connections to larger system components, such as a panel backplane.

[0105] In some embodiments, the substrate 405 is a package substrate 405 such as a multilayer substrate 405 (hereinafter also referred to as 405L). The multilayer substrate 405 can be made of multiple materials such as ceramic, plastic, or resin-based materials. The substrate can be either a double-sided substrate or a multilayer substrate, which are well known in the semiconductor industry. Other substrates and substrate materials 405, such as semiconductor substrates 405S, are conceivable. See, for example, the substrate 405S described below.

[0106] Figure 5 is a block diagram of one embodiment of a chip 100 / 200 comprising front-side 125 and polishing-side 175 power / grounding networks 125 / 175, where an external power supply is brought to the polishing-side power / grounding network 175 through one or more wire joint connections 550. The wire joint connections 550 are connected from one or more substrate power connections 596 on the substrate 405 to a power via top conductive cap or pad 296 or other top external connection 195. The size of the wire joints 550 can be relatively large so that a large amount of current can be supplied from the substrate 405 to the polishing-side power / grounding network 175 without going through the chip, e.g., 100. Wire jointing methods are well known.

[0107] Figure 6A is a cross-sectional elevation view of an embodiment 500, including a notch 675 (in a partial perspective view) in the cover 390 for housing the wire joint connection 550, as shown in Figure 5. The notch 675 allows the wire joint to be attached to the power via a power via top conductive cap or pad 296 either before or after the cover 390 is attached, without the cover 390 interfering with the attachment of the wire joint 550.

[0108] In Figures 5 and 6A, one preferred embodiment of the substrate 405 is the organic substrate 405 / 405L described above.

[0109] Figure 6B is a top cross-sectional view 650 that penetrates section 655 of the structure shown in Figure 6A. Figure 650 shows the top of the power via top conductive cap or pad 296, wire bond 550, and one or more board power connections 596.

[0110] As mentioned above, it should be noted that the lid 390 shown in Figures 6A and 6B may have "legs".

[0111] Figure 7 is a chart showing the steps of process 700 in one embodiment for mounting a chip, e.g., 100, onto a substrate 405 / 405S to form a module, e.g., structures 7B and 7C, along with block diagrams of the structures (7A, 7B, 7C) at different stages of the process. The chip 100 has a front side 125 and a polished side 175 power / grounding distribution network 125 / 175.

[0112] Process 700 begins in step 770 by forming a structure 7A on which one or more embodiments of the chip, e.g., 100, 200, 300, etc., are attached to a handler or carrier 725. The carrier 725 and the attachment of the carrier 725 to the chip are known. Note that the bottom external connection 110 is shown as an embodiment of a metal pad 110. In some embodiments, the carrier 725 is attached to the front side 125 of the chip 100.

[0113] To form structure 7B, step 780 of process 700 performs step 750 of inverting, positioning, and placing the chip 100 on the (first) substrate 405 / 405S, where the top external connection 195 is electrically connected to the associated substrate connection 596 on the substrate 405 / 405S, and the substrate connection 596 is beneath the chip 100. Note that in a preferred embodiment, a carrier 725 is used to "invert" or rotate the chip so that the top external connection 195 is aligned with and electrically connected to the substrate connection 596.

[0114] It should be noted that the preferred substrate 405 / 405S in this embodiment is the (first) substrate 405S made of a semiconductor material, for example, silicon.

[0115] In some embodiments, there is one or more board connections 705 within the (first) board 405 / 405S. Some of these internal board connections 705 connect board connections 596 below the chip 100 to one or more board connections 596 / 597 that are accessible on board 405 / 405S and are located below the chip 597 to the outer board connections 596 / 597. Note that in some embodiments, the board power connections 596 / 597 and internal board connections 705 can be used to connect to ground, signal, control, or data connections, or a combination thereof.

[0116] In step 790, structure 7C is formed by removing the handler or carrier 725 using the known techniques described above. Structure 7C typically has one or more chips (here, at the top of structure 790, "inverted" upwards) 100, with one or more top external connections 195 connected to internal board connections 705 through board power connections 596, while exposing the bottom external connection 110. The board connections 596 below chip 100 are connected by the internal board connections 705 to one or more board connections 596 / 597 that are accessible from the top of the (first) board 405 / 405S rather than below chip 100, so that one or more of these board power connections 596 are connectable to other components on the surface of the board 405 / 405S.

[0117] Figure 8(A) shows a chip module 800 comprising a chip, typically 100, having one or more vertical / side external power distribution conduits 825, and a first substrate 405S, for example, a front-side 125 and polished-side 175 dual power / grounding distribution network 125 / 175 mounted on the (first) semiconductor substrate 405S, which later becomes a top external power distribution conduit 875 bridge. In this embodiment, the first semiconductor substrate 405S is oriented such that the chip, typically 100, is "inverted / rotated", as shown in Figure 7C.

[0118] In some embodiments, the vertical / lateral external power distribution conduit 825 is made of a non-conductive material, such as an undoped semiconductor (silicon) or dielectric. The vertical / lateral conduit 825 has conduit connections 830 made of a conductive material, such as metal or copper. The vertical / lateral conduit connections 830 can penetrate the vertical / lateral conduit 825 vertically, for example, from the top to the bottom of the vertical / lateral conduit connections 830. Conduit connections 110C, such as C4 or a conductive / metal pad, or a combination thereof, can make external connections to the conduit connections 830.

[0119] Some embodiments of the vertical / lateral conduit 825 may have internal electrical interconnects and / or active or passive devices (not shown).

[0120] Embodiments of the vertical / lateral conduit 825 are electrically attached to the (first) substrate 405 / 405S on one or more sides (or possibly around) of the chip 100. Connections are made between the conduit connection 830 of the vertical / lateral conduit 825 (inside the conduit 825, not shown) and the substrate power connection 597, for example, through a conduit connection, typically 110C. Thus, connections between the bottom and top of the vertical / lateral conduit 825 are effective for power, ground, signal, control, or data, or a combination thereof, between the bottom and top of the vertical / lateral conduit 825 and in / near the chip bottom 110 and top 195 / 295 / 296 external connections of the chip 100.

[0121] Figure 8(B) shows a chip module 850 having a chip, typically 100, as shown in Figure 8(A), and a dual power / grounding distribution network 125 / 175 including a front side 125 and a polished side 175. The chip 100 is mounted to a second substrate 805L, e.g., a laminate substrate 805L / 405L, along with one or more vertical / side conduits 825. One or more top external power distribution conduit 875 bridges (formerly the first substrate 405S) provide connections on top of the chip 100. Note that the first substrate 405S becomes (one or more) top external power distribution conduit 875 bridges and will be referred to as such.

[0122] To form the chip module 850 structure in Figure 8(B), structure 800 is moved and inverted / rotated 855 such that the bottom external connection 110 (which is now inverted again to face downward, i.e., toward the second substrate 805L) and the contact 110D of the vertical / side conduit 825 opposite to the first substrate 405S align with the contact on the second substrate 805L and make electrical connection.

[0123] Therefore, after this inversion / rotation 855, the first substrate 405S becomes the top external power distribution conduit 875 / 405S, and the new, second substrate 805L (or substrate 805L) is supported and mounted as the bottom of module 850 (as shown in Figure 8(B)).

[0124] As described above, the top external power distribution conduit 875 / 405S can be made of the same material as the vertical / side conduit 825, for example, a non-conductive semiconductor, dielectric, or insulator. The top external power distribution conduit 875 also has top internal conduit connections 705 that connect two or more top external conduit connections 807. Again, the top external conduit connections 807 can be connected to vertical / side external conduit connections 110C or other connections, or a combination thereof, for example, top external connections 195 / 295 / 296.

[0125] Accordingly, the top power distribution conduit 875 bridges over the chip 100 / 200 and, in combination with the vertical / side conduit 825, provides connections / interconnections between the front side 125, polished side 175 power / grounding distribution network 125 / 175, the chip top external connections 195 / 295 / 296, or the board power connections 597, or a combination thereof.

[0126] Accordingly, the chip module embodiments 800 / 850 can use vertical / side conduits 825 and top distribution conduits 875 to provide additional or redundant connections, or both, resulting in shorter, easier wiring and less power loss.

[0127] Figure 9A is a cross-sectional elevation view of one embodiment 850 of a chip module 900 as seen through cross-section 901 (Figure 9B), showing that one or more vertical / side external power distribution conduits 825 enclose or surround one or more chips 100 / 200 on three or more sides 921.

[0128] An embodiment of a chip module of one or more chips 100 / 200, for example 850, is disposed connected to a substrate 805L as described above, having two or more vertical / lateral conduits 825 around the chips 100 / 200 on its side 921, while being bridged by one or more top conduits 875. The vertical / lateral conduits 825 and the top conduits 875 are arranged such that the chips 100 / 200 are partially or completely enclosed (surrounded) by the conduits 825 / 875, forming a partially or completely enclosed module 900 / 950.

[0129] In an alternative embodiment, the heatsink 350, and optionally the cover 390, would be mounted on the top surface of the top conduit 405S. The heatsink 350 / cover 390 may be necessary if the heat generated by the chip, e.g., 100, is significant, as can occur when power is supplied to both the top and bottom of the chip 100. Not shown, the heatsink 350 / cover 390 may be mounted on the top surface of the top conduit 405S in Figures 8(B), 9A, and 10, for example, by TIM.

[0130] Figure 9B is a top view 950 of Figure 9A. In the shown embodiment 950, the top view of the chip 100 / 200 is shown in local perspective below (through) the top distribution conduit 875, and, for example, the chip side of the chip 100 / 200, typically 921, is shown in local perspective. In this embodiment, a single top distribution conduit 875 covers the entire module 900 / 950. The side 951 of the internal vertical conduit 825 of the vertical / side conduit 825 is also shown in local perspective.

[0131] As can be seen, in Figure 9B, the entire top surface of the top distribution conduit 405S / 875 is visible. In addition to what is shown in the local perspective view of tip 100 / 200, the side 951 of the vertical / lateral conduit 825 is visible in the local perspective view 951, and the top surface of the vertical / lateral conduit 825 is also visible in the local perspective view. This embodiment shows that the vertical / lateral conduit 825 encloses tip 100 / 200 with a sufficient portion of the tip side 921 so that tip 100 / 200 is completely surrounded by the vertical / lateral conduit 825.

[0132] Structures 900 / 950 having multiple vertical / lateral conduits 825 that enclose or surround chips 100 / 200 provide more connectivity access to chips 100 / 200 and provide a stronger module 100 / 200.

[0133] Figure 10 is a cross-sectional elevation view of a chip module 1000 having one or more vertical / side external power distribution conduits 1030 which are metal conductors 1030.

[0134] As described above, this embodiment 1000 comprises one or more top conduits 875 having one or more top conduit internal connections 705 and one or more top conduit external connections 807. These connections 705 / 807 enable greater access, routing, and distribution to the polished surface-side power / grounding distribution network 175.

[0135] However, in this embodiment 1000, power, grounding, and other connections are made between the front-side power / grounding distribution network 125 and the polished-side power / grounding distribution network 175, passing through the vertical / side conduit connections 1030, but the volume of these vertical connections is significantly reduced. In some embodiments, there is little to no material constituting the vertical / side conduits 825 other than the vertical / side conduit connections 1030. This embodiment allows for a lighter structure 1000 and enables more fluid flow around the module 1000 to cool the chips 100 / 200.

[0136] This embodiment of the vertical / lateral conduit connection 1030 can be formed by attaching the top power distribution conduit 875 to the chip 100 / 200 and connecting the associated top conduit external connection 807 and the evaluable board power connection 597. These connections can be made by wire splicing.

[0137] Figure 11 is a flowchart of a process 1100 for manufacturing and assembling a chip, typically 100, which has a dual power / grounding distribution grid 125 / 175 having a front side 125 and a polished side 175.

[0138] Step 1105 initiates process 1100 by forming a device layer 140 on a semiconductor substrate 410, such as a silicon wafer 410, using standard FEOL processes and materials. Next, the front-side power / grounding distribution network 125 is formed on the device layer 140 using standard BEOL processes and materials.

[0139] In step 1110, layers such as the silicon wafer / substrate 410 and the etching stop layer 415 are removed, exposing the back side of the device layer 140.

[0140] In stage 1115, the polishing surface-side power / grounding distribution network 175 is constructed on the back side of the device layer 140.

[0141] In step 1120, the through-power silicon via (PTSV) 292 and other (top) external connections 195 / 295 are formed as needed, for example, in layers 290 and 250. As shown in some embodiments described above, the semiconductor input power layer 250, which includes the through-power silicon via (PTSV) 292 and pads 296 and layer 190A, may not be used.

[0142] In step 1125, a chip, for example 100, is mounted on the substrate 405, and any necessary vertical / lateral conduits 825 or top power distribution conduits 875 or both are installed to make a chip module 800 / 850 / 1000.

[0143] In step 1130, the lid 390 and heatsink 350 are attached as needed. Typically, if the structure, for example 100, is inverted and mounted on a second substrate such as 805L, the lid 390 and heatsink 350 are not attached.

[0144] It should be noted that some of these steps may be performed in a different order or not at all. For example, in some embodiments, the structure 300 may be formed by attaching the lid 390 before the structure 300 is attached to the substrate 405. In some embodiments, steps 1120, 1125, or 1130, or a combination thereof, may be omitted. In alternative embodiments, the structure may be manufactured (and sold as a product) without the heatsink 350 and possibly without the lid 390. See structure 100 / 200. Also see the modules described in Figures 8(A), (B), 9A, and 10, where the substrate / conduit bridge 405S / 875 is attached to structure 100 without the lid 390 or heatsink. As described above, in alternative embodiments, the heatsink 350 and possibly the lid 390 will be attached to the top surface 405S.

[0145] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limit to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments described.

[0146] The terminology used herein has been selected to describe the principles of the embodiments and their practical applications or technical improvements to technologies available on the market, otherwise, those skilled in the art will be able to understand the embodiments disclosed herein. Devices, components, elements, features, apparatus, systems, structures, techniques, and methods described in different terms that perform substantially the same function, operate substantially the same way, have substantially the same uses, or perform similar steps, or combinations thereof, are intended to be embodiments of the present invention.

Claims

1. A semiconductor chip (chip), One or more bottom external connections, wherein one or more of the bottom external connections are bottom external power connections, and one or more of the bottom external connections are bottom external ground connections, A front-side power grid layer, the front-side power grid layer having one or more front-side layers, one of the front-side layers being the top front side, one or more of the front-side layers including one or more front-side power connections and one or more front-side ground connections, one or more of the front-side power connections being electrically connected to one or more bottom external power connections, and one or more of the front-side ground connections being connected to one or more of the bottom external ground connections, At least one device layer, the device layer having a plurality of devices, one or more of the plurality of devices including one or more device power connections and one or more device ground connections, the device layer having a device layer front side and a device layer back polished surface side, the device layer front side is above the top front side layer and attached to the top front side layer, one or more of the front side power connections are electrically connected to one or more of the device power connections, and one or more of the front side ground connections are connected to one or more of the device ground connections, A polishing surface-side power grid layer, the polishing surface-side power grid layer having one or more polishing surface-side layers, one of the polishing surface-side layers being a bottom polishing surface-side layer, the bottom polishing surface-side layer being attached to the back polishing surface side of the device layer and located above the back polishing surface side of the device layer, one or more of the polishing surface-side layers including one or more polishing surface-side power connections, one or more of the polishing surface-side layers including one or more polishing surface-side ground connections, one or more of the polishing surface-side power connections being electrically connected to one or more of the device power connections, and one or more of the polishing surface-side ground connections being electrically connected to one or more of the device ground connections. One or more top external connections, wherein one or more of the top external connections are top external power connections, one or more of the top external connections are top external ground connections, one or more of the top external power connections are connected to one or more of the polishing surface side power connections, and one or more of the top external ground connections are connected to one or more of the polishing surface side ground connections. Equipped with, A chip in which one or more first device power connections are connected to one of the bottom external power connections, one or more second device power connections are connected to one of the top external power connections, and one or more of the device ground connections are connected to one of the bottom external ground connections and one of the top external ground connections.

2. The chip according to claim 1, wherein the front power grid layer includes a plurality of front signal connections, and one or more of the plurality of front signal connections are connected to a device signal connection in one or more of the plurality of devices.

3. The chip according to claim 1 or 2, wherein the polishing surface-side power grid layer includes a plurality of polishing surface signal connections, and one or more of the plurality of polishing surface signal connections are connected to a device signal connection in one or more of the plurality of devices.

4. The chip according to claim 1 or 2, further comprising one or more through-power vias, each of which has a top power via end and a bottom power via end, and one or more of the bottom power via ends of the through-power vias are electrically connected to one or more of the front power connections and one or more of the polishing surface power connections, respectively, so that one or more of the front power connections and one or more of the polishing surface power connections are electrically connected, and one or more of the top power via ends of the through-power vias are electrically connected to one or more of the one or more polishing surface power connections, respectively.

5. The chip according to claim 1 or 2, wherein the bottom external connection is one or more of C4 and conductive pads.

6. The chip according to claim 1 or 2, wherein the top external connection is one or more of C4, conductive pads, and electrically insulated conductive pads in the insulating layer.

7. A circuit board, wherein the circuit board has one or more circuit board connections, and one or more of the circuit board connections are circuit board power connections, A semiconductor chip (chip), wherein the semiconductor chip (chip) is One or more bottom external connections, wherein one or more of the bottom external connections are bottom external power connections, and one or more of the bottom external connections are bottom external ground connections, A front-side power grid layer, the front-side power grid layer having one or more front-side layers, one of the front-side layers being a top front-side layer, one or more of the front-side layers including one or more front-side power connections and one or more front-side ground connections, one or more of the front-side power connections being electrically connected to one or more bottom external power connections, and one or more of the front-side ground connections being connected to one or more of the bottom external ground connections, At least one device layer, the device layer having a plurality of devices, one or more of the plurality of devices including one or more device power connections and one or more device ground connections, the device layer having a device layer front side and a device layer back polished surface side, the device layer front side being above the top front side layer and attached to the top front side layer, one or more of the front side power connections being electrically connected to one or more of the device power connections, and one or more of the front side ground connections being connected to one or more of the device ground connections, and A polishing surface-side power grid layer, wherein the polishing surface-side power grid layer has one or more polishing surface-side layers, one of the polishing surface-side layers is a bottom polishing surface-side layer, the bottom polishing surface-side layer is attached to the back polishing surface side of the device layer and is above the back polishing surface side of the device layer, one or more of the polishing surface-side layers are one or more polishing surface-side power connections, one or more of the polishing surface-side layers are one or more polishing surface-side ground connections, one or more of the polishing surface-side power connections are electrically connected to one or more of the device power connections, and one or more of the polishing surface-side ground connections are electrically connected to one or more of the device ground connections. One or more top external connections, wherein one or more of the top external connections are top external power connections, one or more of the top external connections are top external ground connections, one or more of the top external power connections are connected to one or more of the polishing surface side power connections, and one or more of the top external ground connections are connected to one or more of the polishing surface side ground connections. A semiconductor chip (chip) having Equipped with, A chip module in which one or more first device power connections are connected to one of the bottom external power connections, one or more second device power connections are connected to one of the top external power connections, one or more of the device ground connections are connected to one or more of the bottom external ground connections and one or more of the top external ground connections, and one or more bottom external power connections are connected to one or more of the board power connections.

8. The chip module according to claim 7, wherein the substrate further comprises one or more substrate ground connections and one or more substrate signal connections.

9. The chip module according to claim 7 or 8, wherein one or more of the aforementioned board power connections are connected to one or more of the aforementioned top external power connections.

10. The chip module according to claim 9, wherein one or more of the aforementioned board power connections are connected to one or more of the aforementioned top external connections by wire bonding.

11. The chip module according to claim 9, wherein one or more of the board power connections are connected to one or more of the top external connections by one or more external power distribution conduits.

12. The chip module according to claim 11, wherein one or more of the external power distribution conduits are conductive vertical supports on the sides.

13. The chip module according to claim 12, further comprising a top external power distribution conduit including one or more top internal conduit connections, wherein one or more of the top internal conduit connections are connected to one or more of the top external power connections and one or more of the vertical supports.

14. The chip module according to claim 12, wherein the vertical support columns on the side are one or more of a metal post, a copper post, and a semiconductor post including one or more through-silicon vias (external power supply TSVs).

15. The chip module according to claim 12, wherein one or more of the vertical supports on the side extend to three or more sides of the chip.

16. The chip module according to claim 7 or 8, wherein the substrate is made of one of a laminate, a semiconductor, a laminate having multiple layers, a resin, and a plastic.

17. A method for making a semiconductor chip (chip), wherein the method is A step of forming a device layer on a semiconductor substrate, wherein the device layer has a plurality of devices, one or more of the plurality of devices have one or more device power connections and one or more device ground connections, and the device layer has a front side and a back polishing surface side, A step of forming a front-side power / grounding distribution network on the front side of the device layer, wherein the front-side power / grounding distribution network has one or more front-side power connections and one or more front-side ground connections. The steps include: removing the semiconductor substrate to expose one or more of the plurality of devices on the back polished surface side of the device layer; A step of forming a polishing surface side power / grounding distribution network on the back polishing surface side of the device layer, wherein the polishing surface side power / grounding distribution network has one or more polishing surface side power connections and one or more polishing surface side ground connections. A method that includes [a certain feature].

18. The method according to claim 17, further comprising the step of forming one or more top external connections on the polishing surface side power / grounding distribution network, wherein one or more of the top external connections are connected to one or more of the device power connections through one or more polishing surface side power connections, and one or more of the top external connections are connected to one or more of the device ground connections through one or more of the polishing surface side ground connections.

19. A step of forming one or more bottom external connections below the front power / grounding distribution network, wherein one or more of the bottom external connections are connected to one or more device power connections through one or more front power connections in the front power / grounding distribution network, The steps include electrically connecting one or more of the bottom external connections to one or more board connections on the board, The method according to claim 17 or 18, further comprising:

20. A step of forming one or more top external connections on the polishing surface side power / grounding distribution network, wherein one or more of the top external connections are top external power connections that are connected to one or more device power connections through one or more polishing surface side power connections in the polishing surface side power / grounding distribution network, The step of connecting one or more of the aforementioned substrate connections to one or more of the aforementioned top external connections. The method according to claim 19, further comprising:

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