Semiconductor device package and formation method

Abstract

To provide a semiconductor device package and a method of forming the same.SOLUTION: A semiconductor device package comprises a semiconductor switching device having a body including a first side, and an opposing second side coupled to a substrate. A gate terminal is defined on the first side of the semiconductor switching device body, and has a first side, and an opposing second side facing the semiconductor switching device body. A first gate resistor is disposed on the first side of the gate terminal, and coupled electrically in series with the gate terminal.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly, to semiconductor device packages and methods of forming semiconductor device packages.

Background Art

[0002] Power conversion devices, such as silicon carbide (SiC) power devices, are widely used in conventional electrical systems to convert power from one form to another for consumption by a load. Many power electronics systems utilize various semiconductor devices and components, such as thyristors, diodes, and various types of transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), and other suitable transistors).

Summary of the Invention

Means for Solving the Problems

[0003] The switching behavior of conventional power semiconductor switching devices (e.g., MOSFETs) is controlled by gate capacitance recharge. Gate capacitance recharge is often controlled via a gate resistor disposed in series with the gate terminal of the switching device. The dynamic switching performance (e.g., switching speed) of a semiconductor switching device can be adjusted based on the value of the gate resistor. The gate resistor can affect many other dynamic performance characteristics of the semiconductor switching device, including switching losses, reverse bias safe operating area, and short circuit safe operating area.

Brief Description of the Drawings

[0004] [Figure 1] A cross-sectional view of a semiconductor device package according to various aspects described herein. [Figure 2] A cross-sectional view of another semiconductor device package according to various aspects described herein. [Figure 3] This is an illustrative flowchart illustrating a method for manufacturing a semiconductor device package according to various embodiments described herein. [Modes for carrying out the invention]

[0005] Aspects of this disclosure can be implemented in any environment, apparatus, or method for a semiconductor device package, regardless of the function performed by the semiconductor device.

[0006] As used herein, the term “set” or “set” of elements can be any number of elements, including only one. When introducing elements of the various embodiments of this disclosure, the articles “a,” “an,” and “the” are intended to mean that there is one or more of the elements. The terms “comprising,” “including,” and “having” are intended to mean comprehensive and that there may be additional elements beyond those listed. In addition, it should be understood that any reference to “one aspect” or “an aspect” in this disclosure is not intended to be construed as excluding the existence of additional aspects that incorporate the same enumerated features. For the sake of brevity, the shapes, positions, and alignments of the features disclosed herein are illustrated and described as relatively ideal (e.g., squares, rectangles, and hexagons drawn with features perfectly aligned in straight lines). This can be understood. However, as will be understood by those skilled in the art, process variations and technical constraints may result in designs that are not ideal or have irregular characteristics, but can still be in accordance with this disclosure.

[0007] In addition, terms such as "voltage," "current," and "power" may be used herein, and it will be apparent to those skilled in the art that these terms may be interrelated when describing an electrical circuit or a mode of circuit operation.

[0008] References to all directions (e.g., radial, axial, higher, lower, upward, downward, left, right, lateral, forward, backward, top, bottom, above, below, vertical, horizontal, clockwise, counterclockwise) are used solely for the purpose of identification to aid the reader's understanding of this disclosure and do not impose any limitations, particularly regarding their location, orientation, or application. References to connections (e.g., mounted, coupled, connected, and joined) should be interpreted broadly unless otherwise specified and may include intermediate members between a group of elements and relative motion between elements. Thus, references to connections do not necessarily imply that two elements are directly connected and in a fixed relationship with one another. In non-limiting examples, connections and disconnections may selectively constitute providing, enabling, disabling, etc., electrical connections between the respective elements. In addition, as used herein, “electrical connection” or “electrical coupling” may include wired or wireless connections. Exemplary figures are for illustrative purposes only, and the dimensions, locations, order, and relative sizes reflected in the drawings accompanying this specification may vary.

[0009] As used herein, a controllable switching element or “switch” is an electrical device that may be controllable to switch between a first operating mode in which the switch is “closed” with the intention of transmitting current from an input switch to an output switch, and a second operating mode in which the switch is “open” with the intention of preventing current from being transmitted between an input switch and an output switch. In non-limiting examples, connections and disconnections, such as connections enabled or disabled by the controllable switching element, may be selectively configured such as providing, enabling, or disabling an electrical connection between the respective elements.

[0010] Conventional semiconductor device packages, such as power overlay modules (POLs), typically include a set of semiconductor devices (e.g., MOSFETs) having conductive contacts on two opposing sides (e.g., top and bottom surfaces, respectively). The bottom surface of the semiconductor device is soldered to one side (e.g., the top surface) of a metal insulating substrate layer (e.g., a direct bond copper (DBC) substrate). A dielectric layer is placed on the top surface of the semiconductor device and may be bonded to the device using an adhesive. A metallization layer or conductive layer is typically deposited on top of the dielectric layer through vias or openings defined within the dielectric layer, thereby enabling the metallization layer to electrically connect to the top surface of the semiconductor device through the dielectric layer.

[0011] For example, a semiconductor device can typically include a MOSFET having source and gate terminals formed on the top surface of the semiconductor device. Conventional semiconductor devices can be manufactured with an "in-chip" internal gate resistor located within the semiconductor device chip and coupled to the gate terminal via conductive wires also located within the semiconductor device chip. However, in many cases, different gate resistance values ​​may be desirable depending on the specific application or end use of the semiconductor device. This is typically addressed by semiconductor chip manufacturers by defining multiple MOSFET chips, each having a different gate resistance value and a different part number. However, this approach requires different masking for each chip and incurs increased costs associated with handling additional part numbers, inventory, etc. In some cases, semiconductor device manufacturers have addressed this challenge at the gate driver level by adding separate "off-chip" gate resistors for each die on the power substrate, or for multiple dies. For example, a conventional POL module can typically include separate gate resistors located "off-chip," or in some cases, isolated from the MOSFET. Generally, a metallization layer may be positioned to electrically couple the separate gate resistors to the gate terminals of the MOSFET. In some conventional configurations, a separate gate resistor may be coupled to the gate terminal of the MOSFET via a wire bond or other conductor away from the metallized layer.

[0012] Referring to Figure 1, non-limiting embodiments of the semiconductor device package 10 are shown. The semiconductor device package 10 may include a set of semiconductor devices 12 having a first surface 12a (e.g., a top surface) and an opposing second surface 12b (e.g., a bottom surface). The second surface 12b of a semiconductor device may be coupled to a substrate structure 14 (e.g., the top surface of the substrate structure 14). Each semiconductor device 12 may include a body 13 having a first surface 13a (e.g., a top surface) and an opposing second surface 13b (e.g., a bottom surface). Each semiconductor device 12 may further include a set of first contact pads 31 positioned on the first surface 12a of the semiconductor device and a set of second contact pads 32 positioned on the second surface 12b of the semiconductor device. A first gate resistor 15 may be coupled to at least one semiconductor device 12. For example, the first gate resistor 15 may be coupled to the corresponding first contact pad 31 of at least one semiconductor device 12.

[0013] In the non-limiting embodiment shown in Figure 1, the substrate structure 14 may include an insulating plate 16 (for example, positioned between a first conductive layer 18 (e.g., the top layer) and a second conductive layer 20 (e.g., the bottom layer). The dielectric layer 24 may include a first surface 24a (e.g., the top surface) and an opposing second surface 24b (e.g., the bottom surface). The second surface 24b of the dielectric layer may be positioned on the first surface 12a of the semiconductor device 12. The dielectric layer 24 may define a set of openings 25 extending from the first surface 24a to the second surface 24b of the dielectric layer. A metal interconnect layer 22 (e.g., a copper trace) may include a first surface 22a (e.g., the top surface) and an opposing second surface 22b (e.g., the bottom surface) and may be formed and patterned on the top surface 24a of the dielectric layer. The metal interconnection layer 22 can extend further through a set of openings 25 to define a set of vias 27.

[0014] The semiconductor device 12 may take the form of a die, a diode, another power electronics device, or a passive device such as a capacitor or resistor. In addition to the set of semiconductor devices 12, embodiments of the semiconductor device package 10 may also include any number of additional circuit components, such as gate drivers (not shown). Figure 1 shows three semiconductor devices 12 in the semiconductor device package 10, but other embodiments are not limited thereto, and more or fewer semiconductor devices 12 may be included in the semiconductor device package 10. The semiconductor devices 12 may be attached to the substrate structure 14 by soldering, adhesive bonding, or sintered silver bonding, etc.

[0015] In a non-limiting embodiment, the body 13 may be defined by a die containing silicon carbide. The semiconductor device 12 may include a so-called "vertical conduction" type semiconductor device 12 that enables electrical I / O interconnects created via a first contact pad 31 located on a first surface 13a of the semiconductor device and a second contact pad 32 located on an opposing second surface 13b. Depending on the application, the set of first contact pads 31 and the set of second contact pads 32 may operably couple the semiconductor device 12 to an external circuit (not shown) via a metal interconnect layer 22 and a first conductive layer 18, respectively, and may be electrically coupled to internal elements within the semiconductor device 12.

[0016] For example, in a non-limiting embodiment, the semiconductor device 12 may include a MOSFET semiconductor device 12, and the set of first contact pads 31 may include a source terminal 34 and a gate terminal 35. The gate terminal 35 may define a first surface 35a facing outward (i.e., with respect to the semiconductor device body 13) and a second surface 35b facing inward (i.e., with respect to the semiconductor device body 13) and opposite to the first surface 35a. The source terminal 34 may define a first surface 34a facing outward (i.e., with respect to the semiconductor device body 13) and a second surface 34b facing inward and opposite to the first surface 34a.

[0017] In addition, spaces or gaps defined between sets of semiconductor devices 12 can be optionally filled with dielectric filler material 33. In various embodiments, the dielectric filler material 33 may include polymer materials such as underfill (e.g., capillary underfill or no-flow underfill), encapsulation, silicone, or molding material.

[0018] The first gate resistor 15 may be directly positioned on one of the first contact pads 31. For example, in a non-limiting embodiment, the first gate resistor 15 may be defined on the first surface 35a of the gate terminal 35. In this sense, the first gate resistor 15 may be positioned outside the semiconductor device body 13 in direct contact with the gate terminal 35. In some embodiments, the first gate resistor 15 may be in direct contact with the first surface 35a of the gate terminal 35. In a non-limiting embodiment, the first gate resistor 15 may be physically supported by the gate terminal 35. In some embodiments, the gate terminal 35 may be electrically coupled in series with the first gate resistor 15. In a non-limiting embodiment, the first gate resistor 15 may have a resistance value in the range of 0.1 ohms to 100 ohms in series with the gate terminal 35.

[0019] The first gate resistor 15 can be formed, defined, or optionally structurally positioned on the first contact pads 31 by a “direct writing” type application to form, define, or optionally structurally position the first gate resistor 15 on the first contact pads 31 without adding to or modifying the resistance of the first contact pads 31 themselves. For example, the first gate resistor 15 can be applied on one of the first contact pads 31 using an inkjet or aerosol jet printer type application device, where a resistive material (e.g., a carbon-based material) is precisely deposited or printed on, on, around, or in combination thereof, one of the first contact pads 31. However, it is recognized that any combination of jetting, dispensing, laser writing, or printing may be employed in such direct writing applications.

[0020] In other non-limiting embodiments, any other suitable additional method of applying a resistive material to define a first gate resistor on the gate terminal 35 can also be used, likewise, without departing from the scope of the present disclosure.

[0021] The dielectric layer 24 may be placed on a first surface 13a (e.g., the top surface) of a set of semiconductor devices 12. For example, in a non-limiting embodiment, an adhesive (not shown) may be used to attach the dielectric layer 24 to the set of semiconductor devices 12. In a non-limiting embodiment, the dielectric layer 24 may include lamination or a film. In some non-limiting embodiments, the dielectric layer 24 may be formed from any of a variety of dielectric materials, such as polytetrafluoroethylene (PTFE), polysulfone material, another polymer film, e.g., liquid crystal polymer (LCP) or polyimide material. The dielectric layer 24 may be applied at least partially on top of the semiconductor devices 12 by a "direct write" type application. For example, the dielectric layer 24 may be applied on top of the semiconductor devices 12 using an inkjet printer type application device, where the dielectric material (e.g., polymer, epoxy, or polyimide) is precisely deposited / printed on top of, on, and around the semiconductor devices 12, as well as in the spaces between the devices. However, it is recognized that any combination of spraying, dispensing, laser writing, or printing may be employed in such direct writing applications. In the adoption of direct writing application techniques, the area on the semiconductor device 12 on which electrical connections are created is left open or exposed to define a set of apertures 25. Cleaning processes using laser, dry, or wet processes may be used to further clean the via apertures for metallization, if necessary.

[0022] The metal interconnect layer 22 may be formed or patterned on the upper surface 24a of the dielectric layer. The metal interconnect layer 22 may be directly coupled to the semiconductor device 12 by a set of vias 27. For example, the set of vias 27 may enable electrical connection by the metal interconnect layer 22 to a first contact pad 31 of the semiconductor device 12. The vias 27 may be formed or defined at locations corresponding to the first contact pad 31 formed on the semiconductor device 12, and an electrical connection may be created to the semiconductor device 12 through the first contact pad 31.

[0023] In an aspect of adopting a direct write application technique, the area on the semiconductor device 12 on which the resistor is formed can remain open, for example, through an opening 25 in a dielectric layer defined or formed (e.g., thereon) corresponding to the first gate resistor 15. A cleaning process using a laser process, a dry process, or a wet process can be used to further clean the via opening 25 for metallization as needed to enable the metal interconnect layer 22 to extend through the opening to define a via 27 directly coupled to the first gate resistor 15.

[0024] In an aspect of adopting an optional adhesive to attach the set of semiconductor devices 12 to the dielectric layer 24, it will be understood that the set of openings 25 will similarly extend through an adhesive (not shown). The set of openings 25 can be arranged to have any desired size and spacing and extend through the dielectric layer 24 or the adhesive or both to enable electrical connection from the metal interconnect layer 22 to one or more of at least one first contact pad 31 of the semiconductor device 12. In a non-limiting aspect, the metal interconnect layer 22 can include copper deposited (e.g., electroplated) on and through the set of openings 25 in the dielectric layer 24 to enable electrical connection from the metal interconnect layer 22 to the first contact pad 31 of the semiconductor device 12. The metal interconnect layer 22 can have a thin (e.g., less than 1000 micrometers thick) planar interconnect structure equipped to form I / O connections (not shown) to and from the semiconductor device 12.

[0025] In one non-limiting embodiment, the metal interconnect layer 22 may be formed by applying a metal layer or metallic material, such as by using sputtering and electroplating processes, and then patterning the applied metallic material into a metal interconnect layer 22 having a desired shape. That is, the metal interconnect layer 22 may be formed by applying titanium or other suitable adhesive layers and copper seed layers via sputtering and / or vapor deposition processes, and then electroplating additional copper on those layers to increase the thickness of the metal interconnect layer 22 and form copper traces. In another embodiment, the metal interconnect layer 22 may be formed by a direct writing process, where the metallic material is directly written or printed to form the interconnect. In a non-limiting embodiment, vias 27 may be filled with via-filling materials such as conductive inks, adhesives or pastes, which are later cured to enhance the electrical, thermal or mechanical properties of the metal interconnect layer 22. Other additional methods for applying metal interconnects may also be used. In another embodiment, printing and plating processes may be used when a thin metal layer is printed using metallic ink and used as a seed for plating copper, and electrolytic or electroless processes may be used, for example, for plating copper.

[0026] In a non-limiting aspect, the substrate structure 14 can be in the form of an insulated metal substrate (IMS), a direct bonded copper (DBC) substrate, an active metal brazed (AMB) substrate, or a printed circuit board (PCB). According to a non-limiting aspect shown in FIG. 1, the substrate structure 14 can include an insulator plate 16. In a non-limiting aspect, the insulator plate 16 can be formed from a thermally conductive, electrically insulating material such as aluminum, aluminum nitride, ceramic, or a combination thereof. In a non-limiting aspect, the first conductive layer 18 and the second conductive layer 20 can include a metal sheet (e.g., a copper sheet). The first conductive layer 18 and the second conductive layer 20 can be joined to opposite surfaces of the insulator plate 16, for example, by a high temperature joining process. In various aspects, various brazing and direct bonding techniques can be employed to form the substrate structure 14 based on, for example, the materials used to form the insulator plate 16 (e.g., aluminum or aluminum nitride and silicon nitride, etc.). The second conductive layer 20 can be wholly or partially exposed to provide efficient heat conduction out of the semiconductor device package 10. The aspect shown in FIG. 1 shows the substrate structure 14 in the form of a DBC substrate, but it is recognized that aluminum or any other suitable metallic material can be used in place of copper as the first conductive layer 18 or the second conductive layer 20 or both. Ceramic tiles or other suitable insulators can be used in place of alumina to form the insulator plate 16 without departing from the scope of the present disclosure, but are further contemplated.

[0027] Referring now to FIG. 2, another semiconductor device package 200 is shown in cross-section in a non-limiting aspect. The semiconductor device package 200 includes some components similar to those shown in the semiconductor device package 100 of FIG. 1, and some components are omitted for clarity, and thus, the numbers used to indicate the components of FIG. 1 are also used to indicate similar components of FIG. 2.

[0028] A semiconductor device package 200 is shown together with a semiconductor device 12 coupled to a substrate structure 14 (for example, on the upper surface of the substrate structure 14). A first gate resistor 15 is coupled to the semiconductor device 12. A dielectric layer 24 is placed on top of the semiconductor device 12 (for example, on the first surface 12a of the semiconductor device). The dielectric layer 24 can define a set of openings 25 through it. A metal interconnect layer 22 (for example, a copper trace) is formed and placed on the first surface 24a of the dielectric layer and through the openings 25, defining a set of vias 27 through the openings 25.

[0029] In addition, in non-limiting embodiments, the semiconductor device package 200 may include a second gate resistor 150. For example, in non-limiting embodiments, the semiconductor device package 200 may include a semiconductor device 12 including a gate terminal 35 electrically coupled in series with a first gate resistor 15 and a second gate resistor 150. The first gate resistor may be defined on the gate terminal 35, and the second gate resistor 150 may be separated from the gate terminal 35. In some embodiments, a first conductive wire 151 can electrically couple the first gate resistor 15 and the second gate resistor 150 in series. In some embodiments, a metal interconnect layer 22 may define the first conductive wire 151. In this way, the second gate resistor 150 may be electrically coupled in series with the gate terminal 35 and the first gate resistor 15. In a non-limiting embodiment, the first gate resistor 15 and the second gate resistor 150 can be added in series with the gate terminal 35 to add a total resistance in the range of 0.1 ohms to 100 ohms.

[0030] In some non-limiting embodiments, the semiconductor device may further include a third gate resistor 152, as shown in Figure 2. The third gate resistor may be formed within the semiconductor device body 13. The third gate resistor 152 may further be electrically coupled in series with the first gate terminal 35 using conventional techniques. For example, in some non-limiting embodiments, the third gate resistor 152 may be coupled to the second face of the gate terminal via a conductive element 154 defined within the semiconductor device body 13. In some embodiments, the third gate resistor 152 may define a segment of the conductive element 154.

[0031] The second gate resistor 150 may be applied or placed at least partially on the dielectric layer 24 (for example, on the upper surface of the dielectric layer 24) by a “direct writing” type application. For example, the second gate resistor 150 may be applied on the dielectric layer 24 using an inkjet printer type application device, where the resistive material (for example, a carbon-based material) is precisely deposited or printed on, on, around, or a combination thereof, a portion of the dielectric layer 24. However, it is recognized that any combination of jetting, dispensing, laser writing, or printing may be employed in such direct writing applications.

[0032] In other non-limiting embodiments, other additional methods for defining the second gate resistor 150 by applying a resistive material on the dielectric layer 24 may also be used. In another embodiment, printing and plating steps may be used when a thin layer of resistive material (e.g., carbon-based material) is printed using carbon-based ink.

[0033] The metal interconnect layer 22 is then formed or patterned on the dielectric layer 24 and can further define the first conductive wire 151 coupled to the second gate resistor 150. In other non-limiting embodiments, the second gate resistor 150 may be electrically coupled to the first gate resistor by a wire or other conductive wire (not shown). In some non-limiting embodiments, the second gate resistor may be positioned to define a segment of the first conductive wire 151.

[0034] Figure 3 shows a non-limiting method 300 for forming semiconductor device packages 100, 200 in various embodiments. In non-limiting embodiments, the semiconductor switching device 12 includes a body 13. The body 13 may be defined by a die containing silicon carbide. Method 300 includes the step in 310 of placing a first gate resistor 15 on the gate terminal 35 of the semiconductor device 12. In non-limiting embodiments, the first gate resistor 15 may be formed in place (i.e., on the first surface 35a of the first gate terminal) by a direct writing process. In some non-limiting embodiments, the gate terminal 35 can mechanically support the first gate resistor 15. In non-limiting embodiments, the first gate resistor 15 may therefore be located outside the semiconductor device body 13 in direct contact with the gate terminal 35. Method 300 may include the step in 320 of electrically insulating the gate terminal 35 from the source terminal 34 of the semiconductor device 12 with a dielectric layer 24. Method 300 may further include the step in 330 of defining a second gate resistor 150 spaced apart from the gate terminal 35. For example, in a non-limiting embodiment, the second gate resistor 150 may be formed by a direct writing application. In a non-limiting embodiment, the second gate resistor 150 may be located on the first surface 24a of the dielectric layer. Method 300 may include the step in 340 of electrically coupling the second gate resistor 150 in series with the first gate resistor 15 via a first conductive wire 151. In a non-limiting embodiment, a metal interconnect layer 22 may be deposited on the dielectric layer 24 to define the first conductive wire 151. In some non-limiting embodiments, the second gate resistor 150 may define a segment of the first conductive wire.

[0035] In a non-limiting embodiment, the semiconductor switching device 12 may further include a third gate resistor 152 defined within the semiconductor body 13 and electrically coupled in series with the gate terminal 35. While the present technique may be described herein in the context of SiC MOSFET devices, it should be noted that the present technique may be applicable to other types of material systems (e.g., silicon (Si), germanium (Ge), aluminum nitride (AlN), gallium nitride (GaN), gallium arsenide (GaAs), diamond (C), or any other suitable semiconductor) and other types of device structures (e.g., UMOSFETs, VMOSFETs, insulated-gate bipolar transistors (IGBTs), insulated-base MOS-controlled thyristors (IBMCTs), or any other suitable FET and / or MOS devices) by utilizing n-channel or p-channel designs.

[0036] Beyond what has been described so far, various features and structures of various embodiments may be used in combination with one another as required. The fact that one feature may not necessarily be present in all embodiments does not mean that it cannot be presented, but rather that this is done for the sake of conciseness of description. Thus, various features of various embodiments may be mixed and matched as required to form new embodiments, regardless of whether the new embodiments are explicitly described. Combinations and rearrangements of features described herein are covered by this disclosure.

[0037] This specification, using examples, discloses aspects of the present disclosure, including best modes, and enables those skilled in the art to practice aspects of the present disclosure, including fabricating and using any device or system and performing any incorporated methods. The scope of patentability of the present disclosure is defined by the claims and may include other embodiments that a person skilled in the art may conceive. Such other embodiments are intended to fall within the scope of the claims if they have structural elements that are no different from the literal language of the claims, or if they contain equivalent structural elements with only minor differences from the literal language of the claims. Further aspects of the present invention are provided by the subject matter of the following sections.

[0038] [Item 1] A semiconductor switching device having a body including a first surface and an opposing second surface coupled to a substrate; a semiconductor device package comprising a gate terminal defined on the first surface of the semiconductor switching device body, having the first surface and an opposing second surface facing the body; and a first gate resistor disposed on the first surface of the gate terminal, the gate resistor being electrically coupled in series with the gate terminal.

[0039] [Clause 2] Any semiconductor device package according to the preceding paragraph, further comprising a dielectric layer having a first surface and a second opposing surface facing the first surface of a semiconductor switching device body, wherein the dielectric layer defines an opening through which an aperture passes.

[0040] [Clause 3] Any semiconductor device package according to the preceding paragraph, further comprising a metal interconnect layer disposed on a first surface of a dielectric layer and electrically coupled to a first gate resistor through an opening.

[0041] [Clause 4] The first gate resistor is defined by a direct writing application on the first surface of the gate terminals of any semiconductor device package as described in the preceding paragraph.

[0042] [Clause 5] Any semiconductor device package according to the preceding paragraph, further comprising a second gate resistor disposed on the first surface of the dielectric layer and separated from the semiconductor switching device.

[0043] [Clause 6] Any semiconductor device package as described in the preceding paragraph, further comprising a first gate resistor and a first conductive wire electrically coupled in series with the second gate resistor.

[0044] [Clause 7] The second gate resistor defines a segment of the first conductive wire in any semiconductor device package as described in the preceding paragraph.

[0045] [Clause 8] The second gate resistor is any semiconductor device package as described in the preceding paragraph, formed by a direct writing application.

[0046] [Item 9] The semiconductor switching device body is any semiconductor device package as described in the preceding item, comprising silicon carbide.

[0047] [Clause 10] Any semiconductor device package as described in the preceding paragraph, further comprising a third gate resistor defined within the semiconductor device body and electrically coupled in series with the gate terminal.

[0048] [Clause 11] A method for forming a semiconductor device package, comprising the step of placing a first gate resistor on a gate terminal defined on a first surface of a semiconductor switching device, wherein the first gate resistor is electrically coupled in series with the gate terminal.

[0049] [Clause 12] Any method according to the preceding paragraph, further comprising the step of arranging a dielectric layer having a first surface and a second opposing surface facing a semiconductor switching device, wherein the dielectric layer defines an opening through which it passes.

[0050] [Clause 13] Any method according to the preceding paragraph, further comprising the step of arranging a metal interconnect layer on a first surface of a dielectric layer, which is electrically coupled to a first gate resistor through an opening.

[0051] [Section 14] The first gate resistor is placed on the gate terminal by the direct writing application, as described in any of the preceding paragraphs.

[0052] [Clause 15] Any method according to the preceding paragraph, further comprising the step of arranging a second gate resistor, separated from the semiconductor switching device body, on a first surface of the dielectric layer.

[0053] [Clause 16] The method according to any preceding paragraph, wherein the metal interconnect layer defines a first conductive wire electrically coupled in series with a first gate resistor and a second gate resistor.

[0054] [Clause 17] A second gate resistor is defined by any method according to the preceding paragraph, wherein the second gate resistor defines a segment of the first conductive wire.

[0055] [Section 18] The second gate resistor is provided by the direct writing application, as described in any of the preceding paragraphs.

[0056] [Clause 19] A semiconductor switching device body comprising silicon carbide, any method according to the preceding paragraph.

[0057] [Clause 20] Any method according to the preceding paragraph, wherein the semiconductor switching device body further comprises a third gate resistor defined within the semiconductor switching device body and electrically coupled in series with the gate terminal. [Explanation of symbols]

[0058] 12 Semiconductor Devices 12a First face 12b Second face 13 Main unit, semiconductor device main unit 13a First face, top surface 13b Second face, bottom face 14. Substrate structure 15. First gate resistor 16 Insulator Plate 18 First conductive layer 20 Second conductive layer 22 Metal interconnection layer 22a First surface, top surface 22b Second face, bottom surface 24 Dielectric layer 24a First surface, top surface 24b Second face, bottom 25 Aperture 27 Beer 31. First contact pad 32 Second contact pad 33 Dielectric Filling Materials 34 Source terminals 34a First face 34b Second side 35 Gate terminals 35a First surface 35b Second side 100 semiconductor device packages 150 Second gate resistor 151 First conductive wire 152 Third gate resistor 154 Conductive elements 200 semiconductor device packages

Claims

1. A semiconductor switching device having a body including a first surface and a second opposing surface bonded to a substrate, A gate terminal defined on a first surface of the body of the semiconductor switching device, having the first surface and a second surface facing the body of the semiconductor switching device, A semiconductor device package comprising a first gate resistor disposed on the first surface of the gate terminal, wherein the gate resistor is electrically coupled in series with the gate terminal, The package of the aforementioned semiconductor device is A dielectric layer having a first surface and a second surface facing the first surface of the body of the semiconductor switching device, A metal interconnect layer is disposed on the first surface of the dielectric layer and electrically coupled to the first gate resistor, The device further includes a second gate resistor disposed on the first surface of the dielectric layer and separated from the semiconductor switching device, A semiconductor device package wherein the metal interconnect layer defines a first conductive wire electrically coupled in series with the first gate resistor and the second gate resistor.

2. The semiconductor device package according to claim 1, wherein the dielectric layer defines an opening through which it passes.

3. The semiconductor device package according to claim 1, wherein the first gate resistor is defined by a direct writing application on the first surface of the gate terminal.

4. The semiconductor device package according to claim 2, wherein the second gate resistor defines a segment of the first conductive wire.

5. The semiconductor device package according to claim 2, wherein the second gate resistor is provided by a direct writing application.

6. The semiconductor device package according to claim 1, wherein the main body of the semiconductor switching device contains silicon carbide.

7. The semiconductor device package according to claim 6, further comprising a third gate resistor defined within the body of the semiconductor switching device and electrically coupled in series with the gate terminal.

8. A method for forming a semiconductor device package, The steps include: placing a first gate resistor on a gate terminal defined on a first surface of the body of a semiconductor switching device, wherein the first gate resistor is electrically coupled in series with the gate terminal; The steps include arranging a dielectric layer having a first surface and a second opposing surface facing the semiconductor switching device, The steps include: placing a metal interconnect layer that is electrically coupled to the first gate resistor on the first surface of the dielectric layer; The step includes placing a second gate resistor, separated from the body of the semiconductor switching device, on the first surface of the dielectric layer, A method wherein the metal interconnection layer defines a first conductive wire electrically coupled in series with the first gate resistor and the second gate resistor.

9. The method according to claim 8, wherein the dielectric layer defines an opening through which it passes.

10. The method according to claim 8, wherein the first gate resistor is placed on the gate terminal by a direct writing application.

11. The method according to claim 8, wherein the second gate resistor defines a segment of the first conductive wire.

12. The method according to claim 8, wherein the second gate resistor is placed by a direct writing application.

13. The method according to claim 8, wherein the body of the semiconductor switching device contains silicon carbide.

14. The method according to claim 13, wherein the body of the semiconductor switching device further includes a third gate resistor defined within the body of the semiconductor switching device and electrically coupled in series with the gate terminal.

Images