Semiconductor equipment

Abstract

To provide a semiconductor device that is suitable for microfabrication and high density.SOLUTION: A semiconductor device comprises: a first transistor; a second transistor overlapped with the first transistor; a capacitive element overlapped with the second transistor; and first wiring electrically connected with the capacitive element. The first wiring has a region overlapped with an electrode of the second transistor. The first transistor, the second transistor and the capacitive element are electrically connected with each other. A channel of the first transistor has a single crystal semiconductor. A channel of the second transistor has an oxide semiconductor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device having a field effect transistor.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The invention disclosed in this specification etc. The technical field of one aspect is related to an object, a method, or a manufacturing method. Or, one aspect of the present invention is related to a process, a machine, a manufacture, or a composition (composition ·of·matter). Therefore, more specifically, the technical field of one aspect of the present invention disclosed in this specification includes semiconductor devices, display devices, liquid crystal display devices, light emitting devices, lighting devices, power storage devices, storage devices, their driving methods, or their manufacturing methods, as an example.

[0003] Note that in this specification etc., a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and storage devices are one aspect of semiconductor devices. Imaging devices, display devices, liquid crystal display devices, light emitting devices, electro- optical devices, power generation devices (including thin film solar cells, organic thin film solar cells, etc.), and electronic devices may have a semiconductor device.

Background Art

[0004] Techniques for constructing transistors using semiconductor materials have attracted attention. The transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, but oxide semiconductors are attracting attention as other materials. ​

[0005] For example, a technique for manufacturing a transistor using zinc oxide or an In-Ga-Zn-based oxide semiconductor as an oxide semiconductor is disclosed (see Patent Document 1 and Patent Document 2). In recent years, with the improvement in performance, miniaturization, or weight reduction of electronic devices, the demand for integrated circuits in which semiconductor elements such as fine transistors are integrated at high density has been increasing. For example, a Tri-Gate transistor and a MIM capacitor having a COB (capacitor over bitline) structure have been introduced (Non-Patent Document 1).

[0006] In recent years, with the improvement in performance, miniaturization, or weight reduction of electronic devices, the demand for integrated circuits in which semiconductor elements such as fine transistors are integrated at high density has been increasing. For example, a Tri-Gate transistor and a MIM capacitor having a COB (capacitor over bitline) structure have been introduced (Non-Patent Document 1). Tri-Gate transistor and COB (capacitor over bitlin e) structure MIM capacitor has been introduced (Non-Patent Document 1).

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0008]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0009] One aspect of the present invention is to provide a semiconductor device suitable for miniaturization and high density as one of the problems to be solved.

[0010] Alternatively, one of the objectives is to impart good electrical characteristics to semiconductor devices. Or, reliability One of our objectives is to provide highly efficient semiconductor devices, or to develop a semiconductor device with a novel configuration. One of the objectives is to provide [this].

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. One approach does not require that all of these issues be resolved. The title will become clear from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the drawings, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention is a first transistor and a second transistor that overlaps with the first transistor. A transistor, a first capacitive element that overlaps with the first transistor, and a second transistor A second capacitive element that overlaps with the first element, and a first wiring that is electrically connected to the second capacitive element. , and the first wiring has a region that overlaps with the electrodes of the second transistor, and the first The transistor, the second transistor, the first capacitive element, and the second capacitive element are electrically... The first transistor's channel is connected to the second transistor, which has a single-crystal semiconductor. The channel is a semiconductor device characterized by having an oxide semiconductor.

[0013] Another aspect of the present invention involves a first transistor and a first transistor overlapping each other. A second transistor, a first capacitive element that overlaps with the first transistor, and a second A second capacitive element overlapping with the transistor, and a second element electrically connected to the second capacitive element. It has a first wiring and a second transistor, and the first wiring has a region that overlaps with the electrodes of the second transistor. and a first transistor, a second transistor, a first capacitive element, a second capacitive element The two are electrically connected, and the channel of the first transistor has a single-crystal semiconductor, and the second transistor The channel of the transistor has an oxide semiconductor, and one electrode of the first capacitive element has a convex portion. The semiconductor device is characterized in that the other electrode of the first capacitive element includes a recess.

[0014] Furthermore, the above configuration includes a second wiring that is electrically connected to the first capacitive element, The second wiring has a region that overlaps with the electrodes of the first transistor.

[0015] Furthermore, in the above configuration, the second wiring may also function as a common wiring.

[0016] Furthermore, in the above configuration, it is preferable that the second wiring includes copper.

[0017] Another aspect of the present invention involves a first transistor and a first transistor overlapping each other. A second transistor, a capacitive element that overlaps with the second transistor, and a capacitive element It has a first wire that is electrically connected, and the first wire is connected to the electrodes of the second transistor. It has an overlapping region, and the first transistor, the second transistor, and the capacitive element are electrically Connected electrically, the channel of the first transistor has a single-crystal semiconductor, and the second transistor The channel of the sta is a semiconductor device characterized by having an oxide semiconductor.

[0018] Another aspect of the present invention involves a first transistor and a first transistor overlapping each other. A second transistor, a capacitive element that overlaps with the second transistor, and a capacitive element It has a first wire that is electrically connected, and the first wire is connected to the electrodes of the second transistor. The region overlaps, and the channel of the first transistor has a single-crystal semiconductor, and the second The transistor channel has an oxide semiconductor, and consists of a first transistor and a second transistor. The zista and the capacitive element are electrically connected, and one electrode of the capacitive element includes a protrusion, and the capacitive element The other electrode of this semiconductor device is characterized by including a recess.

[0019] Furthermore, in the above configuration, the capacitive element is located between the first transistor and the second transistor. It is located in [location].

[0020] Furthermore, in the above configuration, the capacitive element is located above the second transistor.

[0021] Furthermore, in the above configuration, the electrode of the second transistor is the gate electrode.

[0022] Furthermore, in the above configuration, it is preferable that the first wiring has the function of a common wiring. stomach.

[0023] Furthermore, in the above configuration, the first transistor and the second transistor are connected by a plug. The connection is made, and the plug preferably contains copper or tungsten.

[0024] Furthermore, in the above configuration, it is preferable that the first wiring includes copper. [Effects of the Invention]

[0025] According to one aspect of the present invention, a semiconductor device suitable for miniaturization and high density can be provided. ru.

[0026] Alternatively, good electrical properties can be imparted to semiconductor devices. Or, reliable We can provide semiconductor devices, or provide semiconductor devices with novel configurations. This is possible. Note that the descriptions of these effects do not preclude the existence of other effects. One aspect of the present invention does not necessarily have to have all of these effects. The external effects will become clear from the description in the specification, drawings, claims, etc. It is possible to extract effects other than those mentioned above from the detailed descriptions, drawings, and claims. [Brief explanation of the drawing]

[0027] [Figure 1] Circuit diagram and configuration example of a semiconductor device according to an embodiment. [Figure 2] A top view showing semiconductor devices arranged according to an embodiment. [Figure 3] A diagram illustrating the layered structure included in a semiconductor device according to an embodiment. [Figure 4] An example of the configuration of a semiconductor device according to an embodiment. [Figure 5] A diagram illustrating the band structure according to an embodiment. [Figure 6] An example of the configuration of a semiconductor device according to an embodiment. [Figure 7] An example of the configuration of a semiconductor device according to an embodiment. [Figure 8] An example of the configuration of a semiconductor device according to an embodiment. [Figure 9] An example of the configuration of a semiconductor device according to an embodiment. [Figure 10] A diagram illustrating an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 11] A diagram illustrating an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 12] A diagram illustrating an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 13] An example of the configuration of a semiconductor device according to an embodiment. [Figure 14] An example of the configuration of a semiconductor device according to an embodiment. [Figure 15] An example of the configuration of a semiconductor device according to an embodiment. [Figure 16] Circuit diagram and configuration example of a semiconductor device according to an embodiment. [Figure 17] A top view showing semiconductor devices arranged according to an embodiment. [Figure 18] A diagram illustrating an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 19] A diagram illustrating an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 20] An example of the configuration of a semiconductor device according to an embodiment. [Figure 21] An example of the configuration of a semiconductor device according to an embodiment. [Figure 22] High-resolution TEM image with Cs correction in cross-section of CAAC-OS, and schematic cross-sectional diagram of CAAC-OS. [Figure 23] High-resolution TEM image with Cs correction in the plane of CAAC-OS. [Figure 24] A diagram illustrating the XRD structural analysis of CAAC-OS and single-crystal oxide semiconductors. [Figure 25] A figure showing the electron diffraction pattern of CAAC-OS. [Figure 26] A diagram showing the changes in the crystalline structure of In-Ga-Zn oxide due to electron irradiation. [Figure 27] A circuit diagram relating to an embodiment. [Figure 28] This figure illustrates an example of a schematic cross-sectional view of the circuit diagram shown in Figure 27. [Figure 29] This figure illustrates an example of a schematic cross-sectional view of the circuit diagram shown in Figure 27. [Figure 30] An example of the configuration of an RF tag according to an embodiment. [Figure 31] An example of a CPU configuration according to an embodiment. [Figure 32] Circuit diagram of a memory element according to an embodiment. [Figure 33] Circuit diagram of a display device according to an embodiment. [Figure 34] An electronic device according to an embodiment. [Figure 35] An example of the use of an RF device according to an embodiment. [Modes for carrying out the invention]

[0028] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be modified in various ways. Those skilled in the art will readily understand what is possible. Therefore, the present invention is as shown in the following embodiments. It should not be interpreted as being limited to the contents described herein.

[0029] Furthermore, in the configuration of the invention described below, the same part or part having a similar function The same reference numeral is used in common across different drawings, and explanations of its repetition are omitted. When referring to a specific function, the hatch pattern may be the same, and no special designation may be assigned.

[0030] In each figure described herein, the size, layer thickness, or area of ​​each component is as follows: It may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. stomach.

[0031] In this specification, ordinal numbers such as "the first," "the second," etc., are used to avoid confusion of constituent elements. This is added for the purpose of providing a numerical limit, and is not intended to limit the number of items.

[0032] A transistor is a type of semiconductor device that amplifies current and voltage, and controls conduction or non-conductivity. It is possible to realize controlled switching operations, etc. Transistors in this specification are , IGFET(Insulated Gate Field Effect Trans istors and thin-film transistors (TFTs) ) includes.

[0033] In this specification, "parallel" means that two lines are positioned at an angle of -10° or more and 10° or less. This refers to a state in which it is in a certain condition. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "abbreviated "Parallel" refers to a state where two straight lines are positioned at an angle between -30° and 30°. Furthermore, "perpendicular" refers to a state where two straight lines are positioned at an angle between 80° and 100°. This refers to the case where the angle is between 85° and 95°. Furthermore, "approximately perpendicular" means This refers to a state where two straight lines are positioned at an angle between 60° and 120°.

[0034] Furthermore, in this specification, if the crystal is trigonal or rhombohedral, it is listed as hexagonal. vinegar.

[0035] (Embodiment 1) [Example of a laminated structure] The following describes an example of a laminated structure that can be applied to a semiconductor device according to one aspect of the present invention. Let me explain. Figure 3 is a schematic cross-sectional view of the laminated structure 10 shown below.

[0036] The stacked structure 10 includes a first layer 11 containing a first transistor, a first insulating film 21, and a first Wiring layer 31, barrier film 41, second wiring layer 32, second insulating film 22, and second transient The second layer 12, which includes the sta, has a laminated structure in which the layers are stacked in sequence.

[0037] The first transistor contained in the first layer 11 is composed of a first semiconductor material. Furthermore, the second transistor included in the second layer 12 is composed of a second semiconductor material. The first semiconductor material and the second semiconductor material may be the same material, but may be different. It is preferable to use a semiconductor material. The first transistor and the second transistor are made of the same material. Each of these is a semiconductor film, gate electrode, gate insulating film, source electrode and drain electrode (or source It has a region and a drain region.

[0038] For example, a semiconductor that can be used as a first semiconductor material or a second semiconductor material. Examples include silicon, silicon carbide, germanium, gallium arsenide, and gallium arsenide. As representative semiconductor materials such as phosphorus and gallium nitride, and III-V group semiconductor materials Then, select one or more from B, Al, Ga, In, Tl and one from N, P, As, Sb. Compound semiconductor materials, which are a combination of one or more of the above, are representative semiconductor materials of the II-VI group. The conductive material is one or more selected from Mg, Zn, Cd, Hg and O, S, Se, Te Compound semiconductor materials, organic semiconductor materials, or oxidative materials, which are combinations of one or more selected from the above. Examples include semiconductor materials.

[0039] Here, single-crystal silicon is used as the first semiconductor material, and oxide is used as the second semiconductor material. This section will explain the case using semiconductors.

[0040] The barrier film 41 has the function of suppressing the diffusion of water and hydrogen from the lower layer to the upper layer. It is a layer having the following: The barrier film 41 is provided above the electrode or wiring and below it It may have openings or plugs for electrically connecting electrodes or wiring provided therein. For example, wiring or electrodes included in the first wiring layer 31 and included in the second wiring layer 32 It has a plug that electrically connects to the wiring or electrodes.

[0041] As a material used for wiring or electrodes included in the first wiring layer 31 and the second wiring layer 32 In addition to metal or alloy materials, conductive metal nitrides can be used. A layer containing such a material may be used as a single layer or in the form of two or more layers stacked together.

[0042] The first insulating film 21 has the function of electrically insulating the first layer 11 and the first wiring layer 31. The first insulating film 21 contains the first transistor and electrodes included in the first layer 11. or for electrically connecting the wiring to the electrodes or wiring included in the first wiring layer 31 It may have openings or plugs.

[0043] The second insulating film 22 has the function of electrically insulating the second layer 12 and the second wiring layer 32. In addition, the second insulating film 22 contains the second transistor and electrodes included in the second layer 12. or for electrically connecting the wiring to the electrodes or wiring included in the second wiring layer 32 It may have openings or plugs.

[0044] Furthermore, it is preferable that the second insulating film 22 contains an oxide. In particular, some oxygen is released when heated. Preferably, it contains an oxide material from which oxygen is removed. Preferably, it contains oxygen that satisfies the stoichiometric composition. It is preferable to use an oxide that contains more oxygen. When a conductor is used, oxygen detached from the second insulating film 22 is supplied to the oxide semiconductor, causing oxidation. This makes it possible to reduce oxygen vacancies in the semiconductor material. As a result, the power of the second transistor This can suppress variations in atmospheric characteristics and improve reliability.

[0045] Here, in the layer below the barrier film 41, hydrogen, water, etc., should be reduced as much as possible. This is preferable. Alternatively, it is preferable to minimize the release of hydrogen, water, etc. Hydrogen and water can cause variations in the electrical properties of oxide semiconductors. Hydrogen and water diffusing from the lower layer to the upper layer through the rear membrane 41 are suppressed by the barrier membrane 41. However, hydrogen and water can diffuse to the upper layer through openings and plugs provided in the barrier membrane 41. This can happen.

[0046] In order to reduce the amount of hydrogen and water contained in each layer located below the barrier film 41, or In order to reduce the release of hydrogen and water, before forming the barrier film 41, or on the barrier film 41 Immediately after forming the opening for plug formation, hydrogen contained in the layer below the barrier film 41 It is preferable to apply a heat treatment to remove water. Conductive films and other materials constituting semiconductor devices. Higher heating temperatures are acceptable as long as the heat resistance and electrical characteristics of the transistor do not deteriorate. It is preferable to be above 450°C, preferably above 490°C, more preferably The temperature should be 530°C or higher, but it may also be carried out at 650°C or higher. In an inert gas atmosphere. Under a gas or reduced pressure atmosphere for 1 hour or more, preferably 5 hours or more, more preferably 10 hours. It is preferable to perform the above heat treatment. Furthermore, the temperature of the heat treatment is the temperature of the first layer 11 and the first layer The wiring or electrode material included in the wire layer 31, and the plug provided in the first insulating film 21 The decision should be made considering the heat resistance of the material, but for example, if the heat resistance of the material is low, 5 The process can be carried out at temperatures below 50°C, or below 600°C, or below 650°C, or below 800°C. That's fine. Also, this type of heat treatment only needs to be done at least once, but if it is done multiple times... More preferable.

[0047] The insulating film provided below the barrier film 41 has a desorption amount of hydrogen molecules (m / z = 2) at a substrate surface temperature of 400 °C measured by temperature-programmed desorption gas spectrometry (also referred to as TDS analysis) that is preferably 130% or less, more preferably 110% or less, of the desorption amount of hydrogen molecules at 300 °C. Alternatively, the desorption amount of hydrogen molecules at a substrate surface temperature of 450 °C measured by TDS analysis is preferably 130% or less, more preferably 110% or less, of the desorption amount of hydrogen molecules at 350 °C. もよぶ)によって測定される、基板表面温度が400℃での水素分子(m / z=2)の脱 離量が、300℃での水素分子の脱離量の130%以下が好ましく、110%以下である ことがより好ましい。または、TDS分析によって基板表面温度が450℃での水素分子 の脱離量が、350℃での水素分子の脱離量の130%以下が好ましく、110%以下で あることがより好ましい。

[0048] また、バリア膜41自体に含まれる水や水素も低減されていることが好ましい。例えば バリア膜41として、TDS分析によって基板表面温度が20℃から600℃の範囲にお ける水素分子の脱離量が、2×10 15 個 / cm 2 未満、好ましくは1×10 15 個 / c m 2 未満、より好ましくは5×10 14 個 / cm 2 未満である材料を用いることが好まし い。または、TDS分析によって基板表面温度が20℃から600℃の範囲における水分 子(m / z=18)の脱離量が、1×10 16 個 / cm 2 未満、好ましくは5×10 15 個 / cm 2 未満、より好ましくは2×10 12 個 / cm 2 未満である材料をバリア膜41 に用いることが好ましい。

[0049] また、第1の層11に含まれる第1のトランジスタの半導体膜に単結晶シリコンを用い た場合では、当該加熱処理は、シリコンの不対結合手(ダングリングボンドともいう)を It can also serve as a hydrogenation process (also called hydrogenation). As a result, some of the hydrogen contained in the first layer 11 and the first insulating film 21 is desorbed, forming the first transistor. By diffusing into the semiconductor film of the zista and terminating the dangling bond in silicon, the first This can improve the reliability and static characteristics of the transistor.

[0050] Materials that can be used for the barrier film 41 include silicon nitride, silicon nitride oxide, Aluminum oxide, aluminum oxide nitride, gallium oxide, gallium oxide nitride, aluminum oxide Examples include thorium, yttrium oxide nitride, hafnium oxide, and hafnium oxide nitride. In particular, aluminum oxide is preferred because it has excellent barrier properties against water and hydrogen.

[0051] The barrier film 41 consists of a film made of a material that is impermeable to water and hydrogen, as well as a film containing other insulating materials. They may be used in layers. For example, a film containing silicon oxide or silicon oxide nitride, a metal acid The film containing the compound may be used in a layered configuration.

[0052] Furthermore, it is preferable to use a material that is impermeable to oxygen for the barrier film 41. The material is a material that exhibits excellent barrier properties not only against hydrogen and water but also against oxygen. As a result, when the second insulating film 22 is heated, the oxygen released is lower than the barrier film 41. Diffusion can be suppressed. As a result, the second insulating film 22 is released, and To increase the amount of oxygen that can be supplied to the semiconductor film of the second transistor in layer 12. It is possible.

[0053] In this way, the concentration of hydrogen and water in each layer located below the barrier film 41 is reduced. Alternatively, hydrogen and water are removed, and the barrier film 41 allows hydrogen and water to diffuse into the second layer. This suppresses the release of hydrogen and water. The insulating film 22 and the hydrogen in each layer constituting the second transistor included in the second layer The water content can be made extremely low. For example, the second insulating film 22, second The hydrogen concentration in the semiconductor film or gate insulating film of the transistor is 5 × 10 18 cm -3 Less than 1 × 10 18 cm -3 Less than 3 × 10 17 cm - 3 It can be reduced to less than [amount missing].

[0054] In a semiconductor device according to one aspect of the present invention, by applying a stacked structure 10, the first layer 11 Which of the first transistors included and the second transistor included in the second layer 12 This also makes it possible to achieve high reliability, resulting in the realization of extremely reliable semiconductor devices. It can be expressed.

[0055] [Example Configuration] Figure 1(A) is an example of a circuit diagram of a semiconductor device according to one embodiment of the present invention. The semiconductor device includes a first transistor 110, a second transistor 100, and a capacitive element 1 It has 30, wiring SL, wiring BL, wiring WL, and wiring CL.

[0056] The first transistor 110 has either its source or drain electrically connected to the wiring BL. The other end is electrically connected to the wiring SL, and the gate is the source of the second transistor 100. The second transient is electrically connected to one electrode of the drain and one electrode of the capacitive element 130. In the 100, the source or drain is electrically connected to the wiring BL, and the gate is connected to the wiring. The capacitive element 130 is electrically connected to WL. The other electrode of the capacitive element 130 is electrically connected to the wiring CL. Furthermore, the gate of the first transistor 110 and the source of the second transistor 100 The node between one side of the drain and one side of the capacitive element 130 is called node FN.

[0057] The semiconductor device shown in Figure 1(A) has the second transistor 100 in a conductive state (on state). Sometimes a potential corresponding to the potential of wiring BL is applied to node FN. Also, the second transistor 10 It has the function of maintaining the potential of node FN when 0 is in a non-conductive state (off state). The semiconductor device shown in Figure 1(A) functions as a memory cell in a memory device. Oh, liquid crystal elements and organic EL (electroluminescent) elements that are electrically connected to node FN. When it has display elements such as a cence element, the semiconductor device in Figure 1(A) is a display device. It can also function as a basic element.

[0058] The selection of the conduction and non-conduction states of the second transistor 100 depends on the potential supplied to the wiring WL. Therefore, it can be controlled. Also, the potential applied to the wiring WL determines the second transistor A threshold voltage of 100 can be controlled. As the second transistor 100, it is turned off. By using a transistor with a small current, the potential of node FN in the non-conductive state can be reduced. This can be maintained over a long period of time. Therefore, the refresh frequency of semiconductor devices can be reduced. Because this can be reduced, it is possible to realize semiconductor devices with low power consumption. One example of a transistor with a low off-current is a transistor using an oxide semiconductor. It can be done.

[0059] Furthermore, a constant potential such as a reference potential, ground potential, or any fixed potential is applied to the wiring CL. At this time, the potential of node FN causes the apparent state of the second transistor 100. The threshold voltage fluctuates. Due to the fluctuation in the apparent threshold voltage, the first transistor 11 By utilizing the change between the conductive and non-conductive states of 0, the potential information held in node FN is obtained. It can be read out as data.

[0060] A semiconductor device according to one aspect of the present invention has a sufficiently reduced hydrogen concentration in the layer below the barrier film. Alternatively, because the diffusion and release of hydrogen concentration is suppressed, the oxidation of the upper layer occurs. Transistors using solid semiconductors can achieve extremely low off-currents.

[0061] By arranging the semiconductor devices shown in Figure 1(A) in a matrix, a memory device (memory cell) can be created. An array can be constructed.

[0062] Figure 1(B) shows an example of a cross-sectional configuration of a semiconductor device that can realize the circuit shown in Figure 1(A). Furthermore, Figure 2(A) shows a top view of the semiconductor devices shown in Figure 1(B) arranged side by side. Note that each semiconductor The devices share a common wiring CL that functions as a shared wiring.

[0063] As shown in Figure 2(A), the second transistor is located within the area occupied by the first transistor 110. 100 and capacitive elements 130 are provided. Furthermore, semiconductor devices are arranged in a matrix. When doing so, as shown in Figure 2(B), the wiring SL (low resistance layer 113b) is shared with the adjacent semiconductor device. You may do so.

[0064] The semiconductor device, as shown in Figure 1(B), has a first transistor 110, a second transistor It has a transistor 100 and a capacitive element 130. The second transistor 100 is the first transistor It is located above transistor 110 and between the first transistor 110 and the second transistor 100. A barrier film 120 is provided therein.

[0065] The first transistor 110 is provided on the semiconductor substrate 111, and one of the semiconductor substrate 111 A semiconductor film 112 consisting of a portion, a gate insulating film 114, a gate electrode 115, and a source region Alternatively, it has low-resistance layers 113a and 113b that function as drain regions.

[0066] The first transistor 110 can be either a p-channel or an n-channel type, but the circuit You should use the appropriate transistor depending on the configuration and driving method.

[0067] The region in which the channel of the semiconductor film 112 is formed, the region near thereto, the source region or In the low-resistance layer 113a and low-resistance layer 113b, etc., which constitute the rain region, silicon-based semiconductor It is preferable to include semiconductors such as G e (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), It may also be formed from a material containing GaAlAs (gallium aluminum arsenide), etc. A silicon-based structure in which the effective mass is controlled by applying stress to the particles and changing the lattice spacing. Alternatively, by using GaAs and GaAlAs, the first transistor 1 10 HEMT (High Electron Mobility Transisto You can also use r).

[0068] The low-resistance layers 113a and 113b are semiconductor materials applied to the semiconductor film 112. In addition, elements that impart n-type conductivity, such as arsenic and phosphorus, or p-type conductivity, such as boron. It contains elements that confer [a certain characteristic].

[0069] The gate electrode 115 is made of an element that imparts n-type conductivity, such as arsenic or phosphorus, or boron. Semiconductor materials such as silicon, metallic materials, and alloy materials containing elements that impart p-type conductivity. Conductive materials such as phosphates or metal oxide materials can be used. The threshold voltage can be adjusted. To do this, it is preferable to adjust the work function using a gate electrode, specifically the gate electrode It is preferable to use materials such as titanium nitride or tantalum nitride for the electrodes. Furthermore, conductivity and filling To achieve both density and durability, metal materials such as tungsten and aluminum are laminated into the gate electrode. It is preferable to use it as such, and in particular, the use of tungsten is preferable in terms of heat resistance.

[0070] Here, the configuration including the first transistor 110 is the first layer 11 in the stacked structure 10. It corresponds to.

[0071] Here, instead of the first transistor 110, we use a transistor 160 as shown in Figure 4. It may be there. To the left of the dashed line in Figure 4, the cross-section of transistor 160 in the channel length direction is shown. The cross-section in the channel width direction is shown to the right of the dashed line. Transistor 160 shown in Figure 4 is channel The semiconductor film 112 (part of the semiconductor substrate) on which the flannel is formed has a convex shape, and its side and top A gate insulating film 114, a gate electrode 115a, and a gate electrode 115b are provided along the surface. Furthermore, the gate electrode 115a may be made of a material that adjusts the work function. Since transistor 160 utilizes the protrusions of the semiconductor substrate, it is a FIN type transistor. It is also called [another name]. Furthermore, it functions as a mask for forming the protrusion, by being in contact with the upper part of the protrusion. It may have an insulating film. In this case, a portion of the semiconductor substrate is processed to form a protrusion. Although this example illustrates the case, a semiconductor film having a convex shape may also be formed by processing the SOI substrate.

[0072] The first transistor 110 is covered by insulating film 121, insulating film 122, insulating film 123 and The insulating film 124 is arranged in a series of stacked layers.

[0073] When a silicon-based semiconductor material is used for the semiconductor film 112, the insulating film 122 contains hydrogen. This is preferable. A hydrogen-containing insulating film 122 is provided on the first transistor 110, and a heat treatment is performed. By doing so, the hydrogen in the insulating film 122 terminates the dangling bond in the semiconductor film 112. This improves the reliability of the first transistor 110.

[0074] The insulating film 123 is formed by the first transistor 110 and the like which are located in the layer below it. It functions as a planarizing film that flattens the difference. The upper surface of the insulating film 123 is to improve flatness. Chemical Mechanical Polishing (CMP) It may also be flattened by a flattening treatment using methods such as the ) method.

[0075] The insulating film 124 may also function as a barrier film. The insulating film 124 may be unnecessary. It is not necessary to set it up.

[0076] In addition, the insulating film 121, insulating film 122, insulating film 123, and insulating film 124 have a low-resistance layer 113. a. Plugs 161, 163, etc., which are electrically connected to the low-resistance layer 113b are embedded. The gate electrode 115 of the first transistor 110 is electrically connected to a plug 162, etc. It is included. Furthermore, in this specification, etc., the electrode and the wiring electrically connected to the electrode are considered to be one. It may also be a physical object. That is, a part of the wiring may function as an electrode, or a part of the electrode may be It can also function as wiring.

[0077] A configuration including insulating film 121, insulating film 122, insulating film 123, and insulating film 124 is a laminated structure 1 This corresponds to the first insulating film 21 at 0.

[0078] The upper part of the insulating film 124 and the upper part of the plug 162 are connected to one electrode 136 of the capacitive element 130. A feature is provided. Electrode 136 is electrically connected to plug 162.

[0079] An insulating film 137 is provided on the electrode 136 of the capacitive element 130, and the capacitive element is provided on the insulating film 137. The other electrode 138 of 130 is provided. Note that electrode 138 is electrically connected to the wiring CL. They are connected. Also, the wiring CL is connected to the gate electrode 105 of the second transistor 100. It has an overlapping area.

[0080] Here, the configuration including electrode 136, electrode 138 and wiring CL, etc., in the laminated structure 10 This corresponds to the first wiring layer 31.

[0081] Each plug (plug 161 to plug 163, etc.) and each electrode (electrode 136, electrode 138, etc.) Materials such as metal materials, alloy materials, or metal oxide materials are used as conductive materials. It is possible to have both heat resistance and conductivity with high melting point materials such as tungsten and molybdenum. It is preferable to use a material, and in particular to use tungsten. Also, copper and other materials are preferable. It is preferable to form it with a low-resistivity conductive material.

[0082] Furthermore, the materials used for the wiring CL include metal materials, alloy materials, or metal oxide materials. Electrical materials can be used. In particular, they can be formed from low-resistance conductive materials such as aluminum or copper. It is preferable to do so. By using the materials described above, the wiring resistance can be reduced. .

[0083] Furthermore, electrodes 136, 138, and wiring CL, etc., are embedded in the insulating film 125. Preferably, the upper surface of the insulating film 125 is flattened.

[0084] The barrier film 120 is provided covering the upper surface of the insulating film 125. The barrier film 120 is This corresponds to the barrier film 41 in the laminated structure 10. The material of the barrier film 120 is the above-mentioned barrier film 41. The description regarding the rear membrane 41 can be used as reference.

[0085] Furthermore, the barrier film 120 is filled with plugs 164, 165, and 166, which will be described later. It has an opening into which it is inserted.

[0086] Wiring 132 is provided on the barrier film 120. The configuration including the wiring 132 is a laminated structure This corresponds to the second wiring layer 32 in structure 10.

[0087] The wiring 132 overlaps with the channel formation region of the second transistor 100, which will be described later. It is provided and functions as the second gate electrode of the second transistor 100.

[0088] Here, the materials constituting the wiring 132 etc. are metal materials, alloy materials, or metal oxides. Conductive materials such as materials can be used. In particular, tungsten can be used when heat resistance is required. It is preferable to use high-melting-point materials such as tene or molybdenum. Also, considering conductivity, It is preferable to use a low-resistance metal or alloy material, such as aluminum, chromium, or copper. , a single layer of a metallic material such as tantalum or titanium, or an alloy material containing such a metallic material, They may be used in stacked form.

[0089] Furthermore, the materials used to constitute the wiring 132, etc., may include phosphorus, boron, carbon, nitrogen, or transition gold. It is preferable to use a metal oxide that contains elements other than the main component, such as group elements. Group oxides can achieve high conductivity. For example, In-Ga oxides and In-Zn oxides. In-M-Zn oxides (where M is Al, Ti, Ga, Y, Zr, La, Ce, Nd) This involves using materials made by incorporating the aforementioned elements into metal oxides such as Hf to enhance conductivity. can.

[0090] An insulating film 126 is provided, covering the barrier film 120 and the wiring 132. The region containing 126 corresponds to the second insulating film 22 in the laminated structure 10.

[0091] It is preferable that the upper surface of the insulating film 126 is flattened by the planarization treatment described above.

[0092] It is preferable to use an oxide material for the insulating film 126 in which some of the oxygen is desorbed by heating. .

[0093] As an oxide material that desorbs oxygen upon heating, it contains more oxygen than satisfactorily satisfying the stoichiometric composition. It is preferable to use an oxide containing oxygen. Oxygen-containing oxide films undergo partial oxygen elimination upon heating. Oxide films containing more oxygen than those described above can be analyzed by thermal desorption gas spectroscopy (TDS). Oxygen converted to oxygen atoms by esorption spectroscopy analysis The amount of detachment is 1.0 × 10 18 atoms / cm 3 Preferably 3.0 × 10 20 at oms / cm 3 The above describes the oxide film. Note that the surface temperature of the film during the above TDS analysis was The preferred temperature range is between 100°C and 700°C, or between 100°C and 500°C. stomach.

[0094] For example, a material containing silicon oxide or silicon oxide nitride can be used as such a material. It is preferable to use metal oxides. Alternatively, metal oxides may be used. Silicon oxidative nitride refers to a material whose composition contains more oxygen than nitrogen. Silicon nitride is a material whose composition contains more nitrogen than oxygen.

[0095] A second transistor 100 is provided on top of the insulating film 126. The configuration including Zista 100 corresponds to the second layer 12 in the laminated structure 10.

[0096] The second transistor 100 has an insulating film 106a in contact with the upper surface of the insulating film 126, and an insulating film The oxide semiconductor film 101a is in contact with the upper surface of 106a, and the oxide semiconductor film 101a is in contact with the upper surface of The oxide semiconductor film 101b and the oxide semiconductor film in contact with the upper surface of the oxide semiconductor film 101b Electrodes 103a and 103b are spaced apart in the region overlapping with 101b, and the oxide semiconductor film 10 Oxide semiconductor film 10 in contact with the upper surface of 1b, the upper surface of electrode 103a, and the upper surface of electrode 103b 1c, the gate insulating film 104 on the oxide semiconductor film 101c, and the gate insulating film 104 and acid The gate electrode 105 overlaps with the oxide semiconductor film 101b via the oxide semiconductor film 101c. In addition, the second transistor 100 is covered with insulating film 107, insulating film 108, and insulating film. A border film 127 is provided.

[0097] Furthermore, the plug 164, which is electrically connected to the plug 161 and electrode 103a, is insulated by the insulating film 125. , barrier film 120, insulating film 126, insulating film 106a, oxide semiconductor film 101a, oxide semiconductor It is provided so as to be embedded in the conductive film 101b and electrode 103a. Also, electrode 136 And the plug 165 that electrically connects to the electrode 103b is an insulating film 125, a barrier film 120, an insulating film Edge film 126, insulating film 106a, oxide semiconductor film 101a, oxide semiconductor film 101b, and It is provided so as to be embedded in electrode 103b.

[0098] Also, simultaneously with the second transistor 100, the insulating film 106b and the oxide semiconductor film 131a, An oxide semiconductor film 131b and an electrode 103c are formed, and the plug 163 and electrode 103c are The electrically connected plug 166 consists of an insulating film 125, a barrier film 120, an insulating film 126, and an insulating film. Embedded in 106b, oxide semiconductor film 131a, oxide semiconductor film 131b, and electrode 103c. It is designed to be inserted.

[0099] Here, the gate electrode 115 of the first transistor 110 and the electrode 136 of the capacitive element 130 , and the node including the electrode 103b of the second transistor 100 is shown in Figure 1(A). It corresponds to FN.

[0100] Furthermore, at least a portion (or all) of electrode 103a (and / or electrode 103b) ) is a semiconductor such as oxide semiconductor film 101b (and / or oxide semiconductor film 101a). Provided on at least a portion (or all) of the surface, sides, top surface, and / or bottom surface of the film It is being done.

[0101] Alternatively, at least a portion (or all) of electrode 103a (and / or electrode 103b) The part is a semiconductor such as oxide semiconductor film 101b (and / or oxide semiconductor film 101a). At least part (or all) of the surface, sides, upper surface, and / or lower surface of the body membrane, and in contact with Touching, or at least part of electrode 103a (and / or electrode 103b). (or all of) the oxide semiconductor film 101b (and / or oxide semiconductor film 101a) It is in contact with at least a portion (or all) of the semiconductor film, such as the one shown.

[0102] Alternatively, at least a portion (or all) of electrode 103a (and / or electrode 103b) The part is a semiconductor such as oxide semiconductor film 101b (and / or oxide semiconductor film 101a). At least part (or all) of the surface, sides, upper surface, and / or lower surface of the body membrane, and They are electrically connected. Or, at least one of the electrodes 103a (and / or electrode 103b) However, some (or all) of them are oxide semiconductor films 101b (and / or oxide semiconductor films It is electrically connected to part (or all) of the semiconductor film, such as 101a).

[0103] Alternatively, at least a portion (or all) of electrode 103a (and / or electrode 103b) The part is a semiconductor such as oxide semiconductor film 101b (and / or oxide semiconductor film 101a). Near the surface, sides, upper surface, and / or lower surface of the body membrane, at least part (or all) of it. They are arranged in contact with each other. Or, at least one of the electrodes 103a (and / or electrode 103b) However, some (or all) of them are oxide semiconductor films 101b (and / or oxide semiconductor films It is positioned in close proximity to a part (or all) of the semiconductor film, such as 101a).

[0104] Alternatively, at least a portion (or all) of electrode 103a (and / or electrode 103b) The part is a semiconductor such as oxide semiconductor film 101b (and / or oxide semiconductor film 101a). The lateral side of at least part (or all) of the surface, lateral, upper, and / or lower surface of the body membrane. It is positioned as follows: or, at least of electrode 103a (and / or electrode 103b) Also, some (or all) of them are oxide semiconductor film 101b (and / or oxide semiconductor film 10 It is located on the side of a part (or all) of a semiconductor film, such as 1a).

[0105] Alternatively, at least a portion (or all) of electrode 103a (and / or electrode 103b) The part is a semiconductor such as oxide semiconductor film 101b (and / or oxide semiconductor film 101a). Oblique surfaces of at least part (or all) of the surface, sides, top, and / or bottom surfaces of the body membrane. It is positioned on the upper side. Or, less of the electrodes 103a (and / or electrode 103b) However, some (or all) of them are oxide semiconductor films 101b (and / or oxide semiconductor films It is positioned diagonally above a part (or all) of the semiconductor film, such as 101a).

[0106] Alternatively, at least a portion (or all) of electrode 103a (and / or electrode 103b) The part is a semiconductor such as oxide semiconductor film 101b (and / or oxide semiconductor film 101a). The upper side of at least part (or all) of the surface, lateral, upper, and / or lower surface of the body membrane. It is positioned as follows: or, at least of electrode 103a (and / or electrode 103b) Also, some (or all) of them are oxide semiconductor film 101b (and / or oxide semiconductor film 10 It is positioned on top of part (or all) of a semiconductor film such as 1a).

[0107] For example, the above oxide semiconductor may contain at least indium (In) or Preferably, it contains zinc (Zn). More preferably, an In-M-Zn oxide (where M is A) is used. (Denoted by metals such as l, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf) Contains oxides.

[0108] In particular, the semiconductor film has multiple crystalline portions, and the c-axis of the crystalline portion is the plane on which the semiconductor film is formed. , or oriented perpendicular to the upper surface of the semiconductor film, and without grain boundaries between adjacent crystalline portions. It is preferable to use an oxide semiconductor film.

[0109] By using such materials as semiconductor films, fluctuations in electrical properties are suppressed, and reliability is improved. High-quality transistors can be achieved.

[0110] Furthermore, regarding preferred forms of oxide semiconductors applicable to semiconductor films and methods for forming them, This will be explained in detail in a later embodiment.

[0111] A semiconductor device according to one aspect of the present invention comprises an oxide semiconductor film and an insulating film that overlaps the oxide semiconductor film. Between them, at least one of the metal elements constituting the oxide semiconductor film is a constituent element. It is preferable to have a first oxide semiconductor film as an element. Suppression of trap level formation at the interface between the film and the insulating film overlapping the oxide semiconductor film. It is possible.

[0112] In other words, one aspect of the present invention relates to at least the channel formation region of an oxide semiconductor film. The top and bottom surfaces are acidic, which functions as a barrier film to prevent the formation of interface states in the oxide semiconductor film. It is preferable to have a configuration that is in contact with the oxide film. With such a configuration, the oxide semi The formation of oxygen vacancies and the introduction of impurities in the conductive film and at the interface, which are factors in the generation of carriers. Because this can be suppressed, oxide semiconductor films can be made highly pure and intrinsically purifiable. Degree intrinsic conversion refers to making an oxide semiconductor film intrinsic or substantially intrinsic. Therefore, This suppresses fluctuations in the electrical characteristics of transistors containing the oxide semiconductor film, thereby enabling highly reliable semiconductor devices. It will become possible to provide a place for this purpose.

[0113] In this specification, when we refer to something as substantially intrinsic, the carrier density of the oxide semiconductor film is , 1 x 10 17 / cm 3 Less than 1 × 10 15 / cm 3 Less than, or 1 × 10⁻⁶ 13 / cm 3 It is less than. By making oxide semiconductor films highly pure and intrinsic, stable electrical properties are obtained for transistors. It is possible to assign gender to it.

[0114] The oxide semiconductor film 101a is provided between the insulating film 106a and the oxide semiconductor film 101b. It is being done.

[0115] The oxide semiconductor film 101c is provided between the oxide semiconductor film 101b and the gate insulating film 104. More specifically, the oxide semiconductor film 101c has an upper surface which is electrode 103a and It is provided in contact with the lower surface of electrode 103b and the lower surface of gate insulating film 104.

[0116] The oxide semiconductor films 101a and 101c each contain an oxide containing one or more of the same metal elements as the oxide semiconductor film 10 1b.

[0117] Note that the boundaries between the oxide semiconductor film 101b and the oxide semiconductor film 101a, and between the oxide semiconductor film 101b and the oxide semiconductor film 101c may be unclear.

[0118] For example, the oxide semiconductor films 101a and 101c contain In or Ga, and typically include In-based oxides, Ga-based oxides, In-Ga-based oxides, In-Zn-based acid oxides, In-M-Zn-based oxides (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf), and a material is used in which the energy of the lower end of the conduction band is closer to the vacuum level than that of the oxide semiconductor film 101b. Typically, the difference between the energy of the lower end of the conduction band of the oxide semiconductor films 101a and 10 1c and the energy of the lower end of the conduction band of the oxide semiconductor film 101b is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 e V or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less, which is preferred.

[0119] By using an oxide with a higher content of Ga that functions as a stabilizer in the oxide semiconductor films 101a and 101c provided so as to sandwich the oxide semiconductor film 101b, the release of oxygen from the oxide semiconductor film 101b can be suppressed.

[0120] As the oxide semiconductor film 101b, for example, In:Ga:Zn = 1:1:1 or 3:1: ​​​​​When using an In-Ga-Zn-based oxide with an atomic ratio of 2, the oxide semiconductor film 101a or as the oxide semiconductor film 101c, for example, In:Ga:Zn = 1:3:2, 1:3:4, 1 :3:6, 1:6:4, 1:6:8, 1:6:10, or 1:9:6, etc. of the atomic ratio of In-Ga-Zn-based oxides can be used. Note that the atomic ratios of the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 101c each include fluctuations of plus or minus 20% of the above atomic ratio as an error. Also, the oxide semiconductor film 101a and the oxide semiconductor film 101c may use materials with the same composition or materials with different compositions.

[0121] Also, when using an In-M-Zn-based oxide as the oxide semiconductor film 101b, the target used to form the semiconductor film that becomes the oxide semiconductor film 101b, when the atomic ratio of the metal elements contained in the target is In:M:Zn = x1:y1:z1, the value of x1 / y 1 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less of the atomic ratio of the oxide is preferably used. Note that by setting z1 / y1 to 6 or less, the CAAC-OS film described later is likely to be formed. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:1:1, 3:1:2 etc.

[0122] Also, when using an In-M-Zn-based oxide as the oxide semiconductor film 101a and the oxide semiconductor film 101c, the target used to form the oxide semiconductor film that becomes the oxide semiconductor film 101a and the oxide semiconductor film 101c, the atomic ratio of the metal elements contained in the target is ​​​​​When In:M:Zn=x2:y2:z2, x2 / y2 <x1 / y1であり、z2 Use an oxide with an atomic ratio of 1 / 3 or more and 6 or less for the value of / y2, preferably 1 or more and 6 or less. This is preferable. Furthermore, by setting z2 / y2 to 6 or less, the CAAC-OS film described later will form This makes it easier to achieve. A typical example of the atomic ratio of the target metal elements is In:M:Zn Examples include 1:3:4, 1:3:6, 1:3:8, etc.

[0123] Furthermore, oxide semiconductor film 101a and oxide semiconductor film 101c are coated with oxide semiconductor film 101 By using a material with energy closer to the vacuum level at the lower end of the conduction band compared to b, Channels are mainly formed in the semiconductor film 101b, and the oxide semiconductor film 101b is the main current channel. This forms a channel. In this way, the oxide semiconductor film 101b in which the channel is formed is made of the same metal element By sandwiching this between oxide semiconductor films 101a and 101c, this The formation of these interface states is suppressed, improving the reliability of the transistor's electrical characteristics.

[0124] Furthermore, this is not limited to the semiconductor characteristics and electrical characteristics (field effect) of the transistor as needed. A suitable composition should be used depending on the mobility, threshold voltage, etc. To obtain the semiconductor characteristics of the transistor, oxide semiconductor film 101a, oxide semiconductor film 10 Carrier density, impurity concentration, defect density, metal elements and acid of 1b and oxide semiconductor film 101c It is preferable to use appropriate ratios of elemental atoms, interatomic distances, densities, etc.

[0125] Here, between the oxide semiconductor film 101a and the oxide semiconductor film 101b, It may have a mixed region of film 101a and oxide semiconductor film 101b. There may be a mixed region between the conductor film 101b and the oxide semiconductor film 101c. The mixed region has a lower interface state density. Therefore, in the laminate of the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 101c, the energy changes continuously (also referred to as a continuous junction) in the vicinity of each interface. This results in a band structure. Here, the band structure will be described. For ease of understanding, the conduction band lower energy (Ec) of the insulating film 125, the oxide semiconductor film 101a, the oxide semiconductor film 101b, the oxide semiconductor film 101c, and the gate insulating film 104 is shown. As shown in FIGS. 5(A) and 5(B), in the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 101c, the energy of the lower end of the conduction band changes continuously.

[0126] This is also understood from the fact that the elements constituting the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 101c are common, and oxygen diffuses easily among them. Therefore, although the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 101c are a laminate of layers with different compositions, it can also be said that they are physically continuous. The oxide semiconductor films laminated with a common main component are fabricated so that not only are the layers simply laminated, but a continuous junction (here, in particular, a U-shaped well structure in which the energy of the lower end of the conduction band changes continuously between the layers) is formed.

[0127] That is, the laminate structure is formed such that there are no impurities that form defect levels such as trap centers or recombination centers at the interfaces of each layer.

[0128]

[0128] If If impurities are present between the layers of a stacked multilayer film, the continuity of the energy bands is lost. Therefore, carriers are trapped or recombined at the interface and disappear.

[0129] Note that in Figure 5(A), the Ec values ​​of oxide semiconductor film 101a and oxide semiconductor film 101c are the same. The examples given are for cases where they are similar, but they may be different. For example, oxide semiconductors. If the Ec of the oxide semiconductor film 101c has a higher energy than that of film 101a, the band Part of the structure is shown in Figure 5(B).

[0130] From Figures 5(A) and 5(B), the oxide semiconductor film 101b becomes a well, and the second In transistor 100, the channel is formed in the oxide semiconductor film 101b. I understand. Note that oxide semiconductor film 101a, oxide semiconductor film 101b, oxide semiconductor film 10 1c is a U-shaped well because the energy at the lower end of the conduction band changes continuously. It can also be called e Well. It can also be called a plug-in channel.

[0131] Furthermore, oxide semiconductor film 101a and oxide semiconductor film 101c, and silicon oxide film, etc. Near the interface with the insulating film, trap levels can form due to impurities and defects. Due to the presence of the semiconductor film 101a and the oxide semiconductor film 101c, the oxide semiconductor film 101 b and the trap level can be kept apart. However, the oxide semiconductor film 101a and The energy difference between the Ec of the oxide semiconductor film 101c and the Ec of the oxide semiconductor film 101b is If the energy difference is small, electrons in the oxide semiconductor film 101b exceed the energy difference and reach the trap level. This can happen. By being trapped in a trap level, negative fixed charges can form at the insulating film interface. As a result, the transistor's threshold voltage shifts in the positive direction.

[0132] Therefore, in order to reduce the fluctuation of the transistor threshold voltage, the oxide semiconductor film 10 An energy is between the Ec of 1a and oxide semiconductor film 101c and oxide semiconductor film 101b. It is necessary to create a difference. The energy difference in each case should preferably be 0.1 eV or greater. A voltage of 0.15 eV or higher is more preferable.

[0133] Furthermore, the oxide semiconductor film 101a, oxide semiconductor film 101b, and oxide semiconductor film 101c It is preferable that the crystalline portion is included. In particular, by using crystals oriented along the c axis, transient This allows for the imparting of stable electrical characteristics to the element.

[0134] Furthermore, in the band structure shown in Figure 5(B), the oxide semiconductor film 101c is not provided. Between the oxide semiconductor film 101b and the gate insulating film 104, In-Ga oxide (for example, original You may also set a ratio of In:Ga = 7:93.

[0135] The oxide semiconductor film 101b is more efficient than the oxide semiconductor film 101a and the oxide semiconductor film 101c. Also, an oxide with low electron affinity is used. For example, as the oxide semiconductor film 101b, The electron affinity is 0.07 eV or more higher than that of semiconductor film 101a and oxide semiconductor film 101c. 3 eV or less, preferably 0.1 eV to 0.7 eV, and more preferably 0.15 eV Use oxides with an electron affinity of 0.4 eV or less. Note that electron affinity is between the vacuum level and the lower edge of the conduction band. It is the difference in energy.

[0136] Here, the thickness of the oxide semiconductor film 101b is at least greater than that of the oxide semiconductor film 101a. It is preferable to form it thickly. The thicker the oxide semiconductor film 101b, the better the transistor's ON state. The current can be increased. Also, oxide semiconductor film 101a is oxide semiconductor film 101b The thickness should be such that the effect of suppressing the formation of interface states is not lost. For example, oxide The thickness of the semiconductor film 101b is greater than 1 times the thickness of the oxide semiconductor film 101a. Preferably, it should be 2 times or more, more preferably 4 times or more, and more preferably 6 times or more. However, this does not apply if there is no need to increase the on-current of the transistor. The thickness of the semiconductor film 101a may be greater than or equal to the thickness of the oxide semiconductor film 101b.

[0137] Furthermore, the oxide semiconductor film 101c is similar to the oxide semiconductor film 101a, The thickness should be such that the effect of suppressing the formation of the 01b interface state is not lost. For example, The thickness of the oxide semiconductor film 101a should be the same as or less than that of the oxide semiconductor film 101a. If 1c is thick, there is a risk that the electric field from the gate electrode will have difficulty reaching the oxide semiconductor film 101b. Therefore, it is preferable to form the oxide semiconductor film 101c thinly. For example, oxide semiconductor It is sufficient to make it thinner than the thickness of the body film 101b. However, it is not limited to this, and the oxide semiconductor film 10 The thickness of 1c is determined considering the breakdown voltage of the gate insulating film 104 and corresponds to the voltage used to drive the transistor. You can set it as appropriate.

[0138] Here, for example, the oxide semiconductor film 101b is an insulating film with different constituent elements (for example, oxide When in contact with an insulating film (such as a reconstituted film), an interface state is formed at the interface, and the interface The levels may form a channel. In such cases, a second level with a different threshold voltage is formed. A transistor may appear, causing the apparent threshold voltage of the transistor to fluctuate. However, in the transistor of this configuration, the metal constituting the oxide semiconductor film 101b Since the oxide semiconductor film 101a contains one or more elements, the oxide semiconductor film 101 It becomes difficult to form interface states at the interface between a and the oxide semiconductor film 101b. By providing the body film 101a, variations in electrical characteristics such as the threshold voltage of the transistor are reduced. This can reduce fluctuations.

[0139] Furthermore, a channel is formed at the interface between the gate insulating film 104 and the oxide semiconductor film 101b. In some cases, interfacial scattering may occur at the interface, which can reduce the field-effect mobility of the transistor. However, in the transistor of this configuration, the oxide semiconductor film 101b is composed of Since it has an oxide semiconductor film 101c containing one or more metal elements, the oxide semiconductor film 1 At the interface between 01b and the oxide semiconductor film 101c, carrier scattering is less likely to occur, and transient This allows for an increase in the field-effect mobility of the sta.

[0140] Electrodes 103a and 103b function as a source electrode, one of which functions as a drain electrode. It functions as a pole.

[0141] Electrodes 103a and 103b are made of aluminum, titanium, chromium, nickel, copper, and Metals such as tungsten, zirconium, molybdenum, silver, tantalum, or tungsten. or an alloy with this as the main component is used as a single-layer or laminated structure. For example, sil A single-layer structure of an aluminum film containing condensate, and a double-layer structure in which an aluminum film is laminated on a titanium film. A two-layer structure in which an aluminum film is laminated on a tungsten film, copper-magnesium-aluminum A two-layer structure in which a copper film is laminated on a um alloy film, a two-layer structure in which a copper film is laminated on a titanium film, tung A two-layer structure in which a copper film is laminated on a stainless steel film, a titanium film or titanium nitride film, and the titanium film Alternatively, an aluminum film or copper film is laminated on top of a titanium nitride film, and then titanium is laid on top of that. A three-layer structure forming a film or titanium nitride film, a molybdenum film or molybdenum nitride film, and An aluminum film or copper film is laminated on top of a molybdenum film or molybdenum nitride film. Furthermore, there are three-layer structures, such as one in which a molybdenum film or molybdenum nitride film is formed on top of the above. Alternatively, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0142] The gate dielectric film 104 can be, for example, silicon oxide, silicon oxide nitride, or silicon oxide nitride. Aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, zirconium titanate Lead conate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)T Insulating films containing so-called high-k materials such as iO3 (BST) are used in single-layer or multi-layer configurations. These insulating films can be made of, for example, aluminum oxide, bismuth oxide, or oxide. Germanium, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yt oxide Zirconium oxide may be added. Alternatively, these insulating films may be nitrided. i. The above insulating film is used with silicon oxide, silicon oxide nitride, or silicon nitride laminated on top. That's fine.

[0143] Furthermore, as the gate insulating film 104, an acid satisfying a stoichiometric composition, similar to the insulating film 126, is used. It is preferable to use an oxide insulating film that contains more oxygen than the element.

[0144] Furthermore, using certain materials as gate insulating films can trap electrons in the gate insulating film under specific conditions. This can also increase the threshold voltage. For example, silicon oxide and hafni oxide Like a multilayer film of aluminum, a portion of the gate insulating film contains hafnium oxide, aluminum oxide, and oxide Using materials with many electron trapping levels, such as tantalum, allows for higher temperatures (semiconductor operating temperature). Alternatively, temperatures higher than the storage temperature, or between 125°C and 450°C, typically 1 Under temperatures between 50°C and 300°C, the potential of the gate electrode is the same as the potential of the source electrode and the drain electrode. By maintaining a higher state for more than one second, typically more than one minute, the gate electricity from the semiconductor film is released. Electrons move toward the poles, and some of them are trapped in electron trapping levels.

[0145] In this way, a transistor that has captured the necessary amount of electrons to reach the electron trapping level will have a threshold voltage This shifts to the positive side. The amount of electrons captured is controlled by controlling the voltage of the gate electrode. This allows for the control of the threshold voltage. Furthermore, it allows for the capture of electrons. The melting process can be performed during the transistor manufacturing process.

[0146] For example, after forming the wiring that connects to the source or drain electrode of a transistor, Alternatively, after the completion of the preceding process (wafer processing), or after the wafer dicing process, It is best to do this at some stage before the animals leave the factory, such as after they have been caged. In any case, afterwards, It is preferable that the product not be exposed to temperatures above 25°C for more than one hour.

[0147] The gate electrode 105 can be made of, for example, aluminum, chromium, copper, tantalum, titanium, molybdenum. N, a metal selected from tungsten, or an alloy containing the above-mentioned metals, or the above-mentioned It can be formed using alloys of combined metals. Also, manganese, zirconium One or more metals selected from the following may be used. In addition, impurities such as phosphorus may be used. Semiconductors such as polycrystalline silicon doped with an element, and silicides such as nickel silicide A ion may also be used. For example, a two-layer structure in which a titanium film is laminated on an aluminum film, or a nitrided titanium film. A two-layer structure in which a titanium film is laminated on a tungsten film, and a two-layer structure in which a tungsten film is laminated on a titanium nitride film. Layered structure, two-layer structure in which a tungsten film is laminated on a tantalum nitride film or tungsten nitride film. A titanium film is constructed, and an aluminum film is laminated on top of the titanium film, and then another titanium film is laid on top of that. It forms a three-layer structure, etc. Also, aluminum, titanium, tantalum, tungsten, A combination of one or more metals selected from molybdenum, chromium, neodymium, and scandium. A combined alloy film or a nitride film may also be used.

[0148] Furthermore, the electrode 105 contains indium tin oxide and tungsten oxide. Indium zinc oxide containing oxides, tungsten oxide, and indium acid containing titanium oxide Indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide are added. It is also possible to apply conductive materials with light-transmitting properties, such as indium tin oxide. Alternatively, a laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal can be used.

[0149] Furthermore, plug 167, which is electrically connected to plug 164, has insulating film 127, insulating film 107, It is provided so as to be embedded in the insulating film 108. It is also electrically connected to the gate electrode 105. The plug 168 is configured to be embedded in the insulating film 127, insulating film 107, and insulating film 108. It can be kicked. Also, plug 169 which is electrically connected to plug 166 has an insulating film 127, insulating film 107 is provided so as to be embedded in the insulating film 108.

[0150] Furthermore, between the gate electrode 105 and the gate insulating film 104, an In-Ga-Zn-based oxynitride semiconductor is used. Conductor films, In-Sn oxynitride semiconductor films, In-Ga oxynitride semiconductor films, In-Zn oxynitride semiconductor films Oxynitride semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (I These films may be provided with nN, ZnN, etc. The film has a voltage of 5 eV or higher, preferably 5.5 eV or higher. It has the above work function, and since it is greater than the electron affinity of oxide semiconductors, oxide semiconductors The threshold voltage of a transistor using a body can be shifted to a positive value, so-called normally - Off-type switching elements can be realized. For example, In-Ga-Zn oxynitride semiconductors. When using a body membrane, the nitrogen concentration should be at least higher than that of the oxide semiconductor film 101b, specifically 7 An In-Ga-Zn-based oxynitride semiconductor film is used in an atomic percentage or greater.

[0151] The insulating film 107, like the barrier film 120, can be made of a material that does not easily diffuse water or hydrogen. It is preferable. In particular, it is preferable to use a material that is not permeable to oxygen as the insulating film 107. It's nice.

[0152] By covering the oxide semiconductor film 101b with an insulating film 107 containing a material that is not easily permeable to oxygen, This suppresses the release of oxygen from the oxide semiconductor film 101b above the insulating film 107. Furthermore, the oxygen detached from the insulating film 126 is contained below the insulating film 107. Because it can be embedded, the amount of oxygen that can be supplied to the oxide semiconductor film 101b can be increased. It is possible.

[0153] Furthermore, the insulating film 107, which is impermeable to water and hydrogen, prevents external interference with the oxide semiconductor. This suppresses the inclusion of impurities such as water and hydrogen, and improves the electrical characteristics of the second transistor 100. This suppresses fluctuations and enables the creation of highly reliable transistors.

[0154] Furthermore, below the insulating film 107, oxygen is desorbed by heating, similar to the insulating film 126. An insulating film is provided, and oxygen is also supplied from above the oxide semiconductor film 101b via the gate insulating film 104. It may also be supplied in this configuration.

[0155] Here, we show an example of a transistor configuration applicable to the second transistor 100. Figure 6(A) is a schematic top view of the transistor illustrated below, and Figures 6(B) and 6(C) These are schematic cross-sectional diagrams when the section is cut along the cutting lines A1-A2 and B1-B2 in Figure 6(A), respectively. Figure 6(B) corresponds to a cross-section of the transistor in the channel length direction, and Figure 6(C) This corresponds to the cross-section in the channel width direction of the transistor.

[0156] As shown in Figure 6(C), in the cross-section of the transistor in the channel width direction, the gate electrode The oxide semiconductor film 101b is provided facing the upper and side surfaces, Channels are formed not only near the top surface of 01b but also near the sides, resulting in an effective channel width. This can increase the current in the ON state (ON current). This is especially true for oxide semiconductors. The width of film 101b is extremely small (for example, 50 nm or less, preferably 30 nm or less, more preferably If the wavelength is less than 20 nm, channels are formed inside the oxide semiconductor film 101b. As the area affected expands, the miniaturization increases, leading to a greater contribution to the on-current.

[0157] Furthermore, as shown in Figures 7(A), 7(B), and 7(C), the width of the gate electrode 105 is narrowed. It is also possible to do so. In that case, for example, electrodes 103a and 103b, and gate electrode 105 Using these as masks, argon, hydrogen, phosphorus, boron, etc. are applied to oxide semiconductor film 101b, etc. Any impurities can be introduced. As a result, in oxide semiconductor films such as 101b, Low resistance region 109a and low resistance region 109b can be provided. 9a and the low-resistance region 109b do not necessarily need to be provided. Note that this applies not only to Figure 6, but also to other figures. In this drawing as well, the width of the gate electrode 105 can be narrowed.

[0158] The transistors shown in Figures 8(A) and 8(B) are different from the transistors exemplified in Figure 6. The oxide semiconductor film 101c is provided in contact with the lower surfaces of electrodes 103a and 103b. The main difference lies in the presence of certain features.

[0159] With this configuration, oxide semiconductor film 101a, oxide semiconductor film 101b and During the deposition of each film constituting the oxide semiconductor film 101c, exposure to air is required. Because the film can be deposited continuously without interruption, defects at each interface can be reduced.

[0160] Furthermore, in the above, the oxide semiconductor film 101a and oxide are in contact with the oxide semiconductor film 101b. Although a configuration in which a semiconductor film 101c is provided has been described, an oxide semiconductor film 101a or an oxide semiconductor film The configuration may also be one or both of the body membranes 101c omitted.

[0161] Furthermore, in Figure 8, as in Figure 6, the width of the gate electrode 105 can be narrowed. Examples of this case are shown in Figures 9(A) and 9(B). Note that in addition to Figures 6 and 8, other In the drawing, the width of the gate electrode 105 can also be narrowed.

[0162] Note that channel length refers to, for example, the length of the semiconductor (or transistor) in a top view of a transistor. The region where the gate electrode overlaps with the part of the semiconductor through which current flows when the inverter is ON. Source (source region or source electrode) in the region where a region or channel is formed. This refers to the distance between the drain (drain region or drain electrode). In a transistor, the channel length is not necessarily the same across all regions. That is, one The channel length of a transistor may not be fixed to a single value. Therefore, in this specification... The channel length is any one value, maximum value, or minimum value in the region where the channel is formed. Use the value or average.

[0163] Channel width refers to, for example, the width of a semiconductor (or transistor) when it is in the ON state. In the region where the current flows (the part) and the gate electrode overlap, or in the region where the channel is formed This refers to the width of the source or drain in a transistor. The channel width is not necessarily the same across all regions. That is, the channel width of a single transistor The width may not be fixed to a single value. Therefore, in this specification, the channel width is defined as the channel width. This is any one value, maximum value, minimum value, or average value in the region where the Nell is formed.

[0164] Furthermore, depending on the transistor structure, the channel may actually be formed in the region where the channel is formed. The channel width (hereinafter referred to as the effective channel width) and the top view of the transistor are shown. The channel width (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In transistors with a three-dimensional structure, the effective channel width is the top surface of the transistor. The apparent channel width shown in the figure becomes larger, and its effect cannot be ignored. In some cases, this may occur. For example, in transistors with a fine and three-dimensional structure, the upper surface of the semiconductor The proportion of channel regions formed on the semiconductor surface is compared to the proportion of channel regions formed on the semiconductor surface. The sum may become larger. In that case, the apparent channel width shown in the top view The effective channel width actually formed is larger than the initial channel width.

[0165] By the way, in transistors with a three-dimensional structure, the effective channel width is Estimation by measurement can sometimes be difficult. For example, it can be difficult to determine the effective channel width from the design value. For accumulation to occur, it is necessary to assume that the shape of the semiconductor is known. Therefore, the shape of the semiconductor When the exact condition is unknown, it is difficult to accurately measure the effective channel width. .

[0166] Therefore, in this specification, in the top view of a transistor, the semiconductor and the gate electrode overlap. In the region, the apparent channel width, which is the width of the source or drain, is called "enclosure". This is called "Surrounded Channel Width (SCW)". There is a match. Also, in this specification, when simply referred to as channel width, it refers to enclosed channels. It may refer to width or apparent channel width. Or, as used herein, simply channel When "width" is mentioned, it may refer to the effective channel width. Note that channel length and channel width may also be mentioned. Channel width, effective channel width, apparent channel width, enclosed channel width, etc., are all measured in cross-section. The value can be determined by acquiring TEM images and analyzing those images. Cut.

[0167] Furthermore, the field-effect mobility of the transistor and the current value per channel width are calculated to determine the value. In some cases, the calculation may be performed using the enclosed channel width. In that case, the effective channel The result may differ from the value obtained when calculating using the channel width.

[0168] The above is a description of the second transistor, 100.

[0169] The insulating film 127 covering the second transistor 100 is flat, covering the uneven shape of the underlying layer. It functions as a film-forming layer. In addition, the insulating film 108 acts as a protective layer when the insulating film 127 is formed. It may have the function of [missing information]. The insulating film 108 may be omitted if it is not needed.

[0170] Furthermore, the plug 170 is provided so as to be embedded in the insulating film 128, and the plug 167 and the electrical They are electrically connected. Furthermore, the plug 171 is provided to be embedded in the insulating film 128. It is electrically connected to plug 168. Also, plug 172 is embedded in insulating film 128. It is designed to be connected to plug 169 and is electrically connected to it.

[0171] Furthermore, electrode 173 is electrically connected to plug 170 and wiring BL, and electrode 174 is connected to plug 171 and wiring WL are electrically connected, and electrode 175 is electrically connected to plug 172 and wiring SL. It is connected.

[0172] A semiconductor device according to one aspect of the present invention comprises a first transistor 110 and the first transistor Since it has a second transistor 100 located above it, these are arranged in a stack. This reduces the area occupied by the element. Furthermore, the capacitive element 130 is a second transistor Since these are located below the ZISTA 100, stacking them reduces the area occupied by the element. It can be reduced in size. Also, the wiring CL is the gate electrode 105 of the second transistor 100. Because they have overlapping regions, the occupied area of ​​the element can be further reduced. A barrier film is provided between the first transistor 110 and the second transistor 100. 120 causes impurities such as water and hydrogen present in the lower layer to enter the second transistor 10 This can suppress diffusion towards the 0 side.

[0173] The above is an explanation of the example configuration.

[0174] [Example of manufacturing method] In the following, an example of a method for manufacturing the semiconductor device shown in the above configuration example is described in Figures 10 to 1. I will explain using example 2.

[0175] First, prepare the semiconductor substrate 111. For example, the semiconductor substrate 111 may be made of single-crystal silicon Condenser substrates (including p-type or n-type semiconductor substrates), silicon carbide and silicon nitride A compound semiconductor substrate made of lium can be used. Also, the semiconductor substrate 111 and SOI substrates may also be used. In the following, single-crystal silicon is used as the semiconductor substrate 111. Let's explain how to use it.

[0176] Next, an element isolation layer (not shown) is formed on the semiconductor substrate 111. The element isolation layer is LOC OS (Local Oxidation of Silicon) method or STI (Sh This can be achieved using methods such as the (allow Trench Isolation) method.

[0177] When forming p-type and n-type transistors on the same substrate, semiconductor substrate 1 n-wells or p-wells may be formed in part of 11. For example, n-type semiconductor substrate 11 By adding impurity elements such as boron that impart p-type conductivity to 1, a p-well is formed, and the same n-type transistors and p-type transistors may be formed on the substrate.

[0178] Next, an insulating film that will become a gate insulating film 114 is formed on the semiconductor substrate 111. For example, After surface nitriding, oxidation treatment is performed to oxidize the silicon-silicon nitride interface, resulting in silicon oxidized nitride. A silicon nitride film may be formed on the surface. For example, a silicon nitride film may be formed at 700°C in an NH3 atmosphere. A silicon oxide nitride film is obtained by performing oxygen radical oxidation after its formation.

[0179] The insulating film is produced by sputtering, CVD (Chemical Vapor Deposition). sition) method (thermal CVD method, MOCVD (Metal Organic CVD) method (including PECVD (Plasma Enhanced CVD) method, MBE (Mo lecular beam epitaxy) method, ALD (Atomic Layer Deposition method, or PLD (Pulsed Laser Deposit) It may also be formed by depositing a film using methods such as the ion method.

[0180] Next, a conductive film to form the gate electrode 115 is deposited. The conductive film is made of tantalum, tan Metals selected from gusten, titanium, molybdenum, chromium, niobium, etc., or these It is preferable to use alloy materials or compound materials that have metal as the main component. Also, phosphorus, etc. Polycrystalline silicon with added impurities can be used. In addition, a metal nitride film and the above A layered structure of metal films may be used. Examples of metal nitrides include tungsten nitride and molybdenum nitride. Titanium nitride can be used. By providing a metal nitride film, the density of the metal film can be increased. Adhesion can be improved and peeling can be prevented. Also, gate electrode 115 A metal film that controls the work function may be provided.

[0181] Conductive films are produced by sputtering, evaporation, and CVD (thermal CVD, MOCVD, PEC). The film can be deposited by methods such as the VD method. Furthermore, damage caused by plasma can be reduced. For lath processing, thermal CVD, MOCVD, or ALD methods are preferred.

[0182] Next, a resist mask is formed on the conductive film using a lithography method or the like, and the conductive Remove the unnecessary parts of the film. Then, remove the resist mask to create the gate electrode. 115 can be formed.

[0183] Here, we will explain the processing method for the film to be processed. When processing the film to be processed finely, Various microfabrication techniques can be used. For example, resins formed by lithography, etc. A method of slimming the mask may be used. Alternatively, lithography or other methods may be used. A dummy pattern is formed, and after forming sidewalls on the dummy pattern, the dummy part The turns are removed, and the remaining sidewalls are used as a resist mask to process the film. Etching is also permitted. Furthermore, as etching of the workpiece film, a high aspect ratio can be achieved. Therefore, it is preferable to use anisotropic dry etching. Also, inorganic films or metal films A hard mask consisting of the following may also be used.

[0184] The light used to form the resist mask is, for example, i-line (wavelength 365 nm) and g-line (wavelength 43 nm). Light can be used that emits 6nm light, h-line light (wavelength 405nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, or ArF laser light can also be used. Alternatively, exposure may be performed using immersion lithography. Furthermore, the light used for exposure may be extreme ultraviolet light. Light (EUV: Extreme Ultra-violet) or X-rays may also be used. Alternatively, an electron beam can be used instead of the light used for exposure. Extreme ultraviolet light, X-rays or Using an electron beam is preferable because it enables extremely fine processing. When exposure is performed by scanning a beam, such as those mentioned above, a photomask is not required.

[0185] Furthermore, before forming the resist film that will serve as the resist mask, the tightness between the film to be processed and the resist film is An organic resin film having a function to improve adhesion may be formed. The organic resin film may be, for example, made of s The surface is formed by covering the steps in the underlying layer using methods such as the pin coating method to make the surface flat. This allows for the reduction of variations in the thickness of the resist mask provided on the upper layer of the organic resin film. It can be done. Also, when performing particularly fine processing, the organic resin film can be exposed to light used for exposure. It is preferable to use a material that functions as an anti-reflective coating. Examples of organic resin films include BARC (Bottom Anti-Reflection This includes coating films, etc. The organic resin film is removed at the same time as the resist mask is removed. You can either remove it or remove it after removing the resist mask.

[0186] After the gate electrode 115 is formed, a side wall is formed to cover the side surface of the gate electrode 115. Alternatively, the sidewall may be formed by depositing an insulating film thicker than the thickness of the gate electrode 115. Anisotropic etching is performed, leaving the insulating film only on the side portion of the gate electrode 115. It can be formed by [this method].

[0187] When the sidewall is formed, the insulating film that will become the gate insulating film 114 is also etched at the same time. As a result, a gate insulating film 114 is formed on the lower part of the gate electrode 115 and the sidewall. Alternatively, after forming the gate electrode 115, the gate electrode 115 or gate electrode 11 The resist mask for processing 5 is used as an etching mask to etch the insulating film. The gate insulating film 114 may be formed by etching the insulating film. Alternatively, the insulating film may be etched. It can also be used as the gate insulating film 114 without any processing by rinsing.

[0188] Next, the gate electrode 115 (and sidewall) of the semiconductor substrate 111 is provided. An element that imparts n-type conductivity, such as phosphorus, or a p-type conductivity, such as boron, to a region where there is no conductivity. The elements to be added are then added. A schematic cross-sectional view at this stage corresponds to Figure 10(A).

[0189] Next, after forming the insulating film 121, the elements that impart conductivity as described above are activated. The first heat treatment is performed.

[0190] The insulating film 121 is, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride Recon, aluminum oxide, aluminum oxide nitride, aluminum nitride A material such as nium may be used, and it can be provided in a multilayer or single layer. The insulating film 121 is formed by sputtering. , CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method Alternatively, it can be formed using methods such as PLD. In particular, the insulating film can be formed by CVD, preferably... Alternatively, deposition by plasma CVD is preferred because it can improve coverage. Furthermore, to reduce damage caused by plasma, thermal CVD, MOCVD, or A The LD method is preferred.

[0191] The first heat treatment is performed under an inert gas atmosphere such as a noble gas or nitrogen gas, or under a reduced pressure atmosphere. For example, this can be done at temperatures above 400°C and below the substrate's strain point.

[0192] At this stage, the first transistor 110 is formed.

[0193] Next, insulating film 122 and insulating film 123 are formed.

[0194] The insulating film 122 is made of materials that can be used for the insulating film 121, as well as nitrogen containing oxygen and hydrogen. Using silicon dioxide (SiNOH) allows for a larger amount of hydrogen to be released by heating. This is preferable because it allows for this. Furthermore, the insulating film 123 is made of a material that can be used for the insulating film 121. In addition, TEOS (Tetra-Ethyl-Ortho-Silicate) or s A stepped silicon oxide with good coating properties formed by reacting orchids with oxygen or nitrous oxide. It is preferable to use a condenser.

[0195] Insulating film 122 and insulating film 123 are coated by, for example, sputtering, CVD (thermal CVD) Using methods such as MOCVD, PECVD, MBE, ALD, or PLD (including MOCVD, PECVD, etc.) The insulating film can be formed by a CVD method, preferably a plasma CVD method. Deposition by this method is preferable because it can improve coverage. To reduce damage, thermal CVD, MOCVD, or ALD methods are preferred.

[0196] Next, the upper surface of the insulating film 123 is planarized using the CMP method or the like.

[0197] Subsequently, the dangling bonds in the semiconductor film 112 are detached from the insulating film 122 by hydrogen. Then, a second heat treatment is performed to terminate the process.

[0198] The second heat treatment can be carried out under the conditions exemplified in the description of the laminated structure 10 above.

[0199] Next, an insulating film 124 is formed on the insulating film 123.

[0200] Next, a low-resistance layer 11 is applied to insulating film 121, insulating film 122, insulating film 123, and insulating film 124. 3a, an opening is formed that reaches the low-resistance layer 113b and the gate electrode 115, etc. A conductive film is formed to fill the gap, and the conductive film is planarized so that the upper surface of the insulating film 124 is exposed. By applying the processing, plugs 161, 162, 163, etc. are formed. Film formation can be done using methods such as sputtering, CVD (thermal CVD, MOCVD, PECV), etc. It can be formed using methods such as the D method, MBE method, ALD method, or PLD method. Figure 10(B) shows a schematic cross-sectional view at this stage.

[0201] Next, a conductive film is deposited on the insulating film 124. Then, a resist is formed using the same method as described above. A mask is formed, and unwanted portions of the conductive film are removed by etching. Then, a resist mass is formed. By removing the 'ku', an electrode 136 is formed, which will become one of the electrodes of the capacitive element.

[0202] Next, using a resist mask as before, an insulating film 137 is applied to the electrode 136, and the electrode... Electrode 138 is formed. Note that electrode 138 is the gateway of the second transistor 100 which will be formed later. It is preferable to have the electrode 105 overlap with the other electrode.

[0203] Furthermore, electrode 138 is electrically connected to wiring CL. Wiring CL is as shown in Figure 2. The second transistor 100 has a region that overlaps with the gate electrode 105. This allows for a reduction in the area occupied by the element.

[0204] At this stage, the capacitive element 130 is formed (see Figure 10(C)).

[0205] Next, an insulating film is deposited to cover the capacitive element 130, and the surface is flattened so that the top surface of each wiring is exposed. By applying the treatment, an insulating film 125 is formed. The insulating film that becomes the insulating film 125 is an insulating film It can be formed using the same materials and methods as 121, etc.

[0206] It is preferable to perform a third heat treatment after forming the insulating film 125. By removing water and hydrogen contained in each layer, the water and hydrogen content can be reduced. This can be done. Immediately before forming the barrier film 120 described later, a third heat treatment is performed, and the barrier film After thoroughly removing hydrogen and water contained in the layer below 120, the barrier film 120 is formed. As a result, water and hydrogen will diffuse and be released again to the layer below the barrier film 120 in subsequent processes. This can suppress the action.

[0207] The third heat treatment can be carried out under the conditions exemplified in the description of the laminated structure 10.

[0208] Next, a barrier film 120 is formed on the insulating film 125 (see Figure 10(D)).

[0209] The barrier film 120 is produced by, for example, sputtering, CVD (thermal CVD, MOCVD), Formed using methods such as PECVD, MBE, ALD, or PLD. This can be done. In particular, the insulating film is deposited by CVD, preferably by plasma CVD. This is preferable because it improves coverage. It also reduces damage caused by plasma. For lath processing, thermal CVD, MOCVD, or ALD methods are preferred.

[0210] After forming the barrier film 120, the water and hydrogen contained in the barrier film 120 are reduced or removed. Heat treatment may be performed to suppress gas separation.

[0211] Next, a conductive film is formed on the barrier film 120, and then a resist is formed using the same method as described above. A mask is formed, and unwanted portions of the conductive film are removed by etching. Then, a resist mass is formed. By removing the 'ku', the wiring 132 can be formed.

[0212] Next, an insulating film to become insulating film 126 is deposited. The insulating film to become insulating film 126 is, for example, Sputtering method, CVD method (including thermal CVD, MOCVD, PECVD, etc.), M It can be formed using methods such as the BE method, ALD method, or PLD method. In particular, the insulating film When the film is formed by CVD, preferably by plasma CVD, the coverage is improved. This is preferable because it allows for this. Furthermore, to reduce damage caused by plasma, thermal CVD and MO methods are available. CVD or ALD methods are preferred.

[0213] In order to make the insulating film that will become insulating film 126 contain an excess of oxygen, for example, under an oxygen atmosphere Then the insulating film 125 can be deposited. Alternatively, oxygen can be added to the insulating film that will become the insulating film 126 after deposition. You may introduce a method to form a region containing an excess of oxygen, or you may combine both methods. stomach.

[0214] For example, oxygen (at least oxygen radicals, oxygen source) is present in the insulating film that will become the insulating film 126 after film formation. A region containing an excess of oxygen is formed by introducing either an acid or an oxygen ion. Methods for introducing the element include ion implantation, ion doping, and plasma immersion ion Injection methods, plasma treatment, and other similar techniques can be used.

[0215] For the oxygen introduction treatment, an oxygen-containing gas can be used. Examples of oxygen-containing gases include: Oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc., can be used. Furthermore, in the oxygen introduction treatment, a noble gas may be added to the oxygen-containing gas, for example, dioxide A mixed gas of carbon dioxide, hydrogen, and argon can be used.

[0216] Furthermore, after forming the insulating film that will become the insulating film 126, CM is used to improve the flatness of its upper surface. An insulating film 126 is formed by a planarization process using the P method or the like (see Figure 11(A)).

[0217] Furthermore, an insulating film that will become an insulating film 126 is formed on the barrier film 120, and a resist is formed on the insulating film. A mask is formed, and unnecessary portions of the insulating film that will become the insulating film 126 are removed by etching. After forming the edge film 126, a conductive film is formed, and a resist mask is formed on the conductive film. Unnecessary portions of the film may be removed by etching to form the wiring 132.

[0218] Next, an insulating film which will become insulating film 106a, and an oxide semiconductor film which will become oxide semiconductor film 101a. Then, oxide semiconductor films that will become oxide semiconductor film 101b are sequentially deposited. It is preferable to continuously deposit the film without exposing it to the atmosphere.

[0219] After forming the oxide semiconductor film that will become the oxide semiconductor film 101b, a fourth heat treatment is performed. Preferably, the heat treatment is performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C. At the following temperatures, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. It should be done in this state. Also, the atmosphere for the heat treatment should be an inert gas atmosphere, followed by decontamination. The process may be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas to replenish the released oxygen. The process may be carried out immediately after the deposition of the oxide semiconductor film that will become the oxide semiconductor film 101b, An oxide semiconductor film to become an oxide semiconductor film 101b is processed to form an island-shaped oxide semiconductor film 101b This may be done after the film has been formed. Heat treatment will cause the insulating film 126 and insulating film 106a to form an insulating film. Oxygen is supplied from the edge film to the oxide semiconductor film, reducing oxygen vacancies in the semiconductor film. ru.

[0220] Subsequently, a conductive film that will become a hard mask is placed on the oxide semiconductor film which will become the oxide semiconductor film 101b. Then, a resist mask is formed using the same method as described above, and the unnecessary parts of the conductive film are etched. It is removed by the conductive film. Then, the insulating film that will become insulating film 106a and the oxide are removed using the conductive film as a mask. Unwanted portions of the semiconductor film are removed by etching. Then the resist mask is removed. As a result, island-shaped conductive film 103, insulating film 106a, island-shaped oxide semiconductor film 101a and island-shaped A stacked structure of oxide semiconductor films 101b can be formed (see Figure 11(B)).

[0221] Also, simultaneously, the electrode 103c, insulating film 106b, island-shaped oxide semiconductor film 131a and island-shaped A stacked structure of oxide semiconductor films 131b can be formed.

[0222] The formation of conductive films can be done by methods such as sputtering, CVD (thermal CVD, MOCVD, P Formed using methods such as ECVD, MBE, ALD, or PLD. Yes, it is possible. In particular, when the insulating film is deposited by CVD, preferably by plasma CVD, This is preferable because it can improve coverage. It also reduces damage caused by plasma. For this purpose, thermal CVD, MOCVD, or ALD methods are preferred.

[0223] Next, a resist mask is formed on the conductive film 103 in the same manner as described above, and the conductive film 1 Remove the unnecessary parts of 03 by etching. Then remove the resist mask. This allows electrodes 103a and 103b to be formed.

[0224] Next, the insulating film 126, electrode 103a and electrode 103b are coated using the same method as described above. A dist mask is formed, and using this mask, oxide semiconductor film 101b, oxide semiconductor film 1 Plug 1 An opening is formed that reaches 61 and electrode 136. At the same time, the same as above is formed on electrode 103c. A resist mask is formed by the method, and the mask is used to form an oxide semiconductor film 131b, and an oxide Material semiconductor film 131a, insulating film 106b, insulating film 126, barrier film 120 and insulating film 125 This forms an opening that reaches the plug 163.

[0225] Next, a conductive film is formed, and the conductive film is processed to produce plug 164, plug 16 5 and plug 166 are formed (see Figure 11(C)).

[0226] Next, the oxide semiconductor film 101c, the gate insulating film 104, and the gate electrode 105 are formed. (See Figure 12(A)).

[0227] At this stage, the second transistor 100 is formed.

[0228] Next, an insulating film 107 is formed. The insulating film 107 is formed, for example, by sputtering or CVD. Methods (including thermal CVD, MOCVD, PECVD, etc.), MBE method, ALD method or P It can be formed using methods such as the LD method. In particular, the insulating film can be formed by the CVD method, preferably by p Deposition by the razma CVD method is preferable because it can improve coverage. Furthermore, to reduce damage caused by plasma, thermal CVD, MOCVD, or ALD methods are used. It is preferable.

[0229] It is preferable to perform a fifth heat treatment after the deposition of the insulating film 107. The heat treatment provides insulation Oxygen is supplied from film 126 etc. to oxide semiconductor film 101b This reduces the oxygen deficiency inside. Also, at this time, the oxygen that has been removed from the insulating film 126 It is blocked by the barrier film 120 and the insulating film 107, and is below the barrier film 120. Furthermore, since it does not diffuse to the layer above the insulating film 107, the oxygen can be effectively contained. Yes, it is possible. Therefore, the amount of oxygen that can be supplied to the oxide semiconductor film 101b can be increased. This effectively reduces oxygen vacancies in the oxide semiconductor film 101b.

[0230] Next, insulating film 108 and insulating film 127 are formed in order (see Figure 12(B)). 108 and the insulating film 127 are coated by, for example, sputtering, CVD (thermal CVD, MOCV). D method, PECVD method, APCVD (Atmospheric Pressure CVD) It can be formed using methods such as the ) method, MBE method, ALD method, or PLD method. In particular, when the insulating film 108 is deposited by the DC sputtering method, a highly barrier film can be produced in a productive manner. It is preferable because it allows for the formation of thick films. Furthermore, when films are formed by the ALD method, ion damage is reduced. This is preferable because it can reduce the amount and improve the coverage. Also, the insulating film 127 is preferable. When using organic insulating materials such as organic resins, coating methods such as spin coating are used. It may also be formed. Alternatively, after forming the insulating film 127, a planarization treatment may be performed on its upper surface. It is preferable to heat treat it to make it fluid and flatten it. To achieve better results, after forming the insulating film 127, the insulating film is laminated using the CVD method. It is preferable to perform a flattening treatment on the upper surface afterward.

[0231] Next, openings are made in insulating film 126, insulating film 108, and insulating film 107 using the same method as described above. A plug 167 reaches plug 164, and a plug 168 reaches gate electrode 105, A plug 169 is formed that reaches plug 166.

[0232] Next, the insulating film 128 is formed. Note that the insulating film 128 is formed in conjunction with the insulating film 127. It is possible.

[0233] Next, an opening is made in the insulating film 128 using the same method as described above, reaching the plug 167. Plug 170, Plug 171 reaching Plug 168, Plug 172 reaching Plug 169 It forms.

[0234] Next, there is an electrode 173 that is electrically connected to plug 170, and an electrode 173 that is electrically connected to plug 171. An electrode 174 is formed, and an electrode 175 is formed that electrically connects to the plug 172.

[0235] Furthermore, electrode 173 is electrically connected to wiring BL, and electrode 174 is electrically connected to wiring WL. The connection is established, and electrode 175 is electrically connected to wiring SL (see Figure 1(B)). The materials for wiring BL, wiring WL, and wiring SL can be replaced with those for wiring CL.

[0236] By following the above steps, a semiconductor device according to one aspect of the present invention can be manufactured.

[0237] <Example 1> Furthermore, as a modified example of this embodiment, the position of the capacitive element is changed to the second position as shown in Figure 13(A). It may be placed above transistor 100. Specifically, wiring BL, wiring WL, wiring SL, an insulating film 151 is formed on insulating film 128. Then, insulating film 151, insulating film 128 Openings are provided in insulating film 127, insulating film 108, and insulating film 107 to electrically connect with plug 165. A plug 153 is formed to connect. Then, electrodes 154 are electrically connected to the plug 153. An insulating film 155 is formed on electrode 154, and an electrode 156 is formed on insulating film 155, forming a capacitive element 150 This is formed. After that, an insulating film 152 is formed to cover the capacitive element 150. Note that electrode 15 6 is electrically connected to wiring CL1 and has an overlapping region with gate electrode 105. .

[0238] Also, as shown in Figure 13(B), the upper and lower gate electrodes 105 of the second transistor 100 A configuration in which capacitive elements 130 and 150 are provided is also possible.

[0239] <Modification 2> Furthermore, as a modified example of this embodiment, the configuration shown in Figure 14 may be used. The difference lies in the shape of the capacitive element 130. This will be explained in detail below.

[0240] An electrode 136a, which will become part of one electrode 136 of the capacitive element 130, is formed on the insulating film 124. Then, an insulating film 119 is formed to cover the electrode 136a, and a resist is applied to the insulating film 119. A mask is formed, and an opening is made in the insulating film 119 using the mask, and an electrode 136a and an electric electrode are placed in the opening. An electrode 136b is formed to be connected by gas. Then, an insulating film that will become the insulating film 125 is deposited. After planarization, the electrode 136b and insulating film 119 are exposed using a resist mask. An insulating film 125 is formed with an opening so as to be. The insulating film that becomes the insulating film 125 is an insulating film Article 128, etc., can be used as a reference.

[0241] Subsequently, insulating film 137 is formed on insulating film 125, electrode 136b and insulating film 119, and Electrodes 138 are formed to fill the openings in the edge film 125. Then, insulating film 118, insulating film Form 117 and insulating film 116. Note that electrode 138 is electrically connected to wiring CL. It has an overlapping region with the gate electrode 105.

[0242] Subsequently, insulating film 118, insulating film 117, insulating film 116, insulating film 137, insulating film 125 and An opening is provided in the insulating film 119, and plugs 157, 158, and 159 are provided. Furthermore, plug 157 is electrically connected to plugs 161 and 164, and plug 158 It is electrically connected to electrode 136 and plug 165, and plug 159 is connected to plug 163 and Connect it electrically to plug 166.

[0243] <Variation 3> Furthermore, as a modified example of this embodiment, as shown in Figure 15, in addition to the configuration in Figure 14, a second A capacitive element 150, as shown in Figure 13, is provided above the gate electrode 105 of transistor 100. That's fine.

[0244] Furthermore, when multiple capacitive elements are provided, the capacitive elements are not limited to one type; for example, as shown in Figure 1, Quantitative elements and capacitive elements as shown in Figure 14 can be combined as appropriate.

[0245] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0246] (Embodiment 2) This embodiment describes a semiconductor device different from that of Embodiment 1.

[0247] [Example Configuration] Figure 16(A) is an example of a circuit diagram of a semiconductor device according to one embodiment of the present invention. The semiconductor device shown comprises a first transistor 110, a second transistor 100, and a capacitance element. Child 130, capacitive element 150, wiring SL, wiring BL, wiring WL, wiring CL2, It has wiring CL3.

[0248] The first transistor 110 has either its source or drain electrically connected to the wiring BL. The other end is electrically connected to the wiring SL, and the gate is the source of the second transistor 100. The drain is connected to one electrode of the capacitive element 130, and the electrode of the capacitive element 150. Connect electrically. The second transistor 100 has either its source or drain wired to BL. The capacitive element 130 is electrically connected to the other electrical One electrode is electrically connected to wiring CL2. The other electrode of the capacitive element 150 is electrically connected to wiring CL3. They are connected precisely. Note that the gate of the first transistor 110 and the second transistor 100 One of the source or drain of the capacitor, one electrode of the capacitor element 130, and one of the electrodes of the capacitor element 150. The node between the two electrodes is called node FN.

[0249] Figure 16(B) shows an example of a cross-sectional configuration of a semiconductor device that can realize the circuit shown in Figure 16(A). This is shown. Furthermore, Figure 17(A) shows a top view of the semiconductor device shown in Figure 16(B) arranged side by side. Each semiconductor device shares wiring CL2 and CL3, which function as common wiring. .

[0250] As shown in Figure 17, the second transistor 10 is located within the area occupied by the first transistor 110. Capacitive elements 0, 130 and 150 are provided.

[0251] The semiconductor device, as shown in Figure 16(B), has a first transistor 110, a second transistor It has a st 100, a capacitive element 130 and a capacitive element 150. The second transistor 100 is It is located above the first transistor 110, and the first transistor 110 and the second transistor A barrier film 120 is provided between the ZISTA 100.

[0252] The components below the barrier film 120, such as the first transistor 110 and the capacitive element 130, are as follows: The description of Embodiment 1 can be used with reference.

[0253] Furthermore, the barrier film 120 is embedded with the plugs 164, 166 and capacitive element 150, which will be described later. It has an opening into which it is fitted.

[0254] Wiring 132 is provided on the barrier film 120. The configuration including the wiring 132 is a laminated structure This corresponds to the second wiring layer 32 in structure 10.

[0255] The wiring 132 overlaps with the channel formation region of the second transistor 100, which will be described later. It is provided and functions as the second gate electrode of the second transistor 100.

[0256] An insulating film 126 is provided, covering the barrier film 120 and the wiring 132. The region containing 126 corresponds to the second insulating film 22 in the laminated structure 10.

[0257] It is preferable that the upper surface of the insulating film 126 is flattened by the planarization treatment described above.

[0258] It is preferable to use an oxide material for the insulating film 126 in which some of the oxygen is desorbed by heating. .

[0259] A second transistor 100 is provided on top of the insulating film 126. The configuration including Zista 100 corresponds to the second layer 12 in the laminated structure 10.

[0260] The second transistor 100 has an insulating film 106a in contact with the upper surface of the insulating film 126, and an insulating film The oxide semiconductor film 101a is in contact with the upper surface of 106a, and the oxide semiconductor film 101a is in contact with the upper surface of The oxide semiconductor film 101b and the oxide semiconductor film in contact with the upper surface of the oxide semiconductor film 101b Electrodes 103a and 103b are spaced apart in the region overlapping with 101b, and the oxide semiconductor film 10 Oxide semiconductor film 10 in contact with the upper surface of 1b, the upper surface of electrode 103a, and the upper surface of electrode 103b 1c, the gate insulating film 104 on the oxide semiconductor film 101c, and the gate insulating film 104 and acid The gate electrode 105 overlaps with the oxide semiconductor film 101b via the oxide semiconductor film 101c. In addition, the second transistor 100 is covered with insulating film 107, insulating film 108, insulating film. 127 and an insulating film 129 are provided.

[0261] Furthermore, the plug 164, which is electrically connected to the plug 161 and electrode 103a, is insulated by the insulating film 125. , barrier film 120, insulating film 126, insulating film 106a, oxide semiconductor film 101a, oxide semiconductor It is provided so as to be embedded in the conductive film 101b and electrode 103a. Also, electrode 136 And the electrode 181 of the capacitive element 150 that is electrically connected to electrode 103b is insulated film 125, burr Film 120, insulating film 126, insulating film 106a, oxide semiconductor film 101a, oxide semiconductor film 101b, electrode 103b, insulating film 107, insulating film 108, insulating film 127, and insulating film 12 It is designed to be embedded in 9.

[0262] Also, simultaneously with the second transistor 100, the insulating film 106b and the oxide semiconductor film 131a, An oxide semiconductor film 131b and an electrode 103c are formed, and the plug 163 and electrode 103c are The electrically connected plug 166 consists of an insulating film 125, a barrier film 120, an insulating film 126, and an insulating film. Embedded in 106b, oxide semiconductor film 131a, oxide semiconductor film 131b, and electrode 103c. It is designed to be inserted.

[0263] Here, the gate electrode 115 of the first transistor 110 and the electrode 136 of the capacitive element 130 The electrode 181 of the capacitive element 150 and the electrode 103b of the second transistor 100 are included in the The code corresponds to node FN shown in Figure 16(A).

[0264] The description of the second transistor 100 can be adapted from the description of Embodiment 1.

[0265] The insulating films 127 and 129 covering the second transistor 100 have an uneven shape in the underlying layer. It functions as a planarizing film that covers the film. In addition, the insulating film 108 is used when the insulating film 127 is formed. It may also function as a protective film. Insulating films 108 and 129 are not required. It is not necessary to set it up.

[0266] Furthermore, the plug 170 is provided so as to be embedded in the insulating film 128, and the plug 167 and the electrical They are electrically connected. Furthermore, the plug 171 is provided to be embedded in the insulating film 128. It is electrically connected to plug 168. Also, plug 172 is embedded in insulating film 128. It is provided to be electrically connected to plug 169. In addition, plug 176 is insulated It is provided so as to be embedded in the film 128 and is electrically connected to the electrode 183 of the capacitive element 150. It is.

[0267] Furthermore, electrode 173 is electrically connected to plug 170 and wiring BL, and electrode 174 is connected to plug 171 and wiring WL are electrically connected, and electrode 175 is electrically connected to plug 172 and wiring SL. It is connected to the plug 176 and the wiring CL3, and electrode 177 is electrically connected to the plug 176 and the wiring CL3.

[0268] A semiconductor device according to one aspect of the present invention comprises a first transistor 110 and the first transistor Since it has a second transistor 100 located above it, these are arranged in a stack. This reduces the area occupied by the element. Furthermore, the capacitive element 130 is a second transistor Because they are located below the ZISTA 100, stacking them together reduces the occupied area of ​​the element. This can be reduced. Furthermore, the capacitive element 150 is located above the first transistor 110. Because of their positioning, stacking these elements together can reduce the area occupied by the element. Furthermore, the wiring CL2 overlaps with the gate electrode 105 of the second transistor 100. Because it has a range, the occupied area of ​​the element can be further reduced. Also, wiring CL3 is Because it has a region that overlaps with the gate electrode 115 of transistor 110, further element The area occupied by the child can be reduced. Furthermore, the first transistor 110 and the second transistor The barrier membrane 120, which is placed between the inverter 100 and the barrier membrane, prevents water in the layer below it from entering. This can suppress the diffusion of impurities such as hydrogen to the second transistor 100.

[0269] The above is an explanation of the example configuration.

[0270] [Example of manufacturing method] In the following, an example of a method for manufacturing the semiconductor device shown in the above configuration example is described in Figures 10 to 1. 2. This will be explained using Figures 18 to 19.

[0271] Using the [Example of Manufacturing Method] of Embodiment 1, the second transistor The gate insulating film 104 and gate electrode 105 of the terminal 100 are formed (see Figure 18(A)).

[0272] At this stage, the second transistor 100 is formed.

[0273] Next, an insulating film 107 is formed. After the deposition of the insulating film 107, it is preferable to perform a heat treatment. The heat treatment supplies oxygen from the insulating film 126, etc., to the oxide semiconductor film 101b. This reduces oxygen vacancies in the oxide semiconductor film 101b. Also, at this time, The oxygen released from the edge film 126 is blocked by the barrier film 120 and the insulating film 107. Therefore, the oxygen does not diffuse to the layer below the barrier film 120 and the layer above the insulating film 107. This allows for effective containment of oxygen that can be supplied to the oxide semiconductor film 101b. This can increase the amount of and effectively reduce oxygen vacancies in the oxide semiconductor film 101b. It is possible.

[0274] Next, insulating film 108, insulating film 127, and insulating film 129 are formed in order (Figure 18(B)). (See reference). Insulating film 108, insulating film 127 and insulating film 129 are, for example, coated by sputtering, C VD method (thermal CVD method, MOCVD method, PECVD method, APCVD (Atmosphere) c. Pressure CVD (including methods such as), MBE, ALD, or PLD, etc. It can be formed using the following method. In particular, the insulating film 108 is deposited by DC sputtering. This is preferable because it allows for the efficient and thick deposition of highly barrier films. Furthermore, the ALD method... When a film is formed in this manner, ionic damage is reduced and good coverage can be achieved, which is preferable. It is also true that when an organic insulating material such as an organic resin is used as the insulating film 127, It may also be formed using a coating method such as a coating method. It is preferable to perform a flattening treatment on the upper surface. Alternatively, heat treatment can be performed to fluidize and flatten it. It may be modified. Also, in order to improve the flatness, after forming the insulating film 127 It is preferable to perform a planarization treatment on the upper surface after laminating an insulating film using the CVD method. It's nice.

[0275] Next, in the same manner as above, insulating film 129, insulating film 127, insulating film 108, insulation An opening is provided in the membrane 107, and the plug 167 reaches the plug 164, and the gate electrode 105 reaches the plug 167. Plug 168, Plug 169 reaching Plug 166, Plug 176 reaching Plug 165 It forms.

[0276] Next, a resist mask is prepared so that plugs 176 and 165 are etched. Then, the plugs 176 and 165 are etched to form the opening 179 (Figure 19(A )reference).

[0277] Next, an electrode 181 of the capacitive element 150 is formed in the opening 179, and an insulating film 1 is placed on the electrode 181. Form 82 and form electrode 183 on insulating film 182 (see Figure 19(B)). The material for the quantitative element 150 can be described using the same explanation as for the capacitive element 130.

[0278] Next, the insulating film 128 is formed. Note that the insulating film 128 is formed in conjunction with the insulating film 127. It is possible.

[0279] Next, an opening is made in the insulating film 128 using the same method as described above, reaching the plug 167. Plug 170, Plug 171 reaching Plug 168, Plug 172 reaching Plug 169 , forming a plug 176 that reaches the electrode 183.

[0280] Next, there is an electrode 173 that is electrically connected to plug 170, and an electrode 173 that is electrically connected to plug 171. Electrode 174, electrode 175 which is electrically connected to plug 172, and electrode 176 which is electrically connected to plug 176. An electrode 177 is formed to connect to it.

[0281] Furthermore, electrode 173 is electrically connected to wiring BL, and electrode 174 is electrically connected to wiring WL. Electrode 175 is electrically connected to wiring SL, and electrode 177 is electrically connected to wiring CL3. It is connected to (see Figure 16(B)). Note that wiring BL, wiring WL, wiring SL, wiring CL3 The materials can be described by referring to the explanation of the wiring CL in Embodiment 1.

[0282] By following the above steps, a semiconductor device according to one aspect of the present invention can be manufactured.

[0283] <Modification 4> Furthermore, as a modified example of this embodiment, the position of the capacitive element 130 is shown in Figure 20(A). The second transistor 100 may be placed above it. Specifically, wiring BL, wiring WL Then, an insulating film 151 is formed on the wiring SL and insulating film 128. After that, an opening is made in the insulating film 151. A plug 178 is formed by providing a plug 176 and electrically connecting it to the plug 178. A capacitive element 130 is formed that is electrically connected to it. Then, an insulating film is placed over the capacitive element 130. Form 152. Note that the capacitive element 130 is electrically connected to the wiring CL2 and the gate electrode. It has an overlapping region with 105.

[0284] Also, as shown in Figure 20(B), the upper and lower gate electrodes 105 of the second transistor 100 A configuration in which capacitive elements 130 and 190 are provided is also possible. As shown, the opening for forming the capacitive element 150 may be deeper than in Figure 20(A), and Figure As shown in 21, the opening for forming the capacitive element 150 may be made shallower than in Figure 20(A). stomach.

[0285] In this embodiment, the capacitive elements 130 and 190 are of the parallel plate type. However, this is not the only example.

[0286] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0287] (Embodiment 3) In this embodiment, it can be suitably used in the semiconductor film of a semiconductor device according to one aspect of the present invention. This section will explain oxide semiconductors.

[0288] Oxide semiconductors have a large energy gap of 3.0 eV or more, making oxide semiconductors suitable for An oxide semiconductor film obtained by processing under certain conditions and sufficiently reducing its carrier density is applied. In a transistor, the leakage current between the source and drain in the off state (off current) This can be made extremely low compared to conventional silicon-based transistors. .

[0289] Applicable oxide semiconductors include at least indium (In) or zinc (Zn). It is preferable that the oxide semiconductor contains ) and is particularly preferable that it contains In and Zn. As stabilizers to reduce variations in the electrical characteristics of transistors using these, In addition, gallium (Ga), tin (Sn), hafnium (Hf), and zirconium (Zr) Titanium (Ti), scandium (Sc), yttrium (Y), lanthanides (for example) One of the following is selected from cerium (Ce), neodymium (Nd), and gadolinium (Gd). It is preferable that multiple species are included.

[0290] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and in-Zn-based acids. compounds, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg acids In-Mg oxides, In-Ga oxides, In-Ga-Zn oxides (IGZO (Also written as), In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga- Zn oxides, Al-Ga-Zn oxides, Sn-Al-Zn oxides, In-Hf-Z n-based oxides, In-Zr-Zn oxides, In-Ti-Zn oxides, In-Sc-Zn oxides In-Y-Zn oxides, In-La-Zn oxides, In-Ce-Zn oxides In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides Materials, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, In-Lu-Zn ​​oxides, I n-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga- Zn oxides, In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, I n-Hf-Al-Zn oxides can be used.

[0291] Here, an In-Ga-Zn oxide is an oxide having In, Ga, and Zn as its main components. It refers to the material itself, and the ratio of In, Ga, and Zn is irrelevant. Also, other than In, Ga, and Zn... It may contain metallic elements.

[0292] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0, and m is not an integer) Materials represented by ) may also be used. Note that M is selected from Ga, Fe, Mn, and Co. This refers to one or more metallic elements, or the elements used as stabilizers as described above. Also, as an oxide semiconductor, In2SnO5(ZnO) n (n > 0, and n is an integer) You may use the materials indicated as follows.

[0293] For example, In:Ga:Zn=1:1:1, In:Ga:Zn=1:3:2, In:Ga :Zn=1:3:4, In:Ga:Zn=1:3:6, In:Ga:Zn=3:1:2A or In-Ga-Zn oxides with an atomic ratio of In:Ga:Zn=2:1:3 and their composition It is preferable to use an oxide from the vicinity of [the specified location].

[0294] When an oxide semiconductor film contains a large amount of hydrogen, it combines with the oxide semiconductor, causing water to form. Some of the elements become donors, generating electrons, which are carriers. This causes the transistor The threshold voltage of the film shifts in the negative direction. Therefore, the formation of oxide semiconductor films is affected. Subsequently, a dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film. It is preferable to remove impurities and purify the product to a high degree of purity so that it contains as few impurities as possible.

[0295] Furthermore, by dehydrating (dehydrogenating) the oxide semiconductor film, Oxygen levels may also decrease at the same time. Therefore, dehydration treatment of oxide semiconductor films (dehydration) A process of adding oxygen to an oxide semiconductor film to compensate for oxygen vacancies that have increased due to the chemical treatment. It is preferable to do so. In this specification, etc., when oxygen is supplied to an oxide semiconductor film, This is sometimes referred to as oxygenation treatment, or the stoichiometric composition of oxygen contained in oxide semiconductor films. When the amount is increased more than that, it is sometimes referred to as a peroxygenation treatment.

[0296] Thus, oxide semiconductor films undergo dehydration treatment (dehydrogenation treatment) to remove hydrogen or water. The oxygen deficiency is removed and compensated for by oxygenation treatment, resulting in type i (true) and This can be an oxide semiconductor film that is very close to type i and is essentially type i (intrinsic). Furthermore, "substantially true" means that there are very few donor-derived carriers in the oxide semiconductor film. (Close to zero), carrier density is 1 × 10⁻⁶ 17 / cm 3 Below, 1 x 10 16 / cm 3 below , 1 x 10 15 / cm 3 Below, 1 x 10 14 / cm 3 Below, 1 x 10 13 / cm 3 Below To say something

[0297] Furthermore, in this manner, a transient having an oxide semiconductor film that is type i or substantially type i This can achieve extremely excellent off-current characteristics. For example, transistors using oxide semiconductor films The drain current when the zista is in the off state is 1 × 10⁻¹⁰ at room temperature (approximately 25°C). -18 After A Below, preferably 1 × 10 -21 A or less, more preferably 1 × 10 -24 A or less, or 1 × 10 at 85℃ -15 A or less, preferably 1 × 10 -18A or less, more preferably A or less. 1 x 10 -21 It can be less than or equal to A. Note that the transistor being in the off state means n channels. In the case of a Nell-type transistor, this refers to a state where the gate voltage is sufficiently lower than the threshold voltage. Specifically, if the gate voltage is 1V, 2V, or 3V lower than the threshold voltage If this happens, the transistor will be in the off state.

[0298] <Oxide semiconductor structure> The structure of oxide semiconductors will be described below.

[0299] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned) is used. Crystalline Oxide Semiconductor, Polycrystalline Oxide Semiconductors, nc-OS (nanocrystalline oxide semiconductor) uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous l Examples include amorphous oxide semiconductors (ike Oxide Semiconductor).

[0300] From another perspective, oxide semiconductors include amorphous oxide semiconductors and other crystalline oxides. They can be divided into semiconductors and crystalline oxide semiconductors. Crystalline oxide semiconductors include single-crystal oxide semiconductors and CAAC- Examples include OS, polycrystalline oxide semiconductors, and nc-OS.

[0301] Generally, an amorphous structure is defined as a structure that is not fixed in a metastable state and is isotropic. It is known that it does not have a heterogeneous structure. Also, the bond angles are flexible and short distance It can also be described as a structure that possesses deorderliness but lacks long-range orderliness.

[0302] Conversely, in the case of oxide semiconductors, which are inherently stable, they are perfectly amorphous (complete It cannot be called an oxide semiconductor (which is amorphous). Also, it is not isotropic. (For example, an oxide semiconductor having a periodic structure in a minute region) is subjected to complete amorphous oxidation. It cannot be called a physical semiconductor. However, a-like OS is a circumferential material in a minute region. Although it has a structural form, it also has voids (also called porous structures) and is therefore an unstable structure. In terms of physical properties, it can be said to be similar to an amorphous oxide semiconductor.

[0303] <caac-os> First, let me explain CAAC-OS.

[0304] CAAC-OS is an oxide having multiple c-axis oriented crystalline portions (also called pellets). It is a type of semiconductor.

[0305] Transmission Electron Microscope (TEM) A composite analysis image of the bright-field image and diffraction pattern of CAAC-OS (high-angle scope) is obtained. Also called a high-resolution TEM image, when observed, multiple pellets can be identified. On the other hand, in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, and It is also said that it is not possible to clearly confirm the grain boundaries. Therefore, CAAC-OS is said to be at the grain boundaries. This means that a decrease in electron mobility caused by this phenomenon is less likely to occur.

[0306] The following describes CAAC-OS observed by TEM. Figure 22(A) The image shows a high-resolution TEM image of the cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. For observing high-resolution TEM images, spherical aberration correction is necessary. The n Corrector function was used. High-resolution TEM images using spherical aberration correction function were obtained. This is specifically called a Cs-corrected high-resolution TEM image. Acquisition of a Cs-corrected high-resolution TEM image can be done, for example, This is performed using an atomic-resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. It is possible.

[0307] Figure 22(B) shows an enlarged Cs-corrected high-resolution TEM image of region (1) in Figure 22(A). Figure 22(B) shows that the metal atoms in the pellet are arranged in layers. The arrangement of metal atoms in each layer is the plane (also called the surface to be formed) that forms the CAAC-OS film. Alternatively, it reflects the irregularities of the upper surface and is parallel to the surface or upper surface of the CAAC-OS that is formed on it.

[0308] As shown in Figure 22(B), CAAC-OS has a characteristic atomic arrangement. Figure 22(C Figures 22(B) and 22(C) show characteristic atomic arrangements indicated by auxiliary lines. ) Therefore, the size of a single pellet can be 1 nm or larger, or 3 nm or larger, It can be seen that the size of the gap created by the tilt between the pellet and the material is approximately 0.8 nm. Therefore, pellets can also be called nanocrystals (nc). Also, CAAC-OS is CANC(C-Axis Aligned nanocry It can also be called an oxide semiconductor containing stals.

[0309] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on substrate 5120 are... The arrangement of the 5100 can be schematically represented as a structure resembling stacked bricks or blocks. This is the result (see Figure 22(D)). Between the pellets observed in Figure 22(C) The area where the inclination occurs corresponds to region 5161 shown in Figure 22(D).

[0310] Furthermore, Figure 23(A) shows the plane of CAAC-OS observed from a direction approximately perpendicular to the sample surface. The s-corrected high-resolution TEM images are shown. Regions (1), (2), and (3) of Figure 23(A) are shown. ) are enlarged Cs-corrected high-resolution TEM images, shown in Figure 23(B), Figure 23(C), and Figure 23(C), respectively. This is shown in Figure 23(D). From Figures 23(B), 23(C), and 23(D), the pellets are It can be confirmed that the metal atoms are arranged in a triangular, square, or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different pellets.

[0311] Next, C was analyzed by X-ray diffraction (XRD). Let's discuss AAC-OS. For example, CAAC-OS having an InGaZnO4 crystal. When structural analysis of S is performed using the out-of-plane method, the result is as shown in Figure 24(A). In some cases, a peak may appear near a diffraction angle (2θ) of 31°. This peak is in InGa Since it is attributed to the (009) plane of the ZnO4 crystal, the CAAC-OS crystal is c-axis oriented. It can be confirmed that it possesses this property, and that the c-axis is oriented in a direction approximately perpendicular to the surface to be formed or the upper surface.

[0312] In addition, in the structural analysis using the out-of-plane method of CAAC-OS, 2θ is 31 In addition to the peak near °, a peak may also appear when 2θ is near 36°. The nearby peak indicates that some of the crystals in CAAC-OS do not exhibit c-axis orientation. This shows that a more preferable CAAC-OS is structured using the out-of-plane method. The analysis shows that 2θ shows a peak near 31°, but does not show a peak near 36°.

[0313] On the other hand, in the CAAC-OS, X-rays are incident from a direction approximately perpendicular to the c-axis in an in-plane configuration. Structural analysis using the ne method reveals a peak near 2θ = 56°. This peak corresponds to I It is attributed to the (110) plane of the nGaZnO4 crystal. In the case of CAAC-OS, 2θ is 5 The sample is fixed at approximately 6° and analyzed while rotating it around the normal vector of the sample surface as the axis (φ axis). Even after performing a (φ scan), no clear peak appears, as shown in Figure 24(B). In contrast, with a single-crystal oxide semiconductor of InGaZnO4, if 2θ is fixed to around 56°, then φ When scanned, it is attributed to a crystal plane equivalent to the (110) plane, as shown in Figure 24(C). Six peaks are observed. Therefore, structural analysis using XRD indicates that CAAC-OS is It can be confirmed that the orientation of the a-axis and b-axis is irregular.

[0314] Next, we will explain CAAC-OS analyzed by electron diffraction. For example, InGa For CAAC-OS containing ZnO4 crystals, a probe with a diameter of 300 nm is used parallel to the sample surface. When the electron beam is incident, a diffraction pattern like the one shown in Figure 25(A) (limited field transmitted electron wave) is produced. This diffraction pattern may appear. (Also called a diffraction pattern.) The spot originates from the (009) plane of the crystal. Therefore, electron diffraction also reveals The pellets contained in CAAC-OS have c-axis orientation, and the c-axis is on the surface to be formed or the upper surface. It can be seen that it is oriented in a nearly perpendicular direction. On the other hand, for the same sample, when the probe is directed perpendicular to the sample surface... Figure 25(B) shows the diffraction pattern when an electron beam with a diameter of 300 nm is incident on the surface. From 5(B), a ring-shaped diffraction pattern is observed. Therefore, electron diffraction also shows It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have orientation. Note that the first ring in Figure 25(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be caused by the nominal (100) plane, etc. Also, the second ring in Figure 25(B) This is thought to be caused by (110) planes, etc.

[0315] As mentioned above, CAAC-OS is a highly crystalline oxide semiconductor. Crystallinity can decrease due to the inclusion of impurities or the formation of defects, so the opposite perspective is also possible. Therefore, CAAC-OS can be described as an oxide semiconductor with few impurities or defects (such as oxygen vacancies).

[0316] Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition gold. There are group elements, for example. For example, silicon and other metal elements that make up oxide semiconductors are more acidic than the metal elements that make up oxide semiconductors. Elements with strong bonding forces can remove oxygen from oxide semiconductors, thereby altering the atomic arrangement of the oxide semiconductor. This disrupts the crystallinity and reduces its properties. Also, heavy metals such as iron and nickel, and argon, Because carbon dioxide and other elements have large atomic radii (or molecular radii), the atomic arrangement of oxide semiconductors This disrupts the crystallinity and reduces its properties.

[0317] When oxide semiconductors contain impurities or defects, their properties may change due to light, heat, etc. Yes. For example, impurities contained in oxide semiconductors can act as carrier traps, or they can cause carriers to be trapped. It can sometimes be a source of rear emissions. Also, oxygen vacancies in oxide semiconductors can trap carriers. In some cases, it may become a carrier source by capturing hydrogen.

[0318] CAAC-OS, with its low impurity and oxygen vacancy rate, is suitable for oxide semiconductors with low carrier density. Yes, such oxide semiconductors are high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. It is called CAAC-OS. CAAC-OS has a low impurity concentration and a low defect level density. In other words, it has stable properties. It can be said that it is an oxide semiconductor possessing [a certain characteristic].

[0319] <nc-os> Next, I will explain nc-OS.

[0320] nc-OS allows for the identification of crystalline regions in high-resolution TEM images, and It has regions where a definite crystalline portion cannot be identified. The crystalline portion contained in nc-OS is They are often between 1 nm and 10 nm in size, or between 1 nm and 3 nm in size. Oh, an oxide semiconductor with a crystal size greater than 10 nm and less than 100 nm is microcrystalline acid It is sometimes called a monoxide semiconductor. nc-OS, for example, shows grain boundaries in high-resolution TEM images. In some cases, this cannot be clearly confirmed. Furthermore, nanocrystals are pellets in CAAC-OS. It may share the same origin. Therefore, below, the crystalline portion of nc-OS will be treated as a pellet. They may call.

[0321] nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially regions larger than 1 nm). It has periodicity in the atomic arrangement in the region of 3 nm or less. In addition, nc-OS has different properties. No regularity is observed in the crystal orientation between the letts. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analytical method, nc-OS may be a-like OS or amorphous oxide semiconductor. It can sometimes be indistinguishable from the body. For example, nc-OS has a larger diameter than pellets. When using X-rays, out-of-plane analysis shows peaks indicating crystal planes. Not detected. Also, for nc-OS, a probe diameter larger than the pellet (e.g., 50 When electron diffraction is performed using an electron beam (of a magnitude greater than nm), a diffraction pattern similar to a halo pattern is obtained. Observed. On the other hand, compared to nc-OS, the pellet size is close to or smaller than the pellet size. When nanobeam electron diffraction is performed using an electron beam with a lobe diameter, spots can be observed. When nanobeam electron diffraction is performed on nc-OS, a high-brightness pattern is observed, forming a circular (ring-shaped) pattern. In some cases, a region may be observed. Furthermore, multiple spots may be observed within a ring-shaped region. There are cases where this occurs.

[0322] Thus, since there is no regularity in the crystal orientation between pellets (nanocrystals), nc -OS has RANC (Random Aligned nanocrystals) Oxide semiconductors, or NANC (Non-Aligned nanocrystals), It can also be called an oxide semiconductor having s).

[0323] nc-OS is an oxide semiconductor with higher orderliness than amorphous oxide semiconductors. nc-OS has a lower defect level density than a-like OS and amorphous oxide semiconductors. However, nc-OS does not show any regularity in crystal orientation between different pellets. Therefore, nc-OS has a higher defect level density compared to CAAC-OS.

[0324] <a-like OS> a-like OS is an oxide having a structure between nc-OS and amorphous oxide semiconductors. It is a semiconductor.

[0325] a-like OS may exhibit porosity in high-resolution TEM images. Furthermore, In the high-resolution TEM image, there are regions where the crystalline portion can be clearly identified, and regions where the crystalline portion can be clearly identified. It has areas that cannot be done.

[0326] Due to its porous nature, a-like OS has an unstable structure. Below, a-lik This demonstrates that e OS has a less stable structure compared to CAAC-OS and nc-OS. Therefore, it shows the structural changes caused by electron irradiation.

[0327] The samples to be irradiated with electrons are a-like OS (referred to as sample A) and nc-OS. Prepare (referred to as Sample B) and CAAC-OS (referred to as Sample C). This sample is also an In-Ga-Zn oxide.

[0328] First, high-resolution cross-sectional TEM images are obtained for each sample. It can be seen that all of the materials contain crystalline parts.

[0329] The determination of which part should be considered a single crystal can be made as follows. The unit cell of the InGaZnO4 crystal has three In-O layers and a Ga-Zn-O layer. It is known to have a structure in which a total of nine layers, consisting of six layers, are stacked in layers along the c-axis. The spacing between these adjacent layers is approximately the same as the spacing between the grid planes of the (009) plane (also called the d value). Therefore, the value has been determined to be 0.29 nm from crystal structure analysis. The areas where the spacing is between 0.28 nm and 0.30 nm are considered to be the crystalline parts of InGaZnO4. It can be considered as such. Furthermore, the lattice patterns correspond to the ab-plane of the InGaZnO4 crystal.

[0330] Figure 26 shows an example of investigating the average size of the crystalline regions (22 to 45 locations) in each sample. However, the length of the lattice fringes mentioned above is used as the size of the crystal portion. From Figure 26, a-li It can be seen that the crystalline portion of keOS increases in proportion to the cumulative amount of electron irradiation. Specifically, as shown in (1) in Figure 26, the initial TEM observation is approximately 1.2 nm. The crystal region (also called the initial nucleus), which was initially a certain size, increased in size when the cumulative irradiation dose reached 4.2 × 10⁻⁶. 8 e - / n m 2 In this case, it can be seen that it has grown to a size of about 2.6 nm. On the other hand, nc-O S and CAAC-OS have a cumulative electron dose of 4.2 × 10⁻⁶ from the start of electron irradiation. 8 e - / nm 2 Within this range, it can be seen that there is no change in the size of the crystal portion. Specifically, As shown in (2) and (3) in Figure 26, regardless of the cumulative dose of electrons, nc-OS The crystal size of CAAC-OS is approximately 1.4 nm and 2.1 nm, respectively. It can be seen that this is the case.

[0331] Thus, in a-like OS, crystalline growth can be observed upon electron irradiation. Yes. On the other hand, in nc-OS and CAAC-OS, the growth of the crystal portion by electron irradiation is almost entirely... It can be seen that it cannot be seen. In other words, a-like OS is nc-OS and CAAC- Compared to an operating system, it appears to have an unstable structure.

[0332] Furthermore, because it is porous, a-like OS is compared to nc-OS and CAAC-OS. All of them are low-density structures. Specifically, the density of a-like OS is low compared to single-layer structures of the same composition. The density of the crystal will be between 78.6% and 92.3%. Also, the density of nc-OS and CAA The density of C-OS is between 92.3% and 100% of the density of a single crystal of the same composition. Oxide semiconductors with a crystal density of less than 78% are inherently difficult to deposit into film.

[0333] For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm³. 3 This is how it will be. For example, in an oxide semiconductor that satisfies In:Ga:Zn=1:1:1 [atomic ratio] The density of a-like OS is 5.0 g / cm³. 3 More than 5.9g / cm 3 It will be less than. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio] The densities of nc-OS and CAAC-OS are 5.9 g / cm³. 3 More than 6.3g / cm 3 It will be less than.

[0334] Note that single crystals with the same composition may not exist. In that case, a mixture of crystals with different compositions in any proportion may be used. By combining single crystals, the density equivalent to a single crystal at a desired composition can be estimated. This is possible. The density corresponding to a single crystal of the desired composition can be obtained by combining single crystals of different compositions. The proportion can be estimated using a weighted average. However, the density should be as small as possible. It is preferable to estimate by combining different types of single crystals.

[0335] As described above, oxide semiconductors can take on various structures, each possessing a variety of properties. Oxide semiconductors include, for example, amorphous oxide semiconductors, a-like OS, and nc-OS. The laminated film may have two or more types of CAAC-OS.

[0336] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0337] (Embodiment 4) In this embodiment, an example of a circuit utilizing a transistor according to one aspect of the present invention is shown in the drawings. See the explanation below.

[0338] [Circuit Configuration Example] In the configuration shown in Embodiment 1, the connection configuration of the transistors, wiring, and electrodes is different. By doing so, various circuits can be configured. Below, one embodiment of the present invention of semiconductor This section describes an example of a circuit configuration that can be realized using the device.

[0339] [CMOS circuit] The circuit diagram shown in Figure 27(A) is a p-channel type transistor 2200 and an n-channel type This is a so-called CM configuration, where two transistors 2100 are connected in series, and their gates are connected. This shows the configuration of the OS circuit. Note that in the figure, the transistor to which the second semiconductor material is applied is shown. These are indicated by the symbol "OS".

[0340] [Analog switch] Furthermore, the circuit diagram shown in Figure 27(B) is for transistors 2100 and 2200. This shows a configuration where each source and drain is connected. It can function as a so-called analog switch.

[0341] [Examples of storage devices] Using a transistor according to one aspect of the present invention, the stored contents can be stored even when power is not supplied. Figure 2 shows an example of a semiconductor device (memory device) that can retain data and has no limit on the number of write cycles. This is shown in 7(C).

[0342] The semiconductor device shown in Figure 27(C) is a transistor 3200 using a first semiconductor material and The device includes a transistor 3300 and a capacitive element 3400, both made from a second semiconductor material. The transistor 3300 used is the transistor exemplified in the above embodiment. It is possible.

[0343] Transistor 3300 is a transistor in which a channel is formed in a semiconductor film having an oxide semiconductor. It is a transistor. The 3300 transistor is used because it has a low off-current. It is possible to retain memory content for a longer period of time. In other words, refresh operations are unnecessary. To create a semiconductor memory device that does not require refresh operations, or one that requires extremely infrequent refresh operations. This makes it possible to significantly reduce power consumption.

[0344] In Figure 27(C), the first wiring 3001 is connected to the source electrode of transistor 3200. The second wire 3002 is electrically connected to the drain electrode of transistor 3200. They are connected. Also, the third wire 3003 is the source electrode of transistor 3300 or Electrically connected to one of the drain electrodes, the fourth wire 3004 is connected to transistor 3300. It is electrically connected to the gate electrode. And the gate electrode of transistor 3200, The source electrode or drain electrode of transistor 3300, the other of which is a capacitive element 3400 The fifth wire 3005 is electrically connected to one of the electrodes, and the other electrode of the capacitive element 3400 is connected to the other electrode. They are electrically connected.

[0345] In the semiconductor device shown in Figure 27(C), the potential of the gate electrode of transistor 3200 is maintained. By taking advantage of this capability, it is possible to write, store, and read information as follows: be.

[0346] The writing and retention of information will be explained. First, the potential of the fourth wiring 3004 is set to the tracer. The potential is set to the ON state for transistor 3300, thereby turning on transistor 3300. As a result, the potential of the third wiring 3003 is the gate electrode of transistor 3200, and It is supplied to the capacitive element 3400. That is, the gate electrode of transistor 3200 is supplied. A constant charge is given (written). Here, a charge that gives two different potential levels ( (Hereafter referred to as Low-level charge and High-level charge) are assumed to be given. Then, the potential of the fourth wire 3004 is set to the potential at which transistor 3300 turns off. By turning off transistor 3300, the gate of transistor 3200 The charge applied to the electrode is retained (held).

[0347] Because the off-current of transistor 3300 is extremely small, the gate of transistor 3200 The charge on the electrodes is retained for a long period of time.

[0348] Next, we will explain how to read the information. A predetermined potential (constant potential) is applied to the first wiring 3001. When the appropriate potential (readout potential) is applied to the fifth wiring 3005 while the current is being applied, the transient Depending on the amount of charge held at the gate electrode of terminal 3200, the second wiring 3002 will have different powers. To take a position. Generally, if transistor 3200 is an n-channel type, then transistor 320 Apparent threshold V when a high level charge is applied to a terminal station with zero charge. th_ H This is the case when a low level charge is applied to the gate electrode of transistor 3200. The threshold value V th_L This is because it becomes lower. Here, the apparent threshold voltage is The potential of the fifth wire 3005, which is necessary to turn on transistor 3200, Therefore, the potential of the fifth wiring 3005 is set to V th_H and V th_L During By setting the potential V0, the charge applied to the gate electrode of transistor 3200 can be determined. They can be separated. For example, in the case of writing, if a high-level charge is given, The potential of the fifth wire 3005 is V0 (>V th_H ) In that case, transistor 3200 is It becomes "on". If a low-level charge is applied, the fifth wiring 3005 The potential is V0( <V th_L Even if this happens, transistor 3200 remains in the "off state". Therefore, by determining the potential of the second wiring 3002, the information being held can be read. It is possible to break out of it.

[0349] Furthermore, when memory cells are arranged in an array, only the information of the desired memory cell can be read. It becomes necessary to be able to extract the information. If the information is not read in this way, the state of the gate electrode Regardless, the potential at which transistor 3200 is in the "off state" is V th_ H A smaller potential should be applied to the fifth wire 3005. Alternatively, depending on the state of the gate electrode... The potential at which transistor 3200 remains "on" is, that is, V th_L Yo A larger potential should be applied to the fifth wiring 3005.

[0350] Note that here we have a schematic cross-sectional view of the circuit diagram in Figure 27(A) and wiring 3001 in Figure 27(C). Figure 28 shows a schematic cross-sectional view of the configuration in which wiring 3003 is common (circuit diagram in Figure 1(A)). This is shown. Note that the schematic cross-sectional view of Figure 27(A) is shown to the left of the dotted line, and the cross-sectional view of Figure 1(A) is shown to the right of the dotted line. A schematic cross-sectional view of the circuit diagram is shown.

[0351] From the diagram, we can see transistor 3200 and the transistor located above transistor 3200. Since it has 3300, stacking them together reduces the occupied area of ​​the element. This is possible. Furthermore, since the capacitive element 3400 is located below the transistor 3300, By stacking these components, the area occupied by the element can be reduced. Also, wiring Because it has a region that overlaps with the gate electrode of the 3005 transistor 3300, it is even more The area occupied by the child can be reduced.

[0352] Furthermore, as shown in Figure 29, transistors 3300 and 2100 are manufactured in separate processes. It is also acceptable to use this configuration.

[0353] The semiconductor device shown in Figure 27(D) is mainly similar to Figure 2 in that it does not have transistor 3200. This differs from 7(C). In this case as well, the same operation as above is used to write and hold information. It is possible to create it.

[0354] Next, we will explain how to read the information. When transistor 3300 is turned ON, The third wiring 3003, which is in a floating state, and the capacitive element 3400 are electrically connected, and the third wiring 3003 The charge is redistributed between the capacitor and the capacitive element 3400. As a result, the potential of the third wiring 3003 is It changes. The amount of change in the potential of the third wiring 3003 is equal to the potential of the first terminal of the capacitive element 3400. It takes on different values ​​depending on (or the charge stored in the capacitive element 3400).

[0355] For example, let V be the potential of the first terminal of the capacitive element 3400, C be the capacitance of the capacitive element 3400, and the second terminal The capacitive component of the third wiring 3003 is CB, and the third wiring 3003 before the charge is redistributed. If the potential of is VB0, then the potential of the third wiring 3003 after the charge has been redistributed is (CB The formula becomes (×VB0+C×V) / (CB+C). Therefore, the state of the memory cell is, If the potential of the first terminal of element 3400 takes on two states, V1 and V0 (V1 > V0), The potential of the third wiring 3003 when the potential V1 is maintained is (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is maintained (=( It can be seen that this is higher than (CB × VB0 + C × V0) / (CB + C)).

[0356] Then, by comparing the potential of the third wiring 3003 with a predetermined potential, the information can be read out. It is possible.

[0357] In this case, the first semiconductor material described above is applied to the drive circuit for driving the memory cell. Using a transistor, a second semiconductor material was applied to transistor 3300. The inverters can be stacked on top of the drive circuit.

[0358] In the semiconductor device shown in this embodiment, an oxide semiconductor is used in the channel formation region for off-voltage applications. By using transistors with extremely low current, it is possible to retain memory content for extremely long periods of time. It is possible to do so. In other words, a refresh operation will become unnecessary, or a refresh will be required. Because the frequency of operation can be made extremely low, power consumption can be significantly reduced. It is possible. Also, in the absence of power supply (however, it is desirable that the potential be fixed). Even if memory is impaired, it is possible to retain the contents of that memory over a long period of time.

[0359] Furthermore, the semiconductor device shown in this embodiment does not require a high voltage for writing information. There are no issues with element degradation. For example, unlike conventional non-volatile memory, floating-point memory... Because there is no need to inject electrons into the gate or extract electrons from the floating gate. Furthermore, problems such as deterioration of the gate insulating layer do not occur at all. In other words, the semiconductor according to the disclosed invention In this device, there is no limitation on the number of rewrite cycles, which is a problem with conventional non-volatile memory. Reliability improves dramatically. Furthermore, information is obtained depending on the on and off states of the transistor. Because data is written to the system, high-speed operation can be easily achieved.

[0360] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0361] (Embodiment 5) In this embodiment, R includes the transistor or memory device exemplified in the above embodiment. The F tag will be explained using Figure 30.

[0362] The RF tag in this embodiment has a memory circuit inside, and the memory circuit records the necessary information. This involves using contactless means, such as wireless communication, to exchange information with the outside world. Based on these characteristics, RF tags identify items by reading individual information about those items. It can be used in individual authentication systems, etc. However, to use it for these purposes... Extremely high reliability is required.

[0363] The configuration of an RF tag will be explained using Figure 30. Figure 30 shows an example of an RF tag configuration. This is a block diagram.

[0364] As shown in Figure 30, the RF tag 800 is connected to the communicator 801 (interrogator, reader / writer, etc.) An antenna that receives a radio signal 803 transmitted from antenna 802 connected to (also known as) It has 804. The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, and a demodulation circuit. It has a path 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Furthermore, ensure that sufficient reverse current is supplied to the rectifying transistor included in the demodulation circuit 807. A configuration using materials that can suppress this, such as oxide semiconductors, may also be used. This suppresses the decrease in rectification due to reverse current and prevents the output of the demodulation circuit from saturating. This prevents the output of the demodulation circuit from becoming more linear to the input of the demodulation circuit. Yes, it is possible. The data transmission method involves a pair of coils facing each other and communicating through mutual induction. Electromagnetic coupling methods, electromagnetic induction methods that communicate using induced electromagnetic fields, and methods that communicate using radio waves. They can be broadly classified into three types of radio wave methods. The RF tag 800 shown in this embodiment does not use any of these methods. It can also be used in formulas.

[0365] Next, the configuration of each circuit will be explained. Antenna 804 is connected to the communication device 801. This is for transmitting and receiving wireless signals 803 with the antenna 802. Also, a rectifier circuit... 805 processes the input AC signal generated by receiving a wireless signal with antenna 804. For example, half-wave voltage doubling rectification is performed, and the rectified signal is then smoothed by a capacitive element placed in the subsequent stage. This is a circuit for generating input potential by smoothing. Note that the input side of the rectifier circuit 805... Alternatively, a limiter circuit may be provided on the output side. A limiter circuit controls the amplitude of the input AC signal. When the internally generated voltage is high, do not input power above a certain level to the subsequent circuit. This is a circuit for controlling it in that way.

[0366] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. This is the circuit. Note that the constant voltage circuit 806 has a reset signal generation circuit inside. Good. The reset signal generation circuit utilizes the stable rise of the power supply voltage to generate the logic circuit 8. This is a circuit for generating the 09 reset signal.

[0367] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. This is a circuit for that purpose. Furthermore, the modulation circuit 808 is used to process the data output from the antenna 804. This is a circuit for modulating accordingly.

[0368] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. The memory circuit 810 is It is a circuit that holds the input information, such as a row decoder, column decoder, and memory area. It has the following. Furthermore, ROM811 stores a unique number (ID), etc., and outputs according to the processing. This is the circuit for performing the action.

[0369] Furthermore, the circuits described above can be selected or omitted as needed.

[0370] Here, the memory circuit described in the previous embodiment can be used in the memory circuit 810. A memory circuit according to one aspect of the present invention can retain information even when the power supply is cut off. It can be suitably used in RF tags. Furthermore, a storage circuit according to one aspect of the present invention stores data Because the power (voltage) required for writing is significantly lower than that of conventional non-volatile memory, data It is also possible to eliminate the difference in the maximum communication distance between data reading and writing. This prevents malfunctions or incorrect data writing that may occur due to insufficient power during data writing. It is possible.

[0371] Furthermore, a memory circuit according to one aspect of the present invention can be used as a non-volatile memory. Therefore, it can also be applied to ROM811. In that case, the manufacturer will need to provide the ROM811. A separate command is provided for writing data, preventing users from freely overwriting it. It is preferable that the producer writes a unique number on the product before shipping it. Therefore, instead of assigning a unique number to every RF tag produced, only the good quality tags that are shipped will have a unique number assigned to them. This makes it possible to assign a unique number to each individual product, preventing discontinuity in the unique numbers of products after shipment. This eliminates the need for customer management after product shipment, making it easier to handle customer issues related to the product.

[0372] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0373] (Embodiment 6) In this embodiment, at least the transistors described in the embodiments can be used. Next, we will describe a CPU including the memory device described in the previous embodiment.

[0374] Figure 31 shows a CPU that uses at least some of the transistors described in the previous embodiment. This is a block diagram showing an example of a configuration.

[0375] The CPU shown in Figure 31 is an ALU1191 (ALU: Arithmetic) mounted on board 1190. tic logic unit (arithmetic circuit), ALU controller 1192, instruction Action decoder 1193, interrupt controller 1194, timing controller R1195, Register 1196, Register Controller 1197, Bus Interface 1198 (Bus I / F), rewritable ROM1199, and ROM interface It has a ROM I / F (1189). The substrate 1190 is a semiconductor substrate, SOI base A plate, glass substrate, etc., is used. ROM1199 and ROM interface1189 are, It may also be provided on a separate chip. Of course, the CPU shown in Figure 31 is a simplified representation of its configuration. This is just one example; actual CPUs have a wide variety of configurations depending on their application. A configuration including the CPU or arithmetic circuit shown in Figure 31 is considered as one core, and a configuration including multiple such cores is considered as one core. Alternatively, the configuration may be such that each core operates in parallel. Also, the CPU's internal calculations The number of bits that can be handled by a path or data bus is, for example, 8 bits, 16 bits, 32 bits, 64 bits. It can be written as ".net" or similar.

[0376] Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to the decoder 1193, decoded, and then sent to the ALU controller 1192. Trap controller 1194, register controller 1197, timing controller This is entered into Ra1195.

[0377] ALU controller 1192, interrupt controller 1194, register controller The driver 1197 and timing controller 1195 perform various operations based on the decoded instructions. It performs control. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal to do so. In addition, the interrupt controller 1194 generates a signal to the CPU's program. During RAM execution, interrupt requests from external input / output devices and peripheral circuits are processed based on their priority and mass. The system determines and processes based on the state. The register controller 1197 processes the state of register 1196. It generates a dress and reads or writes to register 1196 depending on the CPU state. .

[0378] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 11 92, instruction decoder 1193, interrupt controller 1194, and It generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 generates an internal clock signal based on the reference clock signal. It is equipped with an internal clock generation unit that supplies the internal clock signal to the various circuits mentioned above.

[0379] In the CPU shown in Figure 31, a memory cell is located in register 1196. The transistor shown in the previous embodiment can be used as the memory cell of TA1196. Cut.

[0380] In the CPU shown in Figure 31, the register controller 1197 receives from ALU 1191. Following the instructions, select the hold operation in register 1196. That is, register 1 In the memory cell of 196, data is retained by a flip-flop, or Select whether to use quantitative elements for data retention. (Data retention using flip-flops) If selected, power voltage is supplied to the memory cells in register 1196. If data retention in the capacitive element is selected, the data will not be rewritten to the capacitive element. This process can be performed to stop the supply of power voltage to the memory cell in register 1196. ru.

[0381] Figure 32 is an example of a circuit diagram of a memory element that can be used as register 1196. The memory element 1200 has a circuit 1201 in which the stored data volatilizes when the power is cut off, and a memory element 1200 that volatilizes when the power is cut off. Circuit 1202 that prevents data loss, switch 1203, switch 1204, and logic It comprises element 1206, capacitive element 1207, and a circuit 1220 having a selection function. The path 1202 is connected to the capacitive element 1208, transistor 1209, and transistor 1210. , has. The memory element 1200 may include a diode, a resistor, an industrial diode as needed. It may also have other elements such as connectors.

[0382] Here, the memory device described in the previous embodiment can be used in circuit 1202. When the power supply voltage to the memory element 1200 is stopped, the transistor 12 of circuit 1202 The gate of transistor 09 is input to ground potential (0V) or the potential that turns off transistor 1209. The configuration will continue to be such that the gate of transistor 1209 is connected via a load such as a resistor. The configuration will be grounded.

[0383] Switch 1203 uses a single-conductivity (e.g., n-channel) transistor 1213. The configuration is such that the switch 1204 has a conductivity type opposite to that of a single-conductivity type (for example, a p-channel type). An example is shown using transistor 1214. Here, the first of switch 1203 The terminals correspond to one of the source and drain terminals of transistor 1213, and the other terminal of switch 1203. Terminal 2 corresponds to the source and drain of transistor 1213, and switch 1203 The control signal RD input to the gate of transistor 1213 controls the first terminal and the second terminal. The continuity or non-continuity between the terminals (i.e., the ON or OFF state of transistor 1213) The state is selected. The first terminal of switch 1204 is connected to the source and dot of transistor 1214. Corresponding to one side of the rain, the second terminal of switch 1204 is the source of transistor 1214. Corresponding to the other side of the drain, switch 1204 is input to the gate of transistor 1214. The control signal RD determines whether the first terminal and the second terminal are conductive or non-conductive (i.e., The ON or OFF state of transistor 1214 is selected.

[0384] One of the sources and drains of transistor 1209 is connected to the pair of electrodes of capacitive element 1208. One of them is electrically connected to the gate of transistor 1210. Here, the connection part Let the minute be node M2. One of the sources and drains of transistor 1210 is at a low power supply potential. It is electrically connected to a wire (e.g., a GND wire) that can supply power, and the other is a switch. The first terminal of 1203 (one of the source and drain of transistor 1213) is electrically connected. The second terminal of switch 1203 (source and drain of transistor 1213) On the other hand, the first terminal of switch 1204 (the source and drain of transistor 1214) is the first terminal of switch 1204. It is electrically connected to the second terminal of switch 1204 (the terminal of transistor 1214). The other end of the drain is electrically connected to wiring that can supply the power potential VDD. The second terminal of switch 1203 (the other terminal of the source and drain of transistor 1213) ) and the first terminal of switch 1204 (one of the source and drain of transistor 1214) ) and the input terminal of logic element 1206 and one of the pair of electrodes of capacitive element 1207, These are electrically connected. Here, the connection point is called node M1. A pair of capacitive elements 1207. The other electrode can be configured to receive a constant potential. For example, a low potential The system can be configured to receive either a source potential (such as GND) or a high power supply potential (such as VDD) as input. The other of the pair of electrodes of the capacitive element 1207 is a distribution capable of supplying a low power supply potential. It is electrically connected to a wire (for example, a GND wire). This configuration allows for a constant potential to be input. For example, a low power supply potential (such as GND). ) or a high power supply potential (VDD, etc.) can be input. Capacitive element 120 The other of the pair of electrodes (8) is connected to a wire capable of supplying a low power potential (e.g., GND). It is electrically connected to a wire.

[0385] Capacitive elements 1207 and 1208 are used to absorb parasitic capacitance from transistors and wiring. It was possible to omit it by actively using it.

[0386] The control signal WE is input to the first gate (first gate electrode) of transistor 1209. Switches 1203 and 1204 use a different control signal RD than control signal WE. The conduction or non-conduction state between the first terminal and the second terminal is selected by this, and one of the terminals When there is continuity between the first and second terminals of one switch, the first terminal of the other switch and the second terminal The area between terminals 2 becomes non-conductive.

[0387] The source and drain of transistor 1209 are connected to the data held by circuit 1201. A signal corresponding to the traffic signal is input. In Figure 32, the signal output from circuit 1201 is the traffic signal. An example is shown where the source and drain of the inverter 1209 are input to the other side. Switch 1203 The signal output from the second terminal (the other of the source and drain of transistor 1213) is The logic value is inverted by the logic element 1206, becoming an inverted signal, and then transmitted through the circuit 1220. This is then input to circuit 1201.

[0388] Note that in Figure 32, the second terminal of switch 1203 (the source of transistor 1213 and The signal output from the other side of the drain is routed through logic element 1206 and circuit 1220. An example of input to path 1201 is shown, but it is not limited to this. The second terminal of switch 1203 The signal output from (the other side of the source and drain of transistor 1213) is the inverse of the logic value. It may be input to circuit 1201 without being converted. For example, within circuit 1201, If there is a node that holds a signal that is the inverted logical value of the signal input from the input terminal The second terminal of switch 1203 (the other of the source and drain of transistor 1213) The signal output from this node can be input to the node in question.

[0389] Furthermore, in Figure 32, among the transistors used in the memory element 1200, The transistors other than STA1209 are made of a layer or substrate 11 made of a semiconductor other than an oxide semiconductor. A transistor can be formed with a channel at 90. For example, a silicon layer or This can be a transistor in which a channel is formed on a silicon substrate. All transistors used in the child 1200 have channels formed from oxide semiconductor films. It can also be a transistor. Alternatively, the memory element 1200 is a transistor 1209 or higher. In addition, it may include transistors in which the channel is formed of an oxide semiconductor film, and the rest The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It can also be considered a transistor.

[0390] In Figure 32, circuit 1201 can be, for example, a flip-flop circuit. Furthermore, the logic element 1206 can be, for example, an inverter or a clocked inverter. It is possible.

[0391] In a semiconductor device according to one aspect of the present invention, when the power supply voltage is not supplied to the memory element 1200 The data stored in circuit 1201 is transferred to the capacitive element 120 provided in circuit 1202. It can be held by 8.

[0392] Furthermore, transistors with channels formed in oxide semiconductor films exhibit extremely low off-currents. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor film depends on the crystalline properties. It is significantly lower than the off-current of a transistor in which a channel is formed in silicon. Therefore, by using the transistor as transistor 1209, the memory element Even when power voltage is not supplied to 1200, the signal held in the capacitive element 1208 will remain for a long period of time. The memory element 1200 retains its stored contents even when the power supply voltage is interrupted. It is possible to retain data.

[0393] Furthermore, by providing switches 1203 and 1204, the pre-charge function is activated. Since it is a memory element characterized by performing an operation, after the power supply voltage is restored, the circuit 1201 This can shorten the time it takes to restore the original data.

[0394] Furthermore, in circuit 1202, the signal held by the capacitive element 1208 is a transistor It is input to the gate of TA 1210. Therefore, the power supply voltage to memory element 1200 is restored. After opening, the signal held by the capacitive element 1208 is controlled by the state of transistor 1210. It can be converted to (on state or off state) and read from circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitive element 1208 fluctuates slightly, the original signal remains. It is possible to read the issue number accurately.

[0395] Such memory elements 1200 are stored in registers and cache memory of the processor. By using it in a storage device, it prevents the loss of data in the storage device due to a power supply interruption. It is possible to restore the system to its state before the power supply was interrupted in a short time after the power supply voltage is restored. Therefore, it can be attributed to the entire processor, or to one of the components of the processor. Alternatively, in multiple logic circuits, power can be shut off even for a short time, thus reducing power consumption. It can suppress this.

[0396] In this embodiment, the memory element 1200 was described as an example of being used in a CPU, but the memory element 1200 is a DSP (Digital Signal Processor), custom LSI, PLD (Programmable Logic Device), etc. It can also be applied to RF (Radio Frequency) devices.

[0397] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0398] (Embodiment 7) This embodiment describes an example of the configuration of a display panel according to one aspect of the present invention.

[0399] [Example Configuration] Figure 33(A) is a top view of a display panel according to one embodiment of the present invention, and Figure 33(B) is a top view of a display panel according to one embodiment of the present invention. A pixel circuit that can be used when applying liquid crystal elements to the pixels of a display panel in one embodiment of the present invention. This is a circuit diagram to explain the present invention. Also, Figure 33(C) shows a display panel according to one embodiment of the present invention. A circuit diagram illustrating a pixel circuit that can be used when applying organic EL elements to pixels. This is a diagram.

[0400] The transistors placed in the pixel area can be formed according to the above embodiment. Furthermore, since the transistor can easily be made into an n-channel type, the n-channel transistor is used in the drive circuit. A portion of the drive circuit, which can be constructed using Nell-type transistors, is the same as the transistors in the pixel section. It is formed on a single substrate. In this way, the pixel portion and the drive circuit are formed using the transistors shown in the above embodiment. By using this technology, a highly reliable display device can be provided.

[0401] An example of a block diagram of an active-matrix display device is shown in Figure 33(A). On the substrate 700 are a pixel section 701, a first scan line drive circuit 702, and a second scan line drive circuit. It has a path 703 and a signal line drive circuit 704. Multiple signal lines are driven by the signal line drive circuit in the pixel section 701. Extending from the drive circuit 704, multiple scan lines are arranged in the first scan line drive circuit 702, It is arranged as an extension from the second scan line drive circuit 703. Note the intersection of the scan line and signal line. Each region has pixels, each containing a display element, arranged in a matrix. The circuit board 700 is a connecting FPC (Flexible Printed Circuit) and the like. It is connected via a connecting part to a timing control circuit (also called a controller or control IC). ru.

[0402] Figure 33(A) shows the first scan line drive circuit 702, the second scan line drive circuit 703, and the signal The line drive circuit 704 is formed on the same substrate 700 as the pixel unit 701. Therefore, externally Since the number of components such as drive circuits is reduced, costs can be lowered. 700 If an external drive circuit is installed, it becomes necessary to extend the wiring, increasing the number of connections between wires. It is possible to reduce the number of connections between the wiring when the drive circuit is placed on the same circuit board 700. This can lead to improved reliability or increased yield.

[0403] [LCD panel] Furthermore, an example of the pixel circuit configuration is shown in Figure 33(B). Here, a VA-type liquid crystal display panel is shown. This shows a pixel circuit that can be applied to the pixels.

[0404] This pixel circuit can be applied to configurations in which a single pixel has multiple pixel electrodes. The pixel electrodes are connected to different transistors, and each transistor is driven by a different gate signal. It is configured to allow for the individual pixel power of the multi-domain designed pixels. The signals applied to the poles can be controlled independently.

[0405] The gate wiring 712 of transistor 716 and the gate wiring 713 of transistor 717 These are separated so that different gate signals can be applied. On the other hand, the data line is The source or drain electrode 714 that functions is connected to transistor 716 and transistor It is commonly used in 717. Transistors 716 and 717 are used in the above implementation. Transistors described by their form can be used as appropriate. This allows for highly reliable liquid crystals. A display panel can be provided.

[0406] Furthermore, the first pixel electrode is electrically connected to transistor 716, and transistor 7 At point 17, the second pixel electrode is electrically connected. The first pixel electrode and the second pixel electrode are They are separated. The shapes of the first and second pixel electrodes are as follows: There are no particular limitations; for example, it could be V-shaped.

[0407] The gate electrode of transistor 716 is connected to gate wiring 712, and transistor 717 The gate electrode is connected to gate wiring 713. Gate wiring 712 and gate wiring 71 By applying different gate signals to 3, the operating timing of transistors 716 and 717 can be determined. By changing the angle, the alignment of the liquid crystals can be controlled.

[0408] Furthermore, the capacitive wiring 710, the gate insulating film which functions as a dielectric, and the first pixel electrode A retaining capacitance may be formed by a capacitive electrode electrically connected to a second pixel electrode.

[0409] The multi-domain structure comprises a first liquid crystal element 718 and a second liquid crystal element 719 in each pixel. The first liquid crystal element 718 is composed of a first pixel electrode, a counter electrode, and a liquid crystal layer between them. The second liquid crystal element 719 is composed of a second pixel electrode, a counter electrode, and a liquid crystal layer between them.

[0410] Note that the pixel circuit shown in Figure 33(B) is not limited to this. For example, Figure 33(B) A new switch, resistor, capacitive element, transistor, sensor, or logic circuit is added to the indicated pixel. You can add roads and other elements.

[0411] [OLED panel] Another example of a pixel circuit configuration is shown in Figure 33(C). Here, a table using an organic EL element is shown. The pixel structure of the display panel is shown.

[0412] Organic EL elements emit electrons from one of a pair of electrodes when a voltage is applied to the light-emitting element. On the other hand, holes are injected from the other side into layers containing luminescent organic compounds, and an electric current flows. Then, through the recombination of electrons and holes, the luminescent organic compound forms an excited state, It emits light when the excited state returns to the ground state. This mechanism explains why such light emission occurs. The device is called a current-excited light-emitting element.

[0413] Figure 33(C) shows an example of an applicable pixel circuit. Here, an n-channel type is shown. An example of using two transistors in one pixel is shown. Note that the metal oxide film according to one aspect of the present invention This can be used in the channel formation region of an n-channel transistor. The pixel circuit can be fitted with digital time-based grayscale driving.

[0414] Applicable pixel circuit configurations and pixel operation when digital time-gradation driving is applied. I will explain.

[0415] Pixel 720 consists of a switching transistor 721, a driving transistor 722, and a light emitter. It has element 724 and capacitive element 723. The switching transistor 721 is The source electrode is connected to scan line 726, and the first electrode (either the source electrode or the drain electrode) It is connected to signal line 725, and the second electrode (the other of the source electrode and drain electrode) is a drive transistor It is connected to the gate electrode of transistor 722. The drive transistor 722 has a gate electrode The electrode is connected to the power line 727 via the capacitive element 723, and the first electrode is connected to the power line 727. The second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 724. The second electrode of 4 corresponds to the common electrode 728. The common electrode 728 is formed on the same substrate. It is electrically connected to a common potential line.

[0416] The switching transistor 721 and the driving transistor 722 are as described above. The transistors described can be used as appropriate. This allows for a highly reliable organic EL display. A display panel can be provided.

[0417] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to the low power supply potential. Low power supply potential is a potential lower than the high power supply potential supplied to power line 727, for example, GN D, 0V, etc. can be set as low power supply potentials. The forward direction of the light-emitting element 724 The high and low power supply potentials are set so that the voltage is greater than or equal to a certain value, and the potential difference between them is used by the light-emitting element 72 By applying a current to 4, the light-emitting element 724 is made to emit light. The forward voltage of 24 refers to the voltage required to achieve the desired brightness, and at least the forward voltage is Includes key voltage.

[0418] Furthermore, the capacitive element 723 is used by substituting the gate capacitance of the drive transistor 722. This can be omitted. Regarding the gate capacitance of the drive transistor 722, the channel formation region and the gate A capacitance may be formed between the electrode and the other electrode.

[0419] Next, we will explain the signal input to the drive transistor 722. Voltage input, voltage drive. In this method, the drive transistor 722 is either fully on or completely off. A video signal is input to the drive transistor 722. To operate the 722 in the linear region, a voltage higher than the voltage of the power line 727 is used for driving it. It is applied to the gate electrode of transistor 722. Additionally, the signal line 725 is driven by the power line voltage. Apply a voltage greater than or equal to the threshold voltage Vth of transistor 722.

[0420] When performing analog grayscale driving, the gate electrode of the driving transistor 722 is connected to the light-emitting element 72 A voltage greater than or equal to the sum of the forward voltage of 4 and the threshold voltage Vth of the drive transistor 722 is required. The video signal is input so that the drive transistor 722 operates in the saturation region. Then, current is passed to the light-emitting element 724. Also, the drive transistor 722 is operated in the saturation region. To achieve this, the potential of the power line 727 is set higher than the gate potential of the drive transistor 722. By converting the video signal to analog, a current corresponding to the video signal is supplied to the light-emitting element 724. It can perform analog grayscale driving.

[0421] Note that the pixel circuit configuration is not limited to the pixel configuration shown in Figure 33(C). For example, Figure 3 3(C) The pixel circuit includes a switch, a resistor, a capacitive element, a sensor, a transistor or You may add logic circuits or other components.

[0422] When applying the transistor exemplified in the above embodiment to the circuit exemplified in Figure 33, the low power The source electrode (first electrode) is on the high-potential side, and the drain electrode (second electrode) is on the high-potential side. The configuration is designed to be electrically connected. Furthermore, the potential of the first gate electrode is controlled by a control circuit, etc. Furthermore, the second gate electrode is supplied with a potential lower than that supplied to the source electrode by wiring (not shown). The configuration should be such that it can accept the potentials exemplified above.

[0423] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0424] (Embodiment 8) A semiconductor device according to one aspect of the present invention is a display device, a personal computer, and a recording medium. Equipped with an image playback device (typically DVD: Digital Versatile Disc) (Used in a device that has a display capable of playing back recording media such as c and displaying the images thereof) This is possible. In addition, electronic devices that can use a semiconductor device according to one aspect of the present invention. Examples include mobile phones, portable game consoles, portable data terminals, e-readers, and video cameras. Cameras such as digital still cameras, goggle-type displays (head-mounted displays) Playback), navigation system, sound playback device (car audio, digital audio) (Optical players, etc.), photocopiers, fax machines, printers, multifunction printers, ATMs Examples include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 34. show.

[0425] Figure 34(A) shows a portable game console, consisting of a casing 901, casing 902, display unit 903, and display Unit 904, microphone 905, speaker 906, operation key 907, stylus 90 It has 8, etc. Note that the portable game console shown in Figure 31(A) has two display units 903 and Although it has a display unit 904, the number of display units that a portable game console has is not limited to this. stomach.

[0426] Figure 34(B) shows a portable data terminal, consisting of a first housing 911, a second housing 912, and a first display unit. It has 913, a second display unit 914, a connection unit 915, an operation key 916, etc. First display unit 91 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. And the first housing 911 and the second housing 912 are connected by a connecting part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting part 915. The video in the first display unit 913 is connected to the first housing 911 and the second housing in the connection unit 915. The configuration may also be configured to switch according to the angle between 912 and 913. A display device in which at least one of the second display unit 914 is provided with a function as a position input device. You may also use a touch panel. Note that the function as a position input device is provided by the display device. It can be added by providing a panel. Alternatively, the function as a position input device is It can also be added by installing a photoelectric conversion element, also called a photosensor, in the pixel section of the display device. It is possible.

[0427] Figure 34(C) shows a notebook personal computer, comprising a casing 921, a display unit 922, It includes a keyboard 923, a pointing device 924, and the like.

[0428] Figure 34(D) shows an electric refrigerator-freezer, consisting of a casing 931, a refrigerator door 932, and a freezer door 9 It has 33, etc.

[0429] Figure 34(E) shows a video camera, consisting of a first housing 941, a second housing 942, and a display unit 943. It has an operation key 944, a lens 945, a connecting part 946, etc. Operation key 944 and lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. And the first housing 941 and the second housing 942 are connected by a connecting part 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting part 946. The video on the display unit 943 is connected to the first housing 941 and the second housing 94 in the connection unit 946. It could also be configured to switch according to the angle between 2 and 3.

[0430] Figure 34(F) is a regular passenger car, consisting of a body 951, wheels 952, dashboard 953, It has lights such as the 954.

[0431] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0432] (Embodiment 9) In this embodiment, Figure 35 illustrates an example of the use of an RF device according to one aspect of the present invention. Let me explain. RF devices have a wide range of applications, such as banknotes, coins, and securities. Categories, bearer bonds, certificates (such as driver's licenses and resident registration certificates, see Figure 35(A)), recording media (D VDs and videotapes, etc. (see Figure 35(B)), packaging containers (wrapping paper, bottles, etc., see Figure 35) (See (C)), vehicles (bicycles, etc., see Figure 35(D)), personal belongings (bags, glasses, etc.), Food products, plants, animals, human bodies, clothing, household goods, medical products including medicines and drugs, or electricity Items such as sub-devices (LCD displays, EL displays, television equipment, or mobile phones), Alternatively, it can be attached to luggage tags (see Figures 35(E) and 35(F)) attached to each item. It is possible.

[0433] An RF device 4000 according to one aspect of the present invention can be attached to or embedded on a surface. It is then fixed to an object. For example, in the case of a book, it is embedded in the paper, and the package is made of organic resin. If so, it is embedded inside the organic resin and fixed to each article. R according to one aspect of the present invention The F-device 4000 is small, thin, and lightweight, and even after being fixed to an item, it remains attached to the item. It does not detract from the design of the item itself. Also, banknotes, coins, securities, bearer bonds, Alternatively, by providing the RF device 4000 according to one aspect of the present invention on the certificate or other document, authentication This feature can be implemented, and by utilizing this authentication function, forgery can be prevented. Also, packaging containers, recording media, personal belongings, food products, clothing, household goods, or electronic devices. By attaching an RF device according to one aspect of the present invention to systems such as inspection systems, The efficiency of the system can be improved. Furthermore, even in the case of vehicles, according to one aspect of the present invention, R By installing the F device, security against theft and other theft can be enhanced. Cut.

[0434] As described above, the RF device according to one aspect of the present invention can be used for each of the applications listed in this embodiment. By using this method, operating power, including information writing and reading, can be reduced, thus maximizing communication It becomes possible to cover longer distances. Also, even when the power is cut off, information can be transmitted extremely quickly. Because it can retain data for a long period, it is suitable for use in applications where the frequency of writing and reading is low. It is possible.

[0435] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination. [Explanation of Symbols]

[0436] 10 Laminated structure 11. The first layer 12. Second Layer 21 First insulating film 22 Second insulating film 31 First wiring layer 32 Second wiring layer 41 Barrier film 100 Second transistor 101a Oxide semiconductor film 101b Oxide semiconductor film 10¹c oxide semiconductor film 103 Conductive film 103a electrode 103b electrode 103c electrode 104 Gate Insulator 105 Guard Station 106a insulating film 106b insulating film 107 Insulating Film 108 Insulating Film 109a Low resistance area 109b Low resistance region 110 First transistor 111 Semiconductor substrates 112 Semiconductor film 113a Low resistance layer 113b Low resistance layer 114 Gate insulating film 115 Gate Shuttle 115a Terminal 115b Grid gate 116 Insulating film 117 Insulating Film 118 Insulating Film 119 Insulating film 120 Barrier film 121 Insulating film 122 Insulating film 123 Insulating film 124 Insulating film 125 Insulating film 126 Insulating film 127 Insulating film 128 Insulating film 129 Insulating film 130 Capacitive elements 131a Oxide semiconductor film 131b Oxide semiconductor film 132 Wiring 136 Electrode 136a electrode 136b Electrode 137 Insulating Film 138 Electrode 150 Capacitive elements 151 Insulating Film 152 Insulating film 153 plug 154 Electrode 155 insulating film 156 Electrode 157 Plug 158 plug 159 plug 160 transistors 161 plug 162 plug 163 plug 164 plug 165 plug 166 plug 167 plug 168 plug 169 plug 170 plug 171 Plug 172 plug 173 Electrode 174 Electrode 175 Electrode 176 plug 177 Electrode 178 plug 181 Electrode 182 Insulating film 183 Electrode 190 Capacitive element 700 circuit boards 701 pixel section 702 Scan Line Drive Circuit 703 Scan line drive circuit 704 Signal Line Drive Circuit 710 Capacitance wiring 712 Gate Wiring 713 Gate wiring 714 Drain electrode 716 transistors 717 transistors 718 Liquid crystal elements 719 Liquid crystal elements 720 pixels 721 Switching Transistors 722 Driver Transistor 723 Capacitive element 724 Light-emitting element 725 Signal Line 726 scan lines 727 Power line 728 Common electrode 800 RF tags 801 Communication device 802 Antenna 803 Wireless signal 804 Antenna 805 Rectifier circuit 806 Constant Voltage Circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuits 810 Memory circuit 811 ROM 901 cabinet 902 cabinet 903 Display section 904 Display section 905 Microphone 906 Speakers 907 Operation Keys 908 Stylus 911 cabinet 912 cabinet 913 Display section 914 Display section 915 Connection part 916 Operation Keys 921 cabinet 922 Display section 923 Keyboard 924 Pointing Devices 931 cabinet 932 Refrigerator door 933 Freezer door 941 cabinet 942 cabinets 943 Display section 944 Operation Keys 945 lens 946 Connection part 951 Body 952 wheels 953 Dashboard 954 Light 1189 ROM Interface 1190 circuit board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Element 1207 Capacitive element 1208 Capacitive element 1209 Transistors 1210 Transistors 1213 Transistors 1214 Transistors 1220 Circuit 2100 transistors 2200 transistors 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 transistors 3300 transistors 3400 Capacitive element 4000 RF devices 5120 circuit board

Claims

1. A first transistor having a first semiconductor and a first electrode having a region overlapping with the first semiconductor and functioning as a gate electrode, A first insulating layer having a region located above the first electrode, A capacitor having a region located above the first insulating layer and having a pair of electrodes, A second insulating layer having a region located above the capacitance, A second transistor having a region located above the second insulating layer and a second semiconductor, and a second electrode having a region overlapping with the second semiconductor and functioning as a gate electrode, A third electrode penetrating multiple layers including the first insulating layer, A fourth electrode that penetrates the plurality of layers including the second insulating layer, It has, The first semiconductor has silicon, The second semiconductor comprises indium oxide, One of the pair of electrodes has a region that overlaps with the first electrode via the first insulating layer and a region that overlaps with the second electrode via the second insulating layer. The plurality of layers through which the fourth electrode penetrates include the second semiconductor, The fourth electrode has a region that overlaps with the third electrode, The fourth electrode is electrically connected to the third electrode, and is a semiconductor device.

2. A first transistor having a first semiconductor and a first electrode having a region overlapping with the first semiconductor and functioning as a gate electrode, A first insulating layer having a region located above the first electrode, A capacitor having a region located above the first insulating layer and having a pair of electrodes, A second insulating layer having a region located above the capacitance, A second transistor having a region located above the second insulating layer and a second semiconductor, and a second electrode having a region overlapping with the second semiconductor and functioning as a gate electrode, A third electrode penetrating multiple layers including the first insulating layer, A fourth electrode that penetrates the plurality of layers including the second insulating layer, The first semiconductor has silicon, The second semiconductor comprises indium oxide, One of the pair of electrodes has a region that overlaps with the first electrode via the first insulating layer and a region that overlaps with the second electrode via the second insulating layer. The plurality of layers through which the fourth electrode penetrates include semiconductors located in the same layer as the second semiconductor. The fourth electrode has a region that overlaps with the third electrode, The fourth electrode is electrically connected to the third electrode, and is a semiconductor device.

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