Semiconductor equipment

Abstract

To provide a semiconductor device with less variation in characteristics.SOLUTION: A semiconductor device includes a first circuit region and a second circuit region on a substrate. The first circuit region includes a plurality of first transistors, and includes a first insulation body on a plurality of first transistors. The second circuit region includes a plurality of second transistors, and includes a second insulator on the plurality of second transistors. The second insulator includes an opening part. The first transistor and the second transistor each include an oxide semiconductor, and includes a third insulator over so as to be in contact with the top of first insulator and the top of the second insulator. The first insulator, the second insulator, and the third insulator suppress diffusion of oxygen. An arrangement density of the plurality of first transistors in the first circuit region is higher than that of the plurality of second transistors in the second circuit region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, and electronic equipment. Another aspect of the present invention relates to a method for manufacturing a semiconductor device. Another aspect of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are all forms of semiconductor devices. Display devices (such as liquid crystal displays and light-emitting displays), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also be considered to have semiconductor devices.

[0003] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the invention disclosed herein relates to a product, a method, or a method of manufacture. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] In recent years, semiconductor device development has progressed, with LSIs, CPUs, and memory being the main components used. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memory) separated from a semiconductor wafer, and electrodes, which serve as connection terminals, are formed on them.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memory are mounted on circuit boards, such as printed circuit boards, and used as components in various electronic devices.

[0006] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0007] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, low-power CPUs that take advantage of the low leakage current characteristic of transistors using oxide semiconductors have been disclosed (see Patent Document 1). Also, for example, memory devices that can retain stored data for a long period of time have been disclosed that take advantage of the low leakage current characteristic of transistors using oxide semiconductors (see Patent Document 2).

[0008] Furthermore, in recent years, with the miniaturization and weight reduction of electronic devices, there has been an increasing demand for even higher density integrated circuits. There is also a need to improve the productivity of semiconductor devices, including integrated circuits. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 2012-257187 [Patent Document 2] Japanese Patent Publication No. 2011-151383 [Overview of the Initiative] [Problems that the invention aims to solve]

[0010] One aspect of the present invention aims to provide a semiconductor device with less variation in transistor characteristics. Alternatively, one aspect of the present invention aims to provide a semiconductor device with good reliability. Alternatively, one aspect of the present invention aims to provide a semiconductor device with good electrical characteristics. Alternatively, one aspect of the present invention aims to provide a semiconductor device with a large on-current. Alternatively, one aspect of the present invention aims to provide a semiconductor device that can be miniaturized or highly integrated. Alternatively, one aspect of the present invention aims to provide a semiconductor device with low power consumption.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem]

[0012] One aspect of the present invention has a first circuit region and a second circuit region on a substrate, the first circuit region having a plurality of first transistors and a first insulator on the plurality of first transistors, the second circuit region having a plurality of second transistors and a second insulator on the plurality of second transistors, the second insulator having an opening, the first transistors and the second transistors having an oxide semiconductor, a third insulator being in contact with the first insulator and the second insulator, the first insulator, the second insulator and the third insulator suppressing the diffusion of oxygen, and the arrangement density of the plurality of first transistors in the first circuit region is higher than the arrangement density of the plurality of second transistors in the second circuit region.

[0013] One aspect of the present invention has a first circuit region, a second circuit region, and a third circuit region on a substrate, the first circuit region having a plurality of first transistors and a first insulator on the plurality of first transistors, the second circuit region having a plurality of second transistors and a second insulator on the plurality of second transistors, the second insulator having a first opening, the third circuit region having a plurality of third transistors and a third insulator on the plurality of third transistors, the third insulator having a second opening, the first transistor, the second transistor, and the third transistor have oxide semiconductors, on the first insulator, on the second insulator, The circuit has a fourth insulator in contact with the third insulator, and the first, second, third, and fourth insulators suppress the diffusion of oxygen, the arrangement density of multiple first transistors in the first circuit region is higher than the arrangement density of multiple second transistors in the second circuit region and the arrangement density of multiple third transistors in the third circuit region, the arrangement density of multiple second transistors in the second circuit region is higher than the arrangement density of multiple third transistors in the third circuit region, and the ratio of the total area of ​​the first opening in the second circuit region is greater than the ratio of the total area of ​​the second opening in the third circuit region.

[0014] Furthermore, the oxide semiconductor described above includes one or more selected from In, Ga, or Zn.

[0015] One aspect of the present invention is a method for creating a semiconductor device in which a first transistor is formed in a first region on a substrate and a second transistor in a second region, a first insulating film is deposited on the first transistor and the second transistor, a second insulating film is deposited on the first insulating film, oxygen is added to the first insulating film via the second insulating film, a third insulating film is deposited on the second insulating film, an opening is formed in the second region to expose the first insulating film by removing a portion of the second insulating film and the third insulating film, heat treatment is performed, and a fourth insulating film is deposited on the first insulating film and the third insulating film, thereby increasing the arrangement density of the first transistor in the first region compared to the arrangement density of the second transistor in the second region.

[0016] One aspect of the present invention is a method for manufacturing a semiconductor device in which a first transistor is formed in a first region on a substrate, a second transistor in a second region, and a third transistor in a third region; a first insulating film is deposited on the first, second, and third transistors; a second insulating film is deposited on the first insulating film; oxygen is added to the first insulating film via the second insulating film; a third insulating film is deposited on the second insulating film; openings are formed in the second and third regions to expose the first insulating film by removing a portion of the second and third insulating films; heat treatment is performed; a fourth insulating film is deposited on the first and third insulating films; the arrangement density of the first transistor in the first region is higher than that of the second transistor in the second region; the arrangement density of the second transistor in the second region is higher than that of the third transistor in the third region; and the ratio of the total area of ​​the openings in the second region is greater than that of the total area of ​​the openings in the third region.

[0017] Furthermore, in the above, the first transistor, the second transistor, and the third transistor each have an oxide semiconductor containing one or more selected from In, Ga, or Zn.

[0018] Furthermore, in the above, the second insulating film is a silicon oxide film, and the third insulating film is aluminum oxide.

[0019] Furthermore, in the above, the oxygenation treatment is performed by ion implantation.

[0020] Furthermore, the heat treatment described above is carried out in a range of 250°C to 650°C.

[0021] Furthermore, the heat treatment described above is carried out in a range of 350°C to 400°C. [Effects of the Invention]

[0022] According to one aspect of the present invention, a semiconductor device with less variation in transistor characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided.

[0023] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one embodiment of the present invention does not need to possess all of these effects. Other effects will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other effects from the description in the specification, drawings, and claims. [Brief explanation of the drawing]

[0024] [Figure 1] Figure 1 is a top view of a semiconductor device according to one embodiment of the present invention. [Figure 2] Figures 2A to 2C are top views of a semiconductor device according to one embodiment of the present invention. [Figure 3] Figure 3A is a top view of a semiconductor device according to one embodiment of the present invention. Figures 3B and 3C are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 4] Figure 4A is a top view of a semiconductor device according to one embodiment of the present invention. Figures 4B to 4D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 5] Figure 5 is a cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 6] Figure 6A illustrates the classification of IGZO crystal structures. Figure 6B illustrates the XRD spectrum of a CAAC-IGZO film. Figure 6C illustrates the micro-electron diffraction pattern of a CAAC-IGZO film. [Figure 7] Figure 7A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 7B to 7D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 8] Figure 8A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 8B to 8D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 9] Figure 9A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 9B to 9D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 10] Figure 10A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 10B to 10D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 11] Figure 11A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 11B to 11D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 12] Figure 12A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 12B to 12D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 13] Figure 13A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 13B to 13D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 14]Figure 14A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 14B to 14D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 15] Figure 15A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 15B to 15D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 16] Figure 16A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 16B to 16D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 17] Figure 17A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 17B to 17D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 18] Figure 18A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 18B to 18D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 19] Figure 19A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 19B to 19D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 20] Figure 20A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 20B to 20D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 21] Figure 21A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 21B to 21D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 22] Figure 22A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 22B to 22D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 23] Figure 23A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 23B to 23D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 24] Figure 24 is a top view illustrating a microwave processing apparatus according to one aspect of the present invention. [Figure 25] Figure 25 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention. [Figure 26] Figure 26 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention. [Figure 27] Figure 27A is a top view of a semiconductor device according to one embodiment of the present invention. Figures 27B to 27D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 28] Figure 28A is a top view of a semiconductor device according to one embodiment of the present invention. Figure 28B is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 29] Figure 29A is a top view of a semiconductor device according to one embodiment of the present invention. Figure 29B is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 30] Figure 30A is a top view of a semiconductor device according to one embodiment of the present invention. Figure 30B is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 31] Figures 31A and 31B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 32] Figure 32 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. [Figure 33] Figure 33 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. [Figure 34] Figures 34A and 34B are cross-sectional views of a semiconductor device according to one aspect of the present invention. [Figure 35] Figures 35A and 35B are cross-sectional views of a semiconductor device according to one aspect of the present invention. [Figure 36] Figure 36 is a cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 37] Figure 37 is a cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 38]Figure 38A is a block diagram showing an example of the configuration of a storage device according to one aspect of the present invention. Figure 38B is a perspective view of a storage device according to one aspect of the present invention. [Figure 39] Figures 39A to 39H are circuit diagrams showing an example of the configuration of a storage device according to one aspect of the present invention. [Figure 40] Figures 40A and 40B are schematic diagrams of a semiconductor device according to one aspect of the present invention. [Figure 41] Figures 41A and 41B illustrate an example of an electronic component. [Figure 42] Figures 42A to 42E are schematic diagrams of a storage device according to one aspect of the present invention. [Figure 43] Figures 43A to 43H show an electronic device according to one aspect of the present invention. [Figure 44] Figure 44 is a diagram illustrating a cross-section of a semiconductor device according to an embodiment. [Modes for carrying out the invention]

[0025] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope. Therefore, the present invention is not to be construed as being limited to the following embodiments.

[0026] Furthermore, in drawings, size, layer thickness, or area may be exaggerated for clarity. Therefore, they are not necessarily limited to that scale. Also, the drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers or resist masks may be unintentionally reduced due to processes such as etching, but this may not be reflected in the drawings for ease of understanding. In addition, in drawings, the same reference numerals may be used in common across different drawings for the same part or parts with similar functions, and repeated explanations may be omitted. Also, when referring to similar functions, the hatch pattern may be the same, and no specific reference numeral may be assigned.

[0027] Furthermore, in particular, in top views (also called "plan views") and perspective views, descriptions of some components may be omitted to facilitate understanding of the invention. Also, descriptions of some hidden lines may be omitted.

[0028] Furthermore, the ordinal numbers used in this specification, such as "first," "second," etc., are for convenience only and do not indicate the order of processes or stacking. Therefore, for example, "first" can be replaced with "second" or "third," etc., as appropriate in the explanation. Also, the ordinal numbers described in this specification may not be the same as the ordinal numbers used to specify an aspect of the present invention.

[0029] Furthermore, in this specification, terms indicating placement, such as "above" and "below," are used for convenience to explain the positional relationships between components with reference to the drawings. The positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms used are not limited to those described in the specification and can be appropriately rephrased depending on the situation.

[0030] For example, if it is explicitly stated in this specification that X and Y are connected, then the disclosure in this specification includes cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected. Therefore, it is not limited to predetermined connection relationships, such as those shown in the figures or text, but also includes connection relationships other than those shown in the figures or text. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0031] Furthermore, in this specification, a transistor is defined as an element having at least three terminals, including a gate, a drain, and a source. It also has a region where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) (hereinafter also referred to as the channel-forming region), and current can flow between the source and the drain through the channel-forming region. In this specification, the channel-forming region refers to the region through which current primarily flows.

[0032] Furthermore, the functions of the source and drain may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, the terms source and drain may be used interchangeably in this specification.

[0033] The channel length refers to the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or in the channel formation region, as seen in a top view of a transistor. It should be noted that the channel length is not necessarily the same in all regions of a single transistor. That is, the channel length of a single transistor may not be a single fixed value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0034] Channel width refers to the length of the channel formation region perpendicular to the channel length direction, for example, in a top view of a transistor, where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or within the channel formation region. Note that the channel width is not necessarily the same across all regions in a single transistor. That is, the channel width of a single transistor may not be a single fixed value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value within the channel formation region.

[0035] In this specification, depending on the transistor structure, the channel width in the region where the channel is actually formed (hereinafter also referred to as the "effective channel width") may differ from the channel width shown in the top view of the transistor (hereinafter also referred to as the "apparent channel width"). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may become larger than the apparent channel width, and this effect may not be negligible. For example, in a miniature transistor where the gate electrode covers the side surface of the semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width will be larger than the apparent channel width.

[0036] In such cases, it can be difficult to estimate the effective channel width through actual measurements. For example, estimating the effective channel width from design values ​​requires the assumption that the semiconductor shape is known. Therefore, if the semiconductor shape is not precisely known, it is difficult to accurately measure the effective channel width.

[0037] In this specification, when simply referred to as "channel width," it may refer to the apparent channel width. Alternatively, when simply referred to as "channel width," it may refer to the effective channel width. Note that channel length, channel width, effective channel width, apparent channel width, etc., can be determined by analyzing cross-sectional TEM images, etc.

[0038] Impurities in semiconductors refer to elements other than the main components that make up the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. The presence of impurities can cause problems such as an increase in the defect level density of the semiconductor or a decrease in crystallinity. In the case of oxide semiconductors, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of oxide semiconductors, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen vacancies (V) in oxide semiconductors. O (Also known as an oxygen vacancy) may form.

[0039] In this specification, silicon oxide nitride refers to a material whose composition contains more oxygen than nitrogen. Similarly, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0040] Furthermore, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." Similarly, the term "conductor" may be replaced with "conductive film" or "conductive layer." Finally, the term "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer."

[0041] Furthermore, in this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Also, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Also, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0042] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the semiconductor layer of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0043] Furthermore, in this specification, normally off means that when no potential is applied to the gate, or when the gate is given a ground potential, the drain current flowing through the transistor per 1 μm of channel width is 1 × 10⁻¹⁶ at room temperature. -20 A or less, 1 × 10 at 85℃ -18 A or less, or 1 × 10 at 125°C -16 This means being less than or equal to A.

[0044] (Embodiment 1) In this embodiment, an example of a semiconductor device 500 according to one aspect of the present invention and a method for manufacturing the same will be described with reference to Figures 1 to 26.

[0045] The semiconductor device 500 has, on the same substrate, regions that constitute multiple circuits, and peripheral regions that are not composed of circuits, which are the outer edges of the regions that constitute the circuits.

[0046] An example of a semiconductor device 500 is shown in Figure 1. Figure 1 is a top view of the semiconductor device 500. The semiconductor device 500 has multiple elements and includes circuit regions 510, 512, and 514, which constitute a circuit. Peripheral regions 516 are arranged between circuit region 510 and circuit region 512, between circuit region 512 and circuit region 514, and between circuit region 510 and circuit region 514. Peripheral regions 516 are also arranged between circuit regions 510, 512, and 514 and the substrate edge.

[0047] Figure 2A is a top view of circuit region 510, Figure 2B is a top view of circuit region 512, and Figure 2C is a top view of circuit region 514. As shown in Figure 2, each circuit region has at least a number of transistors 200 and a sealing portion 265.

[0048] Note that the peripheral region 516 does not necessarily have to be provided between each circuit region. For example, the circuit regions may be divided by providing a common sealing portion 265 for circuit region 510 and a common sealing portion 265 for circuit region 512.

[0049] In this case, it is preferable that the channel formation region of the transistor 200 uses a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0050] Transistors using oxide semiconductors in the channel formation region exhibit extremely low leakage current in the non-conductive state, thus providing low-power semiconductor devices. On the other hand, transistors using oxide semiconductors are prone to exhibiting normally-on characteristics (where a channel exists and current flows through the transistor even without applying voltage to the gate electrode) due to variations in their electrical properties caused by impurities and oxygen vacancies in the oxide semiconductor.

[0051] Therefore, it is preferable to use a high-purity intrinsic oxide semiconductor with reduced impurities and oxygen vacancies for the channel formation region of a transistor. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. To make an oxide semiconductor high-purity intrinsic, oxygen vacancies can be reduced by compensating for the oxygen vacancies in the oxide semiconductor with oxygen.

[0052] Specifically, by placing an insulator containing oxygen that is desorbed by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen can be supplied from the insulator to the oxide semiconductor, thereby reducing oxygen deficiency.

[0053] Furthermore, to provide an insulator containing excess oxygen near an oxide semiconductor, it is advisable to perform an oxygen-adding treatment (hereinafter also referred to as oxygen addition treatment, oxygen implantation treatment, or oxygen doping treatment) on the insulator. Specifically, ion implantation, ion doping, plasma immersion ion implantation, etc., can be used as oxygen-adding treatments. Alternatively, oxygen may be injected by performing plasma treatment on the insulator. Dry etching equipment, plasma CVD equipment, sputtering equipment, etc., can be used as plasma generation equipment.

[0054] Furthermore, it is preferable that the circuit regions are sealed with a material that suppresses oxygen diffusion. By sealing excess oxygen within the circuit regions, the release of excess oxygen outside the circuit regions during heat treatment is suppressed, allowing for efficient supply to the oxide semiconductor. In addition, materials that suppress oxygen diffusion may also suppress the diffusion of hydrogen, water, and impurities, which can adversely affect the oxide semiconductor. Therefore, by sealing each circuit region, the diffusion of impurities from outside the substrate and from other structures can be suppressed, thereby improving the reliability of the semiconductor device.

[0055] On the other hand, an excessive amount of oxygen supplied to the source or drain region can cause a decrease in the transistor's on-current or field-effect mobility. Furthermore, variations in the oxygen supplied to the source or drain region across the substrate surface can lead to variations in the characteristics of semiconductor devices containing transistors.

[0056] Therefore, it is necessary to adjust the amount of excess oxygen detached from the insulator near the oxide semiconductor in order to make the oxide semiconductor highly pure and intrinsic, and to avoid affecting the source and drain regions.

[0057] For example, in the semiconductor device 500 shown in Figures 1 and 2, the density of transistors 200 per unit area differs between circuit region 510 and circuit region 514. Specifically, as shown in Figure 2, if the transistor arrangement density in circuit region 510 is higher than that of circuit region 514, the amount of excess oxygen required by circuit region 510 will be greater than that required by circuit region 514.

[0058] Therefore, the entire surface of the substrate having circuit regions 510 and 514 is subjected to an oxygenation treatment. This oxygenation treatment creates an excess oxygen region in the insulator located near the oxide semiconductor of the transistor 200. It is preferable that the oxygenation treatment be performed by adding the required amount of excess oxygen to the circuit region with the highest transistor placement density among the multiple circuit regions. Specifically, it is preferable to add the required amount of excess oxygen to circuit region 510, which has a higher transistor placement density than circuit region 514.

[0059] Next, a film is provided to cover the circuit region 510 and the circuit region 514 to suppress oxygen diffusion. Here, multiple opening regions 400 are provided in the film that suppresses oxygen diffusion covering the circuit region 514. Subsequently, by performing a heat treatment, oxygen is desorbed from the insulator placed near the oxide semiconductor and supplied to the oxide semiconductor, compensating for the oxygen deficiency in the channel formation region.

[0060] In the circuit region 514, when heat treatment is performed, some of the excess oxygen detached from the insulator placed near the oxide semiconductor is released to the outside through the opening region 400. Another portion of the excess oxygen is supplied to the oxide semiconductor, compensating for oxygen deficiencies in the channel formation region. In other words, by releasing the excess oxygen added to the circuit region 514 through the opening region 400, the amount of excess oxygen detached from the insulator near the oxide semiconductor can be adjusted so as not to affect the source and drain regions.

[0061] On the other hand, in the circuit region 510, excess oxygen that is removed during the heat treatment is supplied to the oxide semiconductor without being released to the outside, thereby compensating for the oxygen deficiency in the channel formation region.

[0062] Therefore, according to the present invention, circuit region 510 and circuit region 514 can be provided on the same substrate without adding a mask.

[0063] Furthermore, by appropriately designing the aperture region 400 according to the transistor arrangement density, it is possible to provide multiple circuit regions on the same substrate.

[0064] For example, a circuit region 512 may have a transistor arrangement density lower than that of circuit region 510 and higher than that of circuit region 514. As shown in Figure 2B, circuit region 512 has fewer transistors 200 per unit area than circuit region 510, but has aperture regions 400. On the other hand, it is preferable that circuit region 512 has more transistors 200 per unit area than circuit region 514, but has a smaller area of ​​aperture regions 400. Alternatively, the ratio of the total area of ​​aperture regions 400 in circuit region 512 (the product of the area of ​​one aperture region 400 viewed from above and the number of aperture regions 400) should be smaller than the ratio of the total area of ​​aperture regions 400 in circuit region 514.

[0065] In other words, the higher the density of transistors 200 placed in each circuit region, the fewer aperture regions 400 should be placed. Alternatively, the higher the density of transistors 200 placed in each circuit region, the smaller the ratio of the total area of ​​the apertures to the area of ​​the circuit region should be. Note that the number of transistors 200 and aperture regions 400 in each circuit region are not limited to those shown in Figure 2. The number of aperture regions 400 should be adjusted as appropriate according to the density of transistors 200 in each circuit region.

[0066] Therefore, when multiple circuit regions with different transistor densities are provided on the same substrate, the excess oxygen required for the circuit region with a high transistor density can be supplied to each circuit region by adding it to an insulator placed near the oxide semiconductor, then providing a film with an opening to suppress oxygen diffusion, and performing a heat treatment.

[0067] When there are multiple circuit regions with different transistor placement densities, for example, the number of aperture regions 400 should be inversely proportional to the placement density of transistors 200. Alternatively, it is preferable that the total area of ​​aperture regions 400 be larger when the placement density of transistors 200 is small, and smaller when the placement density of transistors 200 is large.

[0068] Figure 3A is an enlarged view of the region 291 enclosed by the dashed line in Figure 2C. Figure 3B is a cross-sectional view of the region indicated by the dashed line A1-A2 in Figure 3A, and is also a cross-sectional view of the transistor 200 in the channel direction, and a cross-sectional view of the sealing portion 265. Figure 3C is a cross-sectional view of the region indicated by the dashed line A3-A4 in Figure 3A, and is also a cross-sectional view of the opening region 400, and a cross-sectional view of the sealing portion 265.

[0069] As shown in Figure 3A, the transistor 200 is positioned at a distance L1 from the end of the transistor 200 to the end of the sealing portion 265 in the A1-A2 direction, and at a distance L2 from the end of the transistor 200 to the end of the sealing portion 265 in the direction perpendicular to A1-A2. The aperture regions 400 are arranged at intervals of distance L3 in the direction perpendicular to A1-A2. Here, distance L3 is the distance between the upper parts of adjacent aperture regions in the direction perpendicular to A1-A2. The shape of the aperture region 400 in top view is not limited to the rectangle shown in Figure 3A. For example, the shape of the aperture region 400 in top view may be a square, ellipse, circle, rhombus, or a combination thereof. Distances L1 and L2 are 0.10 μm or more and 2.0 μm or less, preferably 0.15 μm or more and 1.5 μm or less. Distance L3 is 1.5 μm or more and 6.0 μm or less. Typically, we'll use 1.5 μm.

[0070] As shown in Figures 3B and 3C, the semiconductor device 500 includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a plurality of transistors 200 on the insulator 214, an insulator 280 on the transistors 200, an insulator 282 on the insulator 280, an insulator 283 on the insulator 282, a sealing portion 265 in which a part of the upper surface of the insulator 212 and the insulator 283 are in contact, and an opening region 400 in which a part of the insulator 282 is open. In the opening region 400, the insulator 280 may have a recess, and the depth of the recess of the insulator 280 is set to be 1 / 4 or more and 1 / 2 or less of the maximum film thickness of the insulator 280 in the semiconductor device 500.

[0071] Furthermore, by performing a heat treatment after the formation of the opening region 400 in the manufacturing process of the semiconductor device 500, oxygen contained in the insulator 280 and hydrogen combined with that oxygen can be released to the outside through the opening region 400. The hydrogen combined with oxygen is released as water. Therefore, the amount of unwanted oxygen and hydrogen contained in the insulator 280 can be reduced.

[0072] <Example of semiconductor device configuration> Figures 4A to 4D illustrate an example of the configuration of a semiconductor device having a transistor 200 and an aperture region 400. Figures 4A to 4D are top views and cross-sectional views of the semiconductor device having a transistor 200 and an aperture region 400. Figure 4A is a top view of the semiconductor device. Figures 4B to 4D are cross-sectional views of the semiconductor device. Here, Figure 4B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 4A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Figure 4C is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 4A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Figure 4D is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure 4A, and is also a cross-sectional view of the aperture region 400. Note that some elements have been omitted from the top view of Figure 4A for clarity.

[0073] A semiconductor device according to one aspect of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 (insulator 282a and insulator 282b) on the insulator 280, an insulator 283 on the insulator 282, an insulator 286 on the insulator 283, and an insulator 274 on the sealing portion 265. The insulator 283 is in contact with the side surface of the insulator 282, the side surface of the insulator 280, the side surface of the transistor 200, the side surface of the insulator 214, and a part of the upper surface of the insulator 212. The insulators 212, 214, 280, 282, 283, 286, and 274 function as interlayer films. Furthermore, it has a conductor 240 (conductor 240a and conductor 240b) that is electrically connected to the transistor 200 and functions as a plug. An insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surface of the conductor 240 that functions as a plug. In addition, a conductor 246 (conductor 246a and conductor 246b) that is electrically connected to the conductor 240 and functions as wiring is provided on the insulator 286 and on the conductor 240.

[0074] Insulator 241a is provided in contact with the inner wall of the opening of insulators 280, 282, 283, and 286, a first conductor of conductor 240a is provided in contact with the side surface of insulator 241a, and a second conductor of conductor 240a is provided further inside. Insulator 241b is provided in contact with the inner wall of the opening of insulators 280, 282, 283, and 286, a first conductor of conductor 240b is provided in contact with the side surface of insulator 241b, and a second conductor of conductor 240b is provided further inside. Here, the height of the upper surface of conductor 240 and the height of the upper surface of insulator 286 in the region overlapping with conductor 246 can be made to be approximately the same. Note that in transistor 200, a configuration in which the first conductor and the second conductor of conductor 240 are stacked is shown, but the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or as a laminated structure of three or more layers. When the structure has a laminated structure, an ordinal number may be assigned to distinguish it according to the order of formation.

[0075] [Transistor 200] As shown in Figures 4A to 4C, the transistor 200 comprises an insulator 216 on an insulator 214, a conductor 205 (conductors 205a, 205b, and 205c) arranged to be embedded in the insulator 214 or insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an oxide 243 (oxides 243a and 243b) on the oxide 230b, a conductor 242a on the oxide 243a, and an oxide 242a on the conductor 242a. The device includes a rim 271a, a conductor 242b on the oxide 243b, an insulator 271b on the conductor 242b, an insulator 250a on the oxide 230b, an insulator 250b on the insulator 250a, a conductor 260 (conductors 260a and 260b) located on the insulator 250b and overlapping with a portion of the oxide 230b, and an insulator 272 arranged to cover the insulator 224, oxide 230 (oxides 230a and 230b), oxide 243, conductor 242 (conductors 242a and 242b), and insulator 271 (insulators 271a and 271b). Here, as shown in Figures 4B to 4D, the insulator 272 has a region that is in contact with a portion of the upper surface of the insulator 222. Furthermore, the upper surface of the conductor 260 is positioned to substantially coincide with the upper surfaces of the insulator 250 and the insulator 280. In addition, the insulator 282 is in contact with the upper surfaces of the conductor 260, the insulator 250, and the insulator 280, respectively.

[0076] In the following, oxides 230a and 230b may be collectively referred to as oxide 230. Also, insulators 250a and 250b may be collectively referred to as insulator 250. Furthermore, insulators 271a and 271b may be collectively referred to as insulator 271.

[0077] Insulators 280 and 272 are provided with openings that reach oxide 230b. Insulator 250 and conductor 260 are arranged within these openings. Furthermore, in the channel length direction of transistor 200, conductor 260 and insulator 250 are provided between insulator 271a, conductor 242a and oxide 243a and insulator 271b, conductor 242b and oxide 243b. Insulator 250 has a region in contact with the side surface of conductor 260 and a region in contact with the bottom surface of conductor 260.

[0078] Preferably, the oxide 230 has an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on top of the oxide 230a. By having oxide 230a below oxide 230b, the diffusion of impurities from structures formed below oxide 230a to oxide 230b can be suppressed.

[0079] In the transistor 200, the oxide 230 is shown as having a configuration in which two layers of oxide 230a and oxide 230b are stacked, but the present invention is not limited to this. For example, a single layer of oxide 230b or a stacked structure of three or more layers may be provided, or oxide 230a and oxide 230b may each have a stacked structure.

[0080] Conductor 260 functions as the first gate (also called the top gate) electrode, and conductor 205 functions as the second gate (also called the back gate) electrode. Insulator 250 functions as the first gate insulator, and insulators 222 and 224 function as the second gate insulators. Conductor 242a functions as either the source or the drain, and conductor 242b functions as either the source or the drain. At least a portion of the region of oxide 230 that overlaps with conductor 260 functions as a channel-forming region.

[0081] Here, FIG. 5 shows an enlarged view of the vicinity of the channel formation region in FIG. 4B. As shown in FIG. 5, the oxide 230b has a region 230bc that functions as a channel formation region of the transistor 200, and regions 230ba and 230bb that are provided so as to sandwich the region 230bc and function as a source region or a drain region. At least a part of the region 230bc overlaps with the conductor 260. In other words, the region 230bc is provided in the region between the conductor 242a and the conductor 242b. The region 230ba is provided so as to overlap with the conductor 242a, and the region 230bb is provided so as to overlap with the conductor 242b.

[0082] The region 230bc that functions as a channel formation region is a high-resistance region with a low carrier concentration because it has less oxygen deficiency or a lower impurity concentration than the regions 230ba and 230bb. Also, the regions 230ba and 230bb that function as a source region or a drain region are regions with an increased carrier concentration and a lower resistance due to a large amount of oxygen deficiency or a high impurity concentration such as hydrogen, nitrogen, or a metal element. That is, the regions 230ba and 230bb are regions with a high carrier concentration and a low resistance compared to the region 230bc.

[0083] Here, the carrier concentration of the region 230bc that functions as a channel formation region is preferably 18 cm -3 or less, more preferably less than 17 cm -3 even more preferably less than 16 cm -3 even more preferably less than 13 cm -3 even more preferably less than 12 cm -3 even more preferably less than. Note that the lower limit value of the carrier concentration of the region 230bc that functions as a channel formation region is not particularly limited, but for example, it can be -9 cm -3

[0084] ​ Furthermore, a region may be formed between region 230bc and region 230ba or region 230bb, where the carrier concentration is equal to or lower than that of regions 230ba and 230bb, and equal to or higher than that of region 230bc. In other words, this region functions as a junction region between region 230bc and region 230ba or region 230bb. The hydrogen concentration in this junction region may be equal to or lower than that of regions 230ba and 230bb, and equal to or higher than that of region 230bc. Also, the oxygen deficiency in this junction region may be equal to or less than that of regions 230ba and 230bb, and equal to or greater than that of region 230bc.

[0085] Although Figure 5 shows an example in which regions 230ba, 230bb, and 230bc are formed in oxide 230b, the present invention is not limited to this. For example, each of the above regions may be formed not only in oxide 230b but also in oxide 230a.

[0086] Furthermore, in oxide 230, it can be difficult to clearly detect the boundaries between each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region may not be limited to stepwise changes between regions, but may also change continuously within each region. In other words, the closer a region is to the channel-forming region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen should be.

[0087] In transistor 200, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for the oxide 230 (oxide 230a and oxide 230b) which includes the channel formation region.

[0088] Furthermore, it is preferable to use a metal oxide that functions as a semiconductor and has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0089] As oxide 230, for example, a metal oxide such as In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 230.

[0090] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a.

[0091] In this way, by placing oxide 230a below oxide 230b, the diffusion of impurities and oxygen from structures formed below oxide 230a to oxide 230b can be suppressed.

[0092] Furthermore, because oxides 230a and 230b share a common element other than oxygen (as a main component), the defect level density at the interface between oxide 230a and oxide 230b can be reduced. Because the defect level density at the interface between oxide 230a and oxide 230b can be reduced, the influence of interfacial scattering on carrier conduction is small, resulting in a high on-current.

[0093] It is preferable that oxide 230b is crystalline. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as oxide 230b.

[0094] CAAC-OS has a highly crystalline, dense structure, and is free from impurities and defects (e.g., oxygen vacancies (V)). O CAAC-OS is a metal oxide with low oxygen vacancy (also known as oxygen vacancy). In particular, by heat-treating the CAAC-OS after its formation at a temperature that does not cause polycrystallization of the metal oxide (for example, between 400°C and 600°C), a more crystalline and dense structure can be achieved. By increasing the density of CAAC-OS in this way, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0095] On the other hand, because it is difficult to identify clear grain boundaries in CAAC-OS, the decrease in electron mobility caused by grain boundaries is less likely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. As a result, metal oxides containing CAAC-OS are heat resistant and highly reliable.

[0096] In transistors using oxide semiconductors, the electrical properties tend to fluctuate and reliability may be poor if impurities and oxygen vacancies are present in the region where the channel is formed in the oxide semiconductor. Furthermore, hydrogen near the oxygen vacancy can fill the oxygen vacancy, creating a defect (hereinafter referred to as V). O Sometimes called H, it forms a channel and generates electrons that become carriers. For this reason, if the region where the channel is formed in the oxide semiconductor contains oxygen vacancies, the transistor is likely to exhibit normally-on characteristics (a characteristic in which the channel exists and current flows through the transistor even without applying voltage to the gate electrode). Therefore, in the region where the channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V are likely to be present. O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where the channel is formed has a reduced carrier concentration and is type i (intrinsed) or substantially type i.

[0097] In contrast, by placing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, eliminating oxygen deficiencies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the on-current of transistor 200 or a decrease in the field-effect mobility. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface will result in variations in the characteristics of the semiconductor device containing the transistor.

[0098] Therefore, in an oxide semiconductor, the region 230bc, which functions as a channel-forming region, preferably has a reduced carrier concentration and is i-type or substantially i-type, while the regions 230ba and 230bb, which function as a source region or drain region, preferably have a high carrier concentration and are n-type. In other words, oxygen vacancies in region 230bc of the oxide semiconductor, and V O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to regions 230ba and 230bb.

[0099] Therefore, in this embodiment, with the conductor 242a and conductor 242b placed on the oxide 230b, microwave treatment is performed in an oxygen-containing atmosphere to eliminate oxygen deficiencies in region 230bc, and V O The aim is to reduce H. Here, microwave processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example.

[0100] By performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be converted into plasma using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied. At this time, microwaves or high-frequency waves such as RF can also be irradiated into region 230bc. Due to the action of plasma, microwaves, etc., the V of region 230bc O By cleaving H, hydrogen H is removed from region 230bc, and oxygen is lost V. OIt can be supplemented with oxygen. In other words, in region 230bc, "V O H → H + V O The following reaction occurs, which reduces the hydrogen concentration in region 230bc. Therefore, the oxygen deficiency in region 230bc, and V O This can reduce H and lower the carrier concentration.

[0101] Furthermore, when performing microwave processing in an oxygen-containing atmosphere, the effects of microwaves, high frequencies such as RF, and oxygen plasma are shielded by conductors 242a and 242b and do not reach regions 230ba and 230bb. In addition, the effect of oxygen plasma can be reduced by insulators 271a, 271b, and 280, which are provided covering oxide 230b and conductor 242. As a result, during microwave processing, the effects of V are reduced in regions 230ba and 230bb. O This prevents a decrease in H and avoids excessive oxygen supply, thus preventing a drop in carrier concentration.

[0102] In particular, the above-mentioned effect is greatly enhanced when microwave treatment is performed in an oxygen-containing atmosphere after deposition of the insulating film that will become insulator 250b. Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after deposition of the insulating film that will become insulator 250a, and then perform microwave treatment in an oxygen-containing atmosphere after deposition of the insulating film that will become insulator 250b. By performing microwave treatment in an oxygen-containing atmosphere via insulator 250a or insulator 250b in this way, oxygen can be efficiently injected into region 230bc. The oxygen injected into region 230bc can take various forms, such as oxygen atoms, oxygen molecules, oxygen radicals (atoms or molecules with unpaired electrons, or ions). Note that the oxygen injected into region 230bc can be one or more of the above forms, and oxygen radicals are particularly preferred. In addition, the film quality of insulators 250a and 250b can be improved, thereby improving the reliability of transistor 200.

[0103] In this way, oxygen vacancies are selectively created in the oxide semiconductor region 230bc, and V O By removing H, region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to regions 230ba and 230bb, which function as source or drain regions, can be suppressed, thereby maintaining the n-type configuration. This suppresses variations in the electrical properties of transistor 200 and prevents variations in the electrical properties of transistor 200 within the substrate plane.

[0104] By adopting the above configuration, it is possible to provide a semiconductor device with minimal variation in transistor characteristics. Furthermore, it is possible to provide a semiconductor device with good reliability and excellent electrical characteristics.

[0105] In Figure 4 and other figures, the side surface of the opening into which the conductor 260 is embedded, including the groove portion of the oxide 230b, is generally perpendicular to the surface of the oxide 230b being formed. However, this embodiment is not limited to this. For example, the bottom of the opening may have a gently curved surface, resulting in a U-shape. Alternatively, for example, the side surface of the opening may be inclined with respect to the surface of the oxide 230b being formed.

[0106] Furthermore, as shown in Figure 4C, in a cross-sectional view of the transistor 200 in the channel width direction, there may be a curved surface between the side surface and the top surface of the oxide 230b. In other words, the ends of the side surface and the ends of the top surface may be curved (hereinafter also referred to as rounded).

[0107] The radius of curvature of the curved surface is preferably greater than 0 nm and less than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm to 15 nm, and more preferably 2 nm to 10 nm. By adopting such a shape, the coverage of the oxide 230b by the insulator 250 and the conductor 260 can be improved.

[0108] It is preferable that oxide 230 has a layered structure of multiple oxide layers with different chemical compositions. Specifically, it is preferable that the atomic ratio of element M to the main metal element in the metal oxide used in oxide 230a is greater than the atomic ratio of element M to the main metal element in the metal oxide used in oxide 230b. Furthermore, it is preferable that the atomic ratio of element M to In in the metal oxide used in oxide 230a is greater than the atomic ratio of element M to In in the metal oxide used in oxide 230b. Furthermore, it is preferable that the atomic ratio of In to element M in the metal oxide used in oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used in oxide 230a.

[0109] Furthermore, it is preferable that the oxide 230b is a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), and possess a dense structure with high crystallinity. Therefore, the extraction of oxygen from the oxide 230b by the source electrode or drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0110] Here, at the junction of oxide 230a and oxide 230b, the lower end of the conduction band changes smoothly. In other words, the lower end of the conduction band at the junction of oxide 230a and oxide 230b can be said to change continuously or be a continuous junction. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 230a and oxide 230b.

[0111] Specifically, by having oxides 230a and 230b share a common element other than oxygen as a main component, a mixed layer with a low defect level density can be formed. For example, if oxide 230b is In-M-Zn oxide, oxide 230a may be In-M-Zn oxide, M-Zn oxide, an oxide of element M, In-Zn oxide, indium oxide, etc.

[0112] Specifically, for oxide 230a, a metal oxide with a composition of In:M:Zn = 1:3:4 [atomic ratio] or close to it, or In:M:Zn = 1:1:0.5 [atomic ratio] or close to it, may be used. For oxide 230b, a metal oxide with a composition of In:M:Zn = 1:1:1 [atomic ratio] or close to it, or In:M:Zn = 4:2:3 [atomic ratio] or close to it, or In:M:Zn = 5:1:3 [atomic ratio] or close to it, may be used. Note that "close to it" includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use gallium as element M.

[0113] Furthermore, when depositing metal oxide films by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide film, but may also be the atomic ratio of the sputtering target used for depositing the metal oxide film.

[0114] By configuring oxides 230a and 230b as described above, the defect level density at the interface between oxide 230a and oxide 230b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 200 can obtain a large on-current and high frequency characteristics.

[0115] It is preferable that at least one of insulators 212, 214, 271, 272, 282, and 283 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, it is preferable that at least one of insulators 212, 214, 271, 272, 282, and 283 is an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., the above impurities do not easily permeate through it). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one such as oxygen atoms or oxygen molecules) (i.e., the above oxygen does not easily permeate through it).

[0116] In this specification, a barrier insulating film refers to an insulating film that has barrier properties. In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (also called low permeability), or the function of capturing and fixing the corresponding substance (also called gettering).

[0117] It is preferable to use insulators 212, 214, 271, 272, 282, and 283 that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride, which has higher hydrogen barrier properties, as insulators 212 and 283. Also, for example, it is preferable to use aluminum oxide or magnesium oxide, which have high hydrogen capture and hydrogen fixation functions, as insulators 214, 271, 272, and 282. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side via insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film located outside of insulator 283 to the transistor 200 side. Alternatively, the diffusion of oxygen contained in insulator 224, etc., to the substrate side via insulator 212 and insulator 214 can be suppressed. Alternatively, the diffusion of oxygen contained in insulator 280, etc., upward from the transistor 200 via insulator 282, etc. can be suppressed. Thus, it is preferable to have a structure in which the transistor 200 is surrounded by insulators 212, 214, 271, 272, 282, and 283, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0118] Here, it is preferable to use oxides having an amorphous structure as insulators 212, 214, 271, 272, 282, and 283. For example, AlO x (x is any number greater than 0), or MgO yIt is preferable to use a metal oxide such as (y is any number greater than 0). In such an amorphous metal oxide, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. By using such an amorphous metal oxide as a component of the transistor 200, or by providing it around the transistor 200, hydrogen contained in the transistor 200, or hydrogen present around the transistor 200, can be captured or fixed. It is particularly preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using an amorphous metal oxide as a component of the transistor 200, or by providing it around the transistor 200, it is possible to manufacture a transistor 200 and a semiconductor device that have good characteristics and are highly reliable.

[0119] Furthermore, while insulators 212, 214, 271, 272, 282, and 283 are preferably amorphous, they may also have regions of polycrystalline structure. In addition, insulators 212, 214, 271, 272, 282, and 283 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, a stacked structure in which a polycrystalline layer is formed on top of an amorphous layer is also possible.

[0120] Furthermore, the insulator 272 may have a laminated structure. For example, the insulator 272 may have a laminated structure of aluminum oxide and silicon nitride formed on the aluminum oxide. Such a laminated structure is preferable because it can improve barrier properties compared to a single layer of aluminum oxide or a single layer of silicon nitride.

[0121] The insulators 212, 214, 216, 271, 272, 280, 282, 283, and 286 may be deposited using, for example, a sputtering method. Since sputtering does not require the use of hydrogen as a deposition gas, the hydrogen concentration of insulators 212, 214, 216, 271, 272, 280, 282, 283, and 286 can be reduced. The deposition method is not limited to sputtering, and chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), etc., may be used as appropriate.

[0122] Furthermore, it may be preferable to lower the resistivity of insulators 212 and 283. For example, the resistivity of insulators 212 and 283 may be approximately 1 × 10⁻⁶. 13 By setting the resistivity to Ωcm, insulators 212 and 283 may be able to mitigate charge-up of conductors 205, 242, 260, or 246 during plasma-based processing in semiconductor device manufacturing processes. The resistivity of insulators 212 and 283 is preferably 1 × 10⁻⁶. 10 Ωcm or more, 1 × 10 15 The density should be less than or equal to Ωcm.

[0123] Furthermore, it is preferable that insulators 216, 274, 280, and 286 have a lower dielectric constant than insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide may be used as insulators 216, 274, 280, and 286 as appropriate.

[0124] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Here, it is preferable that the conductor 205 is embedded in an opening formed in the insulator 216.

[0125] The conductor 205 comprises conductor 205a, conductor 205b, and conductor 205c. Conductor 205a is provided in contact with the bottom surface and side wall of the opening. Conductor 205b is provided so as to be embedded in a recess formed in conductor 205a. Here, the upper surface of conductor 205b is lower than the upper surface of conductor 205a and the upper surface of insulator 216. Conductor 205c is provided in contact with the upper surface of conductor 205b and the side surface of conductor 205a. Here, the height of the upper surface of conductor 205c is approximately equal to the height of the upper surface of conductor 205a and the upper surface of insulator 216. In other words, conductor 205b is enclosed by conductors 205a and conductor 205c.

[0126] Here, it is preferable to use conductive materials for conductors 205a and 205c that have the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use conductive materials that have the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0127] By using conductive materials that have the function of reducing hydrogen diffusion for conductors 205a and 205c, it is possible to prevent impurities such as hydrogen contained in conductor 205b from diffusing into oxide 230 via insulator 224, etc. Furthermore, by using conductive materials that have the function of suppressing oxygen diffusion for conductors 205a and 205c, it is possible to suppress oxidation of conductor 205b and a decrease in conductivity. As conductive materials that have the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. Therefore, conductor 205a may be made of the above conductive material in a single layer or laminate. For example, titanium nitride may be used for conductor 205a.

[0128] Furthermore, it is preferable to use a conductive material whose main component is tungsten, copper, or aluminum for the conductor 205b. For example, tungsten may be used for the conductor 205b.

[0129] Conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 200 can be controlled by changing the potential applied to conductor 205 independently of the potential applied to conductor 260, without linking it to the potential applied to conductor 260. In particular, by applying a negative potential to conductor 205, it is possible to increase the Vth of transistor 200 and reduce the off-current. Therefore, applying a negative potential to conductor 205 reduces the drain current when the potential applied to conductor 260 is 0V compared to not applying a negative potential.

[0130] Furthermore, the electrical resistivity of the conductor 205 is designed considering the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 as thin as possible within the limits permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of these impurities into the oxide 230.

[0131] Furthermore, as shown in Figure 4A, the conductor 205 should be provided in a size larger than the area that does not overlap with the conductors 242a and 242b of the oxide 230. In particular, as shown in Figure 4C, it is preferable that the conductor 205 extends to the area outside the ends of the oxide 230a and oxide 230b in the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 are superimposed on the outside of the side surface of the oxide 230 in the channel width direction, with an insulator in between. With this configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 which functions as the first gate electrode and the electric field of the conductor 205 which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0132] In this specification, an S-channel transistor refers to a transistor structure in which the channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. Furthermore, the S-channel structure disclosed in this specification is different from the Fin-type structure and the Planar-type structure. By adopting an S-channel structure, it is possible to create a transistor that has improved resistance to short-channel effects, or in other words, a transistor in which short-channel effects are less likely to occur.

[0133] Furthermore, as shown in Figure 4C, the conductor 205 is extended to function as wiring. However, the configuration is not limited to this, and a conductor that functions as wiring may be provided beneath the conductor 205. Also, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0134] In the transistor 200, the conductor 205 is shown as a stacked structure of conductors 205a, 205b, and 205c, but the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer, two layers, or a stacked structure of four or more layers.

[0135] Insulators 222 and 224 function as gate insulators.

[0136] Preferably, the insulator 222 has the function of suppressing the diffusion of hydrogen (for example, at least one such as a hydrogen atom or a hydrogen molecule). Furthermore, preferably, the insulator 222 has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or an oxygen molecule). For example, it is preferable that the insulator 222 has the function of suppressing the diffusion of one or both hydrogen and oxygen more effectively than the insulator 224.

[0137] The insulator 222 may be an insulator containing an oxide of either or both of the insulating materials aluminum and hafnium. Preferably, the insulator is an oxide containing aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and to suppress the generation of oxygen vacancies in the oxide 230. In addition, it is possible to suppress the reaction of the conductor 205 with the oxygen contained in the insulator 224 and the oxide 230.

[0138] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above-mentioned insulator. Alternatively, these insulators may be subjected to nitriding treatment. Furthermore, insulator 222 may be used by laminating silicon oxide, silicon oxide nitride, or silicon nitride onto these insulators.

[0139] Furthermore, the insulator 222 may be a single-layer or multi-layer insulator containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0140] The insulator 224 in contact with the oxide 230 can be, for example, silicon oxide, silicon oxide nitride, or the like, as appropriate.

[0141] Furthermore, during the manufacturing process of the transistor 200, it is preferable to perform a heat treatment while the surface of the oxide 230 is exposed. This heat treatment may be performed at, for example, 100°C to 600°C, more preferably 350°C to 550°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 230, thereby preventing oxygen deficiency (V O This can reduce the amount of oxygen released. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then continuously in an atmosphere of nitrogen gas or an inert gas.

[0142] Furthermore, by performing an oxygenation treatment on oxide 230, oxygen deficiencies in oxide 230 are repaired by the supplied oxygen, or in other words, "V O This can accelerate the reaction "+O→null". Furthermore, the oxygen supplied reacts with the hydrogen remaining in oxide 230, removing the hydrogen as H2O (dehydration). As a result, the hydrogen remaining in oxide 230 recombines with the oxygen vacancy and V O This can suppress the formation of H.

[0143] Furthermore, the insulators 222 and 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, but may be made of different materials. Also, the insulator 224 may be formed in an island-like manner by being superimposed with the oxide 230a. In this case, the insulator 272 will be in contact with the side surface of the insulator 224 and the upper surface of the insulator 222.

[0144] Oxide 243a and oxide 243b are provided on oxide 230b. Oxide 243a and oxide 243b are provided separated by the conductor 260.

[0145] It is preferable that the oxide 243 (oxide 243a and oxide 243b) has the function of suppressing oxygen permeation. Placing oxide 243, which has the function of suppressing oxygen permeation, between the conductor 242, which functions as a source electrode or drain electrode, and oxide 230b is preferable because it reduces the electrical resistance between the conductor 242 and oxide 230b. With such a configuration, the electrical characteristics and reliability of the transistor 200 can be improved. However, if the electrical resistance between the conductor 242 and oxide 230b can be sufficiently reduced, a configuration without oxide 243 may be used.

[0146] As oxide 243, a metal oxide containing element M may be used. In particular, element M may be aluminum, gallium, yttrium, or tin. It is preferable that oxide 243 has a higher concentration of element M than oxide 230b. Gallium oxide may also be used as oxide 243. Furthermore, metal oxides such as In-M-Zn oxide may be used as oxide 243. Specifically, in the metal oxide used for oxide 243, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. The film thickness of oxide 243 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. It is also preferable that oxide 243 is crystalline. When oxide 243 is crystalline, the release of oxygen from oxide 230 can be suitably suppressed. For example, if oxide 243 has a crystalline structure such as hexagonal, the release of oxygen from oxide 230 can be suppressed.

[0147] It is preferable that the conductor 242a is provided in contact with the upper surface of the oxide 243a, and the conductor 242b is provided in contact with the upper surface of the oxide 243b. Conductors 242a and 242b function as the source electrode or drain electrode of the transistor 200, respectively.

[0148] As the conductor 242 (conductor 242a and conductor 242b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0149] Furthermore, hydrogen contained in oxide 230b, etc., may diffuse into conductor 242a or conductor 242b. In particular, by using tantalum-containing nitrides for conductor 242a and conductor 242b, hydrogen contained in oxide 230b, etc., is more likely to diffuse into conductor 242a or conductor 242b, and the diffused hydrogen may combine with nitrogen present in conductor 242a or conductor 242b. In other words, hydrogen contained in oxide 230b, etc., may be absorbed by conductor 242a or conductor 242b.

[0150] Furthermore, it is preferable that no curved surface is formed between the side surface of the conductor 242 and the top surface of the conductor 242. By using a conductor 242 without such a curved surface, the cross-sectional area of ​​the conductor 242 in the channel width direction can be increased. This increases the conductivity of the conductor 242 and increases the on-current of the transistor 200.

[0151] The insulator 271a is provided in contact with the upper surface of the conductor 242a, and the insulator 271b is provided in contact with the upper surface of the conductor 242b. Preferably, the upper surface of insulator 271a is in contact with insulator 272, and the side surface of insulator 271a is in contact with insulator 250. Preferably, the upper surface of insulator 271b is in contact with insulator 272, and the side surface of insulator 271b is in contact with insulator 250. The insulator 271 preferably functions as a barrier insulating film against oxygen. Therefore, it is preferable that the insulator 271 has a function to suppress the diffusion of oxygen. For example, it is preferable that the insulator 271 has a function to suppress the diffusion of oxygen more than the insulator 280. As the insulator 271, for example, a silicon-containing nitride such as silicon nitride may be used. It is also preferable that the insulator 271 has a function to capture impurities such as hydrogen. In that case, the insulator 271 can be an amorphous metal oxide, such as aluminum oxide or magnesium oxide. In particular, using amorphous aluminum oxide or aluminum oxide as the insulator 271 is preferable because it can more effectively capture or fix hydrogen. This makes it possible to fabricate a transistor 200 and semiconductor device with good properties and high reliability.

[0152] The insulator 272 is provided so as to cover the insulator 224, oxide 230a, oxide 230b, oxide 243, conductor 242, and insulator 271. Preferably, the insulator 272 has the function of capturing and fixing hydrogen. In that case, it is preferable that the insulator 272 includes an insulator such as an amorphous metal oxide, for example, aluminum oxide or magnesium oxide.

[0153] By providing the insulators 271 and 272 described above, the conductor 242 can be surrounded by an insulator that has barrier properties against oxygen. In other words, the oxygen contained in the insulators 224 and 280 can be prevented from diffusing into the conductor 242. This prevents the conductor 242 from being directly oxidized by the oxygen contained in the insulators 224 and 280, which would increase its resistivity and reduce the on-current.

[0154] The insulator 250 functions as a gate insulator. It is preferable that the insulator 250 be placed in contact with the upper surface of the oxide 230b. The insulator 250 can be silicon oxide, silicon oxynitride, silicon oxide nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide. In particular, silicon oxide and silicon oxynitride are preferred because they are stable with respect to heat.

[0155] Similar to the insulator 224, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. The film thickness of the insulator 250 is preferably between 1 nm and 20 nm.

[0156] Furthermore, as shown in Figures 4B and 4C, when the insulator 250 has a two-layer laminated structure, it is preferable that the lower insulator 250a is formed using an insulator that is permeable to oxygen, and the upper insulator 250b is formed using an insulator that has the function of suppressing the diffusion of oxygen. With this configuration, it is possible to suppress the diffusion of oxygen contained in the insulator 250a to the conductor 260. In other words, it is possible to suppress the reduction in the amount of oxygen supplied to the oxide 230. In addition, it is possible to suppress the oxidation of the conductor 260 by the oxygen contained in the insulator 250a. For example, the insulator 250a may be made using a material that can be used for the insulator 250 described above, and the insulator 250b may be an insulator containing an oxide of aluminum and / or hafnium. It is preferable to use aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) as the insulator. Furthermore, the film thickness of the insulator 250b is 0.5 nm or more and 3.0 nm or less, preferably 1.0 nm or more and 1.5 nm or less.

[0157] Furthermore, when silicon oxide or silicon oxynitride is used as the lower layer of insulator 250, the upper layer of insulator 250 may be made of an insulating material that is a high-k material with a high dielectric constant. By making the gate insulator a laminated structure of insulator 250a and insulator 250b, a laminated structure that is stable against heat and has a high dielectric constant can be made. Therefore, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator.

[0158] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. It is preferable that the metal oxide suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 by oxygen from the insulator 250 can be suppressed.

[0159] Furthermore, the above-mentioned metal oxide may be configured to function as part of the first gate electrode. For example, a metal oxide that can be used as oxide 230 can be used as the above-mentioned metal oxide. In that case, the electrical resistance of the above-mentioned metal oxide can be reduced by depositing the conductor 260a by sputtering, thereby making it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0160] By having the above-mentioned metal oxide, the on-current of the transistor 200 can be improved without weakening the influence of the electric field from the conductor 260. Furthermore, by maintaining the distance between the conductor 260 and the oxide 230 through the physical thickness of the insulator 250 and the above-mentioned metal oxide, leakage current between the conductor 260 and the oxide 230 can be suppressed. In addition, by providing a laminated structure of the insulator 250 and the above-mentioned metal oxide, the physical distance between the conductor 260 and the oxide 230, and the electric field strength applied from the conductor 260 to the oxide 230 can be easily and appropriately adjusted.

[0161] The conductor 260 functions as the first gate electrode of the transistor 200. Preferably, the conductor 260 has a conductor 260a and a conductor 260b disposed on top of the conductor 260a. For example, it is preferable that the conductor 260a is arranged to enclose the bottom and sides of the conductor 260b. Also, as shown in Figures 4B and 4C, the top surface of the conductor 260 is substantially the same as the top surface of the insulator 250. In Figures 4B and 4C, the conductor 260 is shown as a two-layer structure of conductor 260a and conductor 260b, but it may also be a single-layer structure or a stacked structure of three or more layers.

[0162] It is preferable to use a conductive material for the conductor 260a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0163] Furthermore, because the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 260b by the oxygen contained in the insulator 250, which would otherwise reduce its conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0164] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0165] Furthermore, in transistor 200, the conductor 260 is formed self-aligningly to fill the openings formed in the insulator 280 and the like. By forming the conductor 260 in this way, the conductor 260 can be reliably positioned in the region between the conductors 242a and 242b without the need for alignment.

[0166] Furthermore, as shown in Figure 4C, in the channel width direction of transistor 200, with reference to the bottom surface of insulator 222, the height of the bottom surface of the conductor 260 in the region where conductor 260 and oxide 230b do not overlap is preferably lower than the height of the bottom surface of oxide 230b. By configuring conductor 260, which functions as a gate electrode, to cover the side and top surfaces of the channel formation region of oxide 230b via insulator 250 or the like, the electric field of conductor 260 can be more easily applied to the entire channel formation region of oxide 230b. Therefore, the on-current of transistor 200 can be increased and the frequency characteristics can be improved. With reference to the bottom surface of insulator 222, the difference between the height of the bottom surface of conductor 260 in the region where oxide 230a and oxide 230b and conductor 260 do not overlap and the height of the bottom surface of oxide 230b is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0167] [Aperture area 400] The opening region 400 is formed by opening the insulator 282 during the manufacturing process of the semiconductor device. At this time, a recess may be formed in the insulator 280. By performing a heat treatment after the formation of the opening region 400, oxygen contained in the insulator 280 and hydrogen combined with that oxygen can be released to the outside through the opening region 400. The hydrogen combined with oxygen is released as water. Therefore, the amount of unwanted oxygen and hydrogen contained in the insulator 280 can be reduced. Furthermore, the insulator 283 on the insulator 282 is provided so as to be in contact with the insulator 280 within the opening region 400, and an insulator 274 is embedded on the insulator 283 within the opening region 400. The depth of the recess in the insulator 280 is set to be between 1 / 4 and 1 / 2 of the maximum film thickness of the insulator 280 in the semiconductor device.

[0168] The insulator 280 is provided on the insulator 272, and openings are formed in the regions where the insulator 250 and the conductor 260 are provided. The upper surface of the insulator 280 may also be flattened.

[0169] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between the wiring can be reduced. The insulator 280 is preferably made of the same material as the insulator 216, for example. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0170] Preferably, the insulator 280 has a reduced concentration of impurities such as water and hydrogen. For example, the insulator 280 may be made of silicon oxide such as silicon oxide or silicon oxynitride.

[0171] The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above, and preferably has the function of capturing impurities such as hydrogen. Furthermore, it is preferable that the insulator 282 functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 282, an amorphous metal oxide, such as aluminum oxide, may be used. By providing an insulator 282 that is in contact with the insulator 280 in the region sandwiched between the insulator 212 and the insulator 283 and has the function of capturing impurities such as hydrogen, impurities such as hydrogen contained in the insulator 280 can be captured, and the amount of hydrogen in that region can be kept constant. In particular, it is preferable to use an amorphous aluminum oxide, or an amorphous aluminum oxide, as the insulator 282, as this may allow for more effective capture or fixation of hydrogen. This makes it possible to manufacture a transistor 200 and a semiconductor device with good characteristics and high reliability.

[0172] The insulator 283 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above. The insulator 283 is placed on top of the insulator 282. Preferably, the insulator 283 is a silicon-containing nitride such as silicon nitride or silicon nitride oxide. For example, silicon nitride deposited by sputtering may be used as the insulator 283. By depositing the insulator 283 by sputtering, a silicon nitride film with high density and less susceptibility to porosity can be formed. Alternatively, as the insulator 283, silicon nitride deposited by ALD may be further laminated on top of the silicon nitride deposited by sputtering. This structure is preferable because even if defects, such as voids, occur in the silicon nitride deposited by sputtering, these voids can be filled by the silicon nitride deposited by the ALD method, which has good coverage, thereby improving sealing performance.

[0173] The insulator 286 is provided on the insulator 283 and on the insulator 274.

[0174] It is preferable that the conductors 240a and 240b are made of conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, the conductors 240a and 240b may be arranged in a laminated structure.

[0175] Furthermore, when the conductor 240 has a laminated structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the conductors that are in contact with the insulators 286, 283, 282, 280, 272, and 271. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Also, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminate. In addition, it is possible to suppress the mixing of impurities such as water and hydrogen contained in the layer above insulator 283 into the oxide 230 through conductors 240a and 240b.

[0176] For insulators 241a and 241b, for example, insulators such as silicon nitride, aluminum oxide, and silicon oxide nitride may be used. Since insulators 241a and 241b are provided in contact with insulators 286, 283, 282, 280, 272, and 271, it is possible to suppress the mixing of impurities such as water and hydrogen contained in insulator 280, etc., into the oxide 230 through conductors 240a and 240b. Silicon nitride is particularly suitable because it has high blocking properties for hydrogen. In addition, it is possible to prevent oxygen contained in insulator 280 from being absorbed by conductors 240a and 240b.

[0177] Furthermore, conductors 246 (conductors 246a and 246b) that function as wiring may be placed in contact with the upper surfaces of conductors 240a and 240b. It is preferable that the conductors 246 be made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductors may also be in a laminated structure, for example, a laminate of titanium or titanium nitride and the conductive material. The conductors may also be formed to be embedded in openings provided in the insulator.

[0178] <Component materials for semiconductor devices> The following describes the constituent materials that can be used in semiconductor devices.

[0179] <<Substrate>> As the substrate for forming transistor 200, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0180] <<Insulator>> Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0181] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0182] Furthermore, examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0183] Insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with voids, or resins.

[0184] Furthermore, the electrical properties of transistors using metal oxides can be stabilized by surrounding them with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxide nitride, and silicon nitride can be used.

[0185] Furthermore, the insulator that functions as a gate insulator is preferably an insulator that has a region containing oxygen that is desorbed by heating. For example, by having a silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated for.

[0186] <<Conductive material>> As the conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0187] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0188] Furthermore, when using an oxide in the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to place the conductive material containing oxygen on the channel formation region side. By placing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0189] In particular, it is preferable to use a conductive material containing metal elements and oxygen contained in the metal oxide in which the channel is formed as the conductor that functions as the gate electrode. Alternatively, conductive materials containing the aforementioned metal elements and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-doped indium tin oxide may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator or the like.

[0190] <<Metal Oxides>> It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as oxide 230. Below, metal oxides applicable to oxide 230 according to the present invention will be described.

[0191] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that it contains indium and zinc. In addition, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0192] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Element M can be aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, it is sometimes permissible to use a combination of multiple of the aforementioned elements as element M.

[0193] In this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be called metal oxynitrides.

[0194] <Classification of crystal structures> First, we will explain the classification of crystal structures in oxide semiconductors using Figure 6A. Figure 6A is a diagram illustrating the classification of crystal structures in oxide semiconductors, specifically IGZO (a metal oxide containing In, Ga, and Zn).

[0195] As shown in Figure 6A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous semiconductors. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite). Note that single crystal, polycrystal, and completely amorphous semiconductors are excluded from the "Crystalline" classification. "Crystal" includes single crystal and polycrystal semiconductors.

[0196] The structure within the thick frame shown in Figure 6A represents an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from the energetically unstable "Amorphous" and "Crystal" states.

[0197] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 6B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 6B will simply be referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 6B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 6B is 500 nm.

[0198] As shown in Figure 6B, the XRD spectrum of the CAAC-IGZO film shows a peak indicating clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating c-axis orientation near 2θ=31°. As shown in Figure 6B, the peak near 2θ=31° is asymmetrical with respect to the angle at which the peak intensity was detected.

[0199] Furthermore, the crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 6C. Figure 6C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 6C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0200] As shown in Figure 6C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0201] <<Oxide semiconductor structure>> Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 6A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0202] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0203] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0204] Each of the multiple crystalline regions described above is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of that crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers.

[0205] Furthermore, in In-M-Zn oxides (where element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Also, the In layer may contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0206] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the c-axis orientation peak (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0207] Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0208] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction, and the bond distance between atoms changes due to the substitution of metal atoms.

[0209] A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more than In oxide.

[0210] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities or the generation of defects, CAAC-OS can be considered an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0211] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0212] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a loose or low-density region; that is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS. Further, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and the CAAC-OS.

[0213] [<Composition of Oxide Semiconductor>] Next, the details of the above-described CAC-OS will be described. Note that the CAC-OS relates to the material composition.

[0214] [CAC-OS] The CAC-OS is, for example, a configuration of a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in a metal oxide, a state in which one or more metal elements are unevenly distributed and regions having the metal element are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0215] Furthermore, the CAC-OS is a configuration in which a material is separated into a first region and a second region to form a mosaic state, and the first region is distributed in the film (hereinafter also referred to as a cloud state). That is, the CAC-OS is a composite metal oxide having a configuration in which the first region and the second region are mixed.

[0216] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region.

[0217] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga.

[0218] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0219] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0220] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. on This enables high field-effect mobility (μ) and good switching operation.

[0221] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0222] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0223] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0224] It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of a transistor. For example, the carrier concentration in the channel formation region of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3It is less than 1 × 10 -9 cm -3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0225] Furthermore, oxide semiconductor films that are highly pure or substantially highly pure have a low defect level density, which may result in a low trap level density.

[0226] Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0227] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0228] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0229] In oxide semiconductors, the presence of silicon or carbon, which are Group 14 elements, leads to the formation of defect levels in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the concentrations of silicon and carbon at the interface between the insulator and the channel formation region of the oxide semiconductor, and near the interface (concentrations obtained by secondary ion mass spectrometry (SIMS)) are compared by 2 × 10⁻⁶.18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0230] Furthermore, if an oxide semiconductor contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0231] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of oxide semiconductors obtained by SIMS should be set to 5 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 19 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following:

[0232] Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. When hydrogen fills these oxygen vacancies, electrons, which act as carriers, may be generated. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to minimize the amount of hydrogen in the channel formation region of the oxide semiconductor. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 5 × 10 19 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0233] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0234] <<Other Semiconductor Materials>> The semiconductor material that can be used for oxide 230 is not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used as oxide 230. For example, it is preferable to use semiconductors of elemental elements such as silicon, compound semiconductors such as gallium arsenide, or layered materials that function as semiconductors (also called atomic layer materials, two-dimensional materials, etc.) as the semiconductor material. In particular, it is preferable to use layered materials that function as semiconductors as the semiconductor material.

[0235] Here, in this specification and the like, the layer material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layer material has high electrical conductivity within the unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0236] Examples of the layer material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens. Chalcogens are a general term for elements belonging to Group 16 and include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0237] As the oxide 230, for example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor. Specific examples of the transition metal chalcogenide applicable as the oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), and the like.

[0238] <Method for manufacturing a semiconductor device> Next, a method for manufacturing a semiconductor device, which is an aspect of the present invention shown in FIGS. 4A to 4D, will be described using FIGS. 7A to 23D.

[0239] In Figures 7A to 23D, A in each figure shows a top view. B in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in Figure A, and is also a cross-sectional view of transistor 200 in the channel length direction. C in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in Figure A, and is also a cross-sectional view of transistor 200 in the channel width direction. D in each figure is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure A, and is also a cross-sectional view of the aperture region 400. Note that in the top view of Figure A, some elements have been omitted for clarity.

[0240] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or oxide materials for forming oxides can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD as appropriate.

[0241] Sputtering methods include RF sputtering, which uses a high-frequency power supply; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. RF sputtering is mainly used for depositing insulating films, while DC sputtering is mainly used for depositing conductive metal films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0242] Furthermore, CVD methods can be classified into plasma-enhanced CVD (PECVD), which utilizes plasma; thermal CVD (TCVD), which utilizes heat; and photo-CVD (Photo-CVD), which utilizes light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD) depending on the source gas used.

[0243] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and elements (transistors, capacitive elements, etc.) contained in semiconductor devices can be charged up by receiving charge from the plasma. In this case, the accumulated charge can destroy the wiring, electrodes, and elements contained in the semiconductor device. In contrast, thermal CVD, which does not use plasma, does not cause such plasma damage, thus increasing the yield of semiconductor devices. Furthermore, because thermal CVD does not cause plasma damage during film formation, films with fewer defects can be obtained.

[0244] Furthermore, ALD methods include thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD (Plasma Enhanced ALD), which uses plasma-excited reactants.

[0245] Furthermore, the ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, resulting in advantages such as the ability to deposit extremely thin films, deposit films on structures with high aspect ratios, deposit films with fewer defects such as pinholes, deposit films with excellent coverage, and deposit films at low temperatures. In the PEALD (Plasma Enhanced ALD) method, the use of plasma allows for even lower temperature deposition, which can be preferable in some cases. However, some precursors used in the ALD method contain impurities such as carbon. Therefore, films formed by the ALD method may contain more impurities such as carbon compared to films formed by other deposition methods. The quantitative determination of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0246] Unlike film deposition methods where particles emitted from a target or other source are deposited, CVD and ALD methods form films through reactions on the surface of the workpiece. Therefore, they are less affected by the shape of the workpiece and offer good step-level coverage. In particular, the ALD method is suitable for coating the surface of openings with high aspect ratios due to its excellent step-level coverage and uniform thickness. However, because the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods that have a faster deposition rate, such as the CVD method.

[0247] CVD and ALD methods allow for control of the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, CVD and ALD methods can deposit films of any composition by changing the flow rate ratio of the source gases. Furthermore, CVD and ALD methods can deposit films with continuously changing compositions by changing the flow rate ratio of the source gases during film deposition. When depositing films while changing the flow rate ratio of the source gases, the time required for film deposition can be shortened compared to depositing films using multiple deposition chambers, because time spent on transport and pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0248] First, a substrate (not shown) is prepared, and an insulator 212 is deposited on the substrate (see Figures 7A to 7D). The deposition of the insulator 212 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 212 can be reduced. However, the deposition of the insulator 212 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0249] In this embodiment, silicon nitride is deposited as the insulator 212 using a silicon target in a nitrogen gas-containing atmosphere by pulsed DC sputtering. By using pulsed DC sputtering, the generation of particles due to arcing on the target surface can be suppressed, resulting in a more uniform film thickness distribution. Furthermore, by using a pulsed voltage, the rise and fall of the discharge can be made steeper than with a high-frequency voltage. This allows for more efficient power supply to the electrode, improving the sputtering rate and film quality.

[0250] By using an insulator that is impermeable to impurities such as water and hydrogen, such as silicon nitride, the diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212 can be suppressed. Furthermore, by using an insulator that is impermeable to copper, such as silicon nitride, as the insulator 212, even if a diffusive metal such as copper is used in the conductor layer below the insulator 212 (not shown), the diffusion of that metal upward through the insulator 212 can be suppressed.

[0251] Next, an insulator 214 is deposited on the insulator 212 (see Figures 7A to 7D). The deposition of the insulator 214 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 214 can be reduced. However, the deposition of the insulator 214 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0252] In this embodiment, aluminum oxide is deposited as the insulator 214 using a pulsed DC sputtering method with an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Here, RF (Radio Frequency) power may be applied to the substrate. The amount of oxygen injected into the layer below the insulator 214 can be controlled by the magnitude of the RF power applied to the substrate. The RF power is 0 W / cm². 2The above is 1.86 W / cm². 2 The following applies: In other words, the amount of oxygen injected can be varied to suit the characteristics of the transistor by changing the RF power used during the formation of the insulator 214. Therefore, an amount of oxygen suitable for improving the reliability of the transistor can be injected. Furthermore, the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage can be inflicted on the substrate.

[0253] It is preferable to use an amorphous metal oxide, such as aluminum oxide, as the insulator 214, which has a high ability to capture and fix hydrogen. This allows for the capture or fixation of hydrogen contained in the insulator 216, etc., preventing the hydrogen from diffusing into the oxide 230. In particular, it is preferable to use amorphous aluminum oxide, or aluminum oxide with an amorphous structure, as the insulator 214, as this may allow for more effective capture or fixation of hydrogen. This makes it possible to fabricate a transistor 200 and semiconductor device with good properties and high reliability.

[0254] Next, an insulator 216 is deposited on the insulator 214 (see Figures 7A to 7D). The deposition of the insulator 216 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0255] In this embodiment, silicon oxide is deposited as the insulator 216 using a silicon target in an atmosphere containing oxygen gas by pulsed DC sputtering. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0256] It is preferable to continuously deposit insulators 212, 214, and 216 without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This allows for the deposition of insulators 212, 214, and 216 with reduced hydrogen content in the films, and further reduces the incorporation of hydrogen into the films between each deposition process.

[0257] Next, openings are formed in the insulator 216 that reach the insulator 214 (see Figures 7A to 7D). Openings include, for example, grooves and slits. In some cases, the term "opening" refers to the region in which the opening is formed. While wet etching may be used to form the openings, dry etching is preferable for microfabrication. Furthermore, it is preferable to select an insulator 214 that functions as an etching stopper film when etching the insulator 216 to form grooves. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 in which grooves are formed, silicon nitride, aluminum oxide, or hafnium oxide may be used for the insulator 214.

[0258] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. A dry etching apparatus having a high-density plasma source may be, for example, an inductively coupled plasma (ICP) etching apparatus.

[0259] After the opening is formed, a conductive film 205A is deposited (see Figures 7A to 7D). The conductive film 205A preferably contains a conductor that has the function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc., can be used. Alternatively, a laminated film can be formed of a conductor that has the function of suppressing oxygen permeation and a tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum-tungsten alloy. The conductive film 205A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc.

[0260] In this embodiment, titanium nitride is deposited as the conductive film 205A. By using such a metal nitride as a layer beneath the conductor 205b, oxidation of the conductor 205b by the insulator 216 and the like can be suppressed. Furthermore, even if a highly diffusive metal such as copper is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0261] Next, a conductive film 205B is deposited (see Figures 7A to 7D). As the conductive film 205B, tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum-tungsten alloy, etc., can be used. The conductive film can be deposited using methods such as plating, sputtering, CVD, MBE, PLD, and ALD. In this embodiment, tungsten is deposited as the conductive film 205B.

[0262] Next, a CMP (Chemical Polymer Processing) treatment is performed to remove a portion of the conductive films 205A and 205B, exposing the insulator 216 (see Figures 8A to 8D). As a result, the conductors 205a and 205b remain only in the openings. Note that this CMP treatment may remove a portion of the insulator 216.

[0263] Next, etching is performed to remove the upper part of the conductor 205b (see Figures 9A to 9D). As a result, the upper surface of the conductor 205b is lower than the upper surface of the conductor 205a and the upper surface of the insulator 216. Dry etching or wet etching can be used to etch the conductor 205b, but dry etching is preferable for microfabrication.

[0264] Next, a conductive film 205C is formed on the insulator 216, conductor 205a, and conductor 205b (see Figures 10A to 10D). It is desirable that the conductive film 205C, like the conductive film 205A, contains a conductor that has the function of suppressing oxygen permeation.

[0265] In this embodiment, titanium nitride is deposited as the conductive film 205C. By using such a metal nitride as the upper layer of the conductor 205b, oxidation of the conductor 205b by the insulator 222 and the like can be suppressed. Furthermore, even if a highly diffusive metal such as copper is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205c.

[0266] Next, a CMP treatment is performed to remove a portion of the conductive film 205C, exposing the insulator 216 (see Figures 11A to 11D). As a result, the conductors 205a, 205b, and 205c remain only in the openings. This allows for the formation of a conductor 205 with a flat top surface. Furthermore, the conductor 205b is enclosed by the conductors 205a and 205c. Therefore, it is possible to prevent impurities such as hydrogen from conductor 205b from diffusing out of conductors 205a and 205c, and to prevent oxygen from entering from outside conductors 205a and 205c and oxidizing conductor 205b. Note that a portion of the insulator 216 may be removed during this CMP treatment.

[0267] Next, an insulator 222 is deposited on the insulator 216 and the conductor 205 (see Figures 12A to 12D). It is preferable to deposit an insulator 222 containing an oxide of either or both aluminum and hafnium. Preferably, the insulator containing an oxide of either or both aluminum and hafnium is an aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). An insulator containing an oxide of either or both aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. Because the insulator 222 has barrier properties against hydrogen and water, the diffusion of hydrogen and water contained in the structure surrounding the transistor 200 into the transistor 200 through the insulator 222 is suppressed, thereby suppressing the formation of oxygen vacancies in the oxide 230.

[0268] The insulator 222 can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD. In this embodiment, hafnium oxide is deposited as the insulator 222 using the ALD method.

[0269] Next, it is preferable to perform a heat treatment. The heat treatment should be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then further in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0270] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from moisture or other substances being incorporated into the insulator 222 and the like.

[0271] In this embodiment, as a heat treatment, after the insulator 222 is formed, a nitrogen gas to oxygen gas flow rate ratio of 4 slm:1 slm is used, and the treatment is performed at a temperature of 400°C for 1 hour. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. Furthermore, when an oxide containing hafnium is used as the insulator 222, a portion of the insulator 222 may crystallize as a result of this heat treatment. The heat treatment can also be performed at a later time, such as after the insulator 224 is formed.

[0272] Next, an insulator 224 is deposited on the insulator 222 (see Figures 12A to 12D). The insulator 224 can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, silicon oxide is deposited as the insulator 224 using the sputtering method. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 224 can be reduced. Since the insulator 224 will come into contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration is reduced in this way.

[0273] Next, oxide films 230A and 230B are sequentially deposited on the insulator 224 (see Figures 12A to 12D). It is preferable to deposit oxide films 230A and 230B continuously without exposing them to the atmosphere. By depositing the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to oxide films 230A and 230B, and to keep the vicinity of the interface between oxide films 230A and 230B clean.

[0274] The oxide films 230A and 230B can be deposited using sputtering, CVD, MBE, PLD, ALD, and other methods.

[0275] For example, when depositing oxide films 230A and 230B by sputtering, oxygen or a mixture of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. Furthermore, when depositing the above oxide films by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0276] In particular, during the formation of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

[0277] Furthermore, when the oxide film 230B is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to be more than 30% but 100% or less, preferably 70% or more but 100%, an oxygen-rich oxide semiconductor is formed. Transistors using an oxygen-rich oxide semiconductor in the channel formation region can achieve relatively high reliability. However, the present invention is not limited to this. When the oxide film 230B is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to be 1% or more but 30% or less, preferably 5% or more but 20%, an oxygen-deficient oxide semiconductor is formed. Transistors using an oxygen-deficient oxide semiconductor in the channel formation region can achieve relatively high field-effect mobility. In addition, the crystallinity of the oxide film can be improved by performing film formation while heating the substrate.

[0278] In this embodiment, oxide film 230A is deposited by sputtering using an oxide target with an In:Ga:Zn ratio of 1:3:4. Oxide film 230B is deposited by sputtering using an oxide target with an In:Ga:Zn ratio of 4:2:4.1. Note that each oxide film may be formed according to the desired properties of oxide 230a and oxide 230b by appropriately selecting the deposition conditions and atomic ratios.

[0279] Next, an oxide film 243A is deposited on the oxide film 230B (see Figures 12A to 12D). The oxide film 243A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable that the atomic ratio of Ga to In in the oxide film 243A is greater than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 243A is deposited by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 1:3:4.

[0280] Furthermore, it is preferable to deposit the insulator 222, insulator 224, oxide film 230A, oxide film 230B, and oxide film 243A by sputtering without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This allows for the deposition of the insulator 222, insulator 224, oxide film 230A, oxide film 230B, and oxide film 243A with reduced hydrogen content in the films, and further reduces the incorporation of hydrogen into the films between each deposition process.

[0281] Next, it is preferable to perform a heat treatment. The heat treatment should be performed within a temperature range in which oxide films 230A, 230B, and 243A do not undergo polycrystallization, and should be performed between 250°C and 650°C, preferably between 400°C and 600°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0282] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from the incorporation of water and other substances into the oxide film 230A, oxide film 230B, and oxide film 243A, etc.

[0283] In this embodiment, the heat treatment involves treating the oxide film at 400°C for 1 hour in a nitrogen atmosphere, followed by a continuous treatment at 400°C for 1 hour in an oxygen atmosphere. This heat treatment can remove impurities such as water and hydrogen from oxide films 230A, 230B, and 243A. Furthermore, this heat treatment can improve the crystallinity of oxide film 230B, resulting in a denser, more compact structure. This reduces the diffusion of oxygen or impurities within oxide film 230B.

[0284] Next, a conductive film 242A is deposited on the oxide film 243A (see Figures 12A to 12D). The conductive film 242A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. For example, tantalum nitride can be deposited as the conductive film 242A using sputtering. Before depositing the conductive film 242A, a heat treatment may be performed. This heat treatment may be performed under reduced pressure, and the conductive film 242A may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 243A can be removed, and the moisture and hydrogen concentrations in the oxide film 230A, oxide film 230B, and oxide film 243A can be further reduced. The temperature of the heat treatment is preferably between 100°C and 400°C. In this embodiment, the temperature of the heat treatment is set to 200°C.

[0285] Next, an insulating film 271A is deposited on the conductive film 242A (see Figures 12A to 12D). The insulating film 271A can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to use an insulating film 271A that has the function of suppressing oxygen permeation. For example, aluminum oxide or silicon nitride can be deposited as the insulating film 271A by sputtering.

[0286] In this embodiment, aluminum oxide is deposited as the insulating film 271A using a pulsed DC sputtering method with an aluminum target in an atmosphere containing oxygen gas. The RF power applied to the substrate is 0.62 W / cm². 2 The following applies: Preferably, 0 W / cm² 2 More than 0.31W / cm 2 The following applies: By reducing the RF power, the amount of oxygen injected into the conductive film 242A can be suppressed, thereby preventing oxidation of the conductive film 242A.

[0287] Furthermore, it is preferable to deposit the conductive film 242A and the insulating film 271A by sputtering without exposing them to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This reduces the amount of hydrogen in the films when depositing the conductive film 242A and the insulating film 271A, and also reduces the amount of hydrogen introduced into the films between each deposition process. In addition, if a hard mask is provided on the insulating film 271A, the hard mask film can also be deposited continuously without exposing it to the atmosphere.

[0288] Next, using lithography, the oxide film 230A, oxide film 230B, oxide film 243A, conductive film 242A, and insulating film 271A are processed into island-like structures to form oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, and insulating layer 271B (see Figures 13A to 13D). This processing can be performed using either dry etching or wet etching. Dry etching is suitable for microfabrication. Furthermore, the oxide film 230A, oxide film 230B, oxide film 243A, conductive film 242A, and insulating layer 271B may be processed under different conditions. In this process, the insulator 224 is superimposed with oxide 230a and processed into island-like structures.

[0289] In lithography, the resist is first exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, the conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask. For example, the resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. Alternatively, immersion technology can be used, where a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, electron beams or ion beams can be used instead of the aforementioned light. When using electron beams or ion beams, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0290] Furthermore, a hard mask made of an insulator or conductor may be used beneath the resist mask. When using a hard mask, an insulating film or conductive film that serves as the hard mask material is formed on the conductive film 242A, a resist mask is formed on top of it, and a hard mask of the desired shape can be formed by etching the hard mask material. Etching of the conductive film 242A, etc., may be performed after removing the resist mask, or it may be performed while the resist mask is still in place. In the latter case, the resist mask may disappear during etching. The hard mask may also be removed by etching after etching of the conductive film 242A, etc. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not always necessary to remove the hard mask. In this embodiment, an insulating layer 271B is used as the hard mask. When the insulating layer 271B is used as the hard mask, it is preferable to appropriately adjust the film thickness of the insulating layer 271B to suppress the disappearance of the insulating layer 271B during etching of the conductive film 242A, etc.

[0291] Here, the insulating layer 271B functions as a mask for the conductive layer 242B, so as shown in Figures 13B and 13C, the conductive layer 242B does not have a curved surface between its side and top surfaces. As a result, the ends of the conductors 242a and 242b shown in Figure 4B where the side and top surfaces meet are angular. Because the ends of the conductor 242 where the side and top surfaces meet are angular, the cross-sectional area of ​​the conductor 242 is larger compared to when the ends have a curved surface. As a result, the resistance of the conductor 242 is reduced, and the on-current of the transistor 200 can be increased.

[0292] Furthermore, the insulator 224, oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, and insulating layer 271B are formed so that at least a portion of them overlaps with the conductor 205. It is also preferable that the sides of the insulator 224, oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, and insulating layer 271B are approximately perpendicular to the upper surface of the insulator 222. Having the sides of the insulator 224, oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, and insulating layer 271B approximately perpendicular to the upper surface of the insulator 222 allows for smaller area and higher density when providing multiple transistors 200. Alternatively, the angle between the sides of the insulator 224, oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, and insulating layer 271B and the top surface of the insulator 222 may be low. In this case, the angle between the sides of the insulator 224, oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, and insulating layer 271B and the top surface of the insulator 222 is preferably 60 degrees or more and less than 70 degrees. By adopting such a shape, the coverage of the insulator 272 and the like can be improved in subsequent processes, and defects such as porosity can be reduced.

[0293] Furthermore, by-products generated during the etching process may form in layers on the sides of the insulator 224, oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, and insulating layer 271B. In this case, the layered by-products will be formed between the insulator 224, oxide 230a, oxide 230b, oxide 243, conductive layer 242, and insulators 271 and 272. If the transistor 200 is manufactured by proceeding with the process while these layered by-products are formed, the reliability of the transistor 200 may deteriorate. Therefore, it is preferable to remove these layered by-products.

[0294] Next, an insulator 272 is deposited on insulator 222, insulator 224, oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, and insulating layer 271B (see Figures 14A to 14D). The insulator 272 can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, aluminum oxide is deposited as the insulator 272 using pulsed DC sputtering with an aluminum target in an atmosphere containing oxygen gas. The RF power applied to the substrate is 0.62 W / cm². 2 The following is preferred: Preferably, 0 W / cm² or more and 0.31 W / cm². 2 The following applies: By reducing the RF power, the amount of oxygen injected into the insulator 224 can be suppressed. In addition, the insulator 272 is in close contact with a portion of the upper surface of the insulator 222.

[0295] Furthermore, the insulator 272 may have a multilayer structure. For example, aluminum oxide may be deposited by sputtering, and silicon nitride may be deposited on the aluminum oxide by sputtering. By making the insulator 272 such a multilayer structure, the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen may be improved.

[0296] In this way, oxide 230a, oxide 230b, oxide layer 243B, and conductive layer 242B can be covered with insulator 272 and insulating layer 271B, which have the function of suppressing oxygen diffusion. This reduces the diffusion of oxygen into oxide 230a, oxide 230b, oxide layer 243B, and conductive layer 242B in subsequent processes.

[0297] Next, an insulating film, which will become an insulator 280, is deposited on the insulator 272. This insulating film can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. For example, a silicon oxide film can be deposited as the insulating film using sputtering. By depositing the insulating film that will become the insulator 280 using sputtering in an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. Furthermore, by using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 280 can be reduced. Note that a heat treatment may be performed before depositing the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 272 can be removed, and the moisture and hydrogen concentrations in the oxide 230a, oxide 230b, oxide layer 243B, and insulator 224 can be further reduced. The heat treatment conditions described above can be used for this heat treatment.

[0298] Next, the insulating film that will become the insulator 280 is subjected to CMP treatment to form an insulator 280 with a flat top surface (see Figures 14A to 14D). Alternatively, silicon nitride may be deposited on the insulator 280 by, for example, a sputtering method, and the silicon nitride may be subjected to CMP treatment until it reaches the insulator 280.

[0299] Next, a portion of the insulator 280, a portion of the insulator 272, a portion of the insulating layer 271B, a portion of the conductive layer 242B, and a portion of the oxide layer 243B are processed to form an opening that reaches the oxide 230b. Preferably, the opening is formed so as to overlap with the conductor 205. The formation of the opening creates the insulator 271a, the insulator 271b, the conductor 242a, the conductor 242b, the oxide 243a, and the oxide 243b (see Figures 15A to 15D).

[0300] When forming the above-mentioned opening, the upper part of the oxide 230b may be removed. By removing a portion of the oxide 230b, a groove is formed in the oxide 230b. Depending on the depth of the groove, the groove may be formed in the opening formation step or in a step different from the opening formation step.

[0301] Furthermore, the processing of a portion of the insulator 280, a portion of the insulator 272, a portion of the insulating layer 271B, a portion of the conductive layer 242B, and the oxide layer 243B can be carried out using either a dry etching method or a wet etching method. Dry etching is suitable for microfabrication. In addition, each of these processes may be carried out under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulator 272 and a portion of the insulating layer 271B may be processed by wet etching, and a portion of the conductive layer 242B and a portion of the oxide layer 243B may be processed by dry etching. Also, the processing of a portion of the conductive layer 242B and a portion of the oxide layer 243B may be carried out under different conditions.

[0302] Here, impurities may adhere to the sides of oxide 230a, the top and sides of oxide 230b, the sides of conductor 242, the sides of insulator 280, etc., or diffuse into these surfaces. A step to remove such impurities may be performed. In addition, a damaged area may be formed on the surface of oxide 230b during the dry etching process. Such a damaged area may be removed. Examples of such impurities include those resulting from components contained in insulator 280, insulator 272, a part of insulating layer 271B, and conductive layer 242B, components contained in materials used in the apparatus used to form the opening, and components contained in the gas or liquid used for etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0303] In particular, impurities such as aluminum or silicon inhibit the CAAC-OS conversion of oxide 230b. Therefore, it is preferable that impurity elements that inhibit CAAC-OS conversion, such as aluminum or silicon, are reduced or removed. For example, the concentration of aluminum atoms in oxide 230b and its vicinity should be 5.0 atomic% or less, preferably 2.0 atomic% or less, more preferably 1.5 atomic% or less, even more preferably 1.0 atomic% or less, and even more preferably less than 0.3 atomic%.

[0304] Furthermore, the region of a metal oxide where CAAC-OS formation is inhibited by impurities such as aluminum or silicon, resulting in a pseudo-amorphous-like oxide semiconductor (a-like OS), is sometimes called the non-CAAC region. In the non-CAAC region, the density of the crystal structure is reduced, therefore V O A large amount of H is formed, making it easier for the transistor to become normally-on. Therefore, it is preferable that the non-CAAC region of oxide 230b is reduced or removed.

[0305] In contrast, it is preferable that the oxide 230b has a layered CAAC structure. In particular, it is preferable that the CAAC structure extends to the lower end of the drain of the oxide 230b. Here, in the transistor 200, the conductor 242a or conductor 242b, and its vicinity, function as a drain. That is, it is preferable that the oxide 230b near the lower end of the conductor 242a (conductor 242b) has a CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the damaged region of the oxide 230b is removed and a CAAC structure is present, which further suppresses fluctuations in the electrical characteristics of the transistor 200. Furthermore, the reliability of the transistor 200 can be improved.

[0306] To remove the impurities mentioned above, a cleaning process is performed. Cleaning methods include wet cleaning using a cleaning solution, plasma treatment using plasma, and heat treatment. These cleaning methods may be combined as appropriate. Note that the grooves may become deeper as a result of this cleaning process.

[0307] For wet cleaning, cleaning may be performed using aqueous solutions of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, etc., diluted with carbonated water or distilled water, distilled water, carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, distilled water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0308] In this specification, an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting commercially available ammonia water with pure water may be referred to as diluted ammonia water. The concentration and temperature of the aqueous solution may be adjusted as appropriate depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water should be 0.01% to 5%, preferably 0.1% to 0.5%. The hydrogen fluoride concentration of the diluted hydrofluoric acid should be 0.01 ppm to 100 ppm, preferably 0.1 ppm to 10 ppm.

[0309] Furthermore, it is preferable to use a frequency of 200 kHz or higher, preferably 900 kHz or higher, for ultrasonic cleaning. Using this frequency can reduce damage to oxides such as 230b.

[0310] Furthermore, the above cleaning process may be performed multiple times, and the cleaning solution may be changed each time. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0311] In this embodiment, the cleaning process involves wet cleaning using diluted hydrofluoric acid, followed by wet cleaning using pure water or carbonated water. This cleaning process removes impurities that have adhered to the surface or diffused into the interior of oxides 230a and 230b. Furthermore, it can improve the crystallinity of oxide 230b.

[0312] Heat treatment may be performed after etching or cleaning as described above. The heat treatment should be performed at a temperature of 100°C to 450°C, preferably 350°C to 400°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to oxides 230a and 230b, thereby eliminating oxygen deficiency V O This can reduce the amount of waste. Furthermore, this heat treatment can improve the crystallinity of oxide 230b. The heat treatment may also be carried out under reduced pressure. Alternatively, the heat treatment may be performed in an oxygen atmosphere, followed by continuous heat treatment in a nitrogen atmosphere without exposure to the atmosphere.

[0313] Next, an insulating film 250A, which will become the insulator 250a, is deposited (see Figures 16A to 16D). A heat treatment may be performed before depositing the insulating film 250A, and this heat treatment may be carried out under reduced pressure, allowing for continuous deposition of the insulating film 250A without exposure to the atmosphere. Furthermore, it is preferable to carry out this heat treatment in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture and hydrogen concentrations in the oxide 230a and oxide 230b can be further reduced. The temperature of the heat treatment is preferably between 100°C and 400°C.

[0314] The insulating film 250A can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD. Furthermore, it is preferable to deposit the insulating film 250A using a deposition method that utilizes a gas with reduced or removed hydrogen atoms. This allows for a reduction in the hydrogen concentration of the insulating film 250A. Since the insulating film 250A will become an insulator 250 that comes into contact with the oxide 230b in a later process, such a reduction in hydrogen concentration is preferable.

[0315] Furthermore, it is preferable to deposit the insulating film 250A using the ALD method. The thickness of the insulator 250, which functions as the gate insulating film of the miniaturized transistor 200, needs to be extremely thin (for example, about 5 nm to 30 nm) and have minimal variation. In contrast, the ALD method is a film deposition method that alternately introduces a precursor and a reactant (oxidizing agent), and the film thickness can be adjusted by the number of times this cycle is repeated, thus enabling precise film thickness adjustment. Therefore, the accuracy of the gate insulating film required by the miniaturized transistor 200 can be achieved. Also, as shown in Figures 16B and 16C, the insulating film 250A needs to be deposited with good coverage on the bottom and side surfaces of the opening formed by the insulator 280, etc. Since atomic layers can be deposited one by one on the bottom and side surfaces of the opening, the insulating film 250A can be deposited with good coverage on the opening.

[0316] Furthermore, for example, when depositing insulating film 250A using the PECVD method, the hydrogen-containing deposition gas is decomposed in the plasma, generating a large amount of hydrogen radicals. The reduction reaction of hydrogen radicals extracts oxygen from oxide 230b, resulting in V O When H is formed, the hydrogen concentration in oxide 230b increases. However, by depositing the insulating film 250A using the ALD method, the generation of hydrogen radicals can be suppressed both when the precursor is introduced and when the reactant is introduced. Therefore, by depositing the insulating film 250A using the ALD method, it is possible to prevent the hydrogen concentration in oxide 230b from increasing.

[0317] If the above-mentioned impurities are not removed before the deposition of the insulating film 250A, these impurities may remain between the oxide 230a, oxide 230b, conductor 242, insulator 280, etc., and the insulator 250a.

[0318] Next, microwave treatment may be performed in an oxygen-containing atmosphere (see Figures 16A to 16D). Here, the dotted lines shown in Figures 16B to 16D represent microwaves, high frequencies such as RF, oxygen plasma, or oxygen radicals. For microwave treatment, it is preferable to use a microwave processing apparatus that has a power supply for generating a high-density plasma using microwaves. The microwave processing apparatus may also have a power supply for applying RF to the substrate side. By using a high-density plasma, a high density of oxygen radicals can be generated. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided into the oxide 230b. In addition, the above microwave treatment is preferably performed under reduced pressure, with a pressure of 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and even more preferably 400 Pa or more and 700 Pa or less. Furthermore, it is preferable to perform the treatment with an oxygen flow rate ratio (O2 / O2+Ar) of 50% or less, preferably 10% or more and 30% or less. Furthermore, the processing temperature should be 750°C or lower, preferably 500°C or lower, for example, around 400°C. Alternatively, after oxygen plasma treatment, continuous heat treatment may be performed without exposure to the outside air.

[0319] As shown in FIGS. 16B to 16D, by performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high-frequency waves such as RF, and the oxygen plasma can be made to act on the region between the conductors 242a and 242b of the oxide 230b. At this time, microwaves or high-frequency waves such as RF can also be irradiated onto the region 230bc. That is, microwaves, high-frequency waves such as RF, oxygen plasma, etc. can be made to act on the region 230bc shown in FIG. 5. By the action of plasma, microwaves, etc., the V O H is segmented, and hydrogen H can be removed from the region 230bc. That is, in the region 230bc, the reaction of "V O H→H+V O " occurs, and the hydrogen concentration in the region 230bc can be reduced. Therefore, the oxygen deficiency and V O H in the region 230bc can be reduced, and the carrier concentration can be decreased. Also, by supplying oxygen radicals generated by the above oxygen plasma or oxygen contained in the insulator 250 to the oxygen deficiency formed in the region 230bc, the oxygen deficiency in the region 230bc can be further reduced, and the carrier concentration can be decreased.

[0320] On the other hand, conductors 242a and 242b are provided on the regions 230ba and 230bb shown in FIG. 5. As shown in FIGS. 16B to 16D, the conductors 242a and 242b shield the action of microwaves, high-frequency waves such as RF, oxygen plasma, etc., so these actions do not reach the regions 230ba and 230bb. Thereby, by microwave treatment, reduction of V O H and supply of an excessive amount of oxygen do not occur in the regions 230ba and 230bb, so a decrease in the carrier concentration can be prevented.

[0321] In this way, oxygen deficiency and V OBy removing H, region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to regions 230ba and 230bb, which function as source or drain regions, can be suppressed, thereby maintaining the n-type configuration. This suppresses variations in the electrical properties of transistor 200 and prevents variations in the electrical properties of transistor 200 within the substrate plane.

[0322] Therefore, it is possible to provide a semiconductor device with less variation in transistor characteristics. Furthermore, it is possible to provide a semiconductor device with good reliability. Additionally, it is possible to provide a semiconductor device with good electrical characteristics.

[0323] Next, an insulating film 250B, which will become the insulator 250b, is deposited (see Figures 17A to 17D). The insulating film 250B can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to form the insulating film 250B using an insulator that has the function of suppressing oxygen diffusion. With this configuration, it is possible to suppress the diffusion of oxygen contained in the insulator 250a to the conductor 260. In other words, it is possible to suppress the decrease in the amount of oxygen supplied to the oxide 230. In addition, it is possible to suppress the oxidation of the conductor 260 by the oxygen contained in the insulator 250a. For example, the insulating film 250A can be made using a material that can be used for the insulator 250 as described above, and the insulating film 250B can be made using the same material as the insulator 222.

[0324] Specifically, as the insulating film 250B, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or metal oxides that can be used as oxide 230, can be used. In particular, it is preferable to use an insulator containing oxides of aluminum and hafnium, or both.

[0325] In this embodiment, silicon oxynitride is deposited as insulating film 250A by CVD, and hafnium oxide is deposited as insulating film 250B by thermal ALD.

[0326] Microwave treatment may be performed after the deposition of insulating film 250B. This microwave treatment may use the same microwave treatment conditions as those used after the deposition of insulating film 250A. Alternatively, microwave treatment may be performed after the deposition of insulating film 250B without performing the microwave treatment after the deposition of insulating film 250A.

[0327] Furthermore, after the deposition of insulating film 250A and insulating film 250B, a heat treatment may be performed while maintaining a reduced pressure state after each microwave treatment. By performing such a treatment, hydrogen can be efficiently removed from insulating film 250A, insulating film 250B, oxide 230b, and oxide 230a. In addition, some of the hydrogen may be gettered by the conductor 242 (conductor 242a and conductor 242b). Alternatively, the step of performing a heat treatment while maintaining a reduced pressure state after microwave treatment may be repeated multiple times. By repeating the heat treatment, hydrogen can be removed even more efficiently from insulating film 250A, oxide 230b, and oxide 230a. The heat treatment temperature is preferably 300°C to 500°C.

[0328] Furthermore, by modifying the film quality of insulating film 250A and insulating film 250B by microwave treatment, the diffusion of hydrogen, water, impurities, etc. can be suppressed. Therefore, in subsequent processes such as deposition of a conductive film that becomes the conductor 260, or post-treatment such as heat treatment, the diffusion of hydrogen, water, impurities, etc., into oxides 230b and 230a via the insulator 250 can be suppressed.

[0329] Next, a conductive film to become conductor 260a and a conductive film to become conductor 260b are deposited in sequence. The conductive films to become conductor 260a and conductor 260b can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, the conductive film to become conductor 260a is deposited using the ALD method, and the conductive film to become conductor 260b is deposited using the CVD method.

[0330] Next, by CMP treatment, the insulating film 250A, insulating film 250B, the conductive film that will become the conductor 260a, and the conductive film that will become the conductor 260b are polished until the insulator 280 is exposed, thereby forming the insulator 250a, the insulator 250b, and the conductor 260 (conductor 260a, and conductor 260b) (see Figures 18A to 18D). As a result, the insulator 250 is positioned to cover the openings that reach the oxide 230b and the inner walls (side walls and bottom surface) of the grooves in the oxide 230b. The conductor 260 is positioned to fill the openings and grooves via the insulator 250.

[0331] Next, a heat treatment may be performed under the same conditions as the heat treatment described above. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400°C for 1 hour. This heat treatment can reduce the moisture concentration and hydrogen concentration in the insulator 250 and insulator 280. After the heat treatment, the insulator 282 may be deposited continuously without exposure to the atmosphere.

[0332] Here, the insulator 280 may be subjected to oxygenation treatment. Specifically, ion implantation, ion doping, plasma immersion ion implantation, etc., can be used as the oxygenation treatment. Alternatively, oxygen may be injected into the insulator by performing plasma treatment. As the plasma generation device, a dry etching device, a plasma CVD device, a sputtering device, etc., can be used.

[0333] Furthermore, it is preferable to control the amount and depth of oxygen injected into the insulator 280 so as not to affect the function of the conductors constituting the transistor 200, such as the conductor 260 and the conductor 242.

[0334] Next, an insulator 282a is formed on the insulator 250, the conductor 260, and the insulator 280 (Figures 19A to 19D). It is preferable to use a material that suppresses oxygen diffusion for the insulator 282a. The film thickness of the insulator 282a is set to suppress damage caused by the subsequent oxygen addition treatment and not to hinder oxygen injection into the insulator 280.

[0335] The insulator 282a can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD. In particular, it is preferable to deposit the insulator 282a using the sputtering method. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 282a can be reduced.

[0336] In this embodiment, aluminum oxide is deposited as the insulator 282a using a pulsed DC sputtering method with an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. The RF power applied to the substrate is 1.86 W / cm². 2 The following applies: Preferably, 0 W / cm² 2 More than 0.31W / cm 2 The following applies: By reducing the RF power, the amount of oxygen injected into the insulator 280 can be suppressed. In this embodiment, the insulator 282a applies an RF power of 0 W / cm² to the substrate. 2 It is used to form a film.

[0337] Next, the insulator 280 is subjected to an oxygen-adding treatment via the insulator 282a (indicated by arrows in Figures 19A to 19D). Specifically, ion implantation, ion doping, plasma immersion ion implantation, etc., can be used as the oxygen-adding treatment. Alternatively, oxygen may be injected by performing plasma treatment on the insulator. As the plasma generation device, a dry etching device, a plasma CVD device, a sputtering device, etc., can be used.

[0338] Damage to the insulator 280 caused by oxygen addition treatment can be suppressed via the insulator 282a. Furthermore, since the insulator 282a suppresses the diffusion of oxygen, the oxygen injected into the insulator 280 can be efficiently injected into the insulator 280 without being released to the outside during the process.

[0339] Furthermore, if an oxide is used for the insulator 282a, oxygen may also be added to the insulator 282a. Through subsequent heating processes, excess oxygen in the insulator 282a can be transferred to the insulator 280, and the oxygen transferred to the insulator 280 can compensate for the oxygen deficiency in the oxide semiconductor.

[0340] Next, an insulator 282b is formed on the insulator 282a (see Figures 20A to 20D). It is preferable that the insulator 282b be made of a material that suppresses oxygen diffusion, similar to the insulator 282a. It is also preferable that the film thickness of the insulator 282b be thicker than that of the insulator 282a. By providing the insulator 282b on the insulator 282a which has been damaged by the oxygen addition treatment, it is possible to suppress the release of excess oxygen added to the insulator 280 to the outside.

[0341] The insulator 282b can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD. Sputtering is preferred for depositing the insulator 282b. By using a sputtering method that does not require hydrogen as the deposition gas, the hydrogen concentration in the insulator 282b can be reduced.

[0342] In this embodiment, similar to the insulator 282a, as the insulator 282b, aluminum oxide is formed by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Also, the RF power applied to the substrate is 1.86 W / cm 2 shall be as follows. Preferably, it is 0 W / cm 2 or more and 0.31 W / cm 2 or less. By reducing the RF power, the amount of oxygen injected into the insulator 280 can be suppressed. In this embodiment, the insulator 282b is formed with an RF power of 0.31 W / cm 2 applied to the substrate.

[0343] Next, according to the arrangement density of the transistors in each circuit region, a part of the insulator 282a and a part of the insulator 282b are processed to form the opening region 400 (see FIG. 21D). In the opening region 400, the insulator 280 may have a concave portion. The processing of a part of the insulator 282a, a part of the insulator 282b, and a part of the insulator 280 may use wet etching, but dry etching is more preferable for fine processing. Also, the depth of the concave portion of the insulator 280 is set to be 1 / 4 or more and 1 / 2 or less of the maximum film thickness of the insulator 280 in the semiconductor device.

[0344] Next, the insulator 282a, the insulator 282b, the insulator 280, the insulator 272, the insulator 222, the insulator 216, and the insulator 214 are processed until reaching the upper surface of the insulator 212 (see FIGS. 22A to 22C). This processing may use wet etching, but dry etching is more preferable for fine processing.

[0345] Next, a heat treatment is performed. The heat treatment may be performed at 250°C or higher and 650°C or lower, preferably 400°C or higher and 600°C or lower. By this heat treatment, the excess oxygen in the insulator 280 moves to the oxide 230 and is supplied to the oxygen deficiency in the oxide 230. That is, the oxygen deficiency in the oxide 230 is reduced, and the oxide 230 becomes highly pure and intrinsic.

[0346] Furthermore, it is preferable that the heat treatment temperature is lower than the heat treatment temperature performed after the formation of the oxide film 243A. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas. By performing this heat treatment, oxygen contained in insulator 280 and hydrogen combined with that oxygen can be released to the outside from the side surface of insulator 280 formed by the processing of insulators 282a, 282b, 280, 272, 222, 216, and 214. In addition, oxygen contained in insulator 280 and hydrogen combined with that oxygen can be released to the outside through the opening region 400. The hydrogen combined with oxygen is released as water. Therefore, the amount of unwanted oxygen and hydrogen contained in insulator 280 can be reduced.

[0347] Furthermore, the heat treatment may be performed after the formation of the opening region 400, and may also be performed after processing of the insulators 280, 272, 222, 216, and 214.

[0348] Next, an insulator 283 is formed on the insulator 282b (see Figures 23A to 23D). Preferably, the insulator 283 is in contact with the insulator 280 in the opening region 400. The insulator 283 can be deposited using sputtering, CVD, MBE, PLD, or ALD. Preferably, the insulator 283 is deposited using sputtering. By using a sputtering method that does not require hydrogen as the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. The insulator 283 may also be multilayered. For example, silicon nitride may be deposited using sputtering, and then silicon nitride may be deposited on the silicon nitride using the ALD method. By encasing the transistor 200 with the highly barrier insulator 283 and insulator 212, moisture and hydrogen can be prevented from entering from the outside.

[0349] Next, an insulator 274 is formed on the insulator 283 (see Figures 23A to 23D). The insulator 274 can be formed using sputtering, CVD, MBE, PLD, or ALD. In this embodiment, silicon oxide is formed as the insulator 274 by the CVD method.

[0350] Next, the upper surface of the insulator 274 is flattened by polishing it through a CMP process until the insulator 283 is exposed (see Figures 23A to 23D). This CMP process may remove a portion of the upper surface of the insulator 283. In addition, this CMP process fills the opening region 400 with a portion of the insulator 274 on top of the insulator 283.

[0351] Next, an insulator 286 is formed on the insulator 274 and the insulator 283 (see Figures 23A to 23D). The insulator 286 can be deposited using sputtering, CVD, MBE, PLD, or ALD. In this embodiment, silicon oxide is deposited as the insulator 286 by sputtering.

[0352] Next, openings reaching the conductor 242 are formed in insulators 271, 272, 280, 282, 283, and 286 (see Figures 23A to 23C). These openings may be formed using lithography. In Figure 23A, the shape of the opening is circular in a top view, but it is not limited to this. For example, the opening may be approximately circular, such as an ellipse, polygonal, such as a quadrilateral, or a polygonal shape with rounded corners in a top view.

[0353] Next, an insulating film to form the insulator 241 is deposited, and the insulating film is anisotropically etched to form the insulator 241 (see Figure 23B). The insulating film to form the insulator 241 can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to use an insulating film that has the function of suppressing oxygen permeation as the insulating film to form the insulator 241. For example, it is preferable to deposit aluminum oxide using the ALD method. Alternatively, it is preferable to deposit silicon nitride using the PEALD method. Silicon nitride is preferred because it has high blocking properties for hydrogen.

[0354] Furthermore, for the anisotropic etching of the insulating film that will become the insulator 241, a dry etching method, for example, can be used. By providing the insulator 241 on the side walls of the opening, the permeation of oxygen from the outside can be suppressed, and oxidation of the conductors 240a and 240b that will be formed next can be prevented. In addition, it is possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductors 240a and 240b.

[0355] Next, conductive films that will become conductor 240a and conductor 240b are deposited. It is desirable that the conductive films that will become conductor 240a and conductor 240b have a laminated structure containing a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, a laminate of tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc., can be formed. The conductive film that will become conductor 240 can be deposited using sputtering, CVD, MBE, PLD, or ALD methods.

[0356] Next, by performing a CMP (Chemical Polishing) treatment, a portion of the conductive film that will become conductors 240a and 240b is removed, exposing the upper surface of the insulator 274. As a result, the conductive film remains only in the openings, making it possible to form conductors 240a and 240b with flat upper surfaces (see Figure 23B). Note that a portion of the upper surface of the insulator 286 may be removed by this CMP treatment.

[0357] Next, a conductive film to become conductor 246 is deposited. The conductive film to become conductor 246 can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD.

[0358] Next, a conductive film to become the conductor 246 is processed by lithography to form a conductor 246a that contacts the upper surface of the conductor 240a, and a conductor 246b that contacts the upper surface of the conductor 240b. Although not shown in the diagram, at this time, a portion of the insulator 286 in the region where the conductors 246a and 246b do not overlap with the insulator 286 may be removed.

[0359] Based on the above, a semiconductor device having the transistor 200 shown in Figures 4A to 4D can be fabricated. As shown in Figures 7A to 23D, the transistor 200 can be fabricated by using the semiconductor device fabrication method shown in this embodiment.

[0360] <Microwave Processing Equipment> The following describes a microwave processing apparatus that can be used in the manufacturing method of the semiconductor device described above.

[0361] First, we will explain the configuration of a manufacturing equipment that minimizes the inclusion of impurities during the manufacturing of semiconductor devices and other equipment, using Figures 24, 25, and 26.

[0362] Figure 24 schematically shows a top view of a single-wafer multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes an atmospheric substrate supply chamber 2701 equipped with a cassette port 2761 for housing substrates and an alignment port 2762 for aligning substrates; an atmospheric substrate transport chamber 2702 for transporting substrates from the atmospheric substrate supply chamber 2701; a load lock chamber 2703a for loading substrates and switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure; an unload lock chamber 2703b for unloading substrates and switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure; a transport chamber 2704 for transporting substrates in a vacuum; and chambers 2706a, 2706b, 2706c, and 2706d.

[0363] Furthermore, the atmospheric substrate transport chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to the transport chamber 2704, and the transport chamber 2704 is connected to chambers 2706a, 2706b, 2706c, and 2706d.

[0364] Furthermore, gate valves GV are provided at the connection points of each chamber, and each chamber can be independently maintained in a vacuum state, except for the atmospheric substrate supply chamber 2701 and the atmospheric substrate transport chamber 2702. In addition, a transport robot 2763a is provided in the atmospheric substrate transport chamber 2702, and a transport robot 2763b is provided in the transport chamber 2704. Transport robots 2763a and 2763b can transport substrates within the manufacturing apparatus 2700.

[0365] The back pressure (total pressure) in the transport chamber 2704 and each chamber is, for example, 1 × 10⁻⁶ -4 Pa or less, preferably 3 × 10 -5 Pa or less, more preferably 1 × 10⁻⁶ -5 The pressure shall be less than or equal to Pa. Furthermore, the partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transport chamber 2704 and each chamber shall be, for example, 3 × 10⁻⁶. -5Pa or less, preferably 1 × 10⁻⁶ -5 Pa or less, more preferably 3 × 10 -6 The pressure shall be less than or equal to Pa. Furthermore, the partial pressure of gas molecules (atoms) with an m / z of 28 in the transport chamber 2704 and each chamber shall be, for example, 3 × 10⁻⁶. -5 Pa or less, preferably 1 × 10⁻⁶ -5 Pa or less, more preferably 3 × 10 -6 The pressure shall be less than or equal to Pa. Furthermore, the partial pressure of gas molecules (atoms) with an m / z of 44 in the transport chamber 2704 and each chamber shall be, for example, 3 × 10⁻⁶. -5 Pa or less, preferably 1 × 10⁻⁶ -5 Pa or less, more preferably 3 × 10 -6 It should be Pa or less.

[0366] The total pressure and partial pressure in the transport chamber 2704 and each chamber can be measured using a mass spectrometer. For example, a quadrupole mass spectrometer (also known as Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. can be used.

[0367] Furthermore, it is desirable that the transport chamber 2704 and each chamber be configured to minimize external or internal leaks. For example, the leak rate of the transport chamber 2704 and each chamber should be 3 × 10⁻⁶. -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 The rate should be less than or equal to / s. Also, for example, the leak rate of a gas molecule (atom) with m / z 18 is 1 × 10⁻⁶. -7 Pa·m 3 / s or less, preferably 3 × 10 -8 Pa·m 3 The rate should be less than or equal to / s. Also, for example, the leak rate of a gas molecule (atom) with m / z 28 is 1 × 10⁻⁶. -5 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 The rate should be less than or equal to / s. Also, for example, the leak rate of a gas molecule (atom) with m / z 44 is 3 × 10⁻⁶. -6 Pa·m 3 / s or less, preferably 1 × 10 -6Pa·m 3 Set to / s or less.

[0368] The leak rate can be derived from the total pressure and partial pressure measured using the mass spectrometer mentioned above. The leak rate depends on both external and internal leaks. External leaks are caused by gas flowing in from outside the vacuum system through tiny holes or faulty seals. Internal leaks are caused by leaks from valves and other partitions within the vacuum system, or by gases released from internal components. To keep the leak rate below the values ​​mentioned above, countermeasures must be taken from both external and internal leaks.

[0369] For example, the opening and closing parts of the conveying chamber 2704 and each chamber may be sealed with metal gaskets. Preferably, the metal gaskets are made of metal coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets offer better adhesion than O-rings, reducing external leakage. Furthermore, using a passivated metal coated with iron fluoride, aluminum oxide, or chromium oxide suppresses the release of impurity-containing gases from the metal gasket, thereby reducing internal leakage.

[0370] Furthermore, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emit less impurity-containing gas, are used as components of the manufacturing apparatus 2700. Alternatively, the aforementioned metals that emit less impurity-containing gas may be used as a coating on an alloy containing iron, chromium, and nickel. Alloys containing iron, chromium, and nickel are rigid, heat-resistant, and suitable for processing. Here, reducing the surface area by reducing surface irregularities of the components through polishing or other means can reduce the emission of gas.

[0371] Alternatively, the components of the aforementioned manufacturing apparatus 2700 may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0372] The components of the manufacturing apparatus 2700 are preferably made of metal as much as possible. For example, when installing viewing windows made of quartz or the like, it is advisable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide, etc., to suppress the release of gases.

[0373] The adsorbed substances present in the transport chamber 2704 and each chamber do not affect the pressure in the transport chamber 2704 and each chamber because they are adsorbed onto the inner walls, but they cause gas release when the transport chamber 2704 and each chamber are evacuated. Therefore, although there is no correlation between the leak rate and the exhaust rate, it is important to use a pump with high exhaust capacity to desorb as much of the adsorbed substances present in the transport chamber 2704 and each chamber as possible and evacuate them in advance. In addition, the transport chamber 2704 and each chamber may be baked to promote the desorption of adsorbed substances. Baking can increase the desorption rate of adsorbed substances by about 10 times. Baking should be performed at a temperature between 100°C and 450°C. At this time, if the adsorbed substances are removed while introducing an inert gas into the transport chamber 2704 and each chamber, the desorption rate of water and other substances that are difficult to desorb by exhaust alone can be further increased. In addition, the desorption rate of adsorbed substances can be further increased by heating the introduced inert gas to approximately the same temperature as the baking temperature. It is preferable to use a noble gas as the inert gas here.

[0374] Alternatively, it is preferable to increase the pressure in the transport chamber 2704 and each chamber by introducing an inert gas such as a heated noble gas or oxygen, and then exhaust the transport chamber 2704 and each chamber again after a certain period of time. By introducing a heated gas, adsorbed substances can be removed from the transport chamber 2704 and each chamber, thereby reducing the amount of impurities present in the transport chamber 2704 and each chamber. This process is most effective when repeated 2 to 30 times, preferably 5 to 15 times. Specifically, the pressure in the transport chamber 2704 and each chamber can be increased to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa by introducing an inert gas or oxygen with a temperature of 40°C to 400°C, preferably 50°C to 200°C, and the pressure can be maintained for 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. Subsequently, the transport chamber 2704 and each chamber are evacuated for a period of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

[0375] Next, chambers 2706b and 2706c will be explained using the schematic cross-sectional diagrams shown in Figure 25.

[0376] Chambers 2706b and 2706c are chambers capable of performing microwave processing on an object to be processed. The only difference between chambers 2706b and 2706c is the atmosphere used during microwave processing. Other configurations are common to both chambers, and will therefore be described together below.

[0377] Chambers 2706b and 2706c each have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Outside of chambers 2706b and 2706c, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818.

[0378] The high-frequency generator 2803 is connected to the mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to the slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is positioned in contact with the dielectric plate 2809. The gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is then supplied to chambers 2706b and 2706c through a gas pipe 2806 that passes through the mode converter 2805, waveguide 2807, and dielectric plate 2809. The vacuum pump 2817 has the function of exhausting gas and other substances from chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. The high-frequency power supply 2816 is connected to the substrate holder 2812 via a matching box 2815.

[0379] The substrate holder 2812 has the function of holding the substrate 2811. For example, it has the function of electrostatically or mechanically chucking the substrate 2811. It also functions as an electrode to which power is supplied from the high-frequency power supply 2816. It also has an internal heating mechanism 2813 and has the function of heating the substrate 2811.

[0380] As the vacuum pump 2817, for example, a dry pump, mechanical booster pump, ion pump, titanium sublimation pump, cryopump, or turbomolecular pump can be used. In addition to the vacuum pump 2817, a cryotrap may also be used. Using a cryopump and cryotrap is particularly preferable because it allows for efficient water removal.

[0381] Furthermore, the heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element. Alternatively, it may be a heating mechanism that heats by heat conduction or thermal radiation from a heated medium such as a gas. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs heat treatment using a high-temperature gas. An inert gas is used as the gas.

[0382] Furthermore, the gas supply source 2801 may be connected to the purifier via a mass flow controller. It is preferable to use a gas with a dew point of -80°C or lower, preferably -100°C or lower. For example, oxygen gas, nitrogen gas, and noble gases (such as argon gas) may be used.

[0383] For example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria) may be used as the dielectric plate 2809. Furthermore, another protective layer may be formed on the surface of the dielectric plate 2809. The protective layer may be made of magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. Since the dielectric plate 2809 will be exposed to particularly high-density regions of the high-density plasma 2810 described later, providing a protective layer can mitigate damage. As a result, an increase in particles during processing can be suppressed.

[0384] The high-frequency generator 2803 has the function of generating microwaves in frequencies such as 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to the mode converter 2805 via the waveguide 2804. In the mode converter 2805, the microwaves transmitted as TE mode are converted to TEM mode. The microwaves are then transmitted to the slot antenna plate 2808 via the waveguide 2807. The slot antenna plate 2808 is provided with multiple slot holes, and the microwaves pass through these slot holes and the dielectric plate 2809. This generates an electric field below the dielectric plate 2809, thereby generating a high-density plasma 2810. The high-density plasma 2810 contains ions and radicals depending on the type of gas supplied from the gas supply source 2801. For example, oxygen radicals are present.

[0385] At this time, the substrate 2811 can be modified by ions and radicals generated in the high-density plasma 2810, which can alter films and other structures on the substrate 2811. It is preferable to apply a bias to the substrate 2811 using a high-frequency power supply 2816. For example, an RF (Radio Frequency) power supply with frequencies such as 13.56 MHz or 27.12 MHz can be used as the high-frequency power supply 2816. By applying a bias to the substrate, ions in the high-density plasma 2810 can efficiently reach deep into the openings of films and other structures on the substrate 2811.

[0386] For example, oxygen radical treatment using high-density plasma 2810 can be performed by introducing oxygen from gas supply source 2801 in chamber 2706b or chamber 2706c.

[0387] Next, chambers 2706a and 2706d will be described using the schematic cross-sectional diagrams shown in Figure 26.

[0388] Chambers 2706a and 2706d are chambers capable of irradiating the workpiece with electromagnetic waves, for example. The only difference between chambers 2706a and 2706d is the type of electromagnetic wave they emit. Since many other components are common to both, they will be described together below.

[0389] Chambers 2706a and 2706d each have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. Outside of chambers 2706a and 2706d, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided.

[0390] The gas supply source 2821 is connected to the gas inlet 2823 via valve 2822. The vacuum pump 2828 is connected to the exhaust port 2830 via valve 2829. The lamp 2820 is positioned opposite the substrate holder 2825. The substrate holder 2825 has the function of holding the substrate 2824. The substrate holder 2825 also has an internal heating mechanism 2826 that has the function of heating the substrate 2824.

[0391] For lamp 2820, for example, a light source having the function of emitting electromagnetic waves such as visible light or ultraviolet light may be used. For example, a light source having the function of emitting electromagnetic waves with peaks in wavelengths of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.

[0392] For example, lamp 2820 can be a light source such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp.

[0393] For example, electromagnetic waves emitted from the lamp 2820 can be partially or entirely absorbed by the substrate 2824, thereby modifying the film on the substrate 2824. For example, defects can be created or reduced, or impurities can be removed. Furthermore, if the substrate 2824 is heated during the process, the creation or reduction of defects or the removal of impurities can be performed more efficiently.

[0394] Alternatively, for example, the substrate holder 2825 may be heated by electromagnetic waves emitted from the lamp 2820, thereby heating the substrate 2824. In this case, the substrate holder 2825 does not need to have a heating mechanism 2826 inside.

[0395] For vacuum pump 2828, refer to the description for vacuum pump 2817. For heating mechanism 2826, refer to the description for heating mechanism 2813. For gas supply source 2821, refer to the description for gas supply source 2801.

[0396] By using the above manufacturing equipment, it becomes possible to modify the film while suppressing the inclusion of impurities in the processed material.

[0397] <Modified examples of semiconductor devices> In the following section, an example of a semiconductor device according to one aspect of the present invention will be described using Figures 27A to 27D.

[0398] In each figure, A shows a top view of the semiconductor device. B in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in figure A. C in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in figure A. D in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A5-A6 in figure A. In the top view of figure A, some elements have been omitted for clarity.

[0399] In the semiconductor devices shown in Figures A through D, the same reference numerals are used to denote structures that have the same function as those shown in <Examples of Semiconductor Device Configurations>. Furthermore, in this section as well, the materials used for the semiconductor devices are those described in detail in <Examples of Semiconductor Device Configurations>.

[0400] <Example 1 of a semiconductor device> The semiconductor devices shown in Figures 27A to 27D are modified examples of the semiconductor devices shown in Figures 4A to 4D. The semiconductor devices shown in Figures 27A to 27D differ from those shown in Figures 4A to 4D in that they contain oxide 230c and oxide 230d.

[0401] The semiconductor device shown in Figures 27A to 27D further includes oxide 230c on oxide 230b and oxide 230d on oxide 230c. Oxide 230c and oxide 230d are provided within openings formed in insulators 280 and 272. Oxide 230c is in contact with the sides of oxide 243a, oxide 243b, conductor 242a, conductor 242b, insulator 271a, insulator 271b, and insulator 272, respectively. The upper surfaces of oxide 230c and oxide 230d are in contact with insulator 282.

[0402] By placing oxide 230d on top of oxide 230c, the diffusion of impurities from structures formed above oxide 230d to oxide 230b or oxide 230c can be suppressed. Furthermore, by placing oxide 230d on top of oxide 230c, the upward diffusion of oxygen from oxide 230b or oxide 230c can be suppressed.

[0403] Furthermore, in a cross-sectional view of the transistor in the channel length direction, it is preferable to provide grooves in the oxide 230b and embed oxide 230c in these grooves. In this case, the oxide 230c is arranged to cover the inner walls (side walls and bottom surface) of the grooves. It is also preferable that the film thickness of the oxide 230c is approximately the same as the depth of the grooves. With this configuration, even if a damaged area is formed on the surface of the oxide 230b at the bottom of the opening when forming an opening for embedding a conductor 260 or the like, the damaged area can be removed. This makes it possible to suppress defects in the electrical characteristics of the transistor 200 caused by the damaged area.

[0404] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230c is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a or oxide 230d.

[0405] Furthermore, when oxide 230c is used as the primary carrier pathway, it is preferable that the atomic ratio of indium to the main metal element in oxide 230c is greater than the atomic ratio of indium to the main metal element in oxide 230b. Also, it is preferable that the atomic ratio of In to element M in oxide 230c is greater than the atomic ratio of In to element M in oxide 230b. Using a metal oxide with a high indium content in the channel formation region can increase the on-current of the transistor. Therefore, by making the atomic ratio of indium to the main metal element in oxide 230c greater than the atomic ratio of indium to the main metal element in oxide 230b, oxide 230c can be used as the primary carrier pathway. Additionally, it is preferable that the lower end of the conduction band of oxide 230c is further from the vacuum level than the lower end of the conduction bands of oxides 230a and 230b. In other words, it is preferable that the electron affinity of oxide 230c is greater than that of oxides 230a and 230b. In this case, the main carrier pathway is oxide 230c.

[0406] Specifically, for oxide 230c, metal oxides or indium oxides with compositions of In:M:Zn = 4:2:3 [atomic ratio] or close to it, In:M:Zn = 5:1:3 [atomic ratio] or close to it, or In:M:Zn = 10:1:3 [atomic ratio] or close to it are preferable to use.

[0407] Furthermore, it is preferable to use CAAC-OS as oxide 230c, and it is preferable that the c-axis of the crystal of oxide 230c is oriented in a direction approximately perpendicular to the surface or top surface of oxide 230c. CAAC-OS has the property of easily moving oxygen in a direction perpendicular to the c-axis. Therefore, oxygen from oxide 230c can be efficiently supplied to oxide 230b.

[0408] Furthermore, oxide 230d preferably contains at least one of the metal elements that constitute the metal oxide used in oxide 230c, and more preferably contains all of those metal elements. For example, In-M-Zn oxide, In-Zn oxide, or indium oxide may be used as oxide 230c, and In-M-Zn oxide, M-Zn oxide, or an oxide of element M may be used as oxide 230d. This makes it possible to lower the defect level density at the interface between oxide 230c and oxide 230d.

[0409] Furthermore, it is preferable that the lower end of the conduction band of oxide 230d is closer to the vacuum level than the lower end of the conduction band of oxide 230c. In other words, it is preferable that the electron affinity of oxide 230d is smaller than that of oxide 230c. In this case, it is preferable that oxide 230d is a metal oxide that can be used for oxide 230a or oxide 230b. In this case, the main carrier pathway is oxide 230c.

[0410] Specifically, for oxide 230c, a metal oxide or indium oxide with a composition of In:M:Zn=4:2:3 [atomic ratio] or nearby, In:M:Zn=5:1:3 [atomic ratio] or nearby, or In:M:Zn=10:1:3 [atomic ratio] or nearby may be used. For oxide 230d, a metal oxide or oxide of element M with a composition of In:M:Zn=1:3:4 [atomic ratio] or nearby, M:Zn=2:1 [atomic ratio] or nearby, or M:Zn=2:5 [atomic ratio] or nearby may be used. Note that nearby compositions include a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use gallium as element M.

[0411] Furthermore, it is preferable that oxide 230d is a metal oxide that suppresses oxygen diffusion or permeation more effectively than oxide 230c. By providing oxide 230d between the insulator 250 and oxide 230c, oxygen can be efficiently supplied to oxide 230b via oxide 230c.

[0412] Furthermore, by making the atomic ratio of In to the main metal element in the metal oxide used for oxide 230d smaller than the atomic ratio of In to the main metal element in the metal oxide used for oxide 230c, the diffusion of In to the insulator 250 can be suppressed. For example, in oxide 230d, the atomic ratio of In to element M can be made smaller than the atomic ratio of In to element M in oxide 230c. Since the insulator 250 functions as a gate insulator, if In is mixed into the insulator 250, it will result in a defect in the characteristics of the transistor. Therefore, by providing oxide 230d between oxide 230c and insulator 250, it is possible to provide a highly reliable semiconductor device.

[0413] Furthermore, the oxide 230c may be provided for each transistor 200. In other words, the oxide 230c of transistor 200 and the oxide 230c of an adjacent transistor 200 do not need to be in contact. Alternatively, the oxide 230c of transistor 200 and the oxide 230c of an adjacent transistor 200 may be separated. In other words, the oxide 230c may not be placed between transistor 200 and an adjacent transistor 200.

[0414] In a semiconductor device in which multiple transistors 200 are arranged in the channel width direction, the above configuration ensures that oxide 230c is independently provided on each transistor 200. Therefore, the formation of parasitic transistors between a transistor 200 and an adjacent transistor 200 can be suppressed, thereby preventing the formation of the aforementioned leakage path. Consequently, a semiconductor device with good electrical characteristics and capable of miniaturization or high integration can be provided.

[0415] <Modified example of a semiconductor device 2> In the following section, an example of a semiconductor device according to one aspect of the present invention will be described using Figure 28.

[0416] Figure 28A shows a top view of a semiconductor device. Figure 28B is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in Figure 28A. Note that the cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in Figure 28A can be found by referring to transistor 200 shown in Figure 4B. Some elements have been omitted from the top view in Figure 28A for clarity.

[0417] In the semiconductor device shown in Figure 28, structures having the same function as those constituting the semiconductor device shown in <Example of Semiconductor Device Configuration> are denoted by the same reference numerals. Furthermore, in this section as well, the materials used for the semiconductor device components are those described in detail in <Example of Semiconductor Device Configuration>.

[0418] The semiconductor device shown in Figure 28 is a modified version of the semiconductor device shown in Figure 4. In the semiconductor device shown in Figure 28, the transistor 200 has a configuration in which n oxides 230 (oxides 230_1 to 230_n: n is a natural number), which is different from the semiconductor device in Figure 4. In addition, each oxide 230_1 to 230_n has a channel formation region.

[0419] The semiconductor device shown in Figure 28 has conductors 260 provided on the upper and side surfaces of multiple channel-forming regions via insulators 250. In addition, conductors 246 (conductors 246a and 246b) are extended in the A3-A4 direction and are electrically connected to oxides 230_1 to 230_n via conductor 240.

[0420] In other words, in the semiconductor device shown in Figure 28, the transistor 200 has multiple channel formation regions for a single gate electrode. The transistor 200 shown in Figure 28 can obtain a large on-current by having multiple channel formation regions. Furthermore, since each channel formation region has a structure covered by a gate electrode, i.e., an s-channel structure, a large on-current can be obtained in each channel formation region. Alternatively, in the channel width direction of the transistor 200, the height of the bottom surface of the region of the conductor 260 where the conductor 260 and oxide 230b do not overlap, when the bottom surface of the insulator 222 is used as a reference, is lower than the height of the interface between the top surface of oxide 230b and oxide 230c, so a large on-current can be obtained in each channel formation region.

[0421] For other configurations, refer to the semiconductor device configuration shown in Figure 4.

[0422] <Modified example of semiconductor device 3> Below, an example of a semiconductor device according to one aspect of the present invention will be described using Figure 29.

[0423] Figure 29A shows a top view of a semiconductor device. Figure 29B is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in Figure 29A. Note that the cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in Figure 29A can be found by referring to transistor 200 shown in Figure 4B. Some elements have been omitted from the top view in Figure 29A for clarity.

[0424] In the semiconductor device shown in Figure 29, structures having the same function as those constituting the semiconductor device shown in <Example of Semiconductor Device Configuration> are denoted by the same reference numerals. Furthermore, in this section as well, the materials used for the semiconductor device components are those described in detail in <Example of Semiconductor Device Configuration>.

[0425] The semiconductor device shown in Figure 29 is a modified version of the semiconductor device shown in Figure 28. In the semiconductor device shown in Figure 29, the transistor 200 has n oxides 230 (oxides 230_1 to 230_n: n is a natural number). Each oxide 230_1 to 230_n also has a channel-forming region.

[0426] The semiconductor device shown in Figure 29 has conductors 260 provided on the upper and side surfaces of multiple channel-forming regions via insulators 250. In addition, conductors 246 (conductors 246a and 246b) are extended in the A3-A4 direction and are electrically connected to oxides 230_1 to 230_n via conductor 240.

[0427] The semiconductor device shown in Figure 29 has multiple channel formation regions in transistor 200, with transistor 200D having at least oxide 230D adjacent to oxide 230_1 located at the end of transistor 200. Similarly, transistor 200D is located adjacent to oxide 230_n located at the end of transistor 200.

[0428] In other words, the semiconductor device shown in Figure 29 differs from the semiconductor device shown in Figure 28 in that it has a configuration in which transistors 200D are provided at one end or both ends in the direction in which the multiple channel formation regions of transistor 200 are arranged in parallel.

[0429] Here, transistor 200D does not need to be electrically connected to one or all of the gate, source, or drain wiring. In other words, transistor 200D may be provided in a non-functional state as a transistor. Therefore, transistor 200D may be referred to as a dummy transistor (sacrificial transistor).

[0430] Furthermore, it is preferable that the shortest distance between oxide 230_D and oxide 230_1, and the shortest distance between oxide 230_1 and oxide 230_2, are approximately equal. Similarly, it is preferable that the shortest distance between oxide 230_D and oxide 230_n, and the shortest distance between oxide 230_n-1 and oxide 230_n, are approximately equal. Note that when n is 1, it is preferable that the shortest distance between one oxide 230_D and oxide 230_1, and the shortest distance between the other oxide 230_D and oxide 230_1, are approximately equal.

[0431] Furthermore, the shortest distance between conductors 242a and 242b in oxide 230_D may be approximately equal to or greater than the shortest distance between conductors 242a and 242b in oxide 230_1. Similarly, the shortest distance between conductors 242a and 242b in oxide 230_D may be approximately equal to or greater than the shortest distance between conductors 242a and 242b in oxide 230_n.

[0432] When multiple oxides 230 are formed in parallel, the oxides 230 located at the ends are prone to shape variations due to processing. Furthermore, in the process of removing a portion of the insulator 280 and the laminated structure on the channel-forming region of the oxide 230 to create an opening and expose a portion of the upper surface of the oxide 230, variations may occur in the area of ​​the exposed upper surface of the oxide 230 due to the shape of the end of the removed region (also called the opening) or the distance between the oxide 230 and the end of the opening.

[0433] Therefore, as shown in Figure 29, by providing the transistor 200D, even if a shape defect occurs in the oxide 230_D of the transistor 200D, or if a shape defect occurs in the opening on the oxide 230_D, the shape of the oxide 230 formed in the region sandwiched between the transistors 200D will be uniform.

[0434] Therefore, by placing transistor 200D adjacent to transistor 200, when multiple transistors 200 are provided, variations in characteristics among the multiple transistors 200 can be reduced.

[0435] Furthermore, when multiple oxides 230 are provided at equal intervals in a certain area, circuit design can be easily performed by changing the wiring layout.

[0436] Furthermore, in the semiconductor device shown in Figure 29, the transistor 200 has multiple channel formation regions for a single gate electrode. The transistor 200 shown in Figure 29 can obtain a large on-current by having multiple channel formation regions. In addition, since each channel formation region has a structure covered by a gate electrode, i.e., an s-channel structure, a large on-current can be obtained in each channel formation region. Alternatively, in the channel width direction of the transistor 200, the height of the bottom surface of the region of the conductor 260 where the conductor 260 and oxide 230b do not overlap, when the bottom surface of the insulator 222 is used as a reference, is lower than the height of the interface between the top surface of oxide 230b and oxide 230c, so a large on-current can be obtained in each channel formation region.

[0437] For other configurations, refer to the semiconductor device configuration shown in Figure 4.

[0438] <Modification 4 of semiconductor device> Below, an example of a semiconductor device according to one aspect of the present invention will be described using Figure 30.

[0439] Figure 30A shows a top view of a semiconductor device. Figure 30B is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in Figure 30A. Note that the cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in Figure 30A can be found by referring to transistor 200 shown in Figure 4B. Some elements have been omitted from the top view in Figure 30A for clarity.

[0440] In the semiconductor device shown in Figure 30, structures having the same function as those constituting the semiconductor device shown in <Example of Semiconductor Device Configuration> are denoted by the same reference numerals. Furthermore, in this section as well, the materials used for the semiconductor device are those described in detail in <Example of Semiconductor Device Configuration>.

[0441] The semiconductor device described in this section is a modified version of the semiconductor device shown in Figure 29. Therefore, the transistor 200 differs from the semiconductor device shown in Figure 29 in that it has an oxide 230 having n channel formation regions (wherein n are referred to as channel formation regions 235_1 to 235_n, and n is a natural number). In addition, a conductor 260 is provided on the upper and side surfaces of multiple channel formation regions via an insulator 250.

[0442] Furthermore, the conductor 242 (conductors 242a and 242b) extends in the A3-A4 direction and is electrically connected to the conductor 246 (conductors 246a and 246b) via the conductor 240 (conductors 240a and 240b).

[0443] Here, Figure 30 shows the case where n=2 for the sake of simplicity. Therefore, the transistor 200 has an oxide 230 having two channel formation regions (channel formation region 235_1 and channel formation region 235_2).

[0444] In the oxide 230, the source region and the drain region are electrically connected to the conductor 242a or the conductor 242b. Therefore, for example, by electrically connecting the conductor 242a and the conductor 246a via at least one conductor 240a, a voltage can be applied to multiple channel-forming regions (channel-forming regions 235_1 to 235_n).

[0445] In other words, a transistor 200 having n channel formation regions 235 does not necessarily need to have n conductors 240. For a transistor having n channel formation regions 235, it is preferable to have 1 or more, preferably 1 or more and less than n.

[0446] Furthermore, as transistors become smaller, the size of the plugs that electrically connect the transistors to the conductors that function as wiring also needs to be miniaturized. In addition, as the contact area between the conductors that function as plugs and the conductors that function as wiring decreases, the wiring resistance tends to increase.

[0447] In the semiconductor device described in this section, since a transistor 200 having n channel formation regions is provided with a number of plugs less than n, the size of each conductor 240 that functions as a plug can be made larger than, for example, the conductor 240 shown in the semiconductor device in Figure 29, thus reducing power consumption.

[0448] Furthermore, in the semiconductor device shown in Figure 30, multiple channel formation regions are arranged in the transistor 200, with at least one transistor 200D having oxide 230D adjacent to oxide 230_1 located at the end of the transistor 200. Similarly, the transistor 200D is arranged adjacent to oxide 230_n located at the end of the transistor 200.

[0449] Therefore, in the semiconductor device shown in Figure 30, conductors 260 are provided on the upper and side surfaces of multiple channel-forming regions via insulators 250. Furthermore, conductors 246a and 246b are extended in the A3-A4 direction and are electrically connected to the oxide 230_n.

[0450] Furthermore, in the semiconductor device shown in Figure 30, a transistor 200 has multiple channel formation regions, with a transistor 200D having at least oxide 230D positioned adjacent to a channel formation region 235_1 located at the end of the transistor 200. Similarly, a transistor 200D is positioned adjacent to a channel formation region 235_n located at the end of the transistor 200.

[0451] In other words, transistor 200D is provided at one end or both ends of the direction in which the multiple channel formation regions of transistor 200 are arranged in parallel.

[0452] Here, transistor 200D does not need to be electrically connected to one or all of the gate, source, or drain wiring. In other words, transistor 200D may be provided in a non-functional state as a transistor. Therefore, transistor 200D may be referred to as a dummy transistor (sacrificial transistor).

[0453] Furthermore, it is preferable that the shortest distance between oxide 230_D and oxide 230_1, and the shortest distance between oxide 230_1 and oxide 230_2, are approximately equal. Similarly, it is preferable that the shortest distance between oxide 230_D and oxide 230_n, and the shortest distance between oxide 230_n-1 and oxide 230_n, are approximately equal. Note that when n is 1, it is preferable that the shortest distance between one oxide 230_D and oxide 230_1, and the shortest distance between the other oxide 230_D and oxide 230_1, are approximately equal.

[0454] Furthermore, the shortest distance between conductors 242a and 242b in oxide 230_D may be approximately equal to or greater than the shortest distance between conductors 242a and 242b in oxide 230_1. Similarly, the shortest distance between conductors 242a and 242b in oxide 230_D may be approximately equal to or greater than the shortest distance between conductors 242a and 242b in oxide 230_n.

[0455] Furthermore, the difference between the shortest distance between conductor 242a and conductor 242b in oxide 230_D and the shortest distance between conductor 242a and conductor 242b in oxide 230_1 may be greater than the difference between the shortest distance between conductor 242a and conductor 242b in oxide 230_1 and the shortest distance between conductor 242a and conductor 242b in oxide 230_2.

[0456] When multiple channel-forming regions 235 are formed in parallel, the channel-forming regions 235 located at the ends are prone to shape variations due to processing. Furthermore, in the process of removing a portion of the insulator 280 and the laminated structure on the channel-forming region of the oxide 230 to create an opening and expose a portion of the upper surface of the oxide 230, variations may occur in the area of ​​the exposed upper surface of the oxide 230 due to the shape of the end of the area to be removed (also called the opening), or the distance between the oxide 230 and the end of the opening.

[0457] Therefore, as shown in Figure 30, by providing the transistor 200D, even if a shape defect occurs in the oxide 230_D of the transistor 200D, or if a shape defect occurs in the opening on the oxide 230_D, the shape of the oxide 230 formed in the region sandwiched between the transistors 200D will be uniform.

[0458] Therefore, by placing transistor 200D adjacent to transistor 200, when multiple transistors 200 are provided, variations in characteristics among the multiple transistors 200 can be reduced.

[0459] Furthermore, in the semiconductor device shown in Figure 30, the transistor 200 has multiple channel formation regions for a single gate electrode. The transistor 200 shown in Figure 30 can obtain a large on-current by having multiple channel formation regions. In addition, since each channel formation region has a structure covered by a gate electrode, i.e., an s-channel structure, a large on-current can be obtained in each channel formation region. Alternatively, in the channel width direction of the transistor 200, the height of the bottom surface of the region of the conductor 260 where the conductor 260 and oxide 230b do not overlap, when the bottom surface of the insulator 222 is used as a reference, is lower than the height of the interface between the top surface of oxide 230b and oxide 230c, so a large on-current can be obtained in each channel formation region.

[0460] For other configurations, refer to the semiconductor device configuration shown in Figure 4.

[0461] <Examples of semiconductor device applications> In the following section, using Figures 31A and 31B, an example of a semiconductor device having a transistor 200 and an aperture region 400 according to one aspect of the present invention will be described, which differs from those shown in the previous <Example of Semiconductor Device Configuration> and <Modified Examples of Semiconductor Devices>. In the semiconductor device shown in Figures 31A and 31B, structures having the same function as those constituting the semiconductor device shown in <Example of Semiconductor Device Configuration> (see Figures 4A to 4D) will be denoted by the same reference numerals. In this section, the materials used for the transistor 200 can be those described in detail in <Example of Semiconductor Device Configuration> and <Modified Examples of Semiconductor Devices>.

[0462] Figures 31A and 31B show a configuration in which multiple transistors 200_1 to 200_n are enclosed and sealed with insulators 283 and 212. Note that in Figures 31A and 31B, transistors 200_1 to 200_n appear to be aligned in the channel length direction, but this is not the only arrangement. Transistors 200_1 to 200_n may be aligned in the channel width direction, or arranged in a matrix. Furthermore, they may be arranged without any regularity depending on the design.

[0463] As shown in Figure 31A, an aperture region 400 is positioned between adjacent transistors 200. By performing a heat treatment after the formation of the aperture region 400 in the semiconductor device manufacturing process, oxygen contained in the insulator 280 and hydrogen combined with that oxygen can be released to the outside through the aperture region 400. The hydrogen combined with oxygen is released as water. Therefore, the amount of unwanted oxygen and hydrogen contained in the insulator 280 can be reduced. In addition, a portion where the insulator 283 and the insulator 212 are in contact (hereinafter sometimes referred to as a sealing portion 265) is formed on the outside of multiple transistors 200_1 to 200_n. The sealing portion 265 is formed to surround multiple transistors 200_1 to 200_n. With this structure, multiple transistors 200_1 to 200_n can be enclosed by the insulator 283 and the insulator 212. Thus, multiple groups of transistors surrounded by the sealing portion 265 are provided on the substrate.

[0464] Furthermore, a dicing line (sometimes called a scribe line, division line, or cutting line) may be provided on top of the sealing portion 265. Since the substrate is divided at the dicing line, the group of transistors surrounded by the sealing portion 265 will be extracted as a single chip.

[0465] Furthermore, while Figure 31A shows an example where multiple transistors 200_1 to 200_n are enclosed by a single sealing portion 265, the configuration is not limited to this. As shown in Figure 31B, multiple transistors 200_1 to 200_n may be enclosed by multiple sealing portions. In Figure 31B, multiple transistors 200_1 to 200_n are enclosed by a sealing portion 265a, and further enclosed by an outer sealing portion 265b.

[0466] In this way, by surrounding multiple transistors 200_1 to 200_n with multiple sealing portions, the contact area between the insulator 283 and the insulator 212 increases, thereby improving the adhesion between the insulator 283 and the insulator 212. This allows for more reliable sealing of multiple transistors 200_1 to 200_n.

[0467] In this case, the dicing line may be provided on top of the sealing portion 265a or the sealing portion 265b, or the dicing line may be provided between the sealing portion 265a and the sealing portion 265b.

[0468] According to one aspect of the present invention, a semiconductor device with less variation in transistor characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided.

[0469] The configurations and methods described in this embodiment can be used in appropriate combination with other configurations and methods shown in this embodiment, or with configurations and methods shown in other embodiments or examples.

[0470] (Embodiment 2) In this embodiment, one form of a semiconductor device will be described using Figures 32 to 37.

[0471] [Storage device 1] Figure 32 shows an example of a semiconductor device (memory device) according to one aspect of the present invention. In the semiconductor device according to one aspect of the present invention, the transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above both the transistor 300 and the transistor 200. Note that the transistor 200 can be the same transistor 200 described in the previous embodiment.

[0472] Transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Because transistor 200 has a small off-current, it can be used in a memory device to retain stored data for a long period of time. In other words, because refresh operations are not required, or are performed very infrequently, the power consumption of the memory device can be significantly reduced.

[0473] In the semiconductor device shown in Figure 32, wire 1001 is electrically connected to the source of transistor 300, and wire 1002 is electrically connected to the drain of transistor 300. Wire 1003 is electrically connected to one of the source and drain of transistor 200, wire 1004 is electrically connected to the first gate of transistor 200, and wire 1006 is electrically connected to the second gate of transistor 200. The gate of transistor 300 and the other of the source and drain of transistor 200 are electrically connected to one of the electrodes of capacitive element 100, and wire 1005 is electrically connected to the other electrode of capacitive element 100.

[0474] Furthermore, the memory devices shown in Figure 32 can be arranged in a matrix to form a memory cell array.

[0475] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0476] In Figure 32, the transistor 300 has a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, the sides and top surface of the semiconductor region 313 are covered by a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulator in contact with the top of the convex portion, functioning as a mask for forming the convex portion. While this example shows the formation of the convex portion by processing a part of the semiconductor substrate, a semiconductor film with a convex shape may also be formed by processing an SOI substrate.

[0477] Note that the transistor 300 shown in Figure 32 is just one example, and its structure is not limited to that; any appropriate transistor can be used depending on the circuit configuration and driving method.

[0478] <Capacitive element 100> The capacitive element 100 is provided above the transistor 200. The capacitive element 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Here, it is preferable to use an insulator 130 that can be used as the insulator 286 shown in the above embodiment.

[0479] Furthermore, for example, the conductor 112 provided on the conductor 246 and the conductor 110 can be formed simultaneously. The conductor 112 functions as a plug or wiring that electrically connects to the capacitive element 100, the transistor 200, or the transistor 300.

[0480] In Figure 32, the conductors 112 and 110 are shown as single-layer structures, but the configuration is not limited to this, and a laminated structure of two or more layers is also possible. For example, a conductor with high adhesion to both the barrier conductor and the highly conductive conductor may be formed between the barrier conductor and the highly conductive conductor.

[0481] Furthermore, the insulator 130 may be made of, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide, aluminum oxide, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium oxide nitride, hafnium oxide nitride, hafnium nitride, etc., and can be provided in a laminated or single layer.

[0482] For example, it is preferable to use a laminated structure of a material with high dielectric strength, such as silicon oxidnitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitive element 100 can secure sufficient capacitance by having a high dielectric constant (high-k) insulator, and the dielectric strength is improved by having an insulator with high dielectric strength, thereby suppressing electrostatic discharge breakdown of the capacitive element 100.

[0483] Examples of high-dielectric constant (high-k) materials (materials with a high relative permittivity) that serve as insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0484] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, and porous silicon oxide or resins.

[0485] <Wiring layer> A wiring layer containing interlayer films, wiring, and plugs may be provided between each structure. Furthermore, multiple wiring layers may be provided depending on the design. Here, a conductor functioning as a plug or wiring may be grouped together and assigned the same reference numeral. Also, in this specification, the wiring and the plug that electrically connects to the wiring may be an integrated unit. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0486] For example, on the transistor 300, insulators 320, 322, 324, and 326 are sequentially stacked as interlayer films. Insulators 320, 322, 324, and 326 also have embedded conductive elements such as conductors 328 and 330 that are electrically connected to the capacitive element 100 or the transistor 200. Conductors 328 and 330 function as plugs or wiring.

[0487] Furthermore, the insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0488] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 32, insulators 350, 352, and 354 are stacked in order. Conductors 356 are formed on insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring.

[0489] Similarly, insulators 210, 212, 214, and 216 have conductors 218 and conductors (conductors 205) that constitute the transistor 200 embedded in them. Conductors 218 function as plugs or wires that electrically connect to the capacitive element 100 or the transistor 300. Furthermore, insulators 150 are provided on conductors 120 and insulator 130.

[0490] Here, similar to the insulator 241 shown in the above embodiment, an insulator 217 is provided in contact with the side surface of the conductor 218, which functions as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 212, 214, and 216. In other words, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, so the insulator 217 may also be formed in contact with the side surface of the conductor 205.

[0491] As the insulator 217, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 217 is provided in contact with insulators 210, 212, 214, and 222, it is possible to suppress the mixing of impurities such as water or hydrogen from insulators 210 or 216 into the oxide 230 through the conductor 218. Silicon nitride is particularly suitable because it has high blocking properties for hydrogen. In addition, it is possible to prevent oxygen contained in insulators 210 or 216 from being absorbed by the conductor 218.

[0492] The insulator 217 can be formed in the same manner as the insulator 241. For example, silicon nitride can be deposited using the PEALD method, and an opening reaching the conductor 356 can be formed using anisotropic etching.

[0493] Insulators that can be used as interlayer films include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0494] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0495] For example, it is preferable that insulators 150, 210, 352, and 354 have an insulator with a low dielectric constant. For example, it is preferable that the insulator has fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, or a resin. Alternatively, it is preferable that the insulator has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide, and a resin. Since silicon oxide and silicon oxynitride are thermally stable, combining them with a resin can create a thermally stable laminated structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic.

[0496] Furthermore, the electrical characteristics of a transistor using an oxide semiconductor can be stabilized by surrounding it with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, insulators 214, 212, and 350 should be insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0497] As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride or silicon nitride, etc., can be used.

[0498] Conductors that can be used for wiring and plugs may include materials containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0499] For example, conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials can be used as conductors 328, 330, 356, 218, and 112, either in a single layer or in a laminated form. It is preferable to use high-melting-point materials such as tungsten or molybdenum that provide both heat resistance and conductivity, with tungsten being preferable. Alternatively, it is preferable to form them from low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance.

[0500] <Wiring or plugs in layers containing oxide semiconductors> Furthermore, when an oxide semiconductor is used in the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, it is preferable to provide a barrier insulator between the insulator having the excess oxygen region and the conductor provided on the insulator having the excess oxygen region.

[0501] For example, in Figure 32, an insulator 241 may be provided between the insulators 224 and 280, which have excess oxygen, and the conductor 240. By providing the insulator 241 in contact with the insulators 222, 282, and 283, the insulator 224 and the transistor 200 can be sealed by the barrier insulator.

[0502] In other words, by providing the insulator 241, it is possible to suppress the absorption of excess oxygen present in the insulators 224 and 280 into the conductor 240. Furthermore, by having the insulator 241, it is possible to suppress the diffusion of hydrogen, which is an impurity, into the transistor 200 via the conductor 240.

[0503] Furthermore, as the insulator 241, an insulating material having the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen, is preferable. For example, silicon nitride, silicon oxide nitride, aluminum oxide, or hafnium oxide are preferred. Silicon nitride is particularly preferred because of its high blocking properties for hydrogen. In addition, other materials such as metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide can also be used.

[0504] Furthermore, as shown in the above embodiment, the transistor 200 may be configured to be sealed with insulators 212, 214, 282, and 283. This configuration reduces the amount of hydrogen contained in insulators 274, 150, etc., that mixes into insulator 280, etc.

[0505] Here, the conductor 240 penetrates insulators 283 and 282, and the conductor 218 penetrates insulators 214 and 212. However, as described above, insulator 241 is provided in contact with conductor 240, and insulator 217 is provided in contact with conductor 218. This reduces the amount of hydrogen that enters the inside of insulators 212, 214, 282, and 283 via conductors 240 and 218. In this way, the transistor 200 is sealed with insulators 212, 214, 282, 283, 241, and 217, reducing the amount of impurities such as hydrogen contained in insulator 274, etc., that enter from the outside.

[0506] <Dicing line> The following describes dicing lines (sometimes called scribe lines, division lines, or cutting lines) that are provided when extracting multiple semiconductor devices as chips by dividing a large-area substrate into individual semiconductor elements. One method of division is to first form grooves (dicing lines) in the substrate to divide the semiconductor elements, and then cut along the dicing lines to divide (divide) the substrate into multiple semiconductor devices.

[0507] Here, for example, as shown in Figure 32, it is preferable to design the region where insulator 283 and insulator 212 are in contact to overlap with the dicing line. In other words, in the vicinity of the region that will become the dicing line provided on the outer edge of the memory cell having multiple transistors 200, openings are provided in insulators 282, 280, 272, 224, 222, 216, and 214.

[0508] In other words, insulator 212 and insulator 283 are in contact with each other at the openings provided in insulators 282, 280, 272, 224, 222, 216, and 214. For example, in this case, insulators 212 and 283 may be formed using the same material and method. By providing insulators 212 and 283 using the same material and method, adhesion can be improved. For example, silicon nitride is preferably used.

[0509] This structure allows the transistor 200 to be enclosed by insulators 212, 214, 282, and 283. Since at least one of insulators 212, 214, 282, and 283 has the function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is divided into multiple chips for each circuit region on which the semiconductor element shown in this embodiment is formed, it is possible to prevent impurities such as hydrogen or water from entering from the side of the divided substrate and diffusing into the transistor 200.

[0510] Furthermore, this structure prevents excess oxygen from insulators 280 and 224 from diffusing to the outside. Therefore, excess oxygen from insulators 280 and 224 is efficiently supplied to the oxide in which the channel in transistor 200 is formed. This oxygen reduces oxygen deficiencies in the oxide in which the channel in transistor 200 is formed. As a result, the oxide in which the channel in transistor 200 is formed can be made into an oxide semiconductor with a low defect level density and stable properties. In other words, fluctuations in the electrical properties of transistor 200 can be suppressed and reliability can be improved.

[0511] In the memory device shown in Figure 32, the capacitive element 100 is of the planar type, but the memory device shown in this embodiment is not limited to this. For example, as shown in Figure 33, the capacitive element 100 may be of the cylindrical type. In the memory device shown in Figure 33, the configuration below the insulator 150 is the same as that of the semiconductor device shown in Figure 32.

[0512] The capacitive element 100 shown in Figure 33 includes an insulator 150 on an insulator 130, an insulator 142 on an insulator 150, a conductor 115 disposed in an opening formed in the insulators 150 and 142, an insulator 145 on the conductor 115 and 142, a conductor 125 on the insulator 145, and an insulator 152 on the conductor 125 and 145. Here, at least a portion of the conductor 115, the insulator 145, and the conductor 125 are disposed in the opening formed in the insulators 150 and 142.

[0513] The conductor 115 functions as the lower electrode of the capacitive element 100, the conductor 125 functions as the upper electrode of the capacitive element 100, and the insulator 145 functions as the dielectric of the capacitive element 100. In the openings of the insulators 150 and 142, the upper and lower electrodes of the capacitive element 100 are configured to face each other with the dielectric in between, not only on the bottom surface but also on the sides, allowing for a large capacitance per unit area. Therefore, the deeper the opening, the larger the capacitance of the capacitive element 100 can be. By increasing the capacitance per unit area of ​​the capacitive element 100 in this way, miniaturization or high integration of semiconductor devices can be promoted.

[0514] The insulator 152 may be any insulator that can be used for the insulator 280. Furthermore, the insulator 142 preferably functions as an etching stopper when forming the opening in the insulator 150, and may be any insulator that can be used for the insulator 214.

[0515] The shape of the openings formed in the insulators 150 and 142 when viewed from above may be a rectangle, a polygon other than a rectangle, a polygon with curved corners, or a circle including an ellipse. In this case, it is preferable that the area overlapping between the opening and the transistor 200 is large when viewed from above. By adopting such a configuration, the occupied area of ​​the semiconductor device having the capacitive element 100 and the transistor 200 can be reduced.

[0516] The conductor 115 is positioned in contact with the openings formed in the insulators 142 and 150. Preferably, the upper surface of the conductor 115 substantially coincides with the upper surface of the insulator 142. The lower surface of the conductor 115 is in contact with the conductor 110 through the opening in the insulator 130. The conductor 115 is preferably formed using the ALD method or the CVD method, and for example, any conductor that can be used for the conductor 205 may be used.

[0517] The insulator 145 is arranged to cover the conductor 115 and the insulator 142. For example, it is preferable to deposit the insulator 145 using the ALD method or the CVD method. The insulator 145 can be made of, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon, zirconium oxide, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium oxide nitride, hafnium nitride, hafnium oxide, hafnium nitride, etc., and can be provided in a laminated or single layer. For example, as the insulator 145, an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used.

[0518] Furthermore, it is preferable to use a material with high dielectric strength, such as silicon oxidative nitride, or a high dielectric constant (high-k) material for the insulator 145. Alternatively, a laminated structure of a material with high dielectric strength and a high dielectric constant (high-k) material may be used.

[0519] Examples of high-dielectric constant (high-k) materials (materials with a high relative permittivity) used as insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. By using such high-k materials, the capacitance of the capacitive element 100 can be sufficiently secured even if the insulator 145 is made thicker. By making the insulator 145 thicker, the leakage current generated between the conductor 115 and the conductor 125 can be suppressed.

[0520] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, and resins. For example, silicon nitride (SiN) deposited using the ALD method. x ), silicon oxide (SiO2) deposited using the PEALD method x ), silicon nitride (SiN) deposited using the ALD method x An insulating film can be used that is laminated in the order of zirconium oxide, silicon oxide deposited by the ALD method, and zirconium oxide. Alternatively, an insulating film can be used that is laminated in the order of zirconium oxide, silicon oxide deposited by the ALD method, and zirconium oxide. By using such an insulator with high dielectric strength, the dielectric strength is improved and electrostatic discharge breakdown of the capacitive element 100 can be suppressed.

[0521] The conductor 125 is positioned to fill the openings formed in the insulators 142 and 150. The conductor 125 is also electrically connected to the wiring 1005 via the conductors 140 and 153. The conductor 125 is preferably formed using the ALD method or CVD method, and for example, any conductor that can be used for the conductor 205 may be used.

[0522] Furthermore, the conductor 153 is provided on the insulator 154 and covered by the insulator 156. The conductor 153 may be any conductor that can be used for the conductor 112, and the insulator 156 may be any insulator that can be used for the insulator 152. Here, the conductor 153 is in contact with the upper surface of the conductor 140 and functions as a terminal of the capacitive element 100, the transistor 200, or the transistor 300.

[0523] [Storage device 2] An example of a semiconductor device (memory device) according to one aspect of the present invention is shown in Figures 34A and 34B.

[0524] <Example of memory device configuration 1> Figure 34A is a cross-sectional view of a semiconductor device having a memory device 290. The memory device 290 shown in Figure 34A has a capacitive device 292 in addition to the transistors 200 shown in Figures 4A to 4D. Figure 34A corresponds to a cross-sectional view of the transistor 200 in the channel length direction.

[0525] The capacitive device 292 comprises a conductor 242b, an insulator 271b provided on the conductor 242b, an insulator 272 provided in contact with the upper surface of the insulator 271b, the side surface of the insulator 271b, and the side surface of the conductor 242b, and a conductor 294 on the insulator 272. In other words, the capacitive device 292 constitutes a MIM (Metal-Insulator-Metal) capacitor. One of the pair of electrodes of the capacitive device 292, i.e., the conductor 242b, can also serve as the source electrode of the transistor. Furthermore, the dielectric layer of the capacitive device 292 can also serve as the protective layer provided on the transistor, i.e., the insulator 271 and the insulator 272. Therefore, since part of the transistor manufacturing process can be shared in the manufacturing process of the capacitive device 292, a highly productive semiconductor device can be produced. Furthermore, since one of the pair of electrodes of the capacitive device 292, namely the conductor 242b, also serves as the source electrode of the transistor, it is possible to reduce the area required for the placement of the transistor and the capacitive device.

[0526] For example, the conductor 294 can be any material that can be used for the conductor 242.

[0527] <Example of memory device configuration 2> Figure 34B is a cross-sectional view of a semiconductor device having a memory device 290, which has a different structure from that shown in Figure 34A. The memory device 290 shown in Figure 34B has a capacitive device 292 in addition to the transistor 200 shown in Figures 4A to 4D. Here, unlike the capacitive device 292 shown in Figure 34A, a portion of the capacitive device 292 shown in Figure 34B is provided in openings formed in the insulator 280, insulator 272, and insulator 271b. Note that Figure 34B corresponds to a cross-sectional view of the transistor 200 in the channel length direction.

[0528] The capacitive device 292 includes a conductor 242b, an insulator 293 provided on the conductor 242b, and a conductor 294 provided on the insulator 293. Here, the insulator 293 and the conductor 294 are arranged in openings formed in the insulators 280, 272, and 271b. The insulator 293 is provided in contact with the bottom surface and side walls of the opening. That is, the insulator 293 is in contact with the top surface of the conductor 242b, the side surface of the insulator 271b, the side surface of the insulator 272, and the side surface of the insulator 280. The insulator 293 is also provided so as to form a recess along the shape of the opening. The conductor 294 is provided in contact with the top surface and side surface of the insulator 293 so as to fill the recess. Note that the height of the upper surfaces of the insulator 293 and the conductor 294 may roughly coincide with the height of the upper surfaces of the insulator 280, the insulator 250, and the conductor 260.

[0529] Here, the conductor 242b functions as the lower electrode of the capacitive device 292, the conductor 294 functions as the upper electrode of the capacitive device 292, and the insulator 293 functions as the dielectric of the capacitive device 292. In this way, the capacitive device 292 constitutes a MIM capacitance. One of the pair of electrodes of the capacitive device 292, i.e., the conductor 242b, can also serve as the source electrode of the transistor. Therefore, in the manufacturing process of the capacitive device 292, part of the manufacturing process of the transistor can be shared, resulting in a highly productive semiconductor device. In addition, since the insulator 293 can be provided separately from the configuration of the transistor 200, the structure and material of the insulator 293 can be appropriately selected according to the performance required of the capacitive device 292. Furthermore, since one of the pair of electrodes of the capacitive device 292, i.e., the conductor 242b, also serves as the source electrode of the transistor, it is possible to reduce the area required for the placement of the transistor and the capacitive device.

[0530] It is preferable to use a high-dielectric-constant (high-k) material for the insulator 293. Examples of high-dielectric-constant (high-k) materials (materials with high relative permittivity) for insulators include gallium oxide, hafnium oxide, zirconium oxide, aluminum oxide, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium oxide nitride, hafnium nitride, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, or nitrides containing silicon and hafnium. Alternatively, a laminated film of these high-dielectric-constant materials may be used as the insulator 293. For example, an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used as the insulator 293.

[0531] Furthermore, the conductor 294 may be made of a material that can be used for the conductor 260, for example. Also, the conductor 294 may have a laminated structure similar to that of the conductor 260.

[0532] Note that the formation of the insulator 293 and the conductor 294 may be carried out before the deposition of the insulator 282, that is, before the process shown in Figure 20. The formation of the insulator 293 and the conductor 294 can be carried out in the same manner as the formation of the insulator 250 and the conductor 260. In other words, openings can be formed in the insulator 280, the insulator 272, and the insulator 271b, and a laminated film that will become the insulator 293 and the conductor 294 can be deposited in these openings. Then, a portion of the laminated film can be removed using CMP treatment to form the insulator 293 and the conductor 294.

[0533] <Examples of memory devices> In the following, using Figures 35A, 35B, 36, and 37, an example of a semiconductor device having a transistor 200, an aperture region 400, and a capacitive device 292 according to one aspect of the present invention, different from the one shown in the previous <Memory Device Configuration Example 1>, will be described. In the semiconductor device shown in Figures 35A, 35B, 36, and 37, structures having the same function as the structures constituting the semiconductor device shown in the previous embodiment and <Memory Device Configuration Example 1> (see Figure 34A) will be denoted by the same reference numerals. In this section, the constituent materials of the transistor 200, aperture region 400, and capacitive device 292 can be the same materials described in detail in the previous embodiment and <Memory Device Configuration Example 1>. Also, in Figures 35A, 35B, 36, and 37, the memory device shown in Figure 34A is used as the memory device, but it is not limited to this. For example, the memory device shown in Figure 34B may be used.

[0534] <<Differential Example of Memory Device 1>> In the following, an example of a semiconductor device 600 having transistors 200a, 200b, capacitive device 292a, and capacitive device 292b according to one aspect of the present invention will be described with reference to Figure 35A.

[0535] Figure 35A is a cross-sectional view in the channel length direction of a semiconductor device 600 having transistors 200a, 200b, capacitive devices 292a, and 292b. Here, the capacitive device 292a has a conductor 242a, an insulator 271a on the conductor 242a, an insulator 272 in contact with the upper surface of the insulator 271a, the side surface of the insulator 271a, and the side surface of the conductor 242a, and a conductor 294a on the insulator 272. The capacitive device 292b has a conductor 242b, an insulator 271b on the conductor 242b, an insulator 272 in contact with the upper surface of the insulator 271b, the side surface of the insulator 271b, and the side surface of the conductor 242b, and a conductor 294b on the insulator 272.

[0536] As shown in Figure 35A, the semiconductor device 600 has a symmetrical configuration with respect to the dashed line A3-A4 as the axis of symmetry. One of the source or drain electrodes of transistor 200a and the other of the source or drain electrode of transistor 200b are combined by the conductor 242c. An insulator 271c is provided on the conductor 242c. In addition, the conductor 246, which functions as wiring, and the conductor 240, which functions as a plug, are combined to connect transistors 200a and 200b. In this way, by using the above configuration for the connections between the two transistors, two capacitive devices, wiring and plugs, it is possible to provide a semiconductor device that can be miniaturized or highly integrated.

[0537] The configurations and effects of transistors 200a, 200b, capacitive device 292a, and 292b can be seen in the example semiconductor device configuration shown in Figure 34A.

[0538] <<Modified Memory Device 2>> In the above, transistors 200a, 200b, capacitive devices 292a, and 292b were given as examples of semiconductor device configurations, but the semiconductor device shown in this embodiment is not limited to these. For example, as shown in Figure 35B, a semiconductor device 600 and a semiconductor device having a similar configuration to semiconductor device 600 may be connected via a capacitive section. Alternatively, an aperture region 400 may be placed between adjacent semiconductor devices 600 and a semiconductor device having a similar configuration to semiconductor device 600. In this specification, a semiconductor device having transistors 200a, 200b, capacitive devices 292a, and 292b is referred to as a cell. The configurations of transistors 200a, 200b, capacitive devices 292a, and 292b can be considered in the above-mentioned descriptions relating to transistors 200a, 200b, capacitive devices 292a, and 292b.

[0539] Figure 35B is a cross-sectional view showing a semiconductor device 600 having transistors 200a and 200b, a capacitive device 292a, and a capacitive device 292b, and a cell having a similar configuration to the semiconductor device 600, connected via a capacitive section.

[0540] As shown in Figure 35B, the conductor 294b, which functions as one electrode of the capacitive device 292b of semiconductor device 600, also serves as one electrode of the capacitive device of semiconductor device 601, which has a similar configuration to semiconductor device 600. Although not shown, the conductor 294a, which functions as one electrode of the capacitive device 292a of semiconductor device 600, also serves as one electrode of the capacitive device of the semiconductor device adjacent to the left side of semiconductor device 600, i.e., in the A1 direction in Figure 35B. The same configuration applies to the cells on the right side of semiconductor device 601, i.e., in the A2 direction in Figure 35B. In other words, a cell array (also called a memory device layer) can be formed. By using such a cell array configuration, the spacing between adjacent cells can be reduced, thereby reducing the projected area of ​​the cell array and enabling high integration. Furthermore, by arranging the cell array configuration shown in Figure 35B in a matrix, a matrix-shaped cell array can be formed.

[0541] As described above, by forming transistors 200a, 200b, capacitive devices 292a, and 292b with the configuration shown in this embodiment, the cell area can be reduced, and the semiconductor device having a cell array can be miniaturized or highly integrated.

[0542] Furthermore, the cell array may be configured not only in a planar manner but also in a stacked manner. Figure 36 shows a cross-sectional view of a configuration in which n layers of cell array 610 are stacked. As shown in Figure 36, by stacking multiple cell arrays (cell array 610_1 to cell array 610_n), cells can be accumulated and arranged without increasing the occupied area of ​​the cell array. In other words, a 3D cell array can be constructed.

[0543] <Example 3 of a memory device> Figure 37 shows an example in which the memory unit 470 has a transistor layer 413 having a transistor 200T and four memory device layers 415 (memory device layers 415_1 to 415_4).

[0544] Each of the memory device layers 415_1 to 415_4 has a plurality of memory devices 420.

[0545] The memory device 420 is electrically connected to the memory device 420 on a different memory device layer 415 and the transistor 200T on the transistor layer 413 via the conductors 424 and 205.

[0546] The memory unit 470 is sealed by insulators 212, 214, 282, and 283 (referred to as the sealing structure below for convenience). An insulator 274 is provided around the insulator 283. In addition, a conductor 440 is provided on the insulators 274, 283, and 212, and is electrically connected to the element layer 411.

[0547] Furthermore, an insulator 280 is provided inside the sealing structure. The insulator 280 has the function of releasing oxygen upon heating. Alternatively, the insulator 280 has an excess oxygen region.

[0548] Furthermore, it is preferable that insulators 212 and 283 are materials that have a high blocking function for hydrogen. In addition, it is preferable that insulators 214 and 282 are materials that have the function of capturing or fixing hydrogen.

[0549] For example, materials that have a high blocking property for hydrogen include silicon nitride or silicon nitride oxide. Materials that have the function of capturing or fixing hydrogen include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0550] There are no particular limitations on the crystal structure of the materials used for insulators 212, 214, 282, and 283, but they may be amorphous or crystalline. For example, an amorphous aluminum oxide film is preferable as a material that has the function of capturing or fixing hydrogen. Amorphous aluminum oxide may capture and fix hydrogen in greater quantities than highly crystalline aluminum oxide.

[0551] Here, the excess oxygen in the insulator 280 can be considered in relation to the diffusion of hydrogen in the oxide semiconductor in contact with the insulator 280, as described below.

[0552] Hydrogen present in an oxide semiconductor diffuses to other structures via the insulator 280 in contact with the oxide semiconductor. This hydrogen diffusion occurs when excess oxygen in the insulator 280 reacts with hydrogen in the oxide semiconductor to form an OH bond, which then diffuses through the insulator 280. When the hydrogen atom with the OH bond reaches a material that has the function of capturing or fixing hydrogen (typically the insulator 282), the hydrogen atom reacts with oxygen atoms bonded to atoms in the insulator 282 (e.g., metal atoms), and is captured or fixed within the insulator 282. On the other hand, it is presumed that the oxygen atom of the excess oxygen that had the OH bond remains in the insulator 280 as excess oxygen. In other words, there is a high probability that the excess oxygen in the insulator 280 plays a bridging role in this hydrogen diffusion.

[0553] To satisfy the above model, the semiconductor device manufacturing process is one of the important factors.

[0554] As an example, an insulator 280 containing excess oxygen is formed on an oxide semiconductor, and then an insulator 282 is formed. After that, it is preferable to form an opening region 400 (not shown) and then perform a heat treatment. Specifically, this heat treatment is carried out in a nitrogen-containing atmosphere at a temperature of 350°C or higher, preferably 400°C or higher.

[0555] The above heat treatment allows oxygen contained in the insulator 280, and hydrogen combined with that oxygen, to be released to the outside through the opening region 400. The hydrogen combined with oxygen is released as water. Therefore, the amount of unwanted oxygen and hydrogen contained in the insulator 280 can be reduced.

[0556] After the above heat treatment, an insulator 283 is formed. Since the insulator 283 is a material with high hydrogen blocking properties, it can suppress hydrogen that has diffused outward or hydrogen present in the outside from entering the interior, specifically the oxide semiconductor or the insulator 280 side.

[0557] Furthermore, the heat treatment may be performed, for example, after the formation of the transistor layer 413, or after the formation of memory device layers 415_1 to 415_3. Specifically, the heat treatment is performed in an atmosphere containing nitrogen, or a mixed atmosphere of oxygen and nitrogen, at a temperature of 350°C or higher, preferably 400°C or higher. The heat treatment time is 1 hour or more, preferably 4 hours or more, and more preferably 8 hours or more. This heat treatment allows hydrogen in the oxide of the channel formation region to diffuse outward through the insulators 280 and 282. In other words, the absolute amount of water present in the oxide of the channel formation region and in the vicinity of the oxide of the channel formation region can be reduced. Also, when hydrogen is diffused outward by the heat treatment, the hydrogen diffuses upward or laterally towards the transistor layer 413. Similarly, when the heat treatment is performed after the formation of memory device layers 415_1 to 415_3, the hydrogen diffuses upward or laterally.

[0558] Furthermore, by following the above manufacturing process, the insulator 212 and the insulator 283 are bonded together, thereby forming the aforementioned sealing structure.

[0559] As described above, by using the above structure and manufacturing process, a semiconductor device using an oxide semiconductor with reduced hydrogen concentration can be provided. Therefore, a semiconductor device with good reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided.

[0560] The configurations and methods described in this embodiment can be used in appropriate combination with other configurations and methods shown in this embodiment, or with configurations and methods shown in other embodiments or examples.

[0561] (Embodiment 3) In this embodiment, a transistor using an oxide as a semiconductor (hereinafter sometimes referred to as an OS transistor) and a memory device to which a capacitive element is applied (hereinafter sometimes referred to as an OS memory device) according to one aspect of the present invention will be described with reference to Figures 38A, 38B and 39A to 39H. The OS memory device is a memory device having at least a capacitive element and an OS transistor that controls the charging and discharging of the capacitive element. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a non-volatile memory.

[0562] <Example of storage device configuration> Figure 38A shows an example of the configuration of an OS memory device. The storage device 1400 has peripheral circuits 1411 and a memory cell array 1470. The peripheral circuits 1411 have row circuits 1420, column circuits 1430, output circuits 1440, and control logic circuits 1460.

[0563] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has the function of precharging the wiring. The sense amplifier has the function of amplifying the data signal read from the memory cell. The above wiring is connected to the memory cells of the memory cell array 1470, and will be described in more detail later. The amplified data signal is output to the outside of the storage device 1400 as the data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, etc., and can select the row to access.

[0564] The memory device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from an external source. The memory device 1400 also receives control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA from an external source. The address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.

[0565] The control logic circuit 1460 processes externally input control signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. Control signal CE is the ch...

Claims

[Claim 1] The substrate has a first circuit region, a second circuit region, and a third insulator. The first circuit region is, It comprises a plurality of first transistors and a first insulator located above the plurality of first transistors, The aforementioned second circuit region is, It comprises a plurality of second transistors and a second insulator located above the plurality of second transistors, The second insulator has an opening, The first transistor and the second transistor each have an oxide semiconductor, The oxide semiconductor of the first transistor has a film thickness in the region overlapping with the gate electrode of the first transistor that is smaller than the film thickness in the region overlapping with the source electrode or drain electrode of the first transistor. The third insulator has a region in contact with the upper surface of the first insulator and a region in contact with the upper surface of the second insulator. A semiconductor device wherein the arrangement density of the plurality of first transistors in the first circuit region is higher than the arrangement density of the plurality of second transistors in the second circuit region.

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