Semiconductor equipment

Abstract

To provide a semiconductor device capable of suppressing a defect caused by a residual plating solution while improving the durable life of a main terminal.SOLUTION: A semiconductor element is disposed on a substrate 50, and a drain electrode is electrically connected to a front surface metal body 52. A solid-phase-bonding bonding part 120 is formed between a main terminal 91 and the front surface metal body 52. A plating film 130 is provided on the front surface metal body 52 and the main terminal 91 so as to cover the bonding part 120. The main terminal 91 includes, as an overlapping region 911 that overlaps the front surface metal body 52, a bonding region 912 that provides the bonding part and a non-bonding region 913 that is provided to be adjacent to the bonding region 912 in at least a width direction of the main terminal 91. The main terminal 91 is a wide terminal in which the overlapping region 911 is wider than the bonding part 120.SELECTED DRAWING: Figure 11

Description

Technical Field

[0001] The disclosure in this specification Semiconductor equipment relates to.

Background Art

[0002] Patent Document 1 discloses a semiconductor device. This semiconductor device includes a substrate (insulating substrate), a semiconductor element having main electrodes on both sides, and main terminals (external connection terminals). One of the main electrodes of the semiconductor element is connected to the surface metal body (metal foil) of the substrate via a solder layer. The main terminals are connected to the surface metal body by ultrasonic bonding or the like. The description of the prior art document is incorporated herein by reference as an explanation of the technical elements in this specification.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a configuration where the main terminals are ultrasonically bonded to the surface metal body of the substrate, the substrate may be damaged. From the above viewpoints, or from other viewpoints not mentioned, Semiconductor equipment further improvement is required.

[0005] One object to be disclosed is to provide Semiconductor equipment a semiconductor device capable of suppressing damage to the substrate.

Means for Solving the Problems

[0006] One semiconductor device disclosed is a semiconductor element (40) having a first main electrode (40D) provided on one surface and a second main electrode (40S) provided on the back surface opposite to the one surface in the plate thickness direction, A substrate (50) having an insulating substrate (51), a surface metal body (52) disposed on the surface of the insulating substrate and electrically connected to the first main electrode, and a back metal body (53) disposed on the surface opposite to the surface of the insulating substrate, A bonding material (100) is interposed between the first main electrode and the surface metal body to join the first main electrode and the surface metal body, Main terminals (91, 92, 93) that form a solid-state joint (120) with the surface metal body, Equipped with, The solid-phase joint is an ultrasonic joint. The main terminal is, This is the part that does not come into contact with the ultrasonic tool when forming the ultrasonic joint. Thick-walled section (934), This is the part that the ultrasonic tool contacts, and it is made thinner than the thicker part by a recess (933) that opens on the side opposite to the surface metal body side. It has a thin-walled portion (935), Multiple recesses (931) corresponding to the protrusions of the ultrasonic tool are formed on the bottom surface (933a) of the recess. Thin-walled section Of these, the portion where no recess is provided The thickness T3 is thinner than the thickness T2 of the surface metal body. The thickness T1 of the thickened section is greater than the thickness T2 of the surface metal body.

[0008] Disclosure Semiconductor equipment According to this research, it is possible to suppress substrate damage caused by ultrasonic bonding.

[0009] The various embodiments disclosed in this specification employ different technical means to achieve their respective objectives. The claims and the reference numerals in parentheses in this section are illustrative in their correspondence with the embodiments described later and are not intended to limit the technical scope. The objectives, features, and effects disclosed in this specification will become clearer by referring to the subsequent detailed description and the accompanying drawings. [Brief explanation of the drawing]

[0010] [Figure 1] This diagram shows the circuit configuration of a power conversion device to which the semiconductor device according to the first embodiment is applied. [Figure 2] This is a perspective view showing a semiconductor device. [Figure 3] This is a plan view showing a semiconductor device. [Figure 4]It is a plan view showing a substrate on the drain electrode side. [Figure 5] It is a plan view showing a substrate on the source electrode side. [Figure 6] It is a cross-sectional view taken along line VI-VI of FIG. 3. [Figure 7] It is a cross-sectional view taken along line VII-VII of FIG. 3. [Figure 8] It is a perspective view showing a state where a substrate on the drain electrode side and a lead frame are joined. [Figure 9] It is a plan view showing a connection structure between a substrate on the drain electrode side and a main terminal. [Figure 10] It is an enlarged view of region X in FIG. 9. [Figure 11] It is a cross-sectional view taken along line XI-XI of FIG. 10. [Figure 12] It is a plan view showing a modified example. [Figure 13] It is a plan view showing a modified example. [Figure 14] It is a plan view showing a modified example. [Figure 15] It is a plan view showing a modified example. [Figure 16] It is a cross-sectional view showing a reference example. [Figure 17] It is a cross-sectional view showing a reference example. [Figure 18] It is a cross-sectional view showing a reference example. [Figure 19] In the semiconductor device according to the second embodiment, it is a perspective view showing an enlarged view around a joint portion between a main terminal and a surface metal body. [Figure 20] It is a cross-sectional view taken along line XX-XX of FIG. 19. [Figure 21] It is a cross-sectional view showing a process of ultrasonic bonding. [Figure 22] In the manufacturing method of the semiconductor device according to the third embodiment, it is a cross-sectional view showing ultrasonic bonding between a main terminal and a surface metal body. [Figure 23] It is a cross-sectional view showing an example of a semiconductor device. [Figure 24] It is a cross-sectional view showing a modified example. [Figure 25]This is a cross-sectional view showing the area around the junction between the main terminal and the surface metal body in a semiconductor device according to the fourth embodiment. [Figure 26] This is a cross-sectional view showing the area around the separation portion of the back metal body in a semiconductor device according to the fifth embodiment. [Figure 27] This is a plan view showing an example of the pattern on the back surface of the metal body. [Modes for carrying out the invention]

[0011] Several embodiments will be described below with reference to the drawings. In each embodiment, the same reference numerals are used for corresponding components, and redundant explanations may be omitted. If only a part of the configuration is described in each embodiment, the configuration of other embodiments described earlier can be applied to the other parts of that configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations from multiple embodiments can be partially combined even if not explicitly stated, as long as there are no particular problems with the combination.

[0012] The semiconductor device of this embodiment is applied, for example, to a power conversion device for a mobile body that uses a rotating electric machine as a drive source. Examples of mobile bodies include electric vehicles such as battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), and plug-in hybrid electric vehicles (PHEVs), as well as aircraft such as electric vertical take-off and landing aircraft and drones, ships, construction machinery, and agricultural machinery. An example of its application to a vehicle will be described below.

[0013] (First Embodiment) First, the general configuration of the vehicle's drive system 1 will be explained based on Figure 1.

[0014] <Vehicle drive system> As shown in Figure 1, the vehicle's drive system 1 includes a DC power supply 2, a motor generator 3, and a power converter 4.

[0015] The DC power supply 2 is a DC voltage source composed of rechargeable secondary batteries. These secondary batteries are, for example, lithium-ion batteries or nickel-metal hydride batteries. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as the vehicle's driving source, i.e., an electric motor. During regeneration, the motor generator 3 functions as a generator. The power converter 4 performs power conversion between the DC power supply 2 and the motor generator 3.

[0016] <Power converter> Next, the circuit configuration of the power converter 4 will be described based on Figure 1. The power converter 4 is equipped with a power conversion circuit. The power converter 4 in this embodiment is equipped with a smoothing capacitor 5 and an inverter 6 which is a power conversion circuit.

[0017] The smoothing capacitor 5 primarily smooths the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to the P line 7, which is the high-potential power line, and the N line 8, which is the low-potential power line. The P line 7 is connected to the positive terminal of the DC power supply 2, and the N line 8 is connected to the negative terminal of the DC power supply 2. The positive terminal of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. The negative terminal of the smoothing capacitor 5 is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

[0018] The inverter 6 is a DC-AC conversion circuit. The inverter 6 converts a DC voltage to a three-phase AC voltage according to switching control by a control circuit (not shown) and outputs it to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to the rotational force from the wheels to a DC voltage according to switching control by the control circuit and outputs it to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power supply 2 and the motor generator 3.

[0019] The inverter 6 is configured with three phase upper and lower arm circuits 9. The upper and lower arm circuits 9 are sometimes referred to as legs. The upper and lower arm circuits 9 each have an upper arm 9H and a lower arm 9L. The upper arm 9H and lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. The connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the motor generator 3 via the output line 10. The inverter 6 has six arms. Each arm is configured with a switching element. At least a portion of each of the P line 7, N line 8, and output line 10 is made of conductive material such as a busbar.

[0020] In this embodiment, an n-channel type MOSFET 11 is used as the switching element constituting each arm. The number of switching elements constituting each arm is not particularly limited; there may be one or more. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0021] As an example, in this embodiment, each arm has one MOSFET 11. In the upper arm 9H, the drain of the MOSFET 11 is connected to the P line 7. In the lower arm 9L, the source of the MOSFET 11 is connected to the N line 8. The source of the MOSFET 11 in the upper arm 9H and the drain of the MOSFET 11 in the lower arm 9L are interconnected.

[0022] Each MOSFET 11 has a freewheeling diode 12 connected in antiparallel. Diode 12 may be a parasitic diode (body diode) of the MOSFET 11, or it may be a separate diode. The anode of diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode is connected to the drain.

[0023] Note that the switching element is not limited to MOSFET11. For example, an IGBT may be used. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. A diode for freewheeling is also connected in antiparallel to the IGBT.

[0024] The power converter 4 may further include a converter as a power conversion circuit. The converter is a DC-DC converter circuit that converts a DC voltage to a DC voltage of a different value. The converter is placed between the DC power supply 2 and the smoothing capacitor 5. The converter is configured, for example, with a reactor and the above-described up-and-down arm circuit 9. With this configuration, step-up and step-down voltage conversion is possible. The power converter 4 may also include a filter capacitor to remove power supply noise from the DC power supply 2. The filter capacitor is placed between the DC power supply 2 and the converter.

[0025] The power converter 4 may include a drive circuit for the switching elements that make up the inverter 6, etc. The drive circuit supplies a drive voltage to the gate of the corresponding arm's MOSFET 11 based on a drive command from the control circuit. The drive circuit drives the corresponding MOSFET 11, i.e., turns it on or off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0026] The power converter 4 may include a control circuit for the switching element. The control circuit generates a drive command to operate the MOSFET 11 and outputs it to the drive circuit. The control circuit generates the drive command based on, for example, a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. ECU is an abbreviation for Electronic Control Unit.

[0027] Various sensors include, for example, current sensors, rotation angle sensors, and voltage sensors. The current sensor detects the phase current flowing through the windings 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit is configured, for example, with a processor and memory. PWM is an abbreviation for Pulse Width Modulation.

[0028] <Semiconductor device> Next, the schematic configuration of the semiconductor device will be described based on Figures 2 to 8. Figure 2 is a perspective view of the semiconductor device. Figure 3 is a plan view showing the semiconductor device. In Figure 3, elements covered by the encapsulant are shown with dashed lines. Figure 4 is a plan view showing the substrate on the drain electrode side. Figure 5 is a plan view showing the substrate on the source electrode side. Figures 4 and 5 show the patterns of the surface metal body. In Figures 4 and 5, the semiconductor element, conductive spacer, and substrate connection part are shown with dashed lines to show their positional relationship with the surface metal body. Figure 6 is a cross-sectional view along the line VI-VI in Figure 3. Figure 7 is a cross-sectional view along the line VII-VII in Figure 3. Figure 8 is a perspective view showing the state in which the lead frame is bonded to the substrate on the drain electrode side.

[0029] In the following, the thickness direction of the semiconductor element (semiconductor substrate) will be defined as the Z direction, and the direction in which the semiconductor elements are arranged will be defined as the X direction. The direction perpendicular to both the Z and Y directions will be defined as the Y direction. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, will be defined as the planar shape.

[0030] The semiconductor device 20 shown in Figures 2 and 3 constitutes one of the upper and lower arm circuits 9, that is, one phase of the upper and lower arm circuit 9. The semiconductor device 20 comprises a encapsulant 30, a semiconductor element 40, substrates 50, 60, a conductive spacer 70, substrate connection parts 80, 81, and an external connection terminal 90.

[0031] The encapsulant 30 encapsulates some of the other elements that make up the semiconductor device 20. The remaining parts of the other elements are exposed outside the encapsulant 30. The encapsulant 30 is made of, for example, a resin. An example of a resin is an epoxy resin. The encapsulant 30 is molded from resin by, for example, a transfer molding method. Such an encapsulant 30 may be called a resin encapsulant, molded resin, or resin molded body. The encapsulant 30 may also be formed using, for example, a gel. The gel is filled (placed) in opposing regions of a pair of substrates 50, 60, for example.

[0032] As shown in Figures 2 and 3, the seal 30 has a roughly rectangular shape in plan. The seal 30 has one surface 30a and a back surface 30b which is opposite to the one surface 30a in the Z direction. The one surface 30a and the back surface 30b are, for example, flat surfaces. It also has sides 30c, 30d, 30e, and 30f which are surfaces connecting the one surface 30a and the back surface 30b. Side 30c is the surface from which the main terminals 91, 92, and 93 of the external connection terminals 90 protrude. Side 30d is the surface opposite to side 30c in the Y direction. Side 30d is the surface from which the signal terminal 94 protrudes. Sides 30e and 30f are surfaces from which the external connection terminals 90 do not protrude. Side 30e is the surface opposite to side 30f in the X direction.

[0033] The semiconductor device 40 is formed by forming a switching element on a semiconductor substrate made of materials such as silicon (Si) or a wide-bandgap semiconductor with a wider bandgap than silicon. Examples of wide-bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. The semiconductor device 40 is sometimes referred to as a power device or semiconductor chip.

[0034] The semiconductor element 40 of this embodiment is formed by creating the above-described n-channel type MOSFET 11 on a semiconductor substrate made of SiC. The MOSFET 11 has a vertical structure such that the main current flows in the thickness direction of the semiconductor element 40 (semiconductor substrate), i.e., in the Z direction. The semiconductor element 40 has main electrodes for the switching element on both sides in the Z direction, which is the thickness direction of the semiconductor element itself. Specifically, as main electrodes, it has a drain electrode 40D on one side and a source electrode 40S on the back side, which is the side opposite to the other side in the Z direction. The main current flows between the drain electrode 40D and the source electrode 40S. The drain electrode 40D corresponds to the first main electrode, and the source electrode 40S corresponds to the second main electrode.

[0035] If diode 12 is a parasitic diode, the source electrode 40S also serves as the anode electrode, and the drain electrode 40D also serves as the cathode electrode. Diode 12 may be configured on a separate chip from MOSFET 11. The drain electrode 40D is the main electrode on the high-potential side, and the source electrode 40S is the main electrode on the low-potential side.

[0036] The semiconductor element 40 has a planar shape that is approximately rectangular, for example, approximately square. As shown in Figures 3 and 7, the semiconductor element 40 has a pad 40P on its back surface, which is a signal electrode. The pad 40P is formed at a different position on the back surface from the source electrode 40S. The pad 40P includes at least a gate pad. The semiconductor element 40 of this embodiment has three pads 40P. For example, the pad 40P includes a gate pad, a Kelvin source pad, and a current sense pad. The gate pad 40P is for applying a drive voltage to the gate electrode of the MOSFET 11. The Kelvin source pad 40P is for detecting the source potential of the MOSFET 11, that is, the potential of the source electrode 40S. The current sense pad 40P is for detecting a sense current proportional to the main current, and thereby detecting the main current.

[0037] The semiconductor element 40 includes semiconductor element 40H which constitutes the upper arm 9H and semiconductor element 40L which constitutes the lower arm 9L. The configurations of semiconductor elements 40H and 40L are common to each other. For example, there is one of each semiconductor element 40H and 40L. As shown in Figure 3, the semiconductor elements 40H and 40L are aligned in the X direction. Each semiconductor element 40 is positioned at approximately the same location in the Z direction. The drain electrode 40D of each semiconductor element 40 faces the substrate 50. The source electrode 40S of each semiconductor element 40 faces the substrate 60.

[0038] The substrates 50 and 60 are arranged in the Z direction so as to sandwich the semiconductor element 40. The substrates 50 and 60 are arranged so that at least a portion of them faces each other in the Z direction. In a plan view, the substrates 50 and 60 enclose the entire semiconductor element 40 (40H, 40L).

[0039] Substrate 50 is positioned on the drain electrode 40D side relative to the semiconductor element 40. Substrate 60 is positioned on the source electrode 40S side relative to the semiconductor element 40. Substrate 50 is electrically connected to the drain electrode 40D as described later and provides a wiring function. Similarly, substrate 60 is electrically connected to the source electrode 40S and provides a wiring function. For this reason, substrates 50 and 60 are sometimes referred to as wiring members or wiring boards. Substrate 50 is sometimes referred to as a drain substrate, and substrate 60 is sometimes referred to as a source substrate. Substrates 50 and 60 provide a heat dissipation function to dissipate the heat generated by the semiconductor element 40. For this reason, substrates 50 and 60 are sometimes referred to as heat dissipation members.

[0040] Substrate 50 has a facing surface 50a that faces the semiconductor element 40 and a back surface 50b that is opposite to the facing surface 50a. Substrate 50 comprises an insulating substrate 51, a surface metal body 52, and a back surface metal body 53. Substrate 60 has a facing surface 60a that faces the semiconductor element 40 and a back surface 60b that is opposite to the facing surface 60a. Substrate 60 comprises an insulating substrate 61, a surface metal body 62, and a back surface metal body 63. Hereinafter, surface metal bodies 52, 62 and back surface metal bodies 53, 63 may be simply referred to as metal bodies 52, 53, 62, 63. Substrate 50 is a substrate in which the insulating substrate 51 and metal bodies 52, 53 are laminated. Substrate 60 is a substrate in which the insulating substrate 61 and metal bodies 62, 63 are laminated.

[0041] The insulating substrate 51 electrically separates the surface metal body 52 from the back metal body 53. Similarly, the insulating substrate 61 electrically separates the surface metal body 62 from the back metal body 63. The insulating substrates 51 and 61 are sometimes referred to as insulating layers. The material of the insulating substrates 51 and 61 is resin or an inorganic ceramic material. As resins, for example, epoxy resins and polyimide resins can be used. As ceramics, for example, Al2O3 (alumina) and Si3N4 (silicon nitride) can be used. When the insulating substrates 51 and 61 are resin, the substrates 50 and 60 are sometimes referred to as metal-resin substrates. When the insulating substrates 51 and 61 are ceramic, the substrates 50 and 60 are sometimes referred to as metal-ceramic substrates.

[0042] Considering heat dissipation and insulation, in the case of resin-based materials, the thickness of each insulating substrate 51 and 61, i.e., the length in the Z direction, is preferably about 50 μm to 300 μm. In the case of ceramic-based materials, the thickness of the insulating substrates 51 and 61 is preferably about 200 μm to 500 μm. In the Z direction, the surface of the insulating substrates 51 and 61 is the inner surface, i.e., the surface facing the semiconductor element 40, and the back surface, which is the surface opposite to the surface in the Z direction, is the outer surface. The insulating substrates 51 and 61 may have the same material composition, or they may have different material compositions. In this embodiment, the insulating substrates 51 and 61 have the same material composition.

[0043] The metal bodies 52, 53, 62, and 63 are provided, for example, as metal plates or metal foils. The metal bodies 52, 53, 62, and 63 are formed from metals with good electrical and thermal conductivity, such as Cu. The thickness of each of the metal bodies 52, 53, 62, and 63 is, for example, about 0.1 mm to 3 mm. The surface metal body 52 is located on the surface of the insulating substrate 51 in the Z direction. The back metal body 53 is located on the back surface of the insulating substrate 51. Similarly, the surface metal body 62 is located on the surface of the insulating substrate 61 in the Z direction. The back metal body 63 is located on the back surface of the insulating substrate 61.

[0044] The relationship between the thicknesses of the surface metal bodies 52, 62 and the back metal bodies 53, 63 is not particularly limited. The thickness of the surface metal body 52 may be thicker than that of the back metal body 53, or it may be approximately equal to that of the back metal body 53. The thickness of the surface metal body 52 may be thinner than that of the back metal body 53. Similarly, the thickness of the surface metal body 62 may be thicker than that of the back metal body 63, or it may be approximately equal to that of the back metal body 63. The thickness of the surface metal body 62 may be thinner than that of the back metal body 63. The relationship between the thicknesses of the surface metal bodies 52, 62 is not particularly limited, nor is the relationship between the thicknesses of the back metal bodies 53, 63.

[0045] The surface metal bodies 52 and 62 are patterned. The surface metal bodies 52 and 62 provide wiring, i.e., circuits. For this reason, the surface metal bodies 52 and 62 are sometimes referred to as circuit patterns, wiring layers, circuit conductors, etc. The surface of the surface metal body 52 and the area on the surface of the insulating substrate 51 where the surface metal body 52 is not placed form the opposing surface 50a of the substrate 50. Similarly, the surface of the surface metal body 62 and the area on the surface of the insulating substrate 61 where the surface metal body 62 is not placed form the opposing surface 60a of the substrate 60.

[0046] For example, surface metal bodies 52 and 62, patterned into a predetermined shape by pressing or etching, may be prepared and then attached to a two-layer laminate consisting of insulating substrates 51 and 61 and back metal bodies 53 and 63 to form substrates 50 and 60. Alternatively, after forming a three-layer laminate consisting of surface metal bodies 52 and 62, insulating substrates 51 and 61, and back metal bodies 53 and 63, the surface metal bodies 52 and 62 may be patterned by cutting or etching.

[0047] As shown in Figures 3, 4, 6, and 7, the surface metal body 52 has P wiring 54, intermediate wiring 55, and N wiring 56. The P wiring 54, intermediate wiring 55, and N wiring 56 are electrically isolated from each other by a predetermined interval (gap). This gap is filled with a sealant 30.

[0048] The P wiring 54 is connected to the main terminal 91 and the drain electrode 40D of the semiconductor element 40H. The P wiring 54 electrically connects the main terminal 91 and the drain electrode 40D of the semiconductor element 40H. As an example, the P wiring 54 has a base portion 541 and extension portions 542 and 543. The base portion 541 encloses the semiconductor element 40H in a plan view. The base portion 541 has a substantially rectangular shape in plan with the Y direction as its longitudinal direction.

[0049] The extensions 542 and 543 extend from the base 541 in the Y direction. The length in the X direction, i.e., the width, of each extension 542 and 543 is narrower than the width of the base 541. The extensions 542 and 543 provide at least a portion of the area to which the lead frame element, including the external connection terminal 90, is connected. The extension 542 is connected to one side of the base 541, which has a substantially rectangular shape in plan, and the extension 543 is connected to the side opposite to the extension 542. The main terminal 91 is connected to the extension 542, and the support frame 98, which will be described later, is connected to the extension 543. The lead frame element may be connected only to the extensions 542 and 543, or it may be connected across the base 541 and the extensions 542 and 543. The extensions 542 and 543 may be omitted, and the lead frame element may be connected only to the base 541.

[0050] The relay wiring 55 is connected to the drain electrode 40D of the semiconductor element 40L, the substrate connection portion 80, and the main terminal 93. The relay wiring 55 electrically connects the substrate connection portion 80 and the drain electrode 40D of the semiconductor element 40L. The relay wiring 55 electrically connects the source electrode 40S of the semiconductor element 40H and the drain electrode 40D of the semiconductor element 40L to the main terminal 93. As an example, the relay wiring 55 has a base portion 551 and extension portions 552, 553, and 554. The base portion 551 encloses the semiconductor element 40L in a plan view. The base portion 551 has a substantially rectangular shape in plan with the Y direction as its longitudinal direction.

[0051] The extensions 552 and 553 extend from the base 551 in the Y direction. The length in the X direction, i.e., the width, of each extension 552 and 553 is narrower than the width of the base 551. The extensions 552 and 553 provide at least a portion of the area to which the lead frame element, including the external connection terminal 90, is connected. The extension 552 is connected to one side of the base 551, which has a substantially rectangular shape in plan, and the extension 553 is connected to the side opposite to the extension 552. The main terminal 93 is connected to the extension 552, and the support frame 98 is connected to the extension 553. The lead frame element may be connected only to the extensions 552 and 553, or it may be connected across the base 551 and the extensions 552 and 553. The extensions 552 and 553 may be omitted, and the lead frame element may be connected only to the base 551.

[0052] The extension 554 encloses the substrate connection portion 80 in a plan view. The extension 554 is connected to one side of the base portion 551, which has a roughly rectangular shape in plan. The extension 554 extends in the X direction toward the base portion 541 from the side of the base portion 551 opposite the P wiring 54. In the Y direction, the length of the extension 554 is shorter than the length of the base portion 551. The relay wiring 55 is generally roughly L-shaped in plan.

[0053] The N wiring 56 is connected to the board connection portion 81 and the main terminal 92. The N wiring 56 electrically connects the board connection portion 81 and the main terminal 92. In a plan view, the N wiring 56 encloses the board connection portion 81. As an example, the N wiring 56 has a roughly rectangular shape in plan with the Y direction as its longitudinal direction.

[0054] On the surface metal body 52, the P wiring 54 and the relay wiring 55 are arranged side by side in the X direction. The N wiring 56 is arranged between the base portions 541 and 551 in the X direction. The N wiring 56 is aligned with the extension portion 554 in the Y direction.

[0055] The surface metal body 62 has N wiring 64 and intermediate wiring 65. The N wiring 64 and intermediate wiring 65 are electrically isolated by a predetermined gap. This gap is filled with a sealant 30.

[0056] The N wiring 64 is connected to the source electrode 40S of the semiconductor element 40L and the substrate connection portion 81. The N wiring 64 electrically connects the source electrode 40S of the semiconductor element 40L to the substrate connection portion 81. The N wiring 64, together with the N wiring 56 of the substrate 50 and the substrate connection portion 81, electrically connects the source electrode 40S of the semiconductor element 40L to the main terminal 92.

[0057] The N wiring 64 has a base portion 641 and an extension portion 642. The N wiring 64 has a substantially L-shape in plan view. The base portion 641 has a substantially rectangular shape in plan view with the Y direction as its longitudinal direction. The base portion 641 encloses the semiconductor element 40L in plan view. The extension portion 642 is connected to one of the sides of the base portion 641, which has a substantially rectangular shape in plan view. The extension portion 642 extends toward the base portion 651 in the X direction from the side of the base portion 641 opposite to the relay wiring 65. At least a part of the extension portion 642 overlaps with the N wiring 56 in plan view.

[0058] The relay wiring 65 is connected to the source electrode 40S of the semiconductor element 40H and the substrate connection portion 80. The relay wiring 55 electrically connects the source electrode 40S of the semiconductor element 40H and the substrate connection portion 80. The relay wiring 65 has a base portion 651 and an extension portion 652. The relay wiring 65 is substantially L-shaped in plan view. The base portion 651 is substantially rectangular in plan view. The base portion 651 encloses the semiconductor element 40H in plan view. The extension portion 652 is connected to one of the sides of the base portion 651, which is substantially rectangular in plan view. The extension portion 652 extends in the Y direction toward the base portion 641 from the side of the base portion 651 opposite to the N wiring 64. At least a part of the extension portion 652 overlaps with the extension portion 554 of the relay wiring 55 in plan view.

[0059] The N wiring 64 and the relay wiring 65 are arranged side by side in the X direction. The base portions 641 and 651 are aligned in the X direction. The source electrode 40S of the semiconductor element 40L is electrically connected to the base portion 641. The source electrode 40S of the semiconductor element 40H is electrically connected to the base portion 651. The extension portions 642 and 652 are aligned in the Y direction.

[0060] The back metal bodies 53, 63 are electrically isolated from the circuit including the semiconductor element 40 and the front metal bodies 52, 62 by insulating substrates 51, 61. The back metal bodies 53, 63 are sometimes referred to as metal base substrates. The heat generated by the semiconductor element 40 is transferred to the back metal bodies 53, 63 via the front metal bodies 52, 62 and insulating substrates 51, 61. The back metal bodies 53, 63 provide a heat dissipation function.

[0061] As an example, the back metal bodies 53 and 63 have a roughly rectangular shape in plan. The back metal bodies 53 and 63 are so-called solid conductors arranged over almost the entire back surface of the insulating substrates 51 and 61. Alternatively, the back metal bodies 53 and 63 may be patterned so that they substantially coincide with the front metal bodies 52 and 62 in plan view.

[0062] To further enhance the heat dissipation effect, at least one of the back metal bodies 53 and 63 may be exposed from the sealant 30. In this embodiment, the back metal body 53 is exposed from one side 30a of the sealant 30, and the back metal body 63 is exposed from the back side 30b. The exposed surface of the back metal body 53 is substantially flush with the one side 30a. The exposed surface of the back metal body 63 is substantially flush with the back side 30b. The back metal bodies 53 and 63 constitute the back sides 50b and 60b of the substrates 50 and 60.

[0063] The conductive spacer 70 provides a spacer function to ensure a predetermined gap between the semiconductor element 40 and the substrate 60. The conductive spacer 70 ensures wire height for electrically connecting the corresponding signal terminal 94 to the pad 40P of the semiconductor element 40. The conductive spacer 70 is located in the middle of the electrical and thermal conduction path between the source electrode 40S of the semiconductor element 40 and the substrate 60, and provides wiring and heat dissipation functions. The conductive spacer 70 contains a metallic material with good electrical and thermal conductivity, such as Cu.

[0064] The conductive spacer 70 is sometimes referred to as a terminal, terminal block, or metal block. The semiconductor device 20 is equipped with the same number of conductive spacers 70 as the semiconductor elements 40. Specifically, it is equipped with two conductive spacers 70. The conductive spacers 70 are individually connected to the semiconductor elements 40. The conductive spacer 70 is a columnar body that is approximately the same size as or slightly smaller than the source electrode 40S in a plan view. One of the conductive spacers 70 electrically connects the source electrode 40S of the semiconductor element 40H to the relay wiring 65. The other conductive spacer 70 electrically connects the source electrode 40S of the semiconductor element 40L to the N wiring 64.

[0065] The substrate connection sections 80 and 81 electrically connect the surface metal body 52 of substrate 50 and the surface metal body 62 of substrate 60. In other words, they connect the substrates to each other. The substrate connection section 80 electrically connects the relay wiring 55 and 65. The substrate connection section 80 is located between semiconductor element 40H and semiconductor element 40L in the X direction. In a plan view, the substrate connection section 80 is located in the overlapping region between the extended portion 554 of relay wiring 55 and the extended portion 652 of relay wiring 65. The substrate connection section 81 is also located between semiconductor element 40H and semiconductor element 40L in the X direction. In a plan view, the substrate connection section 81 is located in the overlapping region between the extended portion 642 of N wiring 56 and N wiring 64.

[0066] As an example, each of the substrate connection parts 80 and 81 is a metal columnar body. In the Z direction, a bonding material 103 is interposed between one end of the substrate connection part 80 and the relay wiring 55, and between the other end and the relay wiring 65. In the Z direction, a bonding material 103 is interposed between one end of the substrate connection part 81 and the N wiring 56, and between the other end and the N wiring 64.

[0067] Alternatively, the substrate connection portions 80 and 81 may be continuously connected to at least one of the surface metal bodies 52 and 62. In other words, the substrate connection portions 80 and 81 may be integrally provided with the surface metal bodies 52 and 62 as part of the substrates 50 and 60. The substrate connection portions 80 and 81 may also consist only of the bonding material 103.

[0068] The external connection terminal 90 is a terminal for electrically connecting the semiconductor device 20 to an external device. The external connection terminal 90 is formed using a metal material with good conductivity, such as copper. The external connection terminal 90 is, for example, a plate. The external connection terminal 90 is sometimes referred to as a lead. The external connection terminal 90 includes main terminals 91, 92, 93 and signal terminals 94. The main terminals 91, 92, 93 are external connection terminals 90 that are electrically connected to the main electrodes of the semiconductor element 40. The signal terminal 94 includes signal terminal 94H on the upper arm 9H side and signal terminal 94L on the lower arm 9L side.

[0069] The main terminals 91 and 92 are external connection terminals 90 that are electrically connected to the power lines 7 and 8 described above. Main terminal 91 is electrically connected to the positive terminal of the smoothing capacitor 5. Main terminal 91 is sometimes referred to as the positive terminal, high-potential power terminal, or P terminal. Main terminal 91 is connected to the P wiring 54 of the surface metal body 52. ​​In other words, main terminal 91 is electrically connected to the drain electrode 40D of the semiconductor element 40H that constitutes the upper arm 9H. Main terminal 91 is connected near one end in the Y direction of the P wiring 54. Main terminal 91 extends in the Y direction and protrudes outside the encapsulant 30 from the side surface 30c.

[0070] The main terminal 92 is electrically connected to the negative terminal of the smoothing capacitor 5. The main terminal 92 is sometimes referred to as the negative terminal, low-potential power supply terminal, or N terminal. The main terminal 92 is connected to the N wiring 56 of the surface metal body 52. ​​In other words, the main terminal 92 is electrically connected to the source electrode 40S of the semiconductor element 40L that constitutes the lower arm 9L. The main terminal 92 is connected to the vicinity of one end in the Y direction of the N wiring 56. The main terminal 92 extends in the Y direction and protrudes out of the encapsulant 30 from the side surface 30c.

[0071] The main terminal 93 is electrically connected to the corresponding phase winding 3a (stator coil) of the motor generator 3. The main terminal 93 is sometimes referred to as the O terminal or AC terminal. The main terminal 93 is connected to the relay wiring 55 of the surface metal body 52. ​​In other words, the main terminal 93 is electrically connected to the connection point between the upper arm 9H and the lower arm 9L. The main terminal 93 is connected near one end in the Y direction of the relay wiring 55. The main terminal 93 extends in the Y direction and protrudes out of the sealing body 30 from the side surface 30c.

[0072] The three main terminals 91, 92, and 93 are arranged in a line in the X direction. In the X direction, the main terminals 91, 92, and 93 are arranged in the order of main terminal 91, main terminal 92, and main terminal 93. Adjacent main terminals have sides facing each other for most of their total length. For example, the side of main terminal 91 faces the side of main terminal 92.

[0073] Signal terminals 94 are electrically connected to the pads 40P of the corresponding semiconductor element 40 via connecting members such as bonding wires 110. Signal terminal 94H is connected to the pads 40P of semiconductor element 40H via bonding wires 110. Signal terminal 94L is connected to the pads 40P of semiconductor element 40L via bonding wires 110. Signal terminals 94 extend in the Y direction and protrude out of the encapsulant 30 from the side 30d. Signal terminals 94 extend in the Y direction opposite to the main terminals 91, 92, and 93. As an example, signal terminal 94 includes three signal terminals 94H and three signal terminals 94L.

[0074] The external connection terminals 90 are configured as part of the lead frame 95, as shown in Figure 8. The lead frame 95 comprises the external connection terminals 90, an outer frame 96, tie bars 97, and a support frame 98. Each of the external connection terminals 90 is fixed in series with respect to the outer frame 96 and / or indirectly via the tie bars 97. The outer frame 96 and tie bars 97 are removed as unnecessary parts during the manufacturing process of the semiconductor device 20.

[0075] The support frame 98 is connected to the surface metal body 52 together with the main terminals 91, 92, and 93. The support frame 98 supports the substrate 50 together with the main terminals 91, 92, and 93. The support frame 98 is connected to the substrate 50 on the opposite side from the main terminals 91, 92, and 93 in the Y direction in order to stably support the substrate 50. The support frame 98 is separated from the outer frame 96 and tie bars 97 when unnecessary parts are removed. The semiconductor device 20 comprises two support frames 98. One of the support frames 98 is connected to the portion of the P wiring 54 that includes the extension 543, and the other is connected to the portion of the relay wiring 55 that includes the extension 553. The support frame 98 extends in the Y direction and protrudes out of the encapsulant 30 from the side surface 30d.

[0076] The number of signal terminals 94 on the lead frame 95 is not particularly limited. For example, it may be the same number as the total number of pads 40P of the semiconductor elements 40 arranged on the substrate 50. Alternatively, by connecting the same type of pads 40P of multiple semiconductor elements 40 to a common signal terminal 94, the number may be less than the total number of pads 40P of the semiconductor elements 40.

[0077] For example, the lead frame 95 has five signal terminals 94H and five signal terminals 94L. Depending on the number of pads 40P of the semiconductor element 40 mounted on the substrate 50, any unnecessary signal terminals 94 are removed after the encapsulation body 30 is formed. In this embodiment, since the semiconductor element 40H has three pads 40P, three of the signal terminals 94H are provided for connection to the pads 40P, and the remaining two are removed. Similarly, three of the signal terminals 94L are provided for connection to the pads 40P, and the remaining two are removed. Therefore, the semiconductor device 20 has terminal remnants 99, which are the remaining parts after some of the terminals have been removed. The semiconductor device 20 has four terminal remnants 99.

[0078] The signal terminals 94H and 94L are positioned such that the distance between their respective tip positions and the centers of the multiple pads 40P of the corresponding semiconductor element 40 is approximately equal. The center refers to the central position of the multiple pads 40P in the direction of the arrangement of the pads 40P (X direction). Each of the signal terminals 94H and 94L has a straight portion 941 and an extended portion 942. The straight portion 941 is the part that extends in the Y direction, and at least a part of it is located outside the sealant 30. The extended portion 942 is the part that is continuously connected to one of the ends of the straight portion 941 and extends toward the corresponding pad 40P. At least a part of the extended portion 942 is covered by the sealant 30. The multiple extended portions 942 extend radially toward the centers of the pads 40P of the corresponding semiconductor element 40, and are arranged in a roughly fan shape overall. This makes it possible to make the lengths of the bonding wires 110 approximately equal.

[0079] As described above, in the semiconductor device 20 of this embodiment, a plurality of semiconductor elements 40 constituting one phase of the upper and lower arm circuit 9 are sealed by a sealing body 30. The sealing body 30 integrally seals a plurality of semiconductor elements 40, a part of the substrate 50, a part of the substrate 60, a plurality of conductive spacers 70, substrate connection parts 80, 81, and a part of the external connection terminal 90. The sealing body 30 seals the insulating substrates 51, 61 and surface metal bodies 52, 62 on the substrates 50, 60.

[0080] The semiconductor element 40 is positioned between substrates 50 and 60 in the Z direction. The semiconductor element 40 is sandwiched between the opposing substrates 50 and 60. This allows heat from the semiconductor element 40 to be dissipated on both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50b of substrate 50 is substantially flush with one surface 30a of the encapsulant 30. The back surface 60b of substrate 60 is substantially flush with the back surface 30b of the encapsulant 30. Since the back surfaces 50b and 60b are exposed surfaces, heat dissipation can be enhanced.

[0081] <Manufacturing method> Next, an example of a manufacturing method for the semiconductor device 20 described above will be explained.

[0082] First, the semiconductor element 40, substrates 50, 60, conductive spacer 70, substrate connection parts 80, 81, and lead frame 95 are prepared. As shown in Figure 8, the lead frame 95 is equipped with external connection terminals 90. The lead frame 95 is formed by processing a metal plate, such as by pressing. The external connection terminals 90 are supported on the outer peripheral frame 96 directly and / or via tie bars 97.

[0083] Next, the substrate 50 and the lead frame 95 are joined. First, the substrate 50 and the lead frame 95 are positioned relative to each other so that the joining points of the lead frame 95 and the surface metal body 52 overlap. Then, in this positioned state, the surface metal body 52 and the lead frame 95 are solid-state bonded. Specifically, the main terminals 91, 92, 93 and the support frame 98 are joined to the surface metal body 52. ​​Figure 8 shows this joined state.

[0084] Solid-phase bonding methods include ultrasonic bonding, room-temperature bonding, friction stir bonding, diffusion bonding, and friction pressure welding. In this embodiment, ultrasonic bonding is used as an example. Solid-phase bonding, especially ultrasonic bonding, is easier when no plating film is formed on the metal surfaces of the surface metal body 52 and the lead frame 95. Therefore, the substrate 50 and the lead frame 95 are bonded before the plating process.

[0085] Next, a plating process is performed. A plating film is formed on the surfaces of the surface metal body 52 and the lead frame 95 so as to cover the joint (solid-phase joint) between the surface metal body 52 and the lead frame 95. The plating film includes, for example, a film mainly composed of nickel. In this embodiment, as an example, an undercoat film is formed by electroless nickel plating containing P (phosphorus), and then an overcoat film is formed by Au plating.

[0086] Next, the semiconductor element 40 and the substrate connection parts 80 and 81 are bonded to the substrate 50. A conductive spacer 70 is also bonded to the semiconductor element 40. In other words, the connection targets using bonding materials 100, 101, and 103 are bonded to the substrate 50. Specifically, bonding material 100 is used to bond the drain electrode 40D of the semiconductor element 40 to the surface metal body 52. ​​Bonding material 101 is used to bond the source electrode 40S to the conductive spacer 70. Bonding material 103 is used to bond the substrate connection parts 80 and 81 to the surface metal body 52. ​​As an example, in this embodiment, solder is used as the bonding materials 100, 101, and 103, allowing the bonding to be performed collectively by reflow soldering.

[0087] Next, wire bonding is performed. Specifically, the pad 40P of semiconductor element 40H and the signal terminal 94H are electrically connected using bonding wire 110. Similarly, the pad 40P of semiconductor element 40L and the signal terminal 94L are electrically connected using bonding wire 110.

[0088] Next, the substrate 60 is joined. The conductive spacer 70 and the surface metal body 62 are joined via the bonding material 102. The substrate connection parts 80, 81 and the surface metal body 62 are joined via the bonding material 103. For example, in the case of solder, the joining can be performed all at once by reflow soldering.

[0089] Next, the sealant 30 is formed. In this embodiment, the sealant 30 is formed by the transfer molding method. For example, the sealant 30 is formed so that the substrates 50 and 60 are completely covered, and then cutting is performed after forming. The sealant 30 is cut together with a portion of the back metal bodies 53 and 63 of the substrates 50 and 60. This exposes the back surfaces 50b and 60b. Back surface 50b is substantially flush with one surface 30a of the sealant 30, and back surface 60b is substantially flush with back surface 30b. Alternatively, at least one of the back surfaces 50b and 60b may be pressed against the cavity wall of the molding die and the sealant 30 may be formed in a tightly sealed state. In this case, at least one of the back surfaces 50b and 60b is exposed from the sealant 30 at the time the sealant 30 is formed.

[0090] Next, unnecessary parts of the lead frame 95, such as the outer frame 96, tie bars 97, and unused signal terminals 94, are removed. This completes the process to obtain the semiconductor device 20.

[0091] <Joint and surrounding structure> Figure 9 is a plan view showing the connection structure between the surface metal body 52 of the substrate 50 and the main terminals 91, 92, and 93. In Figure 9, the surface metal body 52 and the main terminals 91, 92, and 93 are shown in a simplified manner. Figure 10 is an enlarged view of the region X shown by the dashed line in Figure 9. Figure 11 is a cross-sectional view along the line XI-XI shown in Figure 10.

[0092] As shown in Figure 9, the main terminal 91 has a length (width) in the direction perpendicular to the extension direction (Y direction) in the X direction, i.e., a constant width. The main terminal 93 also has a width that is approximately constant, similar to the main terminal 91. The widths of the main terminals 91 and 93 are wider than the width of the joint 120 formed between them and the surface metal body 52. ​​On the other hand, the main terminal 92 has a widened portion 921 and a narrowed portion 922 that is narrower than the widened portion 921. The narrowed portion 922 is continuously connected to the widened portion 921 and forms the tip of the main terminal 92. In the main terminal 92, the width of the narrowed portion 922 is approximately the same as the width of the joint 120. The width of the widened portion 921 is wider than the width of the joint 120. Of the main terminals 91, 92, and 93, the main terminals 91 and 93 correspond to wide terminals. The joint 120 corresponds to a solid-state joint.

[0093] The main terminal 91, which is a wide terminal, has a joining region 912 and a non-joining region 913 as an overlapping region 911 with the surface metal body 52 in a plan view, as shown in Figures 10 and 11. The joining region 912 is the region that overlaps with the joint 120 in a plan view. The joining region 912 is the region that provides the joint 120. The joint 120 and the joining region 912 have, for example, a roughly rectangular shape in plan. The non-joining region 913 is the remaining region of the overlapping region 911 excluding the joining region 912. In Figure 10, the part inside the dashed line indicating the joint 120 is the joining region 912, and the part outside the dashed line is the non-joining region 913.

[0094] The non-jointed area 913 is provided so as to be adjacent to the jointed area 912 in at least the width direction. As an example, in this embodiment, the non-jointed area 913 surrounds the jointed area 912 as shown in Figure 10. The non-jointed area 913 surrounds the jointed area 912 all around. In the overlapping area 911, the jointed area 912 is provided in the center, and the non-jointed area 913 is provided around the periphery. In the overlapping area 911, the non-jointed area 913 is provided at both ends in the width direction and at both ends in the extension direction, respectively. The non-jointed area 913 is provided adjacent to each of the four sides of the jointed area 912, which has a substantially rectangular shape in plan.

[0095] As shown in Figure 11, the bonding region 912 forms a joint 120 with the P wiring 54, which is the surface metal body 52. ​​In this embodiment, the joint 120 is an ultrasonic joint. The non-bonding region 913 does not form a joint 120 and has a gap 121 between it and the P wiring 54. The gap 121 is very small, about several tens of micrometers. The gap 121 formed by ultrasonic bonding is 30 micrometers or less.

[0096] The semiconductor device 20 includes a plating film 130. The plating film 130 is provided on the lead frame 95, including the main terminal 91, and on the surface metal body 52, so as to cover the joint portion 120. The plating film 130 is formed by a plating process after ultrasonic bonding. The plating film 130 contains nickel, as described above. The plating film 130 may be placed in the gap 121. That is, it may be provided on the non-bonded region 913 and the opposing surface of the P wiring 54 that constitute the gap 121. The plating film 130 may be provided only in a part of the gap 121, or it may be provided all the way to the back of the gap 121 so as to be in contact with the joint portion 120. As an example, in this embodiment, it is provided only in a part of the gap 121 from the opening.

[0097] The thickness of the main terminal 91 may be substantially uniform throughout, or it may vary in thickness in parts. As an example, the overlapping region 911 in this embodiment has a thin-walled portion 914 and a thick-walled portion 915. The thin-walled portion 914 includes at least the bonding region 912. The thin-walled portion 914 is the part that the ultrasonic tool contacts during ultrasonic bonding. The thin-walled portion 914 is provided so as to enclose the bonding region 912 and, consequently, the bonding portion 120 in a plan view. The area near the outer edge of the thin-walled portion 914 is a non-bonding region 913.

[0098] The thickened portion 915 includes the joining region 912. The thickened portion 915 is provided at both ends of the main terminal 91 in the width direction. In other words, the thinned portion 914 is located between the thickened portions 915. The thickness of the thickened portion 915 is approximately equal to the thickness of the main terminal 91 excluding the overlapping region 911. The main part of the non-jointed region 913 is thicker than the joining region 912. Note that the region between the dashed lines shown in Figure 11 is the joining region 912.

[0099] While the main terminal 91 of the wide terminals has been described, the main terminal 93 has a similar configuration.

[0100] <Summary of the First Embodiment> One possible design for the main terminals, which are joined to the surface metal of the substrate, is to have a tip that provides the joint with a width equal to that of the joint, and a rear end that is wider than the joint. By making the tip thinner, for example, it becomes easier to control the precision of the inclination of the joint surface. By making the rear end thicker, for example, it becomes possible to conduct large currents. For example, inductance can be reduced. However, the electric field may concentrate at the corner of the boundary between the tip and the rear end, which may reduce the lifespan.

[0101] In this embodiment, the semiconductor device 20 is equipped with a main terminal 91 which is a wide terminal. The main terminal 91 has a non-joint region 913. The non-joint region 913 is adjacent to the joint region 912 at least in the width direction (X direction). In other words, the width of the main terminal 91 (width of the overlapping region 911) is wider than the width of the joint 120. As a result, there is little change in width at the main terminal 91. Therefore, electric field concentration can be suppressed and the lifespan of the main terminal 91 can be improved. In addition, the main terminal 91 can conduct large currents. Inductance can be reduced. Because the width of the joint 120 (joint region 912) is narrower than the width of the overlapping region 911, it is easy to control the precision of the inclination of the joint surface.

[0102] In configurations where a plating film is provided to cover the joint, that is, configurations where the plating film 130 is formed after solid-phase bonding, plating solution residue can become a problem. If plating solution residue occurs, it may seep out in subsequent processes, such as the solder reflow process, potentially causing a decrease in adhesion between the surface metal body and the sealant, or a decrease in the wettability of the solder (jointing material). If the main terminal has multiple joints, the plating solution can remain between the joints, making it easier for plating solution residue to form.

[0103] In this embodiment, the main terminal 91 has one joint portion 120. The non-jointed region 913 is open to the side. Therefore, even if the plating solution enters between the non-jointed region 913 and the surface metal body 52, the plating solution is easily discharged. The plating solution is unlikely to remain in the gap 121 between the non-jointed region 913 and the surface metal body 52. ​​As a result, it is possible to suppress the retention of plating solution in the gap 121, that is, the generation of plating solution residue.

[0104] Based on the above, the semiconductor device 20 according to this embodiment can improve the durability life of the main terminal 91 while suppressing malfunctions caused by plating solution residue. The semiconductor element 40 is connected to the surface metal body 52 via the bonding material 100. By suppressing the plating solution residue, it is possible to suppress a decrease in the reliability of the connection between the semiconductor element 40 and the surface metal body 52. ​​The same applies to the wide main terminal 93.

[0105] The positional relationship between the wide main terminals 91 and 93 and the semiconductor element 40 is not particularly limited. In this embodiment, the semiconductor elements 40H and 40L corresponding to the main terminals 91 and 93 are aligned in the extension direction (Y direction) of the main terminals 91 and 93. In such a configuration, if plating solution residue is generated, the wettability of the solder, which is the bonding material 100, will decrease, and the reliability of the connection between the semiconductor element 40 and the surface metal body 52 may decrease. However, the above configuration can suppress the generation of plating solution residue. Therefore, the decrease in the reliability of the connection between the semiconductor element 40 and the surface metal body 52 can be suppressed.

[0106] The semiconductor device 20 of this embodiment includes a sealant 30. With the above configuration, the seepage of plating solution residue onto the surface of the surface metal body 52 is suppressed. Therefore, a decrease in the adhesion of the sealant 30 to the surface metal body 52 can be suppressed.

[0107] In this embodiment, the non-bonded region 913 surrounds the bonded region 912. Specifically, the non-bonded region 913 surrounds the bonded region 912 all around. The bonded region 912 is located inside the non-bonded region 913. The gap 121 formed between the non-bonded region 913 and the surface metal body 52 is open to the outside all around. Therefore, it is possible to effectively suppress the retention of plating solution in the gap 121. Furthermore, with this configuration, the bonding area can be secured regardless of the direction of misalignment.

[0108] The joint 120 in this embodiment is an ultrasonic joint. In ultrasonic bonding, friction is not possible from the second point onward in multi-point bonding, thus reducing the bonding strength. As described above, each of the main terminals 91 and 93 has only one joint 120 (one point). Therefore, bonding strength can be ensured while employing ultrasonic bonding. In other words, durability can be improved.

[0109] In this embodiment, the non-bonded region 913 includes a portion that is thicker than the bonded region 912. Thus, the bonded region 912 is thin. Therefore, the bonded portion 120 can be formed with less load. In other words, the load during ultrasonic bonding can be reduced, and the damage to the substrate 50 can be reduced. Because the non-bonded region 913 includes a portion that is thicker than the bonded region 912, the rigidity of the overlapping region 911 and, consequently, the main terminal 91 can be ensured.

[0110] In this embodiment, the gap 121 between the non-bonded region and the surface metal body is 30 μm or less. By narrowing the gap 121 in this way, the plating solution has difficulty entering the gap 121, thereby suppressing the generation of plating solution residue. Furthermore, in a configuration in which a sealant 30 made of resin mixed with a filler is used, the filler has difficulty entering the gap 121. This suppresses the localized increase in stress caused by the filler becoming trapped, which can reduce durability.

[0111] <Variation> The configuration in which the non-joining region 913 surrounds the joining region 912 is not limited to the example of surrounding it all around as shown in Figure 10. For example, as shown in Figure 12, the non-joining region 913 may be provided adjacent to three sides of the joining region 912. In Figure 12, the joining region 912 is provided over a predetermined range from the tip of the main terminal 91. The non-joining region 913 is adjacent to three of the four sides of the joining region 912, excluding the side that coincides with the tip of the main terminal 91.

[0112] For example, as shown in Figure 13, in a configuration where the non-bonding region 913 surrounds the bonding region 912 all around, the bonding region 912 may be positioned offset towards the tip of the main terminal 91 from the center of the overlapping region 911. The non-bonding region 913 has a tip portion 913a located towards the tip of the main terminal 91 in the extension direction, and a side-by-side portion 913b adjacent to the bonding region 912 in the width direction. The length L1 of the tip portion 913a is shorter than the length L2 of the side-by-side portion 913b. In other words, the non-bonding region 913 is smaller in the extension direction (Y direction) towards the semiconductor element 40 with respect to the width direction (X direction). As a result, the gap 121 on the semiconductor element 40 side is small, which effectively suppresses the seepage of the plating solution towards the semiconductor element 40. Therefore, a decrease in the connection reliability between the semiconductor element 40 and the surface metal body 52 can be effectively suppressed.

[0113] Note that the configuration shown in Figure 12 does not have a tip portion 913a. As a result, the non-bonding region 913 is smaller on the semiconductor element 40 side in the extension direction (Y direction) relative to the width direction (X direction). Therefore, a decrease in connection reliability between the semiconductor element 40 and the surface metal body 52 can be effectively suppressed.

[0114] In the overlapping region 911, the positions of the joining region 912 and the non-joining region 913 are not particularly limited. For a joining region 912 that the overlapping region 911 has only one of, the non-joining region 913 should be provided adjacent to it at least in the width direction. For example, as shown in Figure 14, the non-joining region 913 may be provided adjacent to two sides of the joining region 912. The joining region 912 is provided in the Y direction over a predetermined range from the tip of the main terminal 91. The joining region 912 is provided in the X direction over a predetermined range from one end of the main terminal 91. The non-joining region 913 is adjacent to one side of the joining region 912 in the X direction. The non-joining region 913 is adjacent to one side of the joining region 912 in the Y direction.

[0115] The example shown excludes main terminal 92, which is located in the middle of the main terminals 91, 92, and 93, from being a wide terminal, but this is not the only example. As shown in Figure 15, main terminal 92 may also be treated as a wide terminal, just like main terminals 91 and 93.

[0116] (Second Embodiment) This embodiment is a modification based on a prior embodiment, and the description of the prior embodiment can be referenced. Various modifications may be made to the main terminal and / or substrate to eliminate problems associated with ultrasonic bonding.

[0117] <Semiconductor device> The basic configuration of the semiconductor device 20 according to this embodiment is the same as the schematic configuration of the semiconductor device 20 shown in the prior embodiment (see Figures 2 to 8).

[0118] Although not shown in the diagram, the semiconductor device 20 includes a encapsulant 30, a semiconductor element 40, substrates 50, 60, a conductive spacer 70, substrate connection parts 80, 81, and an external connection terminal 90. The semiconductor device 20 also includes bonding materials 100-103 and bonding wires 110.

[0119] A joint portion 120 is formed between the substrate 50 and the main terminals 91, 92, and 93 by solid-phase bonding. In this embodiment, ultrasonic bonding is used as the solid-phase bonding. The joint portion 120 is an ultrasonic bonding portion. The other configurations are the same as the general configuration of the semiconductor device 20 shown in the prior embodiment.

[0120] <Circuit board damage> Figure 16 is a cross-sectional view showing a reference example. In this reference example, the symbols of each element are the same as the symbols of the related elements of the semiconductor device 20 with "r" added to the end. In Figure 16, the energy applied by the ultrasonic tool and the energy transmitted to the object to be bonded are shown by solid arrows. The size of the solid arrows indicates the magnitude of the energy. As an example, Figure 16 shows ultrasonic bonding between a main terminal 93r and a surface metal body 52r (relay wiring 55r).

[0121] As shown in Figure 16, the ultrasonic tool 140r has a plurality of protrusions 141r on its contact surface. The plurality of protrusions 141r are provided at predetermined intervals. On the other hand, the main terminal 93r has a plurality of recesses 931r on its upper surface that contacts the ultrasonic tool 140r. The plurality of recesses 931r are provided at predetermined intervals. The protrusions 141r and recesses 931r are provided so that they interlock with each other.

[0122] With the protrusions and indentations interlocked, the ultrasonic tool 140r vibrates in a direction perpendicular to the Z-direction. The energy is transmitted from the ultrasonic tool 140r to the main terminal 93r, and further to the surface metal body 52r located below the main terminal 93r. This vibrational energy causes a relative displacement between the surface metal body 52r and the back metal body 53r in a direction perpendicular to the Z-direction. In other words, stress is generated in the substrate 50r. In addition, the substrate 50r generates heat due to the ultrasonic vibration.

[0123] Therefore, the substrate 50r, for example, the insulating substrate 51r, can be damaged. When the insulating substrate 51r is damaged, there is a risk that the insulation reliability will decrease. In particular, the greater the energy applied by the ultrasonic tool 140r, the greater the damage the substrate 50r will suffer.

[0124] <Bali> Figure 17 is a cross-sectional view showing a reference example. Figure 17 corresponds to Figure 20, which will be described later. In the example shown in Figure 17, the main terminal 93r is constructed by press-forming a metal sheet of a certain thickness, that is, a flat metal sheet.

[0125] The main terminal 93r has a recess 931r for ultrasonic bonding. The recess 931r is formed by press working. The main terminal 93 has a burr 932r formed by press working near the open end of the recess 931r. By ultrasonic bonding the lead frame equipped with such a main terminal 93r to the substrate 50r, a joint 150r of the lead frame and the substrate 50r is formed.

[0126] Figure 18 is a cross-sectional view showing a reference example. Figure 18 shows the packaging state of the joint 150r. As shown in Figure 18, multiple joints 150r are stacked in the Z direction and packaged. For simplicity, Figure 18 shows two joints 150r.

[0127] In this packaging state, in two adjacent joints 150r in the Z direction, the burr 932r of the lower main terminal 93r comes into contact with the metal body 53 on the back surface of the upper substrate 50r. This may cause scratches on the metal body 53r on the back surface or generate foreign matter.

[0128] <Structure around the joint> Figure 19 is a perspective view showing the area around the junction between the main terminal 93 and the relay wiring 55 of the surface metal body 52 in the semiconductor device 20 of this embodiment. Figure 19 corresponds to region XIX shown by the dashed line in Figure 8. Figure 20 is a cross-sectional view along the line XX-XX in Figure 19.

[0129] The main terminal 93 has a recess 933 provided so as to include the joint portion 120 in a plan view. The recess 933 opens to the upper surface of the main terminal 93 and has a predetermined depth in the Z direction. As a result, the thickness between the bottom surface 933a of the recess 933 and the lower surface (joint surface) of the main terminal 93, that is, the thickness of the portion where the recess 933 is provided, is thinner than the thickness of the other portions of the main terminal 93. The thickness T1 of the thick portion 934 of the main terminal 93, which is the portion excluding the portion where the recess 933 is provided, is thicker than the thickness T2 of the surface metal body 52. ​​On the other hand, the thickness T3 of the thin portion 935, which is the portion where the recess 933 is provided, is thinner than the thickness T2 of the surface metal body 52. ​​The thickness T3 of the thin portion 935 is the thickness of the portion where the recess 931 is not provided.

[0130] The bottom surface 933a of the recess 933 is in contact with the ultrasonic tool. The recess 933 provides an area where the ultrasonic tool can vibrate ultrasonically. A portion of the ultrasonic tool is positioned in the recess 933. As an example, in this embodiment, the recess 933 is provided at the tip of the main terminal 93. The recess 933 also opens to the tip surface of the main terminal 93.

[0131] In the width direction (X direction), thickened portions 934 are provided at both ends of the main terminal 93. The thinned portion 935 has a roughly rectangular shape in plan. The side surfaces 933b of the recess 933 are provided on the three remaining sides of the main terminal 93, excluding the side on the tip side.

[0132] Multiple recesses 931 are formed on the bottom surface 933a of the recess 933. The solid rectangular area shown in Figure 19 indicates the recess 931 formation region 931a. The height of the burr 932 located near the opening end of the recess 931 is shorter than the depth of the recess 933. The entire burr 932 is located within the recess 933.

[0133] <Summary of the second embodiment> In this embodiment, the thickness T3 of the thin portion 935 including the joint portion 120 is thinner than the thickness T2 of the surface metal body 52 (T3 < T2). Thereby, even if the energy applied by the ultrasonic tool is reduced, the joint portion 120 can be formed. By reducing the energy, for example, the relative displacement between the surface metal body 52 and the back metal body 53 can be suppressed. Therefore, the damage to the substrate 50, for example, the damage to the insulating base material 51, can be reduced.

[0134] In this embodiment, the thickness T1 of the thick portion 934 is thicker than the thickness T2 of the surface metal body 52 (T1 > T2). The thin portion 935 is provided locally. Thereby, the rigidity around the joint portion can be ensured at the main terminal 93. In particular, the thick portions 934 are located on both sides in the width direction with respect to the thin portion 935. Therefore, when gripping and transporting the lead frame 95, the thick portions 934 on both sides function as beams, and the concentration of stress on the joint portion 120 can be suppressed.

[0135] In this embodiment, the height of the burr 932 provided on the bottom surface 933a of the recess 933 is shorter than the depth of the recess 933. Thereby, similar to the reference example shown in FIG. 18, when laminating and packing the joined body of the ultrasonically joined substrate 50 and the lead frame 95, the burr 932 of the lower joined body does not contact the back metal body 53 of the upper joined body. Therefore, it is possible to suppress damage to the back metal body 53 and the generation of foreign matters.

[0136] The angle θ formed by the bottom surface 933a and the side surface 933b of the recess 933 is not particularly limited, but is preferably 45 degrees or more. Further, the corner portion between the bottom surface 933a and the side surface 933b is preferably formed in an R shape. According to this, in the main terminal 93 provided with the thin portion 935, stress concentration at the corner portion can be avoided. For example, it is possible to suppress the occurrence of cracks in the main terminal 93 due to stress concentration.

[0137] Although the main terminal 93 has been described above, the same applies to the other main terminals 91 and 92 joined by ultrasonic waves.

[0138] The configuration described in this embodiment can be combined with the configuration described in the prior embodiment.

[0139] <Third Embodiment> This embodiment is a modification based on a prior embodiment, and the description of the prior embodiment can be referenced. In this embodiment, we propose an alternative configuration that can suppress substrate damage caused by ultrasonic bonding.

[0140] <Ultrasonic bonding process> Figure 21 is a cross-sectional view showing the ultrasonic bonding process. As an example, the objects to be bonded are the surface metal body 52 and the main terminal 93.

[0141] Before ultrasonic bonding, contamination 160 is present on the bonding surface of the surface metal body 52 and the main terminal 93. In ultrasonic bonding, vibration energy is applied to the main terminal 93 while applying pressure using an ultrasonic tool. As a result, the contact point 122 between the surface metal body 52 and the main terminal 93, which is the starting point of bonding, comes into contact at high speed, and a metallic bond is formed by friction and plastic flow. Then, the metallic bond expands, and the bonded portion 120 is formed.

[0142] <Manufacturing method for semiconductor devices> Figure 22 is a cross-sectional view showing a method for manufacturing the semiconductor device 20 according to this embodiment. Figure 22 corresponds to Figure 20. Figure 22 shows ultrasonic bonding between the surface metal body 52 (relay wiring 55) of the substrate 50 and the main terminal 93.

[0143] In this embodiment, before ultrasonic bonding is performed, an uneven surface 936 is provided on the lower surface (bonding surface) of the main terminal 93. The uneven surface 936 is sometimes referred to as a roughened surface. Then, vibration energy is applied to the main terminal 93 having the uneven surface 936 using an ultrasonic tool while applying pressure.

[0144] The uneven surface 936 is formed, for example, by a roughening treatment. Specifically, laser roughening, roughening plating, sandblasting, and chemical treatment are possible. The finer the pitch of the uneven surface 936, the better. The pitch of the uneven surface is, for example, on the order of nanometers or micrometers. The uneven surface 936 has very fine unevenness.

[0145] <Summary of the third embodiment> In this embodiment, ultrasonic bonding is performed using a main terminal 93 having an uneven surface 936 on the bonding surface. This makes it possible to obtain sufficient bonding with weaker pressure and amplitude compared to ultrasonic bonding conditions for flat surfaces. In other words, it is possible to form the bonded portion 120 even when the energy applied by the ultrasonic tool is reduced. The reduction in energy reduces the stress and heat generated in the substrate 50. Therefore, damage to the substrate 50, such as damage to the insulating substrate 51, can be reduced.

[0146] Figure 23 shows an example of a semiconductor device 20 formed by the manufacturing method described above. Figure 23 is an enlarged view of the area around the junction between the main terminal 93 and the substrate 50 in the semiconductor device 20. Figure 23 corresponds to Figure 20. The other configurations are the same as the schematic configuration of the semiconductor device 20 described in the prior embodiment.

[0147] The uneven portion 936 is provided so as to enclose the formation area of ​​the joint portion 120 before ultrasonic bonding. The uneven portion 936 is provided taking into account positional misalignment. In the semiconductor device 20, the uneven portion 936 surrounds the joint portion 120. The uneven portion 936 is adjacent to the joint portion 120. The uneven portion 936 of the semiconductor device 20 is the portion that remains after ultrasonic bonding.

[0148] The number of sides on which the protrusions 936 are adjacent to the joint 120 is not particularly limited. For example, the protrusions 936 may be adjacent to only one side of the joint 120. It is also possible for all of the protrusions 936 to contribute to the formation of the joint 120, resulting in a configuration where the semiconductor device 20 does not have any protrusions 936.

[0149] The above has described the main terminal 93, but the same applies to the other main terminals 91 and 92 that are ultrasonically bonded.

[0150] <Variation> An example of reducing the energy during ultrasonic bonding by providing the uneven portion 936 on the main terminal 93 has been shown, but the invention is not limited to this. As shown in Figure 24, the uneven portion 521 may be provided on the upper surface (bonding surface) of the surface metal body 52. ​​Figure 24 corresponds to Figure 20.

[0151] The configuration described in this embodiment can be combined with the configuration described in the prior embodiment.

[0152] <Fourth Embodiment> This embodiment is a modification based on a prior embodiment, and the description of the prior embodiment can be referenced. In this embodiment, we propose an alternative configuration that can suppress substrate damage caused by ultrasonic bonding.

[0153] Figure 25 is an enlarged cross-sectional view of the area around the junction between the main terminal 93 and the substrate 50 in the semiconductor device 20 according to this embodiment. Figure 25 corresponds to Figure 20.

[0154] As shown in Figure 25, a plating film 131 is formed on the surface of the main terminal 93. A portion of the plating film 131 constitutes a joint 120. The joint 120 contains the metal that makes up the plating film 131. In Figure 25, the joint 120 is shown in a simplified form.

[0155] The plating film 131 is mainly composed of a different metallic material than the surface metal body 52 and the main terminal 93. The main component metal is, for example, Pd or Au.

[0156] <Summary of the fourth embodiment> According to this embodiment, the bonding time can be shortened by the diffusion of dissimilar metals. Therefore, even if the energy applied by the ultrasonic tool is reduced, the bonding portion 120 can be formed. By reducing the energy, damage to the substrate 50, for example, damage to the insulating substrate 51, can be reduced.

[0157] The above has described the main terminal 93, but the same applies to the other main terminals 91 and 92 that are ultrasonically bonded.

[0158] An example of providing a plating film 131 on the main terminal 93 has been shown, but the method is not limited to this. A plating film mainly composed of a different metal material from the surface metal body 52 and the main terminal 93 may be provided on the surface of the surface metal body 52.

[0159] The configuration described in this embodiment can be combined with the configurations described in the prior embodiments, excluding the configuration in which a plating film 130 is formed after bonding and the configuration in which an uneven portion is provided on the bonding surface.

[0160] <Fifth Embodiment> This embodiment is a modification based on a prior embodiment, and the description of the prior embodiment can be referenced. In this embodiment, we propose an alternative configuration that can suppress substrate damage caused by ultrasonic bonding.

[0161] Figure 26 is an enlarged cross-sectional view of the area around the junction between the main terminal 93 and the substrate 50 in the semiconductor device 20 according to this embodiment.

[0162] The back metal body 53 of the substrate 50 is patterned. The back metal body 53 has a main portion 531 and a separate portion 532. The main portion 531 occupies most of the back metal body 53. The main portion 531 is sometimes referred to as the main heat dissipation portion. In a plan view, the main portion 531 encloses the semiconductor element 40.

[0163] The separation portion 532 is electrically isolated from the main portion 531. A gap exists between the separation portion 532 and the main portion 531, where the metal body has been removed. The separation portion 532 is sometimes referred to as an island. The separation portion 532 is located directly below the joint portion 120. In a plan view, the separation portion 532 encloses the joint portion 120. The other configurations are similar to the general configuration of the semiconductor device 20 described in the prior embodiment.

[0164] The semiconductor device 20 is cooled by a cooler 170. The cooler 170 cools the semiconductor device 20 by allowing a coolant to flow through internal channels. As the coolant flowing through the channels, a phase-changing coolant such as water or ammonia, or a non-phase-changing coolant such as ethylene glycol, can be used. A heat-conducting member 180, such as silicone gel, is placed between the cooler 170 and the semiconductor device 20. The heat-conducting member 180 is sometimes referred to as a thermal interface material (TIM). The heat-conducting member 180 conforms to the opposing surfaces of the cooler 170 and the semiconductor device 20, filling the gap between the opposing surfaces.

[0165] As an example, the coolers 170 are arranged on both sides of the semiconductor device 20 in the Z direction. The coolers 170 are stacked on the semiconductor device 20. One of the coolers 170 is positioned so as to overlap the main portion 531 of the back metal body 53 in a plan view, but not overlapping the separation portion 532. The cooler 170 is thermally connected to the main portion 531 of the back metal body 53. The cooler 170 cools the semiconductor device 20 via the main portion 531. The other cooler 170 is positioned so as to overlap the back metal body 63 in a plan view. The cooler 170 is thermally connected to the back metal body 63. The cooler 170 cools the semiconductor device 20 via the back metal body 63.

[0166] Figure 27 shows an example of the pattern of the back metal body 53. The back metal body 53 has one main part 531 and one separation part 532. The separation part 532 is provided to enclose the joints 120 of each main terminal 91, 92, and 93. The separation part 532 is a common area for the main terminals 91, 92, and 93.

[0167] <Summary of the Fifth Embodiment> In this embodiment, a separation portion 532 is provided directly below the joint portion 120. In other words, the separation portion 532 is provided directly below the portion where a load is applied during ultrasonic bonding. The separation portion 532 is separated from the other parts of the back metal body 53 (main portion 531). Compared to an integrated structure, the separation portion 532 is more easily deformed. This makes it possible to suppress the generation of stress on the substrate 50 during ultrasonic bonding. Therefore, damage to the substrate 50, such as damage to the insulating substrate 51, can be reduced.

[0168] Furthermore, the separation portion 532 located directly below the joint portion 120 is electrically isolated from the main portion 531. Therefore, even if a crack occurs in the insulating substrate 51 at a position overlapping with the separation portion 532 during ultrasonic bonding, the insulating properties of the semiconductor device 20 can be ensured on the main portion 531 side.

[0169] The pattern of the back metal body 53 is not limited to the example shown in Figure 27. For example, a separation section 532 may be provided individually for each of the main terminals 91, 92, and 93. In other words, multiple separation sections 532 may be provided.

[0170] The configuration described in this embodiment can be combined with the configuration described in the prior embodiment.

[0171] (Other embodiments) The disclosures in this specification and drawings are not limited to the exemplary embodiments. The disclosures include the exemplary embodiments and variations thereof by those skilled in the art. For example, the disclosures are not limited to combinations of parts and / or elements shown in the embodiments. The disclosures are implementable in a variety of combinations. The disclosures may have additional parts that can be added to the embodiments. The disclosures include those in which parts and / or elements of the embodiments have been omitted. The disclosures include substitutions or combinations of parts and / or elements between one embodiment and another. The scope of the disclosed technical areas is not limited to the descriptions of the embodiments. Some of the scope of the disclosed technical areas are indicated by the claims and should be understood to include all modifications within the meaning and scope equivalent to the claims.

[0172] The disclosures in the specification and drawings are not limited by the claims. The disclosures in the specification and drawings encompass the technical ideas described in the claims and extend to a wider and more diverse range of technical ideas than those described in the claims. Therefore, a variety of technical ideas can be extracted from the disclosures in the specification and drawings without being bound by the claims.

[0173] When an element or layer is referred to as “on top of,” “connected to,” “connected to,” or “joined,” it may be directly on top of, connected to, connected to, or joined to another element or layer, and there may also be an intervening element or layer. In contrast, when an element is referred to as “directly on top of,” “directly connected to,” “directly connected to,” or “directly joined to” another element or layer, there is no intervening element or layer. Other words used to describe relationships between elements should be interpreted in a similar manner (e.g., “between” vs. “directly between,” “adjacent” vs. “directly adjacent,” etc.). As used in this specification, the term “and / or” includes any combination with respect to one or more of the enumerated items relating to the relationship, and all combinations thereof.

[0174] Spatially relative terms such as "inside," "outside," "back," "below," "low," "above," and "high" are used here to facilitate descriptions of the relationship between one element or feature and other elements or features, as illustrated. Spatially relative terms may be intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. For example, if the device in the drawing is turned upside down, an element described as "below" or "directly below" another element or feature will be oriented "above" the other element or feature. Thus, the term "below" can encompass both up and down orientations. The device may also be oriented in other directions (it may be rotated 90 degrees or in other directions), and the spatially relative descriptors used in this specification will be interpreted accordingly.

[0175] The vehicle's drive system 1 is not limited to the configuration described above. For example, although an example with one motor generator 3 has been shown, it is not limited to this. It may have multiple motor generators. The power conversion device 4 is shown as an example with an inverter 6 as a power conversion circuit, but it is not limited to this. For example, it may have a configuration with multiple inverters. It may have a configuration with at least one inverter and a converter. It may have only a converter.

[0176] The example shown illustrates a semiconductor element 40 having a MOSFET 11 as a switching element, but it is not limited to this. For example, an IGBT can also be used. IGBT is an abbreviation for Insulated Gate Bipolar Transistor.

[0177] The semiconductor device 20 may include multiple semiconductor elements 40 that constitute each arm. The semiconductor device 20 may include multiple semiconductor elements 40H that constitute the upper arm 9H, and multiple semiconductor elements 40L that constitute the lower arm 9L. The drain electrodes 40D of the multiple semiconductor elements 40H are connected to a common P wiring 54. The drain electrodes 40D of the multiple semiconductor elements 40L are connected to a common relay wiring 55.

[0178] An example has been shown in which the semiconductor device 20 constitutes a single-phase upper and lower arm circuit 9, but it is not limited to this. The semiconductor device 20 may constitute only one arm. The semiconductor device 20 may constitute a multi-phase upper and lower arm circuit 9.

[0179] The number of main terminals joined to the surface metal body 52 of the substrate 50 is not particularly limited. The semiconductor device 20 only needs to have at least one main terminal joined to the surface metal body 52.

[0180] The pattern of the surface metal body 52 and the arrangement of the surface metal body 52 and the main terminals 91, 92, and 93 are not limited to the examples described above.

[0181] An example has been shown in which the source electrode 40S is electrically connected to the surface metal body 62 of the substrate 60, but the invention is not limited to this. A metal plate material may be used instead of the substrate 60. A configuration without the substrate 60, i.e., a single-sided heat dissipation structure, is also possible.

[0182] Although an example has been shown in which the semiconductor device 20 includes a conductive spacer 70, it is not limited to this. A configuration without a conductive spacer 70 is also possible. For example, instead of the conductive spacer 70, the surface metal body 62 of the substrate 60 may have a protrusion.

[0183] Although an example has been shown in which the semiconductor device 20 includes a sealant 30, the semiconductor device is not limited to this. A configuration without a sealant 30 is also possible. The technical concepts that can be understood from the embodiments and modifications described so far are described below as an addendum. <Note 1> A semiconductor element (40) having a first main electrode (40D) provided on one surface and a second main electrode (40S) provided on the back surface opposite to the first surface in the thickness direction, A substrate (50) having an insulating substrate (51), a surface metal body (52) disposed on the surface of the insulating substrate and electrically connected to the first main electrode, and a back metal body (53) disposed on the surface opposite to the surface of the insulating substrate, A bonding material (100) is interposed between the first main electrode and the surface metal body to join the first main electrode and the surface metal body, Main terminals (91, 92, 93) that form a solid-state joint (120) with the surface metal body, The device comprises the surface metal body and a plating film (130) provided on the main terminal so as to cover the solid-phase bonding portion, The aforementioned main terminal is There is one solid-state bonding portion formed between the surface metal body and the other, The overlapping region with the surface metal body in a plan view in the thickness direction of the plate includes a bonding region (912) that provides the solid-state bonding portion, and a non-bonding region (913) which is a region excluding the bonding region and is provided adjacent to the bonding region in at least the width direction of the main terminal. A semiconductor device including wide terminals (91, 93) in which the width of the overlapping region is wider than the width of the solid-phase bonding portion. <Note 2> The semiconductor device according to Appendix 1, comprising the semiconductor element, at least a portion of the substrate including the surface metal body, the bonding material, and a sealing body (30) that seals a portion of the main terminal including the solid-phase bonding portion. <Note 3> The semiconductor device according to Appendix 1 or Appendix 2, wherein the solid-phase bonding portion is an ultrasonic bonding portion. <Note 4> The semiconductor device according to Appendix 3, wherein the non-bonded region includes a portion that is thicker than the bonded region. <Note 5> A semiconductor device according to any one of the appendices 1 to 4, wherein the semiconductor element and the wide terminal are arranged in a direction perpendicular to the thickness direction and the width direction. <Note 6> The semiconductor device described in Appendix 5, wherein the non-bonding region is smaller on the semiconductor element side in the direction orthogonal to the width direction. <Note 7> A semiconductor device according to any one of the appendices 1 to 6, wherein the gap between the non-bonded region of the wide terminal and the surface metal body is 30 μm or less. <Note 8> The non-bonded region is a semiconductor device described in any one of the appendices 1 to 7, surrounding the bonded region. <Note 9> The non-bonded region surrounds the bonding region all around, as described in Appendix 8, for the semiconductor device described in Appendix 8. [Explanation of symbols]

[0184] 1...Drive system, 2...DC power supply, 3...Motor generator, 4...Power converter, 5...Smoothing capacitor, 6...Inverter, 7...P line, 8...N line, 9...Upper and lower arm circuit, 9H...Upper arm, 9L...Lower arm, 10...Output line, 11...MOSFET, 12...Diode, 20...Semiconductor device, 30...Encapsulation, 30a...One side, 30b...Back side, 30c, 30d, 30e, 30f...Side, 40, 40H, 40L...Semiconductor element, 40D...Drain electrode, 40S...Source electrode, 4 0P...Pad, 50...Substrate, 50a...Opposite side, 50b...Back side, 51...Insulating substrate, 52...Front metal body, 521...Rubber part, 53...Back metal body, 531...Main part, 532...Separation part, 54...P wiring, 541...Base part, 542, 543...Extended part, 55...Intermediate wiring, 551...Base part, 552, 553, 554...Extended part, 56...N wiring, 60...Substrate, 60a...Opposite side, 60b...Back side, 61...Insulating substrate, 62...Front metal body, 63...Back metal body, 64...N wiring, 641...Base part, 642...Extended part, 65 ...relay wiring, 651...base, 652...extension, 70...conductive spacer, 80, 81...board connection, 90...external connection terminal, 91, 92, 93...main terminal, 911...overlapping area, 912...joining area, 913...non-joining area, 913a...tip, 913b...side-by-side, 914...thin-walled area, 915...thick-walled area, 921...widening area, 922...narrowing area, 931...recess, 931a...forming area, 932...burr, 933...recess, 933a...bottom surface, 933b...side surface, 934...thick-walled area, 935...thin-walled area, 936 ...Uneven section, 94, 94H, 94L...Signal terminal, 941...Straight section, 942...Extended section, 95...Lead frame, 96...Outer frame, 97...Tie bar, 98...Support frame, 99...Terminal remaining section, 100, 101, 102, 103...Bonding material, 110...Bonding wire, 120...Joint section, 121...Gap, 122...Contact point, 130, 131...Plating film, 140r...Ultrasonic tool, 141r...Convex section, 150...Joint body, 160...Contamination, 170...Cooler, 180...Heat conductive member

Claims

1. A semiconductor element (40) having a first main electrode (40D) provided on one surface and a second main electrode (40S) provided on the back surface opposite to the first surface in the thickness direction, A substrate (50) having an insulating substrate (51), a surface metal body (52) disposed on the surface of the insulating substrate and electrically connected to the first main electrode, and a back metal body (53) disposed on the surface opposite to the surface of the insulating substrate, A bonding material (100) is interposed between the first main electrode and the surface metal body to join the first main electrode and the surface metal body, Main terminals (91, 92, 93) that form a solid-state joint (120) with the surface metal body, Equipped with, The solid-phase bonding portion is an ultrasonic bonding portion, The main terminal has a thick portion (934) which is a part that the ultrasonic tool does not contact when forming the ultrasonic joint, and a thin portion (935) which is a part that the ultrasonic tool contacts and is made thinner than the thick portion by a recess (933) that opens on the side opposite to the surface metal body side. A plurality of recesses (931) corresponding to the protrusions of the ultrasonic tool are formed on the bottom surface (933a) of the recess. Of the thin-walled portion, the thickness T3 of the portion where the recess is not provided is thinner than the thickness T2 of the surface metal body. A semiconductor device in which the thickness T1 of the thickened portion is greater than the thickness T2 of the surface metal body.

2. The semiconductor device according to claim 1, wherein the height of the burr (932) provided on the bottom surface is shorter than the value obtained by subtracting the thickness T3 from the thickness T1.

3. The semiconductor device according to claim 2, wherein the angle between the bottom surface and the side surface (933b) of the recess is 45 degrees or more.

4. The semiconductor device according to claim 2, wherein the corner between the bottom surface and the side surface (933b) of the recess is R-shaped.

5. A semiconductor device according to any one of claims 1 to 4, wherein a roughened portion (936, 521) is provided on either the bonding surface between the main terminal and the surface metal body, or on either the bonding surface between the surface metal body and the main terminal.

6. The semiconductor device according to claim 5, wherein the roughened portion is any of the following: a laser roughened portion, a roughened plated portion, a sandblasted roughened portion, or a chemically roughened portion.

7. The material of the insulating substrate is resin or ceramic. The semiconductor device according to any one of claims 1 to 6, wherein the thickness in the plate thickness direction is set in the range of 50 μm to 300 μm when resin is used as the material, and in the range of 200 μm to 500 μm when ceramic is used as the material.

8. The semiconductor device according to any one of claims 1 to 7, wherein the back metal body is patterned to coincide with the front metal body in a plan view in the thickness direction of the plate.

9. The semiconductor element has a plurality of pads (40P) arranged in a predetermined direction, The pad is provided with a plurality of signal terminals (94) connected via bonding wires (110), The semiconductor device according to any one of claims 1 to 8, wherein the plurality of signal terminals include portions that extend in a fan shape such that the distance from the center in the predetermined direction of the plurality of pads is equal to each other.

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