Semiconductor equipment

Abstract

To provide a semiconductor device capable of suppressing defects in bonding between a lead and a semiconductor element, and a method of manufacturing the semiconductor device.SOLUTION: Included are a semiconductor element 3, a support member 1, and a bonding layer 4 interposed between the semiconductor element 3 and the support member 1. The bonding layer 4 contains an alloy of first metal and second metal.SELECTED DRAWING: Figure 8

Description

Technical Field

[0007] , , , , ,

[0006]

[0001] This disclosure relates to a semiconductor device Place .

Background Art

[0002] A semiconductor device including leads, a semiconductor element, and solder for joining the leads and the semiconductor element is disclosed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The melting point of Sn contained in the solder is about 240°C or lower. For example, in the mounting process of mounting a semiconductor device on a circuit board or the like, if there is a process exceeding the melting point of Sn, there is a risk of problems such as cracks and peeling in the joining of the leads and the semiconductor element.

[0005] This disclosure has been conceived under the above circumstances, and an object thereof is to provide a semiconductor device and a method for manufacturing a semiconductor device capable of suppressing defects in the joining of leads and a semiconductor element. <000003o>

Means for Solving the Problems

[0006] The semiconductor device provided by the first aspect of this disclosure includes a semiconductor element, a support member, and a bonding layer interposed between the semiconductor element and the support member, and the bonding layer includes an alloy of a first metal and a second metal.

[0007] A method for manufacturing a semiconductor device provided by a second aspect of this disclosure comprises the steps of: preparing a support member having a second metal in at least its surface layer; preparing a semiconductor device having a third layer having a first metal; and forming a bonding layer interposed between the semiconductor device and the support member and containing an alloy of the first metal and the second metal by bringing the third layer and the surface layer into contact and heating. [Effects of the Invention]

[0008] According to this disclosure, defects in the junction between the lead and the semiconductor element can be suppressed.

[0009] Other features and advantages of this disclosure will become more apparent from the detailed description below, with reference to the accompanying drawings. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a perspective view showing a semiconductor device according to the first embodiment of this disclosure. [Figure 2] Figure 2 is a plan view showing a semiconductor device according to the first embodiment of this disclosure. [Figure 3] Figure 3 is a front view showing a semiconductor device according to the first embodiment of this disclosure. [Figure 4] Figure 4 is a side view showing a semiconductor device according to the first embodiment of this disclosure. [Figure 5] Figure 5 is a cross-sectional view along the VV line in Figure 2. [Figure 6] Figure 6 is a cross-sectional view along the line VI-VI in Figure 2. [Figure 7] Figure 7 is an enlarged cross-sectional view of a main part of a semiconductor device according to the first embodiment of this disclosure. [Figure 8] Figure 8 is an enlarged cross-sectional view of the main part along the line VI-VI in Figure 2. [Figure 9] Figure 9 is an enlarged cross-sectional view of the main section along the line IX-IX in Figure 2. [Figure 10] Figure 10 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment of this disclosure. [Figure 11] FIG. 11 is a principal part plan view showing a method of manufacturing a semiconductor device according to the first embodiment of the present disclosure. [Figure 12] FIG. 12 is a principal part enlarged cross-sectional view taken along the line XII-XII of FIG. 11. [Figure 13] FIG. 13 is a principal part plan view showing a method of manufacturing a semiconductor device according to the first embodiment of the present disclosure. [Figure 14] FIG. 14 is a principal part enlarged cross-sectional view taken along the line XIV-XIV of FIG. 13. [Figure 15] FIG. 15 is a principal part cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment of the present disclosure. [Figure 16] FIG. 16 is a principal part enlarged cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment of the present disclosure. [Figure 17] FIG. 17 is a principal part enlarged cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment of the present disclosure. [Figure 18] FIG. 18 is a principal part enlarged cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment of the present disclosure. [Figure 19] FIG. 19 is a principal part cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment of the present disclosure. [Figure 20] FIG. 20 is a principal part enlarged cross-sectional view showing another example of a method of manufacturing a semiconductor device according to the first embodiment of the present disclosure. [Figure 21] FIG. 21 is a plan view showing a first modification example of a semiconductor device according to the first embodiment of the present disclosure. [Figure 22] FIG. 22 is a principal part enlarged cross-sectional view taken along the line XXII-XXII of FIG. 21. [Figure 23] FIG. 23 is a principal part enlarged cross-sectional view showing a second modification example of a semiconductor device according to the first embodiment of the present disclosure. [Figure 24] FIG. 24 is a perspective view showing a semiconductor device according to the second embodiment of the present disclosure. [Figure 25] FIG. 25 is a perspective view showing a first modification example of a semiconductor device according to the second embodiment of the present disclosure. [Figure 26]Figure 26 is a perspective view showing a second modified example of a semiconductor device according to the second embodiment of this disclosure. [Figure 27] Figure 27 is a perspective view showing a third modified example of the semiconductor device according to the second embodiment of this disclosure. [Modes for carrying out the invention]

[0011] Preferred embodiments of this disclosure will be described in detail below with reference to the drawings.

[0012] The terms "first," "second," "third," etc., used in this disclosure are for identification purposes only and are not intended to assign any order to the objects.

[0013] <First Embodiment> Figures 1 to 9 show a semiconductor device according to the first embodiment of this disclosure. The semiconductor device A1 of this embodiment comprises a support member 1, a conductive member 2, a semiconductor element 3, a bonding layer 4, a wire 5, and a sealing resin 6.

[0014] Figure 1 is a perspective view showing semiconductor device A1. Figure 2 is a plan view showing semiconductor device A1. Figure 3 is a front view showing semiconductor device A1. Figure 4 is a side view showing semiconductor device A1. Figure 5 is a cross-sectional view along line VV in Figure 2. Figure 6 is a cross-sectional view along line VI-VI in Figure 2. Figure 7 is an enlarged cross-sectional view of a key part of semiconductor device A1. Figure 8 is an enlarged cross-sectional view of a key part along line VI-VI in Figure 2. Figure 9 is an enlarged cross-sectional view of a key part along line IX-IX in Figure 2. In these figures, the z direction is the thickness direction in this disclosure. The x and y directions are both perpendicular to the z direction and perpendicular to each other. In Figures 1 to 4, the sealing resin 6 is shown by dashed lines. In Figures 1 to 6, the bonding layer 4 is omitted for ease of understanding. Figure 7 is an enlarged cross-sectional view of a key part near the center of the semiconductor element 3, viewed along the z direction.

[0015] [Support member 1] The support member 1 is a member that supports the semiconductor element 3. The specific configuration of the support member 1 is not limited in any way. As shown in Figures 1 to 6, the support member 1 of this embodiment has a die bonding portion 13 and an extension portion 14.

[0016] The die bonding portion 13 is the part that supports the semiconductor element 3. The shape of the die bonding portion 13 is not particularly limited, and in the illustrated example, it is rectangular.

[0017] The extension portion 14 is a part that extends from the die bonding portion 13 to one side in the x-direction. The shape of the extension portion 14 is not particularly limited, and in the illustrated example, it is a strip-like shape that extends in the x-direction when viewed along the z-direction. Furthermore, the extension portion 14 has a bent portion, as shown in Figures 1, 3, and 5.

[0018] In this embodiment, as shown in Figures 7 and 8, the support member 1 has a base material 11 and a surface layer 12. The base material 11 is the main body of the support member 1. The base material 11 contains a metal such as Cu, Fe, or Ni, or an alloy thereof. In the following description, the case in which the base material 11 contains Cu will be described as an example. The thickness of the base material 11 is not particularly limited, and is, for example, 100 mm or more and 400 mm or less.

[0019] The surface layer 12 is a layer formed on the substrate 11 and contains a second metal. Examples of the second metal in this disclosure include Ag, Au, Cu, Pt, Pd, Ni, Co, Fe, Mn, V, Ti, Ce, Dy, Y, Yb, Hf, Mg, and Sn. In this embodiment, the second metal is selected from among metals that can form an alloy with the first metal described later. In the following description, the case where the second metal is Ag will be used as an example. The thickness of the surface layer 12 is, for example, 2 μm or more and 5 μm or less, and is set to, for example, about 3 μm. The method for forming the surface layer 12 is not limited in any way and can be formed by, for example, plating. In this embodiment, the surface layer 12 is formed on the die bonding portion 13. The surface layer 12 constitutes the first surface 1a of the die bonding portion 13. The first surface 1a is a surface facing one side in the z direction.

[0020] As shown in Figures 2 and 8, the support member 1 of this embodiment has a plurality of first recesses 18. In Figure 2, the plurality of first recesses 18 are indicated by a plurality of straight lines extending in the x direction. The plurality of first recesses 18 are recessed from the first surface 1a. The plurality of first recesses 18 are formed in positions that avoid the semiconductor element 3 and the junction layer 4 when viewed along the z direction. In the illustrated example, the plurality of first recesses 18 are formed in an annular region surrounding the semiconductor element 3 when viewed along the z direction. The plurality of first recesses 18 are filled with sealing resin 6.

[0021] The method for forming the multiple first recesses 18 is not limited and can include laser processing, etching, stamping, etc. In the illustrated example, multiple first recesses 18, each extending along the x-direction, are formed by laser processing.

[0022] As shown in Figure 8, the first recess 18 in this embodiment penetrates the surface layer 12 and reaches the substrate 11. In this case, the depth of the first recess 18 is greater than or equal to the thickness of the surface layer 12. The depth of the first recess 18 is, for example, 3 μm or more and 5 μm or less.

[0023] [Conductive member 2] The conductive member 2 is a member that constitutes a conductive path between the semiconductor element 3 and the outside. The specific configuration of the conductive member 2 is not limited in any way. The conductive member 2 is separated from the support member 1, and in this embodiment, it is separated from the support member 1 in the x direction. As shown in Figures 1 to 6, the conductive member 2 in this embodiment has a wire bonding portion 23 and an extension portion 24.

[0024] The wire bonding section 23 is the part where the wires 5 are joined. The shape of the wire bonding section 23 is not particularly limited, and in the illustrated example, it is a long rectangle with the y-direction as the longitudinal direction.

[0025] The extension portion 24 is a portion that extends from the wire bonding portion 23 to the other side in the x-direction. The shape of the extension portion 24 is not particularly limited, and in the illustrated example, it is a strip-like shape that extends in the x-direction when viewed along the z-direction. In addition, the extension portion 24 has a bent portion, as shown in Figures 1, 3, and 5.

[0026] In this embodiment, as shown in Figure 9, the conductive member 2 has a base material 21 and a surface layer 22. The base material 21 is the main body of the conductive member 2. The base material 21 includes, for example, a metal such as Cu, Fe, or Ni, or an alloy thereof. In the following description, the case in which the base material 21 contains Cu will be described as an example. The thickness of the base material 21 is not particularly limited, and is, for example, 100 mm or more and 400 mm or less.

[0027] The surface layer 22 is a layer formed on the substrate 21. The metal contained in the surface layer 22 is not limited in any way, and in this embodiment, it contains the same Ag as the second metal contained in the surface layer 12. However, the surface layer 22 may contain a different metal than the metal contained in the surface layer 12. The thickness of the surface layer 22 is, for example, 2 μm or more and 5 μm or less, and is set to, for example, about 3 μm. The method of forming the surface layer 22 is not limited in any way, and it may be formed by, for example, plating. In this embodiment, the surface layer 22 is formed on the wire bonding portion 23. The surface layer 22 constitutes the second surface 2a of the wire bonding portion 23. The second surface 2a is a surface facing one side in the z direction.

[0028] As shown in Figures 2 and 9, the conductive member 2 of this embodiment has a plurality of second recesses 28. In Figure 2, the plurality of second recesses 28 are indicated by a plurality of straight lines extending in the x direction. The plurality of second recesses 28 are recessed from the second surface 2a. When viewed along the z direction, the plurality of second recesses 28 are formed in a position that avoids the second bonding portion 52 of the wire 5, which will be described later. In the illustrated example, when viewed along the z direction, the plurality of second recesses 28 are formed in an annular region surrounding the second bonding portion 52. The plurality of second recesses 28 are filled with sealing resin 6.

[0029] The method for forming the multiple second recesses 28 is not limited to laser processing, etching, stamping, etc. In the illustrated example, multiple second recesses 28, each extending along the x-direction, are formed by laser processing.

[0030] As shown in Figure 9, the second recess 28 in this embodiment penetrates the surface layer 22 and reaches the substrate 21. In this case, the depth of the second recess 28 is greater than or equal to the thickness of the surface layer 22. The depth of the first recess 18 is, for example, 3 μm or more and 5 μm or less.

[0031] [Semiconductor device 3] The semiconductor element 3 performs the function of forming part of the electrical circuit when the semiconductor device A1 is incorporated into the electrical circuit. The specific configuration of the semiconductor element 3 is not limited in any way. Examples of semiconductor elements 3 include diodes and transistors. In this embodiment, a diode is selected as the semiconductor element 3.

[0032] The semiconductor element 3 is supported by the die bonding portion 13 of the support member 1. A surface layer 12 is formed on the portion of the die bonding portion 13 that supports the semiconductor element 3, and the multiple first recesses 18 are not formed therein.

[0033] As shown in Figures 7 and 8, the semiconductor element 3 comprises a semiconductor layer 30. The semiconductor layer 30 contains semiconductors such as Si, SiC, and GaN. An electrode (not shown) is formed on the semiconductor layer 30, and a wire 5 is joined to this electrode.

[0034] In this embodiment, the semiconductor element 3 has a first layer 31, a second layer 32, and a base layer 39.

[0035] The first layer 31 is interposed between the semiconductor layer 30 and the bonding layer 4. The first layer 31 contains a third metal. Examples of the third metal include Ag, Au, Cu, Pt, Pd, Ni, Co, Fe, Mn, V, Ti, Ce, Dy, Y, Yb, Hf, and Mg. In this embodiment, the third metal is selected from among metals that can form an alloy with the first metal, which will be described later. In the following description, the case where the third metal is Ni will be used as an example. The thickness of the first layer 31 is, for example, The particle size is between 0.1 μm and 0.5 μm, and is set to, for example, around 0.3 μm.

[0036] The second layer 32 is interposed between the first layer 31 and the bonding layer 4. The second layer 32 contains an alloy of a first metal and a third metal. Examples of the first metal include Ag, Au, Cu, Pt, Pd, Ni, Co, Fe, Mn, V, Ti, Ce, Dy, Y, Yb, Hf, Mg, and Sn. In this embodiment, the first metal is selected from among metals that can form alloys with the second and third metals. In the following description, the case where the first metal is Sn will be used as an example. That is, the second layer 32 in this embodiment contains a Sn-Ni alloy, which is an alloy of Sn and Ni. The thickness of the second layer 32 is, for example, 0.1 μm or more and 0.5 μm or less.

[0037] The underlayer 39 is interposed between the semiconductor layer 30 and the first layer 31 and is in direct contact with the semiconductor layer 30. The underlayer 39 contains, for example, Ti. The thickness of the underlayer 39 is, for example, 0.05 μm or more and 0.2 μm or less, and is set to, for example, about 0.1 μm.

[0038] [Joining layer 4] As shown in Figures 7 and 8, the bonding layer 4 is interposed between the semiconductor element 3 and the support member 1. The bonding layer 4 performs the function of bonding the semiconductor element 3 and the support member 1. The bonding layer 4 contains an alloy of a first metal and a second metal. Examples of alloys of a first metal and a second metal include Ag3Sn, PtSn4, PtSn2, Pt2Sn3, PdSn4, PdSn3, PdSn2, Ni3Sn4, CoSn2, FeSn2, MnSn2, V2Sn3, CeSn3, DySn4, Sn3Y, Sn3Yb, and Hf5Sn2. As described above, Sn is selected as the first metal and Ag is selected as the second metal. In this case, the bonding layer 4 contains Ag3Sn, which is an alloy of Sn as the first metal and Ag as the second metal. The bonding layer 4 has an Ag composition ratio of 73% by mass or more. The thickness of the bonding layer 4 is not particularly limited, and is, for example, between 2 μm and 5 μm, and is set to approximately 3 μm.

[0039] As can be seen from the manufacturing method of semiconductor device A1 described later, when viewed along the z-direction, the junction layer 4 mostly overlaps with the semiconductor element 3. As shown in Figure 8, depending on the manufacturing method conditions, the junction layer 4 may have a portion that slightly protrudes from the semiconductor element 3 in directions perpendicular to the z-direction (such as the x-direction or y-direction) when viewed along the z-direction. However, unlike the illustrated example, the junction layer 4 may also be configured not to protrude from the semiconductor element 3 when viewed along the z-direction.

[0040] Furthermore, as shown in Figure 8, depending on the manufacturing method conditions, the bonding layer 4 may have a portion located closer to the substrate 11 in the z-direction than the first surface 1a. In this case, a portion of the bonding layer 4 will be embedded in the surface layer 12. However, the bonding layer 4 may also be configured to be located further away from the substrate 11 in the z-direction than the first surface 1a.

[0041] [Wire 5] Wire 5 constitutes a conductive path between the semiconductor element 3 and the outside. In this embodiment, wire 5 connects the semiconductor element 3 and the conductive member 2. The material of wire 5 is not limited in any way and includes Au, Al, Cu, etc.

[0042] The wire 5 has a first bonding portion 51 and a second bonding portion 52. The first bonding portion 51 is the portion bonded to the aforementioned electrode (not shown) of the semiconductor element 3. The second bonding portion 52 is the portion bonded to the second surface 2a of the wire bonding portion 23 of the conductive member 2.

[0043] [Sealing resin 6] The sealing resin 6 covers a portion each of the support member 1 and the conductive member 2, as well as the semiconductor element 3, the bonding layer 4, and the wire 5. The sealing resin 6 contains an insulating resin, for example, a black epoxy resin.

[0044] The shape of the sealing resin 6 is not limited in any way, and as shown in Figures 1 to 6, in the illustrated example it has a first surface 61, a second surface 62, a third surface 63, a fourth surface 64, a fifth surface 65, and a sixth surface 66.

[0045] The first surface 61 is a surface facing one side in the z direction, and in the illustrated example, it is a flat surface. The second surface 62 is a surface facing the other side in the z direction, and in the illustrated example, it is a flat surface. The third surface 63 is a surface facing one side in the x direction, and in the illustrated example, it is a curved surface. The fourth surface 64 is a surface facing the other side in the x direction, and in the illustrated example, it is a curved surface. The fifth surface 65 is a surface facing one side in the y direction, and in the illustrated example, it is a curved surface. The sixth surface 66 is a surface facing the other side in the y direction, and in the illustrated example, it is a curved surface.

[0046] In this embodiment, the extension portion 14 of the support member 1 protrudes from the third surface 63 of the sealing resin 6 to one side in the x-direction. The extension portion 24 of the conductive member 2 protrudes from the fourth surface 64 of the sealing resin 6 to the other side in the x-direction.

[0047] In this embodiment, the surface of the extension portion 14 facing the other side in the z-direction is flush with the second surface 62. Similarly, the surface of the extension portion 24 facing the other side in the z-direction is flush with the second surface 62.

[0048] Next, the manufacturing method for semiconductor device A1 will be described below with reference to Figures 10 to 19.

[0049] Figure 10 is a flowchart showing an example of a manufacturing method for semiconductor device A1. The illustrated manufacturing method includes the steps of preparing a semiconductor element 3, preparing a support member 1, and forming a bonding layer 4.

[0050] First, a support member 1 is prepared as shown in Figures 11 and 12. The illustrated support member 1, together with the conductive member 2, is incorporated into a part of the lead frame. This lead frame is for manufacturing multiple semiconductor devices A1 at once. However, the semiconductor devices A1 may be manufactured individually.

[0051] The support member 1 shown in these figures includes a base material 11 and a surface layer 12, and has a die bonding portion 13 and an extension portion 14. In this example, the base material 11 contains Cu. The surface layer 12 is a layer of substantially uniform thickness formed on the base material 11 by plating or the like. The thickness of the surface layer 12 is, for example, 2 μm to 5 μm, and is set to, for example, about 3 μm. In this example, the surface layer 12 contains Ag.

[0052] The conductive member 2 includes a base material 21 and a surface layer 22, and has a wire bonding portion 23 and an extension portion 24. In this example, the base material 21 contains Cu. The surface layer 22 is a layer of substantially uniform thickness formed on the base material 21 by plating or the like. The thickness of the surface layer 22 is, for example, 2 μm or more and 5 μm or less, and is set to, for example, about 3 μm. In this example, the surface layer 22 contains Ag.

[0053] Next, as shown in Figures 13 and 14, a plurality of first recesses 18 are formed in the support member 1, and a plurality of second recesses 28 are formed in the conductive member 2. The method for forming the plurality of first recesses 18 and the plurality of second recesses 28 is not limited and can include laser processing, etching, stamping, etc. In the illustrated example, the plurality of first recesses 18 and the plurality of first recesses 18, each extending along the x-direction, are formed by laser processing.

[0054] For example, a laser beam L is irradiated onto the first surface 1a of the die bonding portion 13 of the support member 1 and scanned sequentially in the x direction. This laser beam L removes a portion of the surface layer 12 and reaches the substrate 11. As a result, a plurality of first recesses 18 are formed that penetrate the surface layer 12 and reach the substrate 11.

[0055] Furthermore, a laser beam L is irradiated onto the second surface 2a of the wire bonding portion 23 of the conductive member 2 and scanned sequentially in the x direction. This laser beam L removes a portion of the surface layer 22 and reaches the substrate 21. As a result, a plurality of second recesses 28 are formed that penetrate the surface layer 22 and reach the substrate 21.

[0056] Next, the semiconductor element 3 is prepared as shown in Figures 15 and 16. Note that the order in which the steps for preparing the support member 1 and preparing the semiconductor element 3 are performed is not limited and they may be performed simultaneously.

[0057] As shown in Figure 16, the semiconductor element 3 comprises a semiconductor layer 30 and a third layer 33. The semiconductor layer 30 is a layer containing a semiconductor as described above. The third layer 33 is a layer containing a first metal, and in this example, it contains Sn. The thickness of the third layer 33 is not limited in any way, and is, for example, 1.5 μm or more and 4 μm or less, and is set to about 2.5 μm.

[0058] Furthermore, the semiconductor element 3 in this example has a fourth layer 34, a fifth layer 35, and a base layer 39.

[0059] The fourth layer 34 is interposed between the semiconductor layer 30 and the third layer 33. The fourth layer 34 is the first layer 31 in the semiconductor element 3 of the semiconductor device A1 described above. The fourth layer 34 contains a third metal. Examples of the third metal include Ag, Au, Cu, Pt, Pd, Ni, Co, Fe, Mn, V, Ti, Ce, Dy, Y, Yb, Hf, and Mg, and in this example, it is Ni. The thickness of the fourth layer 34 is, for example, 0.1 μm or more and 0.5 μm or less, and is set to, for example, about 0.3 μm.

[0060] The fifth layer 35 is interposed between the fourth layer 34 and the third layer 33. The fifth layer 35 is a layer containing the same first metal as the surface layer 12, and in this example, it contains Ag. The thickness of the fifth layer 35 is, for example, 0.5 μm or more and 2.0 μm or less, and is set to, for example, about 1.0 μm.

[0061] The underlayer 39 is interposed between the semiconductor layer 30 and the fourth layer 34 and is in direct contact with the semiconductor layer 30. As described above, the underlayer 39 contains, for example, Ti. The thickness of the underlayer 39 is, for example, 0.05 μm to 0.2 μm, and is set to, for example, about 0.1 μm.

[0062] Next, the process of forming the bonding layer 4 is carried out. As shown in Figure 10, in this embodiment, the process of forming the bonding layer 4 includes a process of heating the support member 1 and a process of bringing the third layer 33 and the surface layer 12 into contact.

[0063] In the process of heating the support member 1, the support member 1 is heated to a temperature above which alloying is possible when the first metal contained in the third layer 33 and the second metal contained in the surface layer 12 come into contact with each other.

[0064] Next, as shown in Figure 17, a process is performed to bring the third layer 33 and the surface layer 12 into contact. This brings the surface layer 12, which is part of the heated support member 1, into contact with the third layer 33. Through this contact, heat is transferred from the preheated support member 1 to the semiconductor element 3 including the third layer 33, and the semiconductor element 3 is heated. As a result, the Sn, which is the first metal of the third layer 33, and the Ag, which is the second metal of the surface layer 12, alloy together, producing Ag3Sn, an alloy of Sn and Ag, and forming a bonding layer 4 containing Ag3Sn.

[0065] During the formation of the bonding layer 4, Sn contained in the third layer 33 may diffuse into the portion that was previously the surface layer 12. If the Sn diffuses in the z direction, the bonding layer 4 will have a portion located closer to the substrate 11 in the z direction than the first surface 1a. If the Sn diffuses in a direction perpendicular to the z direction, the bonding layer 4 will have a portion that extends beyond the semiconductor device 3 when viewed along the z direction.

[0066] In this embodiment, during the process, the fifth layer 35, which contains the second metal shown in Figure 17, is heated and alloyed with the third layer 33 to form a part of the bonding layer 4 shown in Figure 18. In this example, the entire fifth layer 35 diffuses into the third layer 33 and forms a part of the bonding layer 4. In addition, Ni, which is the third metal contained in the fourth layer 34 shown in Figure 17, and Sn, which is the first metal contained in the third layer 33, alloy together to form the second layer 32 shown in Figure 18. In this example, the second layer 32 contains a Sn-Ni alloy, which is an alloy of Sn and Ni.

[0067] As described above, by going through the process of forming the bonding layer 4, the semiconductor element 3 is bonded to the support member 1, as shown in Figures 18 and 19.

[0068] Unlike this embodiment, the bonding layer 4 may be formed by first bringing the third layer 33 and the surface layer 12 into contact, and then heating the support member 1 and the semiconductor element 3.

[0069] Subsequently, the semiconductor device A1 described above is obtained by appropriately performing the steps of bonding the wire 5 to the conductive member 2 and the semiconductor element 3, and forming the sealing resin 6.

[0070] Next, the operation of the semiconductor device A1 and the method for manufacturing the semiconductor device A1 will be explained.

[0071] According to this embodiment, as shown in Figures 7 and 8, the bonding layer 4 includes an alloy of a first metal and a second metal. This makes it possible to raise the melting point of the bonding layer 4. As a result, for example, in the mounting process of mounting a semiconductor device onto a circuit board, it is possible to raise the melting point of the bonding layer 4 to a temperature to which the semiconductor device A1 is exposed. Therefore, defects such as cracks and delamination can be suppressed in the bonding between the support member 1 and the semiconductor element 3.

[0072] Sn is selected as the first metal, and Ag is selected as the second metal. As a result, the bonding layer 4 contains Ag3Sn. The melting point of Ag3Sn is 480°C, so even if the semiconductor device A1 is exposed to a temperature of about 400°C during the mounting process of the semiconductor device A1, for example, it is possible to suppress the occurrence of defects such as cracks and delamination in the bonding layer 4. It is preferable that the composition ratio of Ag in the bonding layer 4 is 73 mass% or more in order to ensure that Ag3Sn is present in the bonding layer 4. In addition, Ag has a high degree of diffusion into Sn. As a result, it is possible to diffuse Ag throughout the Sn, and it is possible to reduce the portion in which Sn remains as a single metal. This is preferable in suppressing bonding defects caused by Sn, which has a low melting point.

[0073] In the manufacturing of semiconductor device A1, as shown in Figure 17, a bonding layer 4 is formed by bringing a third layer 33 containing Sn as the first metal and a surface layer 12 containing Ag as the second metal into contact and heating them. This bonding method does not require processing such as high pressure, and alloying is completed quickly upon contact. Therefore, the manufacturing efficiency of semiconductor device A1 can be increased. Furthermore, the bonding layer 4 formed by this process can be made significantly thinner than, for example, the thickness of the solder in a configuration joined by solder. Therefore, it is possible to reduce resistance and increase thermal conductivity between the support member 1 and the semiconductor element 3. As shown in Figure 10, the process of forming the bonding layer 4 can be further shortened by first heating the support member 1 and then bringing the third layer 33 and the surface layer 12 into contact.

[0074] In the process of forming the bonding layer 4, as shown in Figure 17, the third layer 33 is sandwiched between the surface layer 12 and the fifth layer 35. The third layer 33 contains Sn as the first metal, and the surface layer 12 and the fifth layer 35 contain Ag as the second metal. This makes it possible to diffuse Ag from both sides of the third layer 33 in the z direction. Therefore, it is preferable to increase the Ag3Sn occupancy rate in the bonding layer 4 and reduce the portion where Sn remains as a single metal.

[0075] As shown in Figure 8, the semiconductor element 3 of semiconductor device A1 has a first layer 31. The first layer 31 contains Ni as a third metal. In addition, the semiconductor element 3 has a second layer 32 due to the presence of the first layer 31. The second layer 32 contains an alloy of the first metal and the third metal, and in this example, it contains a Sn-Ni alloy. With this configuration, in the process of forming the bonding layer 4, it is possible to suppress the diffusion of the second metal, such as Ag, contained in the third layer 33 for forming the bonding layer 4 into the semiconductor layer 30. Including an underlayer 39 is preferable for suppressing the diffusion of the second metal into the semiconductor layer 30.

[0076] The support member 1 has a plurality of first recesses 18 formed therein. The plurality of first recesses 18 are filled with sealing resin 6. As a result, for example, when the semiconductor device A1 is mounted or used and the semiconductor device A1 is heated, causing the support member 1 to expand relative to the semiconductor element 3, the sealing resin 6 functions to suppress the expansion of the support member 1. This makes it possible to reduce the thermal stress generated in the bonding layer 4 sandwiched between the support member 1 and the semiconductor element 3. In particular, when the bonding layer 4 is formed by alloying treatment of a first metal and a second metal, the thickness of the bonding layer 4 is thinner than, for example, the thickness of solder. The thinner the bonding layer 4, the greater the potential for increased thermal stress. In this embodiment, thermal stress is suppressed by providing a plurality of first recesses 18, and bonding defects in the semiconductor device A1 employing a thin bonding layer 4 can be suppressed.

[0077] The first recess 18 penetrates the surface layer 12 and reaches the base material 11. When the bonding strength between the sealing resin 6 and the surface layer 12 is weaker than the bonding strength between the sealing resin 6 and the base material 11, the bonding strength between the sealing resin 6 and the support member 1 (multiple first recesses 18) can be increased.

[0078] The conductive member 2 has a plurality of second recesses 28 formed therein. The plurality of second recesses 28 are filled with sealing resin 6. This increases the bonding strength between the conductive member 2 (the plurality of second recesses 28) and the sealing resin 6.

[0079] The second recess 28 penetrates the surface layer 22 and reaches the base material 21. When the bonding strength between the sealing resin 6 and the surface layer 22 is weaker than the bonding strength between the sealing resin 6 and the base material 21, the bonding strength between the sealing resin 6 and the conductive member 2 (multiple second recesses 28) can be increased.

[0080] Figures 20 to 27 show modified examples and other embodiments of the present disclosure. In these figures, elements identical or similar to those in the above embodiments are denoted by the same reference numerals.

[0081] Figure 20 shows another example of a method for manufacturing semiconductor device A1. In the illustrated example, the semiconductor device 3 has a semiconductor layer 30, a base layer 39, a fourth layer 34, and a third layer 33, but does not have the fifth layer 35 described above. Even with this configuration, it is possible to form the bonding layer 4 described above.

[0082] <First Embodiment, First Modification> Figures 21 and 22 show a first modified example of semiconductor device A1. In this modified example of semiconductor device A11, the support member 1 does not have a plurality of first recesses 18. Also, the conductive member 2 does not have a plurality of second recesses 28.

[0083] This modified version also suppresses defects such as cracks and delamination in the joint between the support member 1 and the semiconductor element 3. Furthermore, as can be seen from this modified version, there are no limitations regarding the presence or absence of multiple first recesses 18 in the support member 1 or multiple second recesses 28 in the conductive member 2.

[0084] <First Embodiment, Second Modification> Figure 23 is an enlarged cross-sectional view of a key part showing a second modified example of semiconductor device A1. In this modified example, semiconductor device A12 has a semiconductor element 3 that has a semiconductor layer 30 and an underlayer 39, and does not have the first layer 31 and the second layer 32 found in semiconductor device A1.

[0085] This modified version also suppresses defects such as cracks and delamination in the bonding between the support member 1 and the semiconductor element 3. Furthermore, as can be seen from this modified version, there are no limitations on the presence or absence of the first layer 31 and the second layer 32 in the semiconductor element 3.

[0086] <Second Embodiment> Figure 24 is a perspective view showing a semiconductor device according to a second embodiment of the present disclosure. The semiconductor device A2 of this embodiment comprises a support member 1A, a support member 1B, a conductive member 2, a semiconductor element 3A, a semiconductor element 3B, a plurality of bonding layers 4 (not shown), a plurality of wires 5, and a sealing resin 6.

[0087] Support member 1A includes the same constituent elements as support member 1 described above and has a die bonding portion 13 and an extension portion 14. Support member 1A also has a base material 11 and a surface layer 12. The surface layer 12 is provided on the die bonding portion 13. Multiple first recesses 18 are formed in support member 1A. Semiconductor element 3A is bonded to the die bonding portion 13 of support member 1A via a bonding layer 4. The configuration of the bonding layer 4 is appropriately applied from the configuration of the first embodiment and its modified versions described above.

[0088] Support member 1B includes the same constituent elements as support member 1 described above, and has a die bonding portion 13 and an extension portion 14. Support member 1B also has a base material 11 and a surface layer 12. The surface layer 12 is provided on the die bonding portion 13. A plurality of first recesses 18 are formed in support member 1B. The semiconductor element 3B is bonded to the die bonding portion 13 of support member 1B via a bonding layer 4. The configuration of the bonding layer 4 is appropriately applied to the configuration of the first embodiment and its modified versions described above.

[0089] The conductive member 2 is positioned between the support member 1A and the support member 1B. The conductive member 2 includes the same constituent elements as the conductive member 2 described above and has a wire bonding portion 23 and an extension portion 24. The conductive member 2 also has a base material 21 and a surface layer 22. The surface layer 22 is provided on the wire bonding portion 23. The conductive member 2 has a plurality of second recesses 28 formed therein.

[0090] Semiconductor elements 3A and 3B are, for example, both diodes. The electrodes (not shown) of semiconductor elements 3A and 3B are electrically connected to the wire bonding portion 23 of the conductive member 2 by multiple wires 5.

[0091] This embodiment also makes it possible to suppress defects such as cracks and delamination in the bonding between the support members 1A and 1B and the semiconductor elements 3A and 3B. Furthermore, as can be understood from this embodiment, the number of support members, the number of semiconductor elements, and their arrangement in the semiconductor device according to this disclosure are not limited in any way.

[0092] <Second Embodiment, First Modification> Figure 25 is a perspective view showing a first modified example of semiconductor device A2 of the present disclosure. In the semiconductor device A21 of this embodiment, support member 1A and support member 1B are adjacent to each other. Conductive member 2 is positioned on the opposite side of support member 1A, with support member 1B in between. Semiconductor element 3A and support member 1B are connected by wire 5. Semiconductor element 3B and conductive member 2 are connected by wire 5. The joining of semiconductor element 3A and support member 1A and the joining of semiconductor element 3B and support member 1B are the same as in semiconductor device A2 described above.

[0093] This modified version also suppresses defects such as cracks and delamination in the bonding between support members 1A and 1B and semiconductor elements 3A and 3B. Furthermore, as can be understood from this embodiment, the number of support members, the number of semiconductor elements, and their arrangement in the semiconductor device according to this disclosure are not limited in any way.

[0094] <Second Embodiment, Second Modification> Figure 26 is a perspective view showing a third modified example of semiconductor device A2 of the present disclosure. This modified example A22 has a similar configuration to the semiconductor device A21 described above, except that the arrangement of the support member 1A, support member 1B, and conductive member 2 differs from that of semiconductor device A21. In this modified example, support member 1A and support member 1B are adjacent to each other, and conductive member 2 is positioned on the opposite side of support member 1A, with support member 1A in between. Semiconductor element 3B and support member 1A are connected by wire 5. Semiconductor element 3A and conductive member 2 are connected by wire 5. The joining of semiconductor element 3A and support member 1A and the joining of semiconductor element 3B and support member 1B are the same as in semiconductor device A2 described above.

[0095] This modified version also suppresses defects such as cracks and delamination in the bonding between support members 1A and 1B and semiconductor elements 3A and 3B. Furthermore, as can be understood from this embodiment, the number of support members, the number of semiconductor elements, and their arrangement in the semiconductor device according to this disclosure are not limited in any way.

[0096] <Second Embodiment, Third Modification> Figure 27 is a perspective view showing a third modified example of semiconductor device A2 of the present disclosure. The semiconductor device A23 of this modified example comprises a support member 1, a conductive member 2A, a conductive member 2B, a semiconductor element 3, a bonding layer 4 (not shown), a plurality of wires 5, and a sealing resin 6.

[0097] Conductive members 2A and 2B are arranged with the support member 1 in between. The semiconductor element 3 is bonded to the die bonding portion 13 of the support member 1 via a bonding layer 4 (not shown). In this example, the semiconductor element 3 is, for example, a transistor. A gate electrode and a source electrode (neither shown) are formed on the upper surface of the semiconductor element 3 in the figure, and a drain electrode is formed on the lower surface of the semiconductor element 3 in the figure. One of the gate electrode and source electrode is connected to the wire bonding portion 23 of the conductive member 2A by a wire 5, and the other of the gate electrode and source electrode is connected to the wire bonding portion 23 of the conductive member 2B by a wire 5.

[0098] This modified example also makes it possible to suppress defects such as cracks and delamination in the bonding between the support member 1 and the semiconductor element 3. Furthermore, as can be understood from this embodiment, the type of semiconductor element included in the semiconductor device according to this disclosure is not limited in any way.

[0099] The semiconductor device and method for manufacturing the semiconductor device described herein are not limited to the embodiments described above. The specific configuration of the semiconductor device and method for manufacturing the semiconductor device described herein can be modified in various ways.

[0100] [Note 1] Semiconductor elements and Support member and A bonding layer is interposed between the semiconductor element and the support member, The bonding layer comprises an alloy of a first metal and a second metal, wherein the semiconductor device is a semiconductor device. [Note 2] The first metal is Sn, The semiconductor device described in Appendix 1, wherein the second metal is Ag. [Note 3] The semiconductor device described in Appendix 2, wherein the bonding layer contains Ag3Sn. [Note 4] The semiconductor device described in Appendix 3, wherein the bonding layer has a composition ratio of Ag of 73% by mass or more. [Note 5] A semiconductor device according to any one of appendices 2 to 4, comprising a first layer interposed between the bonding layer and the semiconductor element and containing a third metal. [Note 6] The semiconductor device according to Appendix 5, further comprising a second layer interposed between the bonding layer and the first layer and containing an alloy of the first metal and the third metal. [Note 7] The semiconductor device described in Appendix 6, wherein the bonding layer is thicker than the second layer. [Note 8] The semiconductor device according to any one of appendices 2 to 7, wherein the support member includes a base material and a surface layer interposed between the base material and the bonding layer. [Note 9] The semiconductor device described in Appendix 8, wherein the surface layer is thinner than the substrate. [Note 10] The semiconductor device according to Appendix 8 or 9, wherein the surface layer contains Ag. [Note 11] The substrate is a semiconductor device as described in Appendix 10, comprising Cu. [Note 12] The semiconductor device according to any one of appendices 8 to 11, wherein the surface layer protrudes outward from the semiconductor element when viewed in the thickness direction of the support member. [Note 13] The semiconductor device described in Appendix 12, wherein the portion of the surface layer that protrudes from the semiconductor element when viewed in the thickness direction has a first surface facing the thickness direction. [Note 14] The semiconductor device according to Appendix 13, wherein the bonding layer has a portion located on the substrate side in the thickness direction compared to the first surface. [Note 15] The semiconductor element and at least a part of the support member are covered with a sealing resin, The semiconductor device according to appendix 13 or 14, wherein the support member has a plurality of recesses that are recessed from the first surface. [Note 16] The semiconductor device according to Appendix 15, wherein the recess penetrates the surface layer and reaches the substrate. [Note 17] A step of preparing a support member containing a second metal in at least the surface layer, A step of preparing a semiconductor device having a third layer containing a first metal, A step of bringing the third layer and the surface layer into contact and heating to form a bonding layer interposed between the semiconductor element and the support member and containing an alloy of the first metal and the second metal, A method for manufacturing a semiconductor device, comprising: [Note 18] The method for manufacturing a semiconductor device according to Appendix 17, wherein, in the step of forming the bonding layer, the support member is heated and then the third layer and the surface layer are brought into contact. [Explanation of Symbols]

[0101] A1, A11, A12, A2, A21, A23: Semiconductor equipment 1B: Support member 1a: 1st page 2,2A,2B: Conductive member 2a: 2nd side 3,3A,3B: Semiconductor element 4: Bonding layer 5: Wire 6: Sealing resin 11: Base material 12: Surface layer 13: Die Bonding Section 14:Extending part 18: First recess 21: Base material 22: Surface layer 23: Wire bonding section 24:Extension part 28: Second recess 30: Semiconductor layer 31: 1st layer 32: 2nd layer 33:Third layer 34: 4th layer 35: 5th layer 39: Base layer 51: First Bonding Section 52: Second bonding section 61: 1st page 62: 2nd side 63:Side 3 64:Side 4 65:Side 5 66:Side 6 L: Laser light

Claims

1. Semiconductor elements and Support member and A bonding layer is interposed between the semiconductor element and the support member, The bonding layer comprises an alloy of a first metal and a second metal. The support member includes a base material and a surface layer interposed between the base material and the bonding layer. The aforementioned surface layer, when viewed in the thickness direction of the support member, protrudes outward from the semiconductor element. The portion of the surface layer that extends beyond the semiconductor element when viewed in the thickness direction has a first surface facing the thickness direction. The bonding layer has a portion located on the substrate side in the thickness direction compared to the first surface, The surface layer has a portion interposed between the bonding layer and the substrate, The first metal is Sn, The aforementioned second metal is Ag, A first layer is interposed between the bonding layer and the semiconductor element and contains a third metal, A semiconductor device comprising a second layer interposed between the bonding layer and the first layer and containing an alloy of the first metal and the third metal.

2. The bonding layer is Ag 3 A semiconductor device according to claim 1, comprising Sn.

3. The semiconductor device according to claim 2, wherein the bonding layer has a composition ratio of Ag of 73% by mass or more.

4. The semiconductor device according to any one of claims 1 to 3, wherein the bonding layer is thicker than the second layer.

5. The semiconductor device according to any one of claims 1 to 4, wherein the surface layer is thinner than the substrate.

6. The semiconductor device according to any one of claims 1 to 5, wherein the surface layer contains Ag.

7. The semiconductor device according to claim 6, wherein the substrate contains Cu.

8. The semiconductor element and at least a part of the support member are covered with a sealing resin, The semiconductor device according to any one of claims 1 to 7, wherein the support member has a plurality of recesses that are recessed from the first surface.

9. The semiconductor device according to claim 8, wherein the recess penetrates the surface layer and reaches the substrate.

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