Manufacturing method for semiconductor devices

Abstract

To provide a semiconductor device, a semiconductor module, and a manufacturing method of the semiconductor device capable of improving reliability.SOLUTION: A semiconductor device according to the present embodiment includes: a first electrode having a first main surface and a second main surface opposite to the first main surface; a semiconductor substrate disposed on the second main surface; and a second electrode disposed on a fourth main surface of the semiconductor substrate opposite to a third main surface in contact with the first electrode. The first electrode has a first side surface substantially perpendicularly intersecting with the first main surface, and a second side surface substantially perpendicularly intersecting with both the first main surface and the first side surface, and the first main surface, the first side surface, and the second side surface are connected to one another via a curved surface.SELECTED DRAWING: Figure 1

Description

Technical Field

[0006] , , , ,

[0001] Embodiments of the present invention relate to a semiconductor device, a semiconductor module, and a method of manufacturing a semiconductor device.

Background Art

[0002] In a semiconductor module including a semiconductor device such as a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an electrode of the semiconductor device is electrically connected to a lead material (metal member) via a bonding material such as solder.

[0003] Since the semiconductor device is formed by dicing a wafer on which an electrode layer is formed, the corners of the electrodes have a sharp shape. Therefore, in the semiconductor module, stress is likely to concentrate on the corners of the electrodes due to thermal expansion of the bonding material or the like. As a result, when the change in the environmental temperature is large, the semiconductor substrate may be damaged.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] Embodiments of the present invention provide a semiconductor device, a semiconductor module, and a method of manufacturing a semiconductor device capable of improving reliability.

Means for Solving the Problems

[0006] The semiconductor device according to this embodiment comprises a first electrode having a first main surface and a second main surface opposite to the first main surface, a semiconductor substrate disposed on the second main surface, and a second electrode disposed on a fourth main surface of the semiconductor substrate opposite to a third main surface in contact with the first electrode. The first electrode has a first side surface that intersects substantially perpendicularly with the first main surface and a second side surface that intersects substantially perpendicularly with both the first main surface and the first side surface, and the first main surface, the first side surface and the second side surface are connected to each other via a curved surface. [Brief explanation of the drawing]

[0007] [Figure 1] This is a cross-sectional view of a semiconductor module according to the first embodiment. [Figure 2A] This is a top view of a semiconductor device according to the first embodiment. [Figure 2B] Figure 2A is a cross-sectional view of the semiconductor device shown along line II. [Figure 2C] This is a cross-sectional view of the semiconductor device shown in Figure 2A, along the line II-II. [Figure 2D] This is a three-dimensional perspective view of the first electrode provided in the semiconductor device according to the first embodiment. [Figure 3A] This is a cross-sectional view illustrating a step in a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 3B] This is a cross-sectional view illustrating the steps in a first example of a semiconductor device manufacturing method according to the first embodiment, following Figure 3A. [Figure 3C] Figure 3B is a cross-sectional view illustrating the steps in a first example of a semiconductor device manufacturing method according to the first embodiment. [Figure 3D] Figure 3A(3) is a top view illustrating the steps in a first example of a semiconductor device manufacturing method according to the first embodiment. [Figure 3E] Figure 3B(1) is a top view illustrating the steps in a first example of a semiconductor device manufacturing method according to the first embodiment. [Figure 4A]This is a cross-sectional view illustrating a step in a second example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4B] This is a cross-sectional view illustrating a process in a second example of the method for manufacturing a semiconductor device according to the first embodiment, following Figure 4A. [Figure 4C] Figure 4A(2) is a top view illustrating the process in a second example of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 4D] Figure 4A(3) is a top view illustrating the laser processing step in a second example of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 4E] Figure 4A(3) is a top view illustrating another example relating to the laser processing step in a second example of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] This is a three-dimensional perspective view of the first electrode of a semiconductor device according to a modified example of the first embodiment. [Figure 6A] This is a top view of a semiconductor device according to the second embodiment. [Figure 6B] Figure 6A is a cross-sectional view of the semiconductor device shown along line II-II. [Figure 6C] This is a three-dimensional perspective view of the first electrode and semiconductor substrate included in the semiconductor device according to the second embodiment. [Figure 7A] This is a cross-sectional view illustrating a step in a first example of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 7B] This is a cross-sectional view illustrating the steps in the first example of a method for manufacturing a semiconductor device according to a second embodiment, following Figure 7A. [Figure 7C] Figure 7B is a cross-sectional view illustrating the steps in the first example of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 8A] This is a cross-sectional view illustrating a step in a second example of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 8B]FIG. 8A is a cross-sectional view for explaining a process in a second example of a method for manufacturing a semiconductor device according to a second embodiment, following FIG. 8A. [Figure 8C] FIG. 8B is a cross-sectional view for explaining a process in a second example of a method for manufacturing a semiconductor device according to a second embodiment, following FIG. 8B. [Figure 8D] FIG. 8A(2) is a top view for explaining a process in a second example of a method for manufacturing a semiconductor device according to a second embodiment, shown in FIG. 8A(2). [Figure 8E] FIG. 8C(2) is a top view for explaining a process in a second example of a method for manufacturing a semiconductor device according to a second embodiment, shown in FIG. 8C(2). [Figure 9] FIG. is a three-dimensional perspective view of a first electrode and a semiconductor substrate included in a semiconductor device according to a modified example of the second embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments do not limit the present invention. The drawings are schematic or conceptual, and the ratios of each part are not necessarily the same as those in reality. In the specification and drawings, the same reference numerals are given to the same elements as those described above with respect to the already shown drawings, and the detailed description is appropriately omitted.

[0009] In this specification, XYZ coordinates are adopted, the thickness direction of the semiconductor device (the stacking direction of electrode 3, semiconductor substrate 2, and electrode 4 described later) is the Z direction, one direction substantially orthogonal to the Z direction is the X direction, and a direction substantially orthogonal to the X direction and the Z direction is the Y direction.

[0010] (First Embodiment) The semiconductor device 1 according to the first embodiment will be described with reference to FIGS. 1 and FIGS. 2A - 2D.

[0011] First, a semiconductor module 10 comprising a semiconductor device 1 will be described. Figure 1 is a cross-sectional view showing an example of the configuration of the semiconductor module 10. The semiconductor module 10 comprises a semiconductor device 1, a bonding material 11, a metal member 12, a bonding material 13, a metal member 14, and a sealing material 15.

[0012] The bonding material 11 electrically connects the electrode 3 of the semiconductor device 1 to the metal member 12. The bonding material 11 is, for example, solder. The bonding material 11 may also be a sintered material that is sintered between the electrode 3 and the metal member 12 by heat treatment.

[0013] The metal member 12 is arranged to be electrically connected to the electrode 3 via the bonding material 11. For example, a conductive material such as copper is used for the metal member 12.

[0014] The bonding material 13 electrically connects the electrode 4 and the metal member 14 of the semiconductor device 1. The bonding material 13 is, for example, solder. The bonding material 13 may also be a sintered material that is sintered between the electrode 4 and the metal member 14 by heat treatment. The bonding materials 11 and 13 may be, for example, copper (Cu), silver (Ag), lead (Pb), tin (Sn), or a combination thereof.

[0015] The metal member 14 is arranged to be electrically connected to the electrode 4 via the bonding material 13. For example, a conductive material such as copper is used for the metal member 14.

[0016] The sealing material 15 seals the semiconductor device 1 and protects the semiconductor device 1 from the outside of the sealing material 15. The sealing material 15 may seal part or all of at least one of the bonding material 11, metal member 12, bonding material 13, and metal member 14. The sealing material 15 has insulating properties, and for example, a resin may be used.

[0017] Next, the semiconductor device 1 will be described. Figure 2A is a plan view of the semiconductor device 1 according to the first embodiment. Figure 2B is a cross-sectional view taken along line II in Figure 2A. Figure 2C is a cross-sectional view taken along line II-II in Figure 2A.

[0018] The semiconductor device 1 comprises a semiconductor substrate 2, an electrode (first electrode) 3, and an electrode (second electrode) 4. As a semiconductor element, the semiconductor device 1 is configured to allow current to flow between electrode 4 and electrode 3. The semiconductor device 1 may be a vertical MOSFET. If the semiconductor device 1 is a MOSFET, electrode 3 corresponds to the drain electrode and electrode 4 corresponds to the source electrode. More specifically, the semiconductor device 1 may be a low-voltage driven MOSFET (LVMOSFET: Low Voltage MOSFET).

[0019] The semiconductor substrate 2 is formed by creating semiconductor elements on a wafer, for example, by slicing a silicon ingot, and then separating the elements into individual pieces. For example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN) can be used for the semiconductor substrate 2. As shown in Figures 2B and 2C, the semiconductor substrate 2 has a main surface 21 and a main surface 22 opposite to the main surface 21.

[0020] Electrode 3 has a main surface 31 and a main surface 32 opposite to the main surface 31. The semiconductor substrate 2 is placed on the main surface 32. The main surface 21 of the semiconductor substrate 2 is in contact with electrode 3. Also, as shown in Figure 2D, electrode 3 has a side surface 33 that intersects substantially perpendicularly with the main surface 31, and a side surface 34 that intersects substantially perpendicularly with both the main surface 31 and the side surface 33.

[0021] The electrode 4 is located on the main surface 22 of the semiconductor substrate 2. If the semiconductor device 1 is a vertical MOSFET, a gate electrode (not shown) is also located on the main surface 22.

[0022] Electrodes 3 and 4 can be made from materials such as copper, nickel (Ni), silver, gold (Au), or palladium (Pd).

[0023] The sum of the thicknesses T of electrode 3, semiconductor substrate 2, and electrode 4 may be 50 μm or less. A thickness T of 50 μm or less allows for a sufficient reduction in the on-resistance of semiconductor device 1.

[0024] As shown in Figures 2C and 2D, the main surface 31, side surface 33, and side surface 34 of electrode 3 are connected to each other via a curved surface 35. As a result, electrode 3 has rounded corners X1. In other words, electrode 3 has rounded corners X1.

[0025] In this embodiment, as shown in Figure 2D, the electrode 3 has rounded corners at all of its corners, not just one. However, the electrode 3 may have rounded corners at least at one of its corners.

[0026] The radius of curvature of the curved surface 35 (i.e., the radius of curvature of the corner X1) may be, for example, 10 μm or more. This allows for a more effective distribution of the stress applied to the corner X1 of the electrode 3.

[0027] As described above, according to this embodiment, since the electrode 3 has rounded corners X1, the bonding material 11 can distribute the stress applied to the corners X1 of the electrode 3 in the semiconductor module 10. This improves the reliability of the semiconductor device 1.

[0028] <Method for manufacturing semiconductor device 1> The manufacturing method of the semiconductor device 1 will be described below with reference to the drawings. As an example of a manufacturing method for rounding the corners X1 of the electrode 3, a method using etching or laser ablation will be described. Figures 3A to 3E show the manufacturing method by etching (first example), and Figures 4A to 4D show the manufacturing method by laser ablation (second example).

[0029] [Example 1 (Etching)] First, as shown in Figure 3A(1), a wafer 2W is prepared having a main surface 21 and a main surface 22 opposite to the main surface 21, with an electrode layer 3A placed on the main surface 21 and an electrode layer 4A placed on the main surface 22. For reinforcement, the wafer 2W may be bonded to a support member (not shown), such as a glass plate. Various semiconductor regions are already formed on the wafer 2W, and the same applies to the following other examples. For example, if the semiconductor device 1 is a vertical MOSFET, a base region, a source region, a drain region, etc., are formed on the wafer 2W.

[0030] Next, as shown in Figure 3A(2), the resist R is applied to the electrode 3.

[0031] Next, as shown in Figures 3A(3) and 3D, the resist R is selectively exposed at positions corresponding to the intersections of the dicing lines L on the wafer 2W. Subsequently, development is performed to form apertures OP on the bottom surface in a grid pattern (i.e., at positions corresponding to the intersections of the dicing lines L), where the electrode layer 3A is exposed, as shown in Figure 3D. Figure 3D is a top view of the state shown in Figure 3A(3).

[0032] Although Figure 3D shows a rectangular opening OP, the shape of the opening OP is not limited to this and can be any shape, such as a circle.

[0033] Next, as shown in Figure 3A(4), multiple recesses RE1 are formed in a grid pattern on the electrode layer 3A by etching the electrode layer 3A exposed on the bottom surface of the aperture OP. The depth of the recesses RE1 is, for example, 10 μm or more. The etching is either dry etching or wet etching. By forming the recesses RE1, when the wafer 2W is later fragmented into multiple semiconductor devices 1, the electrodes 3 of the semiconductor devices 1 will have rounded corners X1.

[0034] Next, as shown in Figure 3B(1), the resist R is removed using a developer or the like. This results in a state where the recesses RE1 are positioned along the intersections of the dicing lines L, as shown in Figure 3E.

[0035] Next, as shown in Figure 3B(2), the dicing tape D is attached to the electrode layer 3A. After this, if a support member such as a glass plate is attached to the wafer 2W, the support member is removed.

[0036] Next, as shown in Figure 3B(3), the wafer 2W is divided into multiple semiconductor devices 1 by dicing along the dicing line L. Each semiconductor device 1 comprises a semiconductor substrate 2, electrodes 3 and 4. The dicing can be performed by any method, such as blade dicing or laser dicing.

[0037] Next, as shown in Figure 3B(4), the dicing tape D is stretched. Then, as shown in Figure 3C(1), the individual semiconductor devices 1 are pushed up using the push-up pins P and picked up using the collet C.

[0038] The picked-up semiconductor device 1 is transported, for example, to a die bonder and placed on a lead frame (not shown) via a bonding material 11. Subsequently, the semiconductor module 10 is manufactured through processes such as mounting metal members 12 and 14, wire bonding to connect the metal members 12 and 14 to the semiconductor device 1 with wires, and molding to seal the semiconductor device 1 with a sealing material 15. The processes after picking up are similar in the following example.

[0039] Through the above process, the semiconductor device 1 according to the first embodiment is manufactured.

[0040] Next, a method for manufacturing a semiconductor device 1 using laser ablation processing will be described.

[0041] [Second example (laser ablation)] First, a wafer 2W is prepared, as shown in Figure 4A(1), having a main surface 21 and a main surface 22 opposite to the main surface 21, with an electrode layer 3A placed on the main surface 21 and an electrode layer 4A placed on the main surface 22. The wafer 2W is supported by, for example, a support jig J. The support jig J is, for example, glass or dicing tape.

[0042] Next, as shown in Figure 4A(2), the wafer 2W is divided into multiple semiconductor devices 1 by dicing along the dicing line L. This forms electrodes 3 having sides 33 and sides 34. Dicing can be performed by any method, such as blade dicing or laser dicing.

[0043] Figure 4C is a top view of the state shown in Figure 4A(2). In Figure 4C, the gaps created between each of the wafers 2W (multiple semiconductor devices 1) that have been separated by dicing are exaggerated.

[0044] Next, as shown in Figure 4A(3), a portion of the corner of electrode 3 is removed by laser ablation. For example, by removing a portion of the corner consisting of the main surface 31, side surface 33, and side surface 34, a rounded corner X1 is formed.

[0045] During laser ablation, for example, as shown in Figure 4D, laser light is irradiated along the edges of the diced wafer 2W (the boundary line between the main surface 31 and the side surface 33 and the boundary line between the main surface 31 and the side surface 34). That is, laser ablation is performed along arrows A1 and A2 shown in Figure 4D. As a result, the intersection of arrows A1 and A2 is subjected to laser ablation twice, increasing the amount of electrode 3 removed. Therefore, as shown in Figure 2D, the electrode 3 becomes rounded at the corner X1. For example, a UV laser is used in laser ablation.

[0046] Furthermore, laser ablation may be performed selectively only on the corners of electrode 3, for example, as shown in region A in Figure 4E.

[0047] Next, as shown in Figure 4A(4), the dicing tape D is attached to the electrode 3. Then, as shown in Figure 4B(1), the dicing tape D is stretched out. Finally, as shown in Figure 4B(2), the individual semiconductor device 1 is pushed up using the push-up pin P and picked up using the collet C.

[0048] Through the above process, the semiconductor device 1 according to the first embodiment is manufactured.

[0049] In either the first or second example, according to the above-described method for manufacturing the semiconductor device 1, since the electrode 3 has rounded corners X1, the semiconductor device 1 can be easily peeled off the dicing tape D.

[0050] If the corners of the back electrodes (electrodes in contact with the dicing tape) of a semiconductor device are not rounded, it is difficult to detach the semiconductor device from the dicing tape when picking it up. If burrs (metal burrs on the back electrodes, etc.) generated during dicing are embedded in the dicing tape, it becomes even more difficult to detach. In addition, as semiconductor devices become thinner (for example, with a thickness of 50 μm or less), their rigidity decreases, so when the dicing tape is deformed by a push-up pin P during pickup, the semiconductor device may also deform and be damaged.

[0051] In contrast, according to the above-described method for manufacturing the semiconductor device 1, since the electrode 3 has rounded corners X1, the semiconductor device 1 can be easily peeled off the dicing tape D. Furthermore, the possibility of burrs generated during dicing becoming embedded in the dicing tape D can be reduced. As a result, even when the semiconductor device 1 is thin (for example, with a thickness T of 50 μm or less), the success rate of picking up the semiconductor device 1 can be improved, and the yield of the semiconductor device 1 can be improved.

[0052] Furthermore, in either the first or second example, the radius of curvature of the corner X1 may be 10 μm or more. In that case, the semiconductor device 1 becomes easier to peel off from the dicing tape D, and the success rate of picking up the semiconductor device 1 can be improved.

[0053] (modified version) Next, a modified example of the first embodiment will be described with reference to Figure 5. As shown in Figure 5, in this modified example, the main surface 31 and the side surface 33 of the electrode 3 are connected to each other via a curved surface 36. As a result, the electrode 3 has rounded edges Y1 including the main surface 31 and the side surface 33. In other words, the electrode 3 has rounded edges Y1.

[0054] In this modified example, as shown in Figure 5, the electrode 3 has rounded edges on all sides of the main surface 31, not just one side. The electrode 3 may also have rounded edges on at least one side of the main surface 31.

[0055] According to this modified example, since the electrode 3 has a rounded edge Y1, the stress applied to the edge Y1 of the electrode 3 can be distributed by the bonding material 11 in the semiconductor module 10. Therefore, the durability of the semiconductor device 1 can be further improved.

[0056] Furthermore, by having the electrode 3 take the shape shown in this modified example, the individual semiconductor device 1 can be easily peeled off from the dicing tape D not only at the corners X1 but also at the edges Y1 during the picking process. This makes it easier to pick up the semiconductor device 1 and further improves the yield.

[0057] (Second Embodiment) Next, a semiconductor device 1A according to the second embodiment will be described. In the first embodiment, it was explained that the electrode 3 has a rounded corner X1, which prevents stress from concentrating at the corner X1 of the electrode 3 and improves the durability of the semiconductor device 1. In contrast, in the second embodiment, the corner X2 of the semiconductor substrate 2 is also rounded. This prevents stress from concentrating at the corner X2 of the semiconductor substrate 2 as well, providing a semiconductor device with even greater durability. The second embodiment will now be described, focusing on the differences from the first embodiment.

[0058] Figure 6A is a top view illustrating semiconductor device 1A according to the second embodiment. Elements with the same names or functions as those described in the first embodiment are denoted by the same reference numerals. Hereafter, descriptions will be omitted except for changes or additions.

[0059] Figure 6A is a plan view of semiconductor device 1A according to the second embodiment. Figure 6B is a cross-sectional view taken along line II-II in Figure 6A. The cross-sectional view taken along line II in Figure 6A is the same as that of Figure 2B described in the first embodiment and is therefore omitted.

[0060] The semiconductor substrate 2 has a main surface 21 that is in contact with the electrode 3, a side surface 23 that intersects the main surface 21 substantially perpendicularly, and a side surface 24 that intersects both the main surface 21 and the side surface 23 substantially perpendicularly.

[0061] As shown in Figures 6B and 6C, the main surface 21, side surface 23, and side surface 24 of the semiconductor substrate 2 are connected to each other via a curved surface 25. This gives the semiconductor substrate 2 rounded corners X2. In other words, the semiconductor substrate 2 has rounded corners X2. The electrode 3 also has rounded corners, similar to the first embodiment, to match the shape of the semiconductor substrate 2. In other words, the electrode 3 also has rounded corners X1.

[0062] The radius of curvature of the curved surface 25 (i.e., the radius of curvature of the corner X2) may be, for example, 10 μm or more. This allows for a more effective distribution of stress applied to the corner X2 of the semiconductor substrate 2.

[0063] In this embodiment, as shown in Figure 6C, the semiconductor substrate 2 has rounded corners not only at one corner of the main surface 21, but at all corners of the main surface 21. The semiconductor substrate 2 may have rounded corners at at least one corner of the main surface 21.

[0064] Thus, according to the second embodiment, not only the electrode 3 but also the semiconductor substrate 2 has rounded corners X2. Therefore, the stress applied to the corners X2 of the semiconductor substrate 2 can be distributed. This makes it possible to further improve the durability of the semiconductor device 1A. For example, even if the electrode 3 is thin due to the thinning of the semiconductor device, according to this embodiment, the semiconductor substrate 2 also has rounded corners X2, so the durability of the semiconductor device 1A can be maintained and improved.

[0065] Furthermore, in the first embodiment, the electrode 3 had a rounded corner X1, but in the second embodiment, the semiconductor substrate 2 has a rounded corner X2. For this reason, even when the semiconductor device 1 is a horizontal MOSFET and no electrodes are arranged on the main surface 21 (when electrodes are arranged on only one main surface of the semiconductor substrate 2), the second embodiment can be similarly applied.

[0066] <Manufacturing method for semiconductor device 1A> The manufacturing method for semiconductor device 1A will be described below with reference to the drawings. As an example of a manufacturing method to round the corners X2, we will describe a method using etching or a spacer. Figures 7A to 7C show the manufacturing method by etching (third example), and Figures 8A to 8C show the method using a spacer (fourth example).

[0067] [Third example (etching)] First, as shown in Figure 7A(1), a wafer 2W is prepared having a main surface 21 and a main surface 22 opposite to the main surface 21, with an electrode layer 4A placed on the main surface 22. For reinforcement, the wafer 2W may be bonded to a support member (not shown), such as a glass plate.

[0068] Next, as shown in Figure 7A(2), a resist R is applied to the main surface 21 of the wafer 2W.

[0069] Next, as shown in Figure 7A(3), the resist R is selectively exposed at positions corresponding to the intersections of the dicing lines L on the wafer 2W. Subsequently, by development, apertures OP with the main surface 21 exposed on the bottom surface are formed in a grid pattern (i.e., at positions corresponding to the intersections of the dicing lines L). Similar to the first example, the apertures OP are formed in a grid pattern at positions corresponding to the intersections of the dicing lines L. Note that the shape of the apertures OP may be any shape, such as a circular shape.

[0070] Next, as shown in Figure 7A(4), multiple recesses RE2 are formed in a grid pattern on the semiconductor substrate 2 by etching the semiconductor substrate 2 exposed on the bottom surface of the aperture OP. The depth of the recesses RE2 is, for example, 10 μm or more. The etching is performed by dry etching or wet etching. By forming the recesses RE2, when the wafer 2W is later separated into multiple semiconductor devices 1A, the semiconductor substrate 2 will have rounded corners X2.

[0071] Next, as shown in Figure 7B(1), the resist R is removed using a developer or the like. This results in the recessed RE2 being positioned along the intersection of the dicing lines L.

[0072] Next, as shown in Figure 7B(2), an electrode layer 3A is formed on the main surface 21 of the wafer 2W. For example, the electrode layer 3A is formed on the main surface 21 by a vapor deposition method or a sputtering method.

[0073] Next, as shown in Figure 7B(3), the dicing tape D is attached to the electrode layer 3A. After this, if a support member such as a glass plate is attached to the wafer 2W, the support member is removed.

[0074] Next, as shown in Figure 7B(4), the wafer 2W is divided into multiple semiconductor devices 1A by dicing along the dicing line L. Dicing can be performed by any method, such as blade dicing or laser dicing.

[0075] Next, as shown in Figure 7C(1), the dicing tape D is stretched out. Then, as shown in Figure 7C(2), the individual semiconductor devices 1A are pushed up using the push-up pins P and picked up using the collet C.

[0076] After the above process, the semiconductor device 1A according to the second embodiment is manufactured.

[0077] Next, a method for manufacturing a semiconductor device 1A using a spacer will be described.

[0078] [Example 4 (Spacer)] First, as shown in Figure 8A(1), a wafer 2W is prepared having a main surface 21 and a main surface 22 opposite to the main surface 21, with an electrode layer 4A placed on the main surface 22. For reinforcement, the wafer 2W may be bonded to a support member (not shown), such as a glass plate.

[0079] Next, as shown in Figures 8A(2) and 8D, spacers S are formed in a grid pattern on the electrode layer 4A at positions corresponding to the intersections of predetermined dicing lines L on the wafer 2W. The spacers S are made of, for example, polyimide. Figure 8D is a top view of the state shown in Figure 8A(1). The height (thickness) of the spacers S is, for example, 10 μm or more.

[0080] Next, as shown in Figure 8A(3), the wafer 2W is placed on the support jig J such that the main surface 22 side faces the support jig J.

[0081] Next, as shown in Figures 8A(4) and 8B(1), the main surface 21 side of the wafer 2W is ground using the grinding machine PO (backgrinding process). At this time, the grinding machine PO grinds while pressing the wafer 2W against the support jig J. Therefore, the portion of the wafer 2W where the spacer S is formed is subjected to stronger pressure than the portion where the spacer S is not formed, resulting in a larger amount of grinding.

[0082] During grinding, the wafer 2W is pressed against the support jig J by the grinding machine PO, causing the wafer 2W (and electrode layer 4A) to deform, as shown in Figure 8B(1). When grinding is complete and the pressing force of the grinding machine PO is removed, the wafer 2W returns to its original shape, as shown in Figure 8B(2). As a result, the portion of the main surface 21 directly above the spacer S becomes concave, forming a recess RE3. By forming the recess RE3, when the wafer 2W is later fragmented into multiple semiconductor devices 1A, the semiconductor substrate 2 will have rounded corners X1. When the height of the spacer S is 10 μm or more, the depth of the recess RE3 is, for example, 10 μm or more.

[0083] Next, as shown in Figure 8B(3), an electrode layer 3A is formed on the main surface 21 of the wafer 2W. For example, the electrode layer 3A is formed on the main surface 21 by a vapor deposition method or a sputtering method.

[0084] Next, as shown in Figure 8B(4), a dicing tape D is attached to the electrode layer 3A. Then, as shown in Figures 8C(1) and 8E, the wafer 2W is diced along the dicing line L to separate it into multiple semiconductor devices 1A. Dicing can be performed by any method, such as blade dicing or laser dicing.

[0085] Next, the dicing tape D is stretched out as shown in Figures 8C(2) and 8F. Then, as shown in Figure 8C(3), the individual semiconductor devices 1A are pushed up using the push-up pins P and picked up using the collet C.

[0086] After the above process, the semiconductor device 1A according to the second embodiment is manufactured.

[0087] In the above explanation, the spacer S is not removed from the semiconductor device 1A, but the spacer S may be removed from the semiconductor device 1A. Alternatively, a so-called pre-dicing method, in which dicing is performed before the backgrinding process, may be employed.

[0088] In either the third or fourth example, according to the above-described method for manufacturing the semiconductor device 1A, rounding is formed on the corners X2 of the semiconductor substrate 2, thereby also forming rounding on the corners X1 of the electrodes 3. Therefore, the method for manufacturing the semiconductor device 1A according to the second embodiment, as well as the method for manufacturing the semiconductor device 1 according to the first embodiment, makes it easier to peel the semiconductor device 1A from the dicing tape D. Furthermore, the possibility of burrs (such as metal burrs on the electrodes 3) generated during dicing becoming embedded in the dicing tape D can be reduced. As a result, even when the semiconductor device 1A is thin, the success rate of picking up the semiconductor device 1A can be improved, and the yield of the semiconductor device 1A can be improved.

[0089] Furthermore, in either the third or fourth example, the radius of curvature of corner X2 may be 10 μm or more. In that case, the radius of curvature of corner X1 will also be 10 μm or more, following the shape (roundness) of corner X2. This makes it easier to peel the semiconductor device 1A from the dicing tape D, and improves the success rate of picking up the semiconductor device 1A.

[0090] (modified version) Next, a modified example of the second embodiment will be described with reference to Figure 9. As shown in Figure 9, in this modified example, the main surface 21 and the side surface 23 of the semiconductor substrate 2 are connected to each other via a curved surface 26. As a result, the semiconductor substrate 2 also has rounded edges Y2 formed by the main surface 21 and the side surface 23. In other words, the semiconductor substrate 2 has rounded edges Y2.

[0091] In this embodiment, as shown in Figure 9, the semiconductor substrate 2 has rounded edges not only on one edge of the main surface 21, but on all edges of the main surface 21. The semiconductor substrate 2 may have rounded edges on at least one edge of the main surface 21.

[0092] According to this modified example, since the semiconductor substrate 2 has rounded edges not only at the corners X2 but also at the edges Y2, the stress applied to the edges Y2 can be distributed. Therefore, the durability of the semiconductor device 1A can be further improved.

[0093] Furthermore, by having the semiconductor substrate 2 take the shape shown in this modified example, it becomes easier to peel it off from the dicing tape D not only at the corners X2 but also at the edges Y2 during the manufacturing process. This makes it easier to pick up the semiconductor device 1A and further improves the yield of the semiconductor device 1A.

[0094] While embodiments of the present invention have been described, these embodiments and examples are presented as examples only and are not intended to limit the scope of the invention. These embodiments and examples can be carried out in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and examples and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0095] 1, 1A Semiconductor Equipment 2 Semiconductor substrates 2W wafer 3, 4 electrodes 3A, 4A electrode layer 10 Semiconductor Modules 11, 13 Bonding material 12, 14 Metal components 15. Sealing material 21, 22 Main surface 23, 24 Side view 25, 26 curved surface 31, 32 Main surface 33, 34 Side view 35, 36 curved surface Area A A1 Arrow A2 Arrow C Colette D Dicing Tape J Support fixture L Dicing Line OP opening P Push-up pin PO grinding machine R Resist RE1, RE2, RE3 recessed S Spacer T thickness X1, X2 corner Y1, Y2 edges

Claims

1. A step of preparing a wafer having a first main surface and a second main surface opposite to the first main surface, wherein a first electrode layer is disposed on the first main surface and a second electrode layer is disposed on the second main surface, The steps include applying a resist onto the first electrode layer, The process involves selectively exposing the resist at positions corresponding to the intersections of predetermined dicing lines on the wafer and developing it to form a plurality of openings in a grid pattern on the bottom surface in which the first electrode layer is exposed. The process involves etching the first electrode layer exposed on the bottom surface of the opening to form a plurality of recesses in a grid pattern on the first electrode layer, The step of removing the resist, The steps include: attaching a dicing tape to the first electrode layer, A step of dividing the wafer into multiple semiconductor devices by dicing the wafer along the dicing line, The steps include stretching the dicing tape and picking up the semiconductor device, A method for manufacturing a semiconductor device comprising the same equipment.

2. A step of preparing a wafer having a first main surface and a second main surface opposite to the first main surface, wherein a first electrode layer is disposed on the first main surface and a second electrode layer is disposed on the second main surface, A step of dividing the wafer into a plurality of semiconductor devices by dicing the wafer along a predetermined dicing line, wherein each semiconductor device comprises a first electrode having a third main surface opposite to the main surface that contacts the first main surface, a first side surface that intersects substantially perpendicularly with the third main surface, and a second side surface that intersects substantially perpendicularly with both the third main surface and the first side surface. A step of performing laser ablation along the boundary line between the third main surface and the first side surface and the boundary line between the third main surface and the second side surface, or performing laser ablation on the corner consisting of the third main surface, the first side surface and the second side surface, thereby removing a portion of the corner and rounding the corner, The steps include: attaching a dicing tape to the first electrode, The steps include stretching the dicing tape and picking up the individual semiconductor devices, A method for manufacturing a semiconductor device comprising the same equipment.

3. A step of preparing a wafer having a first main surface and a second main surface opposite to the first main surface, wherein a second electrode layer is disposed on the second main surface, The steps include applying a resist to the first main surface, A step of selectively exposing and developing the resist at positions corresponding to the intersections of predetermined dicing lines on the wafer, thereby forming a plurality of openings in a grid pattern on the bottom surface in which the first main surface of the wafer is exposed. A step of etching the wafer exposed in the opening to form a plurality of recesses in a grid pattern on the wafer, The step of removing the resist, The steps include forming a first electrode layer on the first main surface, The steps include: attaching a dicing tape to the first electrode layer, A step of dividing the wafer into multiple semiconductor devices by dicing the wafer along the dicing line, The steps include stretching the dicing tape and picking up the semiconductor device, A method for manufacturing a semiconductor device comprising the same equipment.

4. A step of preparing a wafer having a first main surface and a second main surface opposite to the first main surface, wherein a second electrode layer is disposed on the second main surface, A step of forming spacers in a grid pattern on the second electrode layer at positions corresponding to the intersections of predetermined dicing lines on the wafer, A step of placing the wafer on the support jig such that the second main surface side faces the support jig, A step of grinding the first main surface of the wafer, The steps include forming a first electrode layer on the first main surface, The steps include: attaching a dicing tape to the first electrode layer, A step of dividing the wafer into multiple semiconductor devices by dicing the wafer along the dicing line, The steps include stretching the dicing tape and picking up the semiconductor device, A method for manufacturing a semiconductor device equipped with [the specified features].

Images