SiC semiconductor device

Abstract

This SiC semiconductor device includes: an SiC chip having a main surface; an n-type drift region which is formed on the outer layer of the main surface and which has an impurity concentration that has been adjusted using at least two types of pentavalent elements; and a p-type impurity region which is formed in the drift region so as to form a pn-junction with the drift region.

Description

[Technical Field]

[0001] This application corresponds to Japanese Patent Application No. 2021-014603, filed with the Japan Patent Office on February 1, 2021, and the full disclosure of this application is incorporated herein by reference. The present invention relates to a SiC semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a SiC-SBD including a SiC substrate and a SiC epitaxial layer formed on the SiC substrate. Patent Document 2 discloses a semiconductor device including a SiC substrate and n-type drift regions and p-type pillar regions alternately formed on the SiC substrate in a direction perpendicular to the thickness direction of the SiC substrate. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2008 / 0237608 [Patent Document 2] U.S. Patent Application Publication No. 2019 / 0148485 [Overview of the project] [Problems that the invention aims to solve]

[0004] One embodiment provides a SiC semiconductor device that can improve electrical characteristics. [Means for solving the problem]

[0005] One embodiment provides a SiC semiconductor device comprising a SiC chip having a main surface and an n-type drift region formed on the surface layer of the main surface, having an impurity concentration adjusted by at least two pentavalent elements.

[0006] One embodiment provides a SiC semiconductor device comprising a SiC chip having a main surface and a p-type drift region formed on the surface layer of the main surface, having an impurity concentration adjusted by trivalent elements other than boron.

[0007] One embodiment provides a SiC semiconductor device comprising a SiC chip having a main surface, an n-type drift region formed on the surface layer of the main surface and having an impurity concentration adjusted by at least two pentavalent elements, and a p-type impurity region formed within the drift region so as to form a pn junction with the drift region.

[0008] One embodiment provides a SiC semiconductor device comprising a SiC chip having a main surface, an n-type drift region formed on the surface layer of the main surface, and a p-type impurity region formed within the drift region so as to form a pn junction with the drift region, and having an impurity concentration adjusted by trivalent elements other than boron.

[0009] One embodiment provides a SiC semiconductor device comprising: a SiC chip having a main surface; a p-type drift region formed on the surface layer of the main surface and having an impurity concentration adjusted by trivalent elements other than boron; and an n-type impurity region formed within the drift region so as to form a pn junction with the drift region and having an impurity concentration adjusted by pentavalent elements other than phosphorus and nitrogen.

[0010] The aforementioned or any other purposes, features, and effects will be made clearer by embodiments described with reference to the attached drawings. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is a plan view showing a SiC semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. [Figure 3] Figure 3 is a graph showing the impurity concentration within the SiC chip shown in Figure 2. [Figure 4A] FIG. 4A is a cross-sectional view showing a method of manufacturing the SiC semiconductor device shown in FIG. 1. [Figure 4B] FIG. 4B is a cross-sectional view showing the process after FIG. 4A. [Figure 4C] FIG. 4C is a cross-sectional view showing the process after FIG. 4B. [Figure 4D] FIG. 4D is a cross-sectional view showing the process after FIG. 4C. [Figure 5] FIG. 5 is a cross-sectional view for specifically explaining the process of FIG. 4D. [Figure 6] FIG. 6 corresponds to FIG. 2 and is a cross-sectional view showing the SiC semiconductor device according to the second embodiment. [Figure 7] FIG. 7 is a graph showing the impurity concentration in the SiC chip shown in FIG. 6. [Figure 8A] FIG. 8A is a cross-sectional view showing a method of manufacturing the SiC semiconductor device shown in FIG. 6. [Figure 8B] FIG. 8B is a cross-sectional view showing the process after FIG. 8A. [Figure 9] FIG. 9 corresponds to FIG. 2 and is a cross-sectional view showing the SiC semiconductor device according to the third embodiment. [Figure 10] FIG. 10 is a graph showing the impurity concentration in the SiC chip shown in FIG. 9. [Figure 11] FIG. 11 corresponds to FIG. 9 and is a cross-sectional view showing the SiC semiconductor device according to the fourth embodiment. [Figure 12] FIG. 12 is a graph showing the impurity concentration in the SiC chip shown in FIG. 11. [Figure 13] FIG. 13 corresponds to FIG. 2 and is a cross-sectional view showing the SiC semiconductor device according to the fifth embodiment. [Figure 14] FIG. 14 corresponds to FIG. 2 and is a cross-sectional view showing the SiC semiconductor device according to the sixth embodiment. [[ID=4B]] [Figure 15] FIG. 15 corresponds to FIG. 2 and is a cross-sectional view showing the SiC semiconductor device according to the seventh embodiment. [Figure 16] FIG. 16 corresponds to FIG. 2 and is a cross-sectional view showing the SiC semiconductor device according to the eighth embodiment. [Figure 17] Figure 17 is a plan view showing a SiC semiconductor device according to the ninth embodiment. [Figure 18] Figure 18 is a cross-sectional view along the line XVIII-XVIII shown in Figure 17. [Figure 19A] Figure 19A is a cross-sectional view showing the manufacturing method of the SiC semiconductor device shown in Figure 17. [Figure 19B] Figure 19B is a cross-sectional view showing a process after Figure 19A. [Figure 20] Figure 20 corresponds to Figure 18 and is a cross-sectional view showing a SiC semiconductor device according to the 10th embodiment. [Figure 21A] Figure 21A is a cross-sectional view showing the manufacturing method of the SiC semiconductor device shown in Figure 20. [Figure 21B] Figure 21B is a cross-sectional view showing a process that follows Figure 21A. [Figure 22] Figure 22 corresponds to Figure 18 and is a cross-sectional view showing a SiC semiconductor device according to the 11th embodiment. [Figure 23] Figure 23 corresponds to Figure 18 and is a cross-sectional view showing a SiC semiconductor device according to the 12th embodiment. [Figure 24] Figure 24 is a plan view showing a structure in which a functional device according to the first embodiment is applied to a SiC semiconductor device according to the first embodiment. [Figure 25] Figure 25 is a cross-sectional view along the line XXV-XXV shown in Figure 24. [Figure 26] Figure 26 is a plan view of the SiC chip shown in Figure 25. [Figure 27] Figure 27 is a plan view showing a structure in which a functional device according to the second embodiment is applied to a SiC semiconductor device according to the tenth embodiment. [Figure 28] Figure 28 is a cross-sectional view along the line XXVIII-XXVIII shown in Figure 27. [Figure 29] Figure 29 is a plan view of the SiC chip shown in Figure 28. [Figure 30] Figure 30 is a plan view showing a structure in which a functional device according to a third embodiment is applied to a SiC semiconductor device according to the first embodiment. [Figure 31] Figure 31 is a cross-sectional view along the line XXXI-XXXI shown in Figure 30. [Figure 32] Figure 32 is an enlarged view of region XXXII shown in Figure 30. [Figure 33] Figure 33 is a cross-sectional view along the line XXXIII-XXXIII shown in Figure 32. [Figure 34] Figure 34 is an enlarged view of region XXXIV shown in Figure 31. [Figure 35] Figure 35 is a plan view showing a structure in which a functional device according to the fourth embodiment is applied to a SiC semiconductor device according to the tenth embodiment. [Figure 36] Figure 36 is an enlarged view of region XXXVI shown in Figure 35. [Figure 37] Figure 37 is a cross-sectional view along the line XXXVII-XXXVII shown in Figure 36. [Figure 38] Figure 38 is a cross-sectional view showing a structure in which a functional device according to the fifth embodiment is applied to a SiC semiconductor device according to the tenth embodiment. [Modes for carrying out the invention]

[0012] The attached drawings are schematic diagrams, not strictly accurate representations, and the scale and other aspects may not necessarily match. In the attached drawings, in order to clarify the structure of each semiconductor region, the conductivity type (n-type or p-type) of each semiconductor region, as well as the elements (element symbols) constituting that conductivity type, are indicated in parentheses. The terms "approximately equal" and "approximately constant" in this specification include cases where the numerical value of the measurement target (measurement location) is exactly the same as the numerical value of the comparison target (comparison location), as well as cases where the numerical value of the measurement target (measurement location) falls within the range of 0.9 times or more and 1.1 times or less the numerical value of the comparison target (comparison location).

[0013] Figure 1 is a plan view showing a SiC semiconductor device 1A according to the first embodiment. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a graph showing the impurity concentration within the SiC chip 2 shown in Figure 2. In Figure 3, the vertical axis represents the impurity concentration, and the horizontal axis represents the depth.

[0014] Referring to Figures 1 and 2, the SiC semiconductor device 1A includes a SiC chip 2 formed in a rectangular parallelepiped shape. The SiC chip 2 may also be referred to as a "chip" or "semiconductor chip". In this embodiment, the SiC chip 2 is made of a hexagonal SiC (silicon carbide) single crystal. Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, 6H-SiC single crystals, etc. In this embodiment, an example is shown in which the SiC chip 2 is made of a 4H-SiC single crystal, but this does not exclude other polytypes.

[0015] The SiC chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view (hereinafter simply referred to as "plan view") as seen from their normal direction Z. The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0016] The first principal surface 3 and the second principal surface 4 face the c-plane ((0001) plane) of the SiC single crystal, respectively. Preferably, the first principal surface 3 is formed by the silicon plane of the SiC single crystal, and the second principal surface 4 is formed by the carbon plane of the SiC single crystal. The first principal surface 3 and the second principal surface 4 have an off-angle θ that is inclined at a predetermined angle in a predetermined off-direction D with respect to the c-plane. Preferably, the off-direction D is the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle θ may be greater than 0° and less than or equal to 10°. Preferably, the off-angle θ is 5° or less. Particularly preferably, the off-angle θ is 2° or more and less than or equal to 4.5°.

[0017] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically orthogonal to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in a second direction Y and face a first direction X. In this configuration, the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal, and the second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal. In other words, the first direction X is the off-direction D.

[0018] The SiC semiconductor device 1A includes an n-type base region 6 formed in the region on the second main surface 4 side (the surface layer of the second main surface 4) within the SiC chip 2. The base region 6 is formed in layers extending along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. The base region 6 has an impurity concentration adjusted by a first impurity (=n-type impurity) consisting of a pentavalent element. Preferably, the first impurity consists of one type of pentavalent element. The first impurity may be any one of the pentavalent elements: phosphorus (P), nitrogen (N), arsenic (As), and antimony (Sb). Preferably, the first impurity is a pentavalent element other than phosphorus. In this form, the first impurity is nitrogen.

[0019] Referring to Figure 3, the base region 6 has a first concentration C1 that is approximately constant in the thickness direction. The first concentration C1 is 1 × 10 18 cm -3 The above 1 x 10 21 cm -3 The following is also possible: The base region 6 may have a thickness of 5 μm or more and 300 μm or less. Preferably, the thickness of the base region 6 is 50 μm or more and 250 μm or less. In this embodiment, the base region 6 is formed on a SiC substrate.

[0020] The SiC semiconductor device 1A includes an n-type buffer region 7 formed in a region on the first main surface 3 side with respect to the base region 6 within the SiC chip 2. The buffer region 7 is formed in the middle portion in the thickness direction of the SiC chip 2 spaced apart from the first main surface 3 toward the second main surface 4. The buffer region 7 is formed in a layer shape extending along the first main surface 3 and is exposed from the first to fourth side surfaces 5A to 5D. The buffer region 7 contains a pentavalent element and has an impurity concentration that decreases (specifically, gradually decreases) toward the first main surface 3. The buffer region 7 preferably contains any one of the pentavalent elements of phosphorus, nitrogen, arsenic, and antimony. The buffer region 7 preferably contains a pentavalent element other than phosphorus.

[0021] Referring to FIG. 3, in this form, the buffer region 7 has an impurity concentration adjusted by the first impurity (= nitrogen), and has a concentration gradient (concentration distribution) that decreases (specifically, gradually decreases) from the first concentration C1 to a second concentration C2 (C2 < C1) less than the first concentration C1 from the base region 6 toward the first main surface 3. The second concentration C2 may be 1×10 14 cm -3 or more and 1×10 16 cm -3 or less. The buffer region 7 may have a thickness of 0.1 μm or more and 5 μm or less. The thickness of the buffer region 7 is preferably 1 μm or more and 3 μm or less. In this form, the buffer region 7 is formed in the SiC epitaxial layer.

[0022] The SiC semiconductor device 1A includes an n-type drift region 8 formed in the surface layer portion of the first main surface 3. The drift region 8 is formed in a region between the first main surface 3 and the buffer region 7 within the SiC chip 2. The drift region 8 is formed in a layer shape extending along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. The drift region 8 is concentration-adjusted by at least two kinds of pentavalent elements.

[0023] That is, the drift region 8 includes a region in which at least two kinds of pentavalent elements are mixed in the region between the first main surface 3 and the buffer region 7. The drift region 8 preferably contains a pentavalent element other than phosphorus and has an impurity concentration adjusted by the pentavalent element other than phosphorus. The drift region 8 particularly preferably contains nitrogen as a pentavalent element and a pentavalent element other than nitrogen. The drift region 8 preferably contains at least one of arsenic and antimony as a pentavalent element other than phosphorus and nitrogen.

[0024] Referring to FIG. 3, the drift region 8 has an impurity concentration that increases toward the first main surface 3. Specifically, the drift region 8 has a concentration gradient (concentration distribution) that increases (specifically, gradually increases) from the second concentration C2 to a third concentration C3 (C2 < C3) exceeding the second concentration C2 from the buffer region 7 toward the first main surface 3. The third concentration C3 is the peak concentration of the drift region 8.

[0025] The third concentration C3 only needs to be located in the vicinity (surface layer portion) of the first main surface 3 and does not necessarily have to coincide with the first main surface 3. The third concentration C3 is equal to or less than the first concentration C1 (C2 < C3 ≦ C1). The third concentration C3 is preferably 10 times or more the second concentration C2. The third concentration C3 is preferably less than the first concentration C1 (C3 < C1). The third concentration C3 is 1×10 15 cm -3 or more and may be 1×10 17 cm -3 or less.

[0026] The drift region 8 has a base concentration CA and an additional concentration CB. The additional concentration CB complements the base concentration CA. The impurity concentration of the drift region 8 consists of the sum of the base concentration CA and the additional concentration CB. The base concentration CA is due to a first impurity that is a pentavalent element. The first impurity is a pentavalent element other than phosphorus (in this form, nitrogen). The additional concentration CB is due to a second impurity that is a pentavalent element other than the first impurity. The second impurity is a pentavalent element other than phosphorus and nitrogen. The second impurity is, in this form, at least one of arsenic and antimony.

[0027] The drift region 8 has a base concentration CA (first impurity) and an additional concentration CB (second impurity) in regions on the side of the first main surface 3 and on the side of the second main surface 4 (buffer region 7 side) with respect to the intermediate part MID between the first main surface 3 and the buffer region 7. In this form, the drift region 8 has the base concentration CA (first impurity) and the additional concentration CB (second impurity) throughout the entire thickness direction.

[0028] The base concentration CA has a substantially constant concentration distribution in the thickness direction. In this form, the base concentration CA is approximately equal to the second concentration C2 which is the lower limit value of the concentration of the buffer region 7 (CA≈C2). Of course, the base concentration CA may have a concentration gradient (concentration distribution) that increases from the buffer region 7 toward the first main surface 3. The additional concentration CB has a concentration distribution that increases (specifically, gradually increases) toward the first main surface 3. The additional concentration CB exceeds the base concentration CA (CA < CB). The additional concentration CB is preferably 10 times or more the base concentration CA. The additional concentration CB is preferably less than the first concentration C1 (CA < CB < C1).

[0029] The drift region 8 preferably has a thickness exceeding the thickness of the buffer region 7. The drift region 8 may have a thickness of 1 μm or more and 25 μm or less. The drift region 8 may have a thickness belonging to any one of the ranges of 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, and 20 μm or more and 25 μm or less. The drift region 8 particularly preferably has a thickness of 1 μm or more and 10 μm or less. In this form, the drift region 8 is formed in a SiC epitaxial layer.

[0030] The SiC semiconductor device 1A includes a functional device 9 formed on the first main surface 3 side using a drift region 8. In Figures 1 and 2, the functional device 9 is shown in a simplified form by a dashed line. The functional device 9 has at least a portion of the drift region 8 as a mobile region (=current path) for carriers. The functional device 9 is formed in the inner part of the first main surface 3, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the SiC chip 2.

[0031] The functional device 9 may include at least one of a semiconductor switching device, a semiconductor rectifier device, and a semiconductor passive device. The semiconductor switching device may include at least one of a MISFET (Metal Insulator Semiconductor Field Effect Transistor), a BJT (Bipolar Junction Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor). The semiconductor rectifier device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, an SBD (Schottky Barrier Diode), and an FRD (Fast Recovery Diode). The semiconductor passive device may include at least one of a resistor and a capacitor.

[0032] The functional device 9 may include a circuit network (e.g., an integrated circuit such as an LSI) that combines at least two of the semiconductor switching devices, semiconductor rectifiers, and semiconductor passive devices. The functional device 9 typically includes at least one of the SiC-MISFET and SiC-SBD.

[0033] As described above, the SiC semiconductor device 1A includes a SiC chip 2 and a drift region 8. The SiC chip 2 has a first main surface 3. The drift region 8 is formed on the surface layer of the first main surface 3 and has an impurity concentration adjusted by at least two types of pentavalent elements. The at least two types of pentavalent elements are mixed within a predetermined thickness range on the surface layer of the first main surface 3. With this structure, the impurity concentration due to one pentavalent element can be compensated for by the impurity concentration due to the other pentavalent element. As a result, the drift region 8 can have an impurity concentration with reduced variation from the target concentration. Therefore, a SiC semiconductor device 1A with improved electrical characteristics can be provided.

[0034] Preferably, the drift region 8 has an impurity concentration adjusted to increase toward the first main surface 3. This structure allows for the proper formation of a drift region 8 having a concentration gradient (concentration distribution) that increases toward the first main surface 3 by at least two pentavalent elements.

[0035] The drift region 8 preferably has an impurity concentration adjusted by pentavalent elements other than phosphorus. The drift region 8 preferably contains nitrogen as a pentavalent element and other pentavalent elements. The drift region 8 preferably has a base concentration CA due to a first impurity which is a pentavalent element, and an additional concentration CB due to a second impurity which is a pentavalent element other than the first impurity.

[0036] The first impurity is preferably a pentavalent element other than phosphorus. The first impurity is preferably nitrogen. The second impurity is preferably a pentavalent element other than phosphorus. The second impurity is preferably at least one of arsenic and antimony. The base concentration CA is preferably having a substantially constant concentration distribution in the thickness direction. The added concentration CB is preferably having a concentration distribution that increases toward the first main surface 3.

[0037] The drift region 8 may have a thickness of 1 μm to 25 μm. This structure allows for appropriate adjustment of the impurity concentration in the drift region 8 using at least two pentavalent elements. The thickness of the drift region 8 is preferably 1 μm to 10 μm.

[0038] The SiC chip 2 is preferably made of a hexagonal SiC single crystal. The first main surface 3 is preferably facing the c-plane of the SiC single crystal. The first main surface 3 is preferably having an off-angle θ of 10° or less with respect to the c-plane. The off-angle θ is preferably in an off-direction D along the a-axis direction of the SiC single crystal. The drift region 8 is preferably formed in the SiC epitaxial layer. The SiC semiconductor device 1A preferably includes a functional device 9 formed using at least a portion of the drift region 8 on the first main surface 3. This structure allows for improved electrical characteristics of the functional device 9.

[0039] Figures 4A to 4D are cross-sectional views showing the manufacturing method of the SiC semiconductor device 1A shown in Figure 1. Figure 5 is a cross-sectional view that specifically illustrates the process shown in Figure 4D.

[0040] Referring to Figure 4A, an n-type SiC wafer 10 is prepared. The SiC wafer 10 is a disc-shaped single crystal plate. The SiC wafer 10 has an impurity concentration adjusted by a first impurity. The first impurity is preferably a pentavalent element other than phosphorus. The first impurity is preferably composed of one type of pentavalent element. The first impurity is preferably one of nitrogen, arsenic, and antimony. In this form, the first impurity is nitrogen. The SiC wafer 10 has a first concentration C1 that is approximately constant in the thickness direction. The SiC wafer 10 forms the basis of the base region 6.

[0041] The SiC wafer 10 has a first wafer main surface 11 on one side and a second wafer main surface 12 on the other side. The first wafer main surface 11 and the second wafer main surface 12 face the c-plane of the SiC single crystal. The c-plane includes the silicon plane ((0001) plane) and the carbon plane ((000-1) plane) of the SiC single crystal. Preferably, the first wafer main surface 11 faces the silicon plane and the second wafer main surface 12 faces the carbon plane. The first wafer main surface 11 and the second wafer main surface 12 each face the c-plane of the SiC single crystal. Preferably, the first wafer main surface 11 is formed by the silicon plane of the SiC single crystal and the second wafer main surface 12 is formed by the carbon plane of the SiC single crystal.

[0042] The first wafer main surface 11 and the second wafer main surface 12 have an off-angle θ that is inclined at a predetermined angle in a predetermined off-direction D with respect to the c-plane. The off-direction D is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle θ may be greater than 0° and less than or equal to 10°. The off-angle θ is preferably 5° or less. The off-angle θ is particularly preferably 2° or more and less than or equal to 4.5°. The SiC wafer 10 may have a thickness of 50 μm or more and less than or equal to 500 μm. The thickness of the SiC wafer 10 is adjusted by grinding the second wafer main surface 12.

[0043] Referring to Figure 4B, an n-type first SiC epitaxial layer 13 is formed on the first wafer main surface 11 by epitaxial growth. The first SiC epitaxial layer 13 is formed in such a manner that it inherits the off-direction D and off-angle θ from the SiC wafer 10. The first SiC epitaxial layer 13 is formed by epitaxial growth of SiC on the first wafer main surface 11 while introducing a pentavalent element (first impurity in this configuration). The impurity concentration of the first SiC epitaxial layer 13 is adjusted to decrease (specifically gradually decrease) from a first concentration C1 to a second concentration C2, starting from the SiC wafer 10. The first SiC epitaxial layer 13 forms the basis of the buffer region 7.

[0044] Referring to Figure 4C, an n-type second SiC epitaxial layer 14 is formed on the first SiC epitaxial layer 13 by epitaxial growth. The second SiC epitaxial layer 14 is formed in such a manner that it inherits the off-direction D and off-angle θ from the first SiC epitaxial layer 13. The second SiC epitaxial layer 14 is formed by epitaxial growth of SiC on the first SiC epitaxial layer 13 while introducing a pentavalent element (first impurity in this form). The impurity concentration of the second SiC epitaxial layer 14 is adjusted to be approximately constant in the crystal growth direction.

[0045] In this configuration, the impurity concentration of the second SiC epitaxial layer 14 is adjusted to maintain a nearly constant second concentration C2 from the first SiC epitaxial layer 13 toward the crystal growth direction. Of course, the impurity concentration of the second SiC epitaxial layer 14 may also be adjusted to increase (specifically, gradually increase) toward the crystal growth direction from the first SiC epitaxial layer 13. The second SiC epitaxial layer 14 forms the basis of the drift region 8. In other words, the second SiC epitaxial layer 14 is formed at a lower concentration than the target concentration of the drift region 8.

[0046] Referring to Figure 4D, pentavalent elements are implanted into the second SiC epitaxial layer 14 by ion implantation, forming an n-type drift region 8 with a target concentration. In this process, pentavalent elements are implanted throughout the entire second SiC epitaxial layer 14 so that the impurity concentration increases (specifically, gradually increases) in the direction of crystal growth. This forms an n-type drift region 8 with a concentration gradient (target concentration) that increases from the second concentration C2 to the third concentration C3 in the direction of crystal growth.

[0047] Referring to Figure 5, the ion implantation method in this form is the channeling implantation method. In the channeling implantation method, pentavalent elements are implanted into the second SiC epitaxial layer 14 along the direction of sparse atomic arrangement (= crystal axis direction) of the SiC single crystal. Specifically, the crystal axis of the SiC single crystal is the c-axis of the SiC single crystal ( <0001> This method reduces the probability of pentavalent elements colliding with constituent atoms of the SiC single crystal, allowing pentavalent elements to be implanted into deeper regions of the second SiC epitaxial layer 14. In this process, pentavalent elements are implanted into the region of the second SiC epitaxial layer 14 on the main surface (crystal growth surface) side and the region on the SiC wafer 10 side, relative to the middle portion of the second SiC epitaxial layer 14.

[0048] In this process, a second impurity consisting of a pentavalent element different from the first impurity (=nitrogen) contained in the second SiC epitaxial layer 14 is implanted. In this form, the second impurity is at least one of arsenic and antimony. This creates a drift region 8 having a base concentration CA (=second concentration C2) due to the first impurity and an added concentration CB due to the second impurity. The base concentration CA has a concentration distribution that is almost constant in the thickness direction. The added concentration CB has a concentration distribution that increases toward the first main surface 3.

[0049] The implantation depth of the second impurity into the second SiC epitaxial layer 14 is precisely adjusted by adjusting the implantation energy of the second impurity, the implantation temperature of the second impurity, the implantation angle of the second impurity, etc. The implantation energy of the second impurity may be adjusted in the range of 10 keV to 1000 keV (preferably 100 keV or more). The implantation temperature of the second impurity may be adjusted in the range of 300°C to 1000°C.

[0050] The injection angle of the second impurity is set within a range of ±5° with the crystal axis (=c axis) of the SiC single crystal as the reference (=0°). Preferably, the injection angle of the second impurity is set within a range of ±2°. In this embodiment, the second SiC epitaxial layer 14 (SiC wafer 10) has an off-angle θ tilted in a predetermined off-direction D. Therefore, the injection angle of the second impurity to the second SiC epitaxial layer 14, or the tilt angle of the second SiC epitaxial layer 14 with respect to the injection direction of the second impurity, is adjusted according to the off-direction D and the off-angle θ.

[0051] Of course, the second impurity may be phosphorus or nitrogen as a pentavalent element. However, phosphorus or nitrogen has properties that make it difficult to implant into deep regions of the second SiC epitaxial layer 14 by the channeling implantation method. Therefore, it is preferable that the second impurity be at least one of arsenic and antimony.

[0052] After the injection of the second impurity, the second impurity is electrically activated by annealing, and at the same time, lattice defects and other defects that have formed in the second SiC epitaxial layer 14 are repaired. The annealing temperature of the second SiC epitaxial layer 14 may be between 500°C and 2000°C. This forms a drift region 8. Subsequently, a functional device 9 is formed on the main surface (crystal growth surface) side of the second SiC epitaxial layer 14, utilizing a portion of the drift region 8. The SiC semiconductor device 1A is manufactured through the process including the above.

[0053] It is conceivable to form a second SiC epitaxial layer 14 with the target concentration of the drift region 8 from the outset by epitaxial growth. However, with this method, it is difficult to accurately control the amount of pentavalent elements introduced, resulting in the formation of a drift region 8 with a relatively large concentration variation relative to the target concentration. This problem becomes more pronounced as the thickness of the second SiC epitaxial layer 14 increases. Furthermore, this problem becomes more pronounced as the impurity concentration of the second SiC epitaxial layer 14 increases.

[0054] In contrast, the manufacturing method for the SiC semiconductor device 1A involves a first step of preparing an n-type second SiC epitaxial layer 14, and a second step of forming an n-type drift region 8. In the first step, a low-concentration n-type second SiC epitaxial layer 14 is prepared. Specifically, the impurity concentration of the second SiC epitaxial layer 14 is less than the target concentration of the drift region 8. In the second step, pentavalent elements (n-type impurities) are implanted into the second SiC epitaxial layer 14 by ion implantation, and an n-type drift region 8 with a target concentration is formed.

[0055] According to this manufacturing method, the impurity concentration of the second SiC epitaxial layer 14 is compensated for by the increased impurity concentration resulting from the ion implantation method. Compared to epitaxial growth methods that involve the introduction of impurities, the amount of impurities introduced can be appropriately controlled by the ion implantation method. This reduces the concentration variation in the drift region 8 relative to the target concentration. Therefore, a SiC semiconductor device 1A with improved electrical properties can be manufactured and provided.

[0056] In the manufacturing method of the SiC semiconductor device 1A, a second SiC epitaxial layer 14 having an impurity concentration adjusted by a first impurity may be prepared. In this case, the drift region 8 may be formed by implanting a second impurity different from the first impurity into the second SiC epitaxial layer 14. The first impurity is preferably a pentavalent element other than phosphorus. The first impurity is preferably nitrogen. The second impurity is preferably a pentavalent element other than phosphorus. The second impurity is preferably at least one of arsenic and antimony.

[0057] The ion implantation method is preferably a channeling implantation method in which a second impurity is implanted along the crystal axis of the second SiC epitaxial layer 14. The second impurity is preferably implanted into the second SiC epitaxial layer 14 at an implantation angle of ±5° or less with respect to the crystal axis of the SiC single crystal. The crystal axis of the SiC single crystal is preferably the c-axis. The second SiC epitaxial layer 14 is preferably off-angle θ of 10° or less with respect to the c-plane of the SiC single crystal. The off-angle θ is preferably off-direction D along the a-axis direction of the SiC single crystal.

[0058] Figure 6 is a cross-sectional view showing the SiC semiconductor device 1B according to the second embodiment, corresponding to Figure 2. Figure 7 is a graph showing the impurity concentration within the SiC chip 2 shown in Figure 6. In Figure 7, the vertical axis represents the impurity concentration, and the horizontal axis represents the depth. Hereafter, structures corresponding to those described in the first embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0059] Referring to Figures 6 and 7, the SiC semiconductor device 1B, like the SiC semiconductor device 1A, includes a SiC chip 2, an n-type base region 6, an n-type buffer region 7, an n-type drift region 8, and a functional device 9. In this embodiment, the drift region 8 includes a first region 8a and a second region 8b, formed in this order from the bottom toward the first main surface 3.

[0060] The first region 8a is a region having an impurity concentration adjusted by one type of pentavalent element, and is formed on the surface of the first main surface 3, spaced apart from it. Specifically, the first region 8a is formed in a layered manner extending along the first main surface 3 on top of the buffer region 7, and is exposed from the first to fourth sides 5A to 5D. The first region 8a is formed in the region on the second main surface 4 side (buffer region 7 side) relative to the intermediate region MID. Preferably, the first region 8a is formed with a gap between the intermediate region MID and the second main surface 4 side.

[0061] The first region 8a contains a first impurity and has a base concentration CA due to the first impurity. The first impurity is the same as in the first embodiment. That is, the first impurity may be any one of phosphorus, nitrogen, arsenic, and antimony. Preferably, the first impurity is a pentavalent element other than phosphorus. In this form, the first impurity is nitrogen. The base concentration CA is approximately equal to the lower limit of the concentration in the buffer region 7 (= second concentration C2) (CA ≈ C2). The first region 8a has a concentration distribution that is approximately constant in the thickness direction. Of course, the first region 8a may have a concentration gradient (concentration distribution) that rises from the buffer region 7 (second concentration C2) toward the first main surface 3.

[0062] The second region 8b is a region having an impurity concentration adjusted by at least two pentavalent elements. The second region 8b is formed in a layered manner extending along the first main surface 3 in the region between the first main surface 3 and the first region 8a, and is exposed from the first main surface 3 and the first to fourth sides 5A to 5D. The second region 8b is formed in the region on the first main surface 3 side with respect to the intermediate portion MID. Preferably, the second region 8b is also formed in the region on the second main surface 4 side, crossing the intermediate portion MID.

[0063] The second region 8b has a concentration gradient (concentration distribution) that increases (specifically, gradually increases) from the base concentration CA (≈ second concentration C2) of the first region 8a to the third concentration C3. In this embodiment, the second region 8b has a base concentration CA due to the first impurity and an additional concentration CB due to the second impurity consisting of pentavalent elements other than the first impurity. The second impurity is the same as in the first embodiment. That is, the second impurity preferably contains at least one of arsenic and antimony.

[0064] The base concentration CA of the second region 8b has a substantially constant concentration distribution in the thickness direction, similar to the first embodiment. Of course, the base concentration CA of the second region 8b may have a concentration gradient (concentration distribution) that rises toward the first main surface 3. The added concentration CB of the second region 8b has a concentration gradient (concentration distribution) that rises toward the first main surface 3, similar to the first embodiment. The second region 8b has a resistance value less than that of the first region 8a. In other words, the first region 8a is a high-resistance region, and the second region 8b is a low-resistance region.

[0065] As described above, the SiC semiconductor device 1B exhibits the same effects as those described for the SiC semiconductor device 1A.

[0066] Figures 8A and 8B are cross-sectional views showing the manufacturing method of the SiC semiconductor device 1B shown in Figure 6. Referring to Figure 8A, a first SiC epitaxial layer 13 and a second SiC epitaxial layer 14 are formed on the SiC wafer 10 through the same process as in Figures 4A to 4C.

[0067] Referring to Figure 8B, similar to the process in Figure 4D, pentavalent elements (n-type impurities) are implanted into the second SiC epitaxial layer 14 up to a certain point in the thickness direction by ion implantation (channeling implantation in this embodiment), forming an n-type drift region 8 with a target concentration. In this embodiment, the drift region 8 includes a first region 8a consisting of a part of the second SiC epitaxial layer 14, and a second region 8b in which pentavalent elements are further implanted into the second SiC epitaxial layer 14. The impurity concentration in the second region 8b is adjusted to increase in the direction of crystal growth of the second SiC epitaxial layer 14.

[0068] In this process, a second impurity (at least one of arsenic and antimony), which is a pentavalent element different from the first impurity (nitrogen) contained in the second SiC epitaxial layer 14, is injected into the second SiC epitaxial layer 14 up to a certain point in the thickness direction. This forms a first region 8a having a base concentration CA (second concentration C2) due to the first impurity. In addition, a second region 8b is formed having a base concentration CA due to the first impurity and an added concentration CB due to the second impurity.

[0069] As described above, the manufacturing method for SiC semiconductor device 1B produces the same effects as those described for the manufacturing method for SiC semiconductor device 1A.

[0070] Figure 9 is a cross-sectional view showing the SiC semiconductor device 1C according to the third embodiment, corresponding to Figure 2. Figure 10 is a graph showing the impurity concentration within the SiC chip 2 shown in Figure 9. In Figure 10, the vertical axis represents the impurity concentration, and the horizontal axis represents the depth. Hereafter, structures corresponding to those described in the first and second embodiments are denoted by the same reference numerals, and their descriptions are omitted.

[0071] Referring to Figures 9 and 10, the SiC semiconductor device 1C has a structure in which the "n-type region" is replaced with a "p-type region" in the SiC semiconductor device 1A. Specifically, the SiC semiconductor device 1C includes a p-type base region 16, a p-type buffer region 17, and a p-type drift region 18 instead of the n-type base region 6, the n-type buffer region 7, and the n-type drift region 8.

[0072] The p-type base region 16 has an impurity concentration adjusted by a first impurity (=p-type impurity) consisting of a trivalent element. Preferably, the first impurity consists of one type of trivalent element. The first impurity may be any one of boron (B), aluminum (Al), gallium (Ga), and indium (In). Preferably, the first impurity is a trivalent element other than boron. In this embodiment, the first impurity is aluminum.

[0073] The base region 16 has a substantially constant first concentration C1 in the thickness direction. The first concentration C1 is 1×10 18 cm -3 or more and may be 1×10 21 cm -3 or less. The base region 16 may have a thickness of 5 μm or more and 300 μm or less. The thickness of the base region 16 is preferably 50 μm or more and 250 μm or less. In this form, the base region 16 is formed on the SiC substrate.

[0074] The p-type buffer region 17 contains a trivalent element and has an impurity concentration adjusted so that the impurity concentration decreases (specifically, gradually decreases) toward the first main surface 3. The buffer region 17 preferably contains any one of boron, aluminum, gallium, and indium. The buffer region 17 preferably contains a trivalent element other than boron. In this form, the buffer region 17 is concentration-adjusted by the first impurity (= aluminum).

[0075] [[ID=I5]] The buffer region 17 has a concentration gradient (concentration distribution) that decreases (specifically, gradually decreases) from the first concentration C1 to a second concentration C2 (C2 < C1) less than the first concentration C1 from the base region 16 toward the first main surface 3. The second concentration C2 is 1×10 14 cm -3 or more and may be 1×10 16 cm -3 or less. The buffer region 17 may have a thickness of 0.1 μm or more and 5 μm or less. The thickness of the buffer region 17 is preferably 1 μm or more and 3 μm or less. In this form, the buffer region 17 is formed on the SiC epitaxial layer.

[0076] The p-type drift region 18 contains a trivalent element other than boron and has an impurity concentration adjusted by the trivalent element other than boron. The drift region 18 preferably contains at least one of aluminum, gallium, and indium. The drift region 18 has an impurity concentration adjusted to increase toward the first main surface 3. Specifically, the drift region 18 has a concentration gradient (concentration distribution) that increases (specifically, gradually increases) from the second concentration C2 to a third concentration C3 (C2 < C3) exceeding the second concentration C2 toward the first main surface 3 from the buffer region 17.

[0077] The third concentration C3 is the peak concentration of the drift region 18. The third concentration C3 only needs to be located in the vicinity (surface layer portion) of the first main surface 3 and does not necessarily have to coincide with the first main surface 3. The third concentration C3 is not more than the first concentration C1 (C3 ≦ C1). The third concentration C3 is preferably at least 10 times the second concentration C2. The third concentration C3 is preferably less than the first concentration C1 (C2 < C3 < C1). The third concentration C3 is 1×10 15 cm -3 or more and 1×10 17 cm -3 or less.

[0078] The drift region 18 has a base concentration CA and an additional concentration CB. The additional concentration CB complements the base concentration CA. The impurity concentration (third concentration C3) of the drift region 18 consists of the sum of the base concentration CA and the additional concentration CB. The base concentration CA is due to a first impurity that is a trivalent element. The additional concentration CB is due to a trivalent element of the same type as the first impurity or a second impurity that is a trivalent element of a different type from the first impurity. The second impurity may be at least one of aluminum, gallium, and indium. In this form, the second impurity is aluminum.

[0079] The drift region 18 has a base concentration CA (first impurity) and an additional concentration CB (second impurity) in the region on the side of the first main surface 3 and the region on the side of the second main surface 4 (buffer region 17 side) with respect to the intermediate portion MID. In this form, the drift region 18 has the base concentration CA (first impurity) and the additional concentration CB (second impurity) throughout the thickness direction.

[0080] The base concentration CA has a substantially constant concentration distribution in the thickness direction. In this form, the base concentration CA is approximately equal to the second concentration C2 which is the lower limit of the concentration of the buffer region 17 (CA≈C2). Of course, the base concentration CA may have a concentration gradient (concentration distribution) that increases (specifically, gradually increases) from the buffer region 17 toward the first main surface 3. The additional concentration CB has a concentration distribution that increases toward the first main surface 3. The additional concentration CB exceeds the base concentration CA (CA < CB). The additional concentration CB is preferably 10 times or more the base concentration CA. The additional concentration CB is preferably less than the first concentration C1 (CA < CB < C1).

[0081] The drift region 18 preferably has a thickness exceeding the thickness of the buffer region 17. The drift region 18 may have a thickness of 1 μm or more and 25 μm or less. The drift region 18 may have a thickness belonging to any one of the ranges of 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, and 20 μm or more and 25 μm or less. The drift region 18 particularly preferably has a thickness of 1 μm or more and 10 μm or less. In this form, the drift region 18 is formed in a SiC epitaxial layer.

[0082] As described above, the SiC semiconductor device 1C also exhibits the same effects as those described for the SiC semiconductor device 1A. The SiC semiconductor device 1C is manufactured by replacing a pentavalent element with a predetermined trivalent element in the manufacturing method of the SiC semiconductor device 1A (Figs. 4A to 4D). Therefore, the manufacturing method of the SiC semiconductor device 1C also exhibits the same effects as those described for the manufacturing method of the SiC semiconductor device 1A.

[0083] Figure 11 corresponds to Figure 9 and is a cross-sectional view showing the SiC semiconductor device 1D according to the fourth embodiment. Figure 12 is a graph showing the impurity concentration in the SiC chip 2 shown in Figure 11. In Figure 12, the vertical axis represents the impurity concentration and the horizontal axis represents the depth. Hereafter, structures corresponding to those described in the first to third embodiments are denoted by the same reference numerals, and their descriptions are omitted.

[0084] Referring to Figures 11 and 12, the SiC semiconductor device 1D, like the SiC semiconductor device 1C, includes a SiC chip 2, a p-type base region 16, a p-type buffer region 17, a p-type drift region 18, and a functional device 9. The drift region 18 has an impurity concentration adjusted by trivalent elements other than boron, as in the third embodiment. In this embodiment, the drift region 18 includes a first region 18a and a second region 18b, formed in this order from the bottom toward the first main surface 3.

[0085] The first region 18a is a region having an impurity concentration adjusted by one type of trivalent element, and is formed on the surface of the first main surface 3, spaced apart from it. Specifically, the first region 18a is formed in a layered manner extending along the first main surface 3 on top of the buffer region 17, and is exposed from the first to fourth sides 5A to 5D. The first region 18a is formed on the second main surface 4 side (buffer region 17 side) relative to the intermediate region MID. Preferably, the first region 18a is formed with a gap between the intermediate region MID and the second main surface 4 side.

[0086] In this embodiment, the first region 18a contains a first impurity which is a trivalent element and has a base concentration CA due to the first impurity. The first impurity may be any one of aluminum, gallium, and indium. In this embodiment, the first impurity is aluminum. The base concentration CA is approximately equal to the second concentration C2, which is the lower limit of the concentration in the buffer region 17 (CA ≈ C2). The first region 18a has a concentration distribution that is approximately constant in the thickness direction. Of course, the first region 18a may also have a concentration gradient (concentration distribution) that rises from the buffer region 17 (second concentration C2) toward the first main surface 3.

[0087] The second region 18b is formed in the region between the first main surface 3 and the first region 18a. The second region 18b is formed in layers extending along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. The second region 18b is formed in the region on the first main surface 3 side with respect to the intermediate portion MID. Preferably, the second region 18b is also formed in the region on the second main surface 4 side, crossing the intermediate portion MID.

[0088] The second region 18b is a region having an impurity concentration adjusted by a first impurity and a second impurity which is either the same type of trivalent element as the first impurity or a different type of trivalent element from the first impurity. The second impurity may be any one of aluminum, gallium, and indium. In this form, the second impurity is aluminum. The second region 18b has a concentration gradient (concentration distribution) that increases (specifically gradually increases) from the base concentration CA (= second concentration C2) of the first region 18a to the third concentration C3. In this form, the second region 18b has a base concentration CA due to the first impurity and an additional concentration CB due to the second impurity.

[0089] The base concentration CA of the second region 18b has a substantially constant concentration distribution in the thickness direction, similar to the third embodiment. Of course, the base concentration CA of the second region 18b may have a concentration gradient (concentration distribution) that rises toward the first main surface 3. The added concentration CB has a concentration gradient (concentration distribution) that rises toward the first main surface 3, similar to the third embodiment. The second region 18b has a resistance value less than the resistance value of the first region 18a. In other words, the first region 18a is a high-resistance region, and the second region 18b is a low-resistance region.

[0090] As described above, the SiC semiconductor device 1D produces the same effects as those described for the SiC semiconductor device 1A. The SiC semiconductor device 1D is manufactured by replacing the pentavalent elements with predetermined trivalent elements in the manufacturing method of the SiC semiconductor device 1B according to the second embodiment (Figures 8A to 8B). Therefore, the manufacturing method of the SiC semiconductor device 1D produces the same effects as those described for the manufacturing method of the SiC semiconductor device 1A.

[0091] Figure 13 corresponds to Figure 2 and is a cross-sectional view showing the SiC semiconductor device 1E according to the fifth embodiment. Hereinafter, structures corresponding to those described in the first to fourth embodiments are denoted by the same reference numerals, and their descriptions are omitted.

[0092] Referring to Figure 13, the SiC semiconductor device 1E has a structure in which the n-type base region 6 according to the first embodiment is changed to a p-type base region 16 according to the third embodiment. In this case, the n-type buffer region 17 may have a cancellation region at the boundary with the p-type base region 6 in which the concentration of p-type impurities caused by trivalent elements in the base region 6 is canceled out by the concentration of n-type impurities caused by pentavalent elements.

[0093] As described above, the SiC semiconductor device 1E also produces the same effects as those described for the SiC semiconductor device 1A. The SiC semiconductor device 1E is manufactured by preparing a p-type SiC wafer 10 having an impurity concentration adjusted by a predetermined trivalent element in the manufacturing method of the SiC semiconductor device 1A (Figures 4A to 4D). Therefore, the manufacturing method of the SiC semiconductor device 1E also produces the same effects as those described for the manufacturing method of the SiC semiconductor device 1A according to the first embodiment.

[0094] Figure 14 corresponds to Figure 6 and is a cross-sectional view showing the SiC semiconductor device 1F according to the sixth embodiment. Hereinafter, structures corresponding to those described in the first to fifth embodiments are denoted by the same reference numerals, and their descriptions are omitted.

[0095] Referring to Figure 14, the SiC semiconductor device 1F has a structure in which the n-type base region 6 according to the second embodiment is changed to a p-type base region 16 according to the third embodiment. In this case, the n-type buffer region 17 may have a cancellation region at the boundary with the p-type base region 6 in which the concentration of p-type impurities caused by trivalent elements in the base region 6 is canceled out by the concentration of n-type impurities caused by pentavalent elements.

[0096] As described above, the SiC semiconductor device 1F exhibits the same effects as those described for the SiC semiconductor device 1A. The SiC semiconductor device 1F is manufactured by preparing a p-type SiC wafer 10 having an impurity concentration adjusted by a predetermined trivalent element in the manufacturing method of the SiC semiconductor device 1A (Figures 4A to 4D and 8A to 8B). Therefore, the manufacturing method of the SiC semiconductor device 1F exhibits the same effects as those described for the manufacturing method of the SiC semiconductor device 1A.

[0097] Figure 15 corresponds to Figure 2 and is a cross-sectional view showing the SiC semiconductor device 1G according to the seventh embodiment. Hereinafter, structures corresponding to those described in the first to sixth embodiments are denoted by the same reference numerals, and their descriptions are omitted.

[0098] Referring to Figure 15, the SiC semiconductor device 1G has a structure in which the p-type base region 16 according to the third embodiment is changed to the n-type base region 6 according to the first embodiment. In this case, the p-type buffer region 17 may have a cancellation region at the boundary with the n-type base region 6 in which the n-type impurity concentration due to pentavalent elements in the base region 6 is canceled out by the p-type impurity concentration due to trivalent elements.

[0099] As described above, the SiC semiconductor device 1G also produces the same effects as those described for the SiC semiconductor device 1A. The SiC semiconductor device 1G is manufactured by preparing an n-type SiC wafer 10 having an impurity concentration adjusted by a predetermined pentavalent element in the manufacturing method of the SiC semiconductor device 1C according to the third embodiment. Therefore, the manufacturing method of the SiC semiconductor device 1G also produces the same effects as those described for the manufacturing method of the SiC semiconductor device 1A according to the first embodiment.

[0100] Figure 16 corresponds to Figure 6 and is a cross-sectional view showing the SiC semiconductor device 1H according to the eighth embodiment. Hereinafter, structures corresponding to those described in the first to seventh embodiments are denoted by the same reference numerals, and their descriptions are omitted.

[0101] Referring to Figure 16, the SiC semiconductor device 1H has a structure in which the p-type base region 16 according to the fourth embodiment is changed to an n-type base region 6 according to the first embodiment. In this case, the p-type buffer region 17 may have a cancellation region at the boundary with the n-type base region 6 in which the n-type impurity concentration due to pentavalent elements in the base region 6 is canceled out by the p-type impurity concentration due to trivalent elements.

[0102] As described above, the SiC semiconductor device 1H also produces the same effects as those described for the SiC semiconductor device 1A. The SiC semiconductor device 1H is manufactured by preparing an n-type SiC wafer 10 having an impurity concentration adjusted by a predetermined pentavalent element in the manufacturing method of the SiC semiconductor device 1D according to the fourth embodiment. Therefore, the manufacturing method of the SiC semiconductor device 1H also produces the same effects as those described for the manufacturing method of the SiC semiconductor device 1A according to the first embodiment.

[0103] Figure 17 is a plan view showing the SiC semiconductor device 1I according to the ninth embodiment. Figure 18 is a cross-sectional view taken along the line XVIII-XVIII shown in Figure 17. Hereinafter, structures corresponding to those described in the first to eighth embodiments are denoted by the same reference numerals, and their descriptions are omitted.

[0104] Referring to Figures 17 and 18, the SiC semiconductor device 1I includes a SiC chip 2, an n-type base region 6, an n-type buffer region 7, an n-type drift region 8, and a functional device 9, similar to the SiC semiconductor device 1A according to the first embodiment. The SiC chip 2 has an off-angle θ and an off-direction D, similar to the first embodiment. In this embodiment, the SiC semiconductor device 1I includes a plurality of p-type column regions 19 formed within the drift region 8. The column regions 19 may be referred to as "impurity regions."

[0105] Multiple column regions 19 are formed using a portion of the SiC chip 2. In a plan view, the multiple column regions 19 are formed within the drift region 8, spaced inward from the periphery of the SiC chip 2. In this configuration, in a plan view, the multiple column regions 19 are each formed in a strip shape extending in the first direction X (a-axis direction) and are arranged with spacing in the second direction Y (m-axis direction). In other words, in a plan view, the multiple column regions 19 are formed in a stripe shape extending in the off-direction D (=first direction X).

[0106] Of course, the multiple column regions 19 may be arranged at intervals in the first direction X (a-axis direction) in a plan view, and each may be formed as a strip extending in the second direction Y (m-axis direction). In other words, the multiple column regions 19 may be formed as stripes extending in a direction perpendicular to the off-direction D (= second direction Y) in a plan view. Alternatively, the multiple column regions 19 may be formed as a grid intersecting the first direction X and the second direction Y in a plan view. Furthermore, the multiple column regions 19 may be arranged as dots at intervals in the first direction X and the second direction Y.

[0107] Multiple column regions 19 may be arranged with a spacing (column pitch) of 0.5 μm to 10 μm. Preferably, the multiple column regions 19 are arranged at approximately equal intervals. Each of the multiple column regions 19 may have a width (column width) of 0.5 μm to 10 μm. Preferably, each of the multiple column regions 19 has approximately equal widths.

[0108] Each of the multiple column regions 19 forms a pn junction with the drift region 8. Specifically, the multiple column regions 19 are formed in a column shape extending in the thickness direction of the drift region 8 in a cross-sectional view, and each forms a pn junction with the drift region 8 along the thickness direction. It is preferable that each of the multiple column regions 19 extends from the first main surface 3 across the intermediate portion MID. Each of the multiple column regions 19 is formed at a distance from the bottom of the drift region 8 (i.e., the buffer region 7) toward the first main surface 3. The multiple column regions 19 face the buffer region 7, with the relatively low-density bottom region of the drift region 8 in between.

[0109] Each of the column regions 19 forms a superjunction structure with the drift region 8. In other words, each of the column regions 19 forms a pn junction that extends in the thickness direction of the drift region 8 so as to expand the depletion layer in the width direction of the drift region 8. Preferably, the column regions 19 are arranged at intervals such that the depletion layer extending from one column region 19 is connected to the depletion layer extending from the other adjacent column region 19.

[0110] Multiple column regions 19 are formed in such a manner that the n-type impurity concentration in the drift region 8 is replaced with a p-type impurity concentration by a trivalent element. In other words, each of the multiple column regions 19 has, in addition to the pentavalent elements that constitute the drift region 8 (base concentration CA and added concentration CB), a trivalent element introduced at a p-type impurity concentration that exceeds the n-type impurity concentration in the drift region 8.

[0111] The multiple column regions 19 contain trivalent elements other than boron and have impurity concentrations adjusted by these trivalent elements. Preferably, the multiple column regions 19 contain at least one of aluminum, gallium, and indium. The multiple column regions 19 have impurity concentrations adjusted to increase (specifically, gradually increase) toward the first main surface 3.

[0112] It is preferable that the multiple column regions 19 have a concentration gradient of p-type impurities proportional to the concentration gradient of the drift region 8. It is also preferable that the multiple column regions 19 have impurity concentrations adjusted to maintain a charge balance with the drift region 8. "Maintaining a charge balance" means that the depletion layers extending from the multiple column regions 19 are connected in the regions between adjacent pairs of column regions 19.

[0113] For example, when the column width is x (0 < x) times the column pitch, the plurality of column regions 19 maintain charge balance when the impurity concentration of the plurality of columns is 1 / x times the impurity concentration of the drift region 8. When the column width is equal to the column pitch, the plurality of column regions 19 preferably have a concentration gradient of p-type impurities that rises from the second concentration C2 to the third concentration C3 corresponding to the drift region 8 having a concentration gradient that rises from the second concentration C2 to the third concentration C3.

[0114] In this form, the functional device 9 is formed using the drift region 8 and the plurality of column regions 19. That is, the SiC semiconductor device 1I includes a super junction type functional device 9.

[0115] As described above, the SiC semiconductor device 1I includes a SiC chip 2, an n-type drift region 8, and a p-type column region 19 (impurity region). The SiC chip 2 has a first main surface 3. The drift region 8 is formed in the surface layer portion of the first main surface 3 and has an impurity concentration adjusted by at least two kinds of pentavalent elements. The column region 19 is formed in the drift region 8 so as to form a pn junction with the drift region 8. According to this structure, the same effects as those described for the SiC semiconductor device 1A are achieved. Also, according to this structure, a pn junction can be appropriately formed between the drift region 8 and the column region 19. Therefore, a SiC semiconductor device 1I capable of improving electrical characteristics (for example, breakdown voltage due to the column region 19) can be provided.

[0116] From another perspective, the SiC semiconductor device 1I includes a SiC chip 2, an n-type drift region 8, and a p-type column region 19 (impurity region). The SiC chip 2 has a first main surface 3. The drift region 8 is formed in the surface layer portion of the first main surface 3. The column region 19 is formed in the drift region 8 so as to form a pn junction with the drift region 8 and has an impurity concentration adjusted by a trivalent element other than boron.

[0117] Boron has properties that make it difficult to introduce into deep regions of the SiC chip 2. Therefore, by adjusting the impurity concentration of the column region 19 with trivalent elements other than boron, it is possible to form a column region 19 with an impurity concentration that has reduced variation from the target concentration. This allows for the proper formation of a pn junction between the drift region 8 and the column region 19. Thus, it is possible to provide a SiC semiconductor device 1I with improved electrical properties (for example, breakdown voltage due to the column region 19).

[0118] The drift region 8 preferably has a concentration distribution that increases toward the first main surface 3. The column region 19 preferably has a concentration distribution that increases toward the first main surface 3. The drift region 8 preferably contains at least one trivalent element from nitrogen, arsenic, and antimony. The column region 19 preferably contains at least one trivalent element from aluminum, gallium, and indium.

[0119] Preferably, the column region 19 extends in the thickness direction within the drift region 8 so as to form a superjunction structure with the drift region 8 and the pn joint. Preferably, the column region 19 crosses the intermediate portion MID. Preferably, the column region 19 is formed with a gap from the bottom of the drift region 8 toward the first main surface 3.

[0120] Figures 19A and 19B are cross-sectional views showing the manufacturing method of the SiC semiconductor device 1I shown in Figure 17. Referring to Figure 19A, a drift region 8 is formed in the second SiC epitaxial layer 14 through the same process as in Figures 4A to 4D.

[0121] Referring to Figure 19B, a resist mask RM having a predetermined pattern is formed on the second SiC epitaxial layer 14. The resist mask RM exposes the areas in the drift region 8 where multiple column regions 19 should be formed, and covers the other areas. Next, trivalent elements (p-type impurities) are implanted into the drift region 8 by ion implantation through the resist mask RM, and multiple p-type column regions 19 having a target concentration are formed.

[0122] In this process, trivalent elements are implanted into the drift region 8 such that the impurity concentration increases (specifically, gradually increases) in the direction of crystal growth. The ion implantation method used in this process is the channeling implantation method. In the channeling implantation method, trivalent elements are implanted into the region of the second SiC epitaxial layer 14 on the main surface (crystal growth surface) side and the region on the SiC wafer 10 side of the second SiC epitaxial layer 14.

[0123] The injection depth of the trivalent element into the drift region 8 is precisely adjusted by adjusting the injection energy of the trivalent element, the injection temperature of the second impurity, the injection angle of the second impurity, and so on. The injection energy of the trivalent element may be adjusted in the range of 10 keV to 1000 keV (preferably 100 keV or more). The injection temperature of the trivalent element may be adjusted in the range of 300°C to 1000°C.

[0124] The injection angle of the trivalent element is set within a range of ±5° with the crystal axis (c-axis) of the SiC single crystal as the reference (=0°). Preferably, the injection angle of the trivalent element is set within a range of ±2°. In this configuration, the second SiC epitaxial layer 14 (SiC wafer 10) has an off-angle θ tilted in a predetermined off-direction D. Therefore, in the channeling implantation method, the injection angle of the trivalent element to the second SiC epitaxial layer 14, or the tilt angle of the second SiC epitaxial layer 14 with respect to the injection direction of the trivalent element, is adjusted according to the off-direction D and the off-angle θ.

[0125] In this configuration, multiple column regions 19 extending in the off-direction D (=first direction X) are formed. With this structure, the injection angle of the trivalent element becomes the inclination angle with respect to the off-direction D, so that the vector component of the trivalent element injected into the second SiC epitaxial layer 14 is aligned with the off-direction D. Therefore, the trivalent element is injected along a line extending in the off-direction D in a plan view, and is injected almost perpendicular to the c-plane of the SiC single crystal in a cross-sectional view in a direction perpendicular to the off-direction D.

[0126] The trivalent element used in the channeling implantation method may be at least one of boron, aluminum, gallium, and indium. However, boron is difficult to implant into deep regions of the second SiC epitaxial layer 14 by the channeling implantation method. Therefore, it is preferable that the trivalent element used in the channeling implantation method be a trivalent element other than boron.

[0127] After the injection of trivalent elements, the trivalent elements are electrically activated by an annealing method, and at the same time, lattice defects and other defects that have occurred in the second SiC epitaxial layer 14 are repaired. The annealing temperature of the second SiC epitaxial layer 14 may be between 500°C and 2000°C. The activation of the trivalent elements may be performed simultaneously with the activation of the pentavalent elements in the drift region 8. This forms the trivalent elements. Subsequently, a functional device 9 is formed on the main surface (crystal growth surface) side of the second SiC epitaxial layer 14 using the drift region 8 and multiple column regions 19. A SiC semiconductor device 1I is manufactured through the process including the above.

[0128] The manufacturing method for the SiC semiconductor device 1I includes a first step of preparing a second SiC epitaxial layer 14, a second step of forming an n-type drift region 8, and a third step of forming a p-type column region 19. In the first step, a second SiC epitaxial layer 14 with a low concentration of n-type impurities is prepared. Specifically, the impurity concentration of the second SiC epitaxial layer 14 is less than the target concentration of the drift region 8. In the second step, pentavalent elements (n-type impurities) are implanted into the second SiC epitaxial layer 14 by ion implantation, forming an n-type drift region 8 with a target concentration. In the third step, trivalent elements (p-type impurities) are implanted into the second SiC epitaxial layer 14 by ion implantation, forming a p-type column region 19 that forms a pn junction with the drift region 8.

[0129] This manufacturing method produces the same effects as those described for the manufacturing method of SiC semiconductor device 1A. Furthermore, the manufacturing method of SiC semiconductor device 1I allows for the proper formation of a pn junction between the drift region 8 and the column region 19. Therefore, it is possible to manufacture and provide a SiC semiconductor device 1I with improved electrical characteristics (for example, withstand voltage due to the column region 19).

[0130] From another perspective, the manufacturing method of the SiC semiconductor device 1I includes a first step of preparing a second SiC epitaxial layer 14 on which an n-type drift region 8 is formed, and a second step of forming a p-type column region 19. In the second step, trivalent elements other than boron (p-type impurities) are implanted into the second SiC epitaxial layer 14 by ion implantation, and a p-type column region 19 that forms a pn junction with the drift region 8 is formed.

[0131] Boron has properties that make it difficult to introduce into deep regions of the second SiC epitaxial layer 14. Therefore, by adjusting the impurity concentration of the column region 19 with trivalent elements other than boron, the variation in the impurity concentration of the column region 19 relative to the target concentration can be suppressed. This allows for the proper formation of a pn junction between the drift region 8 and the column region 19. Thus, a SiC semiconductor device 1I with improved electrical properties (for example, breakdown voltage due to the column region 19) can be manufactured and provided.

[0132] In the method for manufacturing the SiC semiconductor device 1I, a second SiC epitaxial layer 14 having an impurity concentration adjusted by a first impurity may be prepared. In this case, the drift region 8 may be formed by implanting a second impurity different from the first impurity into the second SiC epitaxial layer 14. The first impurity is preferably a pentavalent element other than phosphorus. The first impurity is preferably nitrogen. The second impurity is preferably a pentavalent element other than phosphorus. The second impurity is preferably at least one of arsenic and antimony.

[0133] In the process of forming the column region 19, a channeling implantation method may be performed in which a trivalent element is implanted along the crystal axis of the second SiC epitaxial layer 14. The trivalent element used in the channeling implantation method is preferably a trivalent element other than boron. The trivalent element used in the channeling implantation method may be at least one of aluminum, gallium, and indium.

[0134] It is preferable that the trivalent elements are injected into the second SiC epitaxial layer 14 at an injection angle of ±5° or less with respect to the crystal axis of the SiC single crystal. It is preferable that the crystal axis of the SiC single crystal is the c-axis. It is preferable that the second SiC epitaxial layer 14 has an off-angle θ of 10° or less between itself and the c-plane of the SiC single crystal. It is preferable that the off-angle θ has an off-direction D along the a-axis direction of the SiC single crystal.

[0135] In the channeling implantation method, it is preferable to form a column region 19 extending along the off-direction D. This process ensures that the vector component of the implanted trivalent element is aligned with the off-direction D. As a result, the trivalent element is implanted almost perpendicular to the c-plane of the SiC single crystal along the line extending in the off-direction D, thereby allowing for the proper formation of the column region 19.

[0136] Figure 20 corresponds to Figure 18 and is a plan view showing the SiC semiconductor device 1J according to the 10th embodiment. Hereinafter, structures corresponding to those described in the 1st to 9th embodiments are denoted by the same reference numerals, and their descriptions are omitted.

[0137] Referring to Figure 20, the SiC semiconductor device 1J, similar to the SiC semiconductor device 1B according to the second embodiment, includes a SiC chip 2, an n-type base region 6, an n-type buffer region 7, an n-type drift region 8, and a functional device 9. The drift region 8 includes a first region 8a and a second region 8b. In this embodiment, the SiC semiconductor device 1J includes a plurality of p-type column regions 19 formed within the drift region 8.

[0138] The multiple column regions 19 are formed in a similar manner to the column region 19 according to the ninth embodiment in a plan view. In this embodiment, the multiple column regions 19 are each formed within the second region 8b so as to form a pn joint with the second region 8b of the drift region 8. Specifically, the multiple column regions 19 are formed in a column shape extending in the thickness direction of the second region 8b in a cross-sectional view, and each forms a pn joint with the second region 8b along the thickness direction.

[0139] It is preferable that the multiple column regions 19 each extend from the first main surface 3 across the intermediate region MID. It is preferable that the multiple column regions 19 are formed with a gap between them from the first region 8a toward the first main surface 3, and that they each face the buffer region 7 with a portion of the first region 8a and the second region 8b in between. It is preferable that the lower ends of the multiple column regions 19 are located in the region between the intermediate region MID and the first region 8a.

[0140] Each of the column regions 19 forms a superjunction structure with the second region 8b. In other words, each of the column regions 19 forms a pn junction that extends in the thickness direction of the second region 8b so as to extend the depletion layer in the width direction of the second region 8b. Preferably, the column regions 19 are arranged at intervals such that the depletion layer extending from one column region 19 is connected to the depletion layer extending from the other adjacent column region 19.

[0141] In this configuration, the multiple column regions 19 are formed in such a way that the n-type impurity concentration in the second region 8b is replaced (canceled) by trivalent elements to the p-type impurity concentration. That is, each of the multiple column regions 19 has, in addition to the pentavalent elements that constitute the second region 8b (base concentration CA and added concentration CB), trivalent elements introduced at a p-type impurity concentration exceeding the n-type impurity concentration in the second region 8b. It is preferable that the multiple column regions 19 have a concentration gradient of p-type impurities that is proportional to the concentration gradient of the second region 8b. It is also preferable that the multiple column regions 19 have impurity concentrations adjusted to maintain a charge balance with the second region 8b.

[0142] In this embodiment, the functional device 9 is formed using a drift region 8 and multiple column regions 19. In other words, the SiC semiconductor device 1J includes a superjunction-type functional device 9.

[0143] As described above, the SiC semiconductor device 1J also provides the same effects as those described for the SiC semiconductor device 1I according to the 9th embodiment.

[0144] Figures 21A and 21B are cross-sectional views showing the manufacturing method of the SiC semiconductor device 1J shown in Figure 20. Referring to Figure 21A, a drift region 8 is formed in the second SiC epitaxial layer 14 through the same process as in Figures 4A to 4C and Figures 8A to 8B. The drift region 8 includes a first region 8a and a second region 8b.

[0145] Referring to Figure 21B, a resist mask RM having a predetermined pattern is formed on the second SiC epitaxial layer 14. The resist mask RM exposes the areas in the drift region 8 where multiple column regions 19 should be formed, and covers the other areas. Next, trivalent elements (p-type impurities) are implanted into the drift region 8 by an ion implantation method (channeling implantation method in this embodiment) via the resist mask RM, and multiple p-type column regions 19 having a target concentration are formed.

[0146] In this process, trivalent elements other than boron are injected into the second region 8b up to a certain point in the thickness direction. Specifically, the trivalent elements are injected into the second region 8b with a gap between them and the first main surface 3 from the first region 8a. In this configuration, the trivalent elements other than boron are at least one of aluminum, gallium, and indium.

[0147] As described above, the manufacturing method of the SiC semiconductor device 1J also produces the same effects as those described for the manufacturing method of the SiC semiconductor device 1I according to the 9th embodiment.

[0148] Figure 22 corresponds to Figure 18 and is a cross-sectional view showing the SiC semiconductor device 1K according to the 11th embodiment. Hereinafter, structures corresponding to those described in the 1st to 10th embodiments are denoted by the same reference numerals, and their descriptions are omitted.

[0149] Referring to Figure 22, the SiC semiconductor device 1K, like the SiC semiconductor device 1C according to the third embodiment, includes a SiC chip 2, a p-type base region 16, a p-type buffer region 17, a p-type drift region 18, and a functional device 9. In this embodiment, the SiC semiconductor device 1K includes a plurality of n-type column regions 20 formed within the drift region 18. The column regions 20 may be referred to as "impurity regions."

[0150] Multiple column regions 20 are formed using a portion of the SiC chip 2. Multiple column regions 20 are formed in the same manner as the column region 19 according to the ninth embodiment, except that they contain pentavalent elements instead of trivalent elements. In this embodiment, multiple column regions 20 are formed in such a way that the p-type impurity concentration of the drift region 18 is replaced with an n-type impurity concentration by pentavalent elements. In other words, each of the multiple column regions 20 has, in addition to the trivalent elements that constitute the drift region 18 (base concentration CA and added concentration CB), pentavalent elements introduced at an n-type impurity concentration that exceeds the p-type impurity concentration of the drift region 18.

[0151] The multiple column regions 20 contain pentavalent elements other than phosphorus and nitrogen, and have impurity concentrations adjusted by these pentavalent elements. Preferably, the multiple column regions 20 contain at least one of arsenic and antimony. The multiple column regions 20 have impurity concentrations adjusted to increase (specifically, gradually increase) toward the first main surface 3. Preferably, the multiple column regions 20 have a concentration gradient of n-type impurities proportional to the concentration gradient of the drift region 18. Preferably, the multiple column regions 20 have impurity concentrations adjusted to maintain a charge balance with the drift region 18.

[0152] In this embodiment, the functional device 9 is formed using a drift region 18 and multiple column regions 20. In other words, the SiC semiconductor device 1K includes a superjunction-type functional device 9.

[0153] As described above, the SiC semiconductor device 1K also produces the same effects as those described for the SiC semiconductor device 1I according to the ninth embodiment. The SiC semiconductor device 1K is manufactured by replacing the pentavalent elements with predetermined trivalent elements in the manufacturing method of the SiC semiconductor device 1I according to the ninth embodiment (Figures 4A to 4D and 19A to 19B). Therefore, the manufacturing method of the SiC semiconductor device 1K also produces the same effects as those described for the manufacturing method of the SiC semiconductor device 1I according to the ninth embodiment.

[0154] Figure 23 corresponds to Figure 18 and is a plan view showing the SiC semiconductor device 1L according to the 12th embodiment. Hereinafter, structures corresponding to those described in the 1st to 11th embodiments are denoted by the same reference numerals, and their descriptions are omitted.

[0155] Referring to Figure 20, the SiC semiconductor device 1L, similar to the SiC semiconductor device 1D according to the fourth embodiment, includes a SiC chip 2, a p-type base region 16, a p-type buffer region 17, a p-type drift region 18, and a functional device 9. The drift region 18 includes a first region 18a and a second region 18b. In this embodiment, the SiC semiconductor device 1L includes a plurality of n-type column regions 20 formed within the drift region 18.

[0156] The multiple column regions 20 are formed in the same manner as the column region 19 in the 10th embodiment (9th embodiment), except that they contain pentavalent elements instead of trivalent elements. Furthermore, the multiple column regions 20 are formed in the same manner as in the 11th embodiment. In this embodiment, the multiple column regions 20 are each formed within the second region 18b so as to form a pn junction with the second region 18b. Specifically, the multiple column regions 20 are formed in a column shape extending in the thickness direction of the second region 18b in a cross-sectional view, and each forms a pn junction along the thickness direction of the second region 18b.

[0157] Preferably, the multiple column regions 20 extend from the first main surface 3 across the intermediate region MID. Preferably, the multiple column regions 20 are formed with a gap between them from the first region 18a toward the first main surface 3, and face the buffer region 17 with a portion of the first region 18a and the second region 18b in between. Preferably, the lower ends of the multiple column regions 20 are located in the region between the intermediate region MID and the first region 18a.

[0158] In this configuration, the multiple column regions 20 are formed in such a way that the p-type impurity concentration of the second region 18b is replaced (canceled) by the pentavalent element to the n-type impurity concentration. In other words, each of the multiple column regions 20 has, in addition to the trivalent elements that constitute the second region 18b (base concentration CA and added concentration CB), a pentavalent element introduced at an n-type impurity concentration that exceeds the p-type impurity concentration of the second region 18b.

[0159] Each of the column regions 20 forms a superjunction structure with the second region 18b. That is, each of the column regions 20 forms a pn junction that extends in the thickness direction of the second region 18b so as to extend the depletion layer in the width direction of the second region 18b. Preferably, the column regions 20 are arranged at intervals such that the depletion layer extending from one column region 20 is connected to the depletion layer extending from the other adjacent column region 20. Preferably, the column regions 20 have a concentration gradient of n-type impurities that is at least proportional to the concentration gradient of the second region 18b. Preferably, the column regions 20 have impurity concentrations adjusted to maintain a charge balance with the second region 18b.

[0160] In this embodiment, the functional device 9 is formed using a drift region 18 and multiple column regions 20. In other words, the SiC semiconductor device 1L includes a superjunction-type functional device 9.

[0161] As described above, the SiC semiconductor device 1L also produces the same effects as those described for the SiC semiconductor device 1J according to the 10th embodiment. The SiC semiconductor device 1L is manufactured by replacing the pentavalent elements with predetermined trivalent elements in the manufacturing method of the SiC semiconductor device 1J according to the 10th embodiment (Figures 4A to 4D and Figures 21A to 21B). Therefore, the manufacturing method of the SiC semiconductor device 1L also produces the same effects as those described for the manufacturing method of the SiC semiconductor device 1J according to the 10th embodiment.

[0162] The following describes examples of functional device 9 forms that can be applied to the first to twelfth embodiments. In the following, specific examples of functional device 9 forms will be described using one of the SiC semiconductor devices 1A to 1L according to the first to twelfth embodiments.

[0163] Figure 24 is a plan view showing a structure in which a functional device 9 according to the first embodiment is applied to a SiC semiconductor device 1A according to the first embodiment. Figure 25 is a cross-sectional view along the line XXV-XXV shown in Figure 24. Figure 26 is a plan view of the SiC chip 2 shown in Figure 25. Hereinafter, structures corresponding to the structure described in the first embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0164] Referring to Figures 24 to 26, the SiC semiconductor device 1A includes a SiC chip 2, an n-type base region 6, an n-type buffer region 7, an n-type drift region 8, and a functional device 9. In this embodiment, the functional device 9 is a SiC-SBD. The base region 6 is formed in this embodiment as the cathode region of the SiC-SBD. The SiC semiconductor device 1A also includes a p-type guard region 21, an insulating film 22, a first main surface electrode 23, and a second main surface electrode 24.

[0165] The guard region 21 is formed on the surface of the drift region 8, spaced inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. In plan view, the guard region 21 extends in a band shape along the periphery of the first main surface 3. In this configuration, the guard region 21 is formed in an annular shape surrounding the inner part of the first main surface 3 in plan view. Thus, the guard region 21 is formed as a guard ring region. The guard region 21 has an inner edge on the inner side of the first main surface 3 and an outer edge on the periphery side of the first main surface 3. The p-type impurities in the guard region 21 may or may not be activated.

[0166] The insulating film 22 covers the first main surface 3. Specifically, the insulating film 22 covers the area between the periphery of the first main surface 3 and the guard region 21 so as to cover the outer edge of the guard region 21. The insulating film 22 has an opening 25 that exposes the inner portion of the first main surface 3 and the inner edge of the guard region 21.

[0167] The first main surface electrode 23 covers the first main surface 3. Specifically, the first main surface electrode 23 enters the opening 25 from above the insulating film 22 and covers the first main surface 3 within the opening 25. The first main surface electrode 23 is electrically connected to the drift region 8 and the guard region 21 within the opening 25. In this embodiment, the first main surface electrode 23 forms a Schottky junction with the drift region 8. The second main surface electrode 24 covers the second main surface 4. Specifically, the second main surface electrode 24 covers almost the entire area of ​​the second main surface 4. The second main surface electrode 24 forms ohmic contact with the base region 6.

[0168] As described above, this structure makes it possible to provide a SiC semiconductor device 1A having a SiC-SBD whose electrical characteristics are improved by the drift region 8. Of course, the structure of the functional device 9 (SiC-SBD) according to the first embodiment can also be applied to any one of the first to twelfth embodiments, excluding the first embodiment.

[0169] Figure 27 is a plan view showing a structure in which a functional device 9 according to the second embodiment is applied to a SiC semiconductor device 1J according to the tenth embodiment. Figure 28 is a cross-sectional view along the line XXVIII-XXVIII shown in Figure 27. Figure 29 is a plan view of the SiC chip 2 shown in Figure 28. Hereinafter, structures corresponding to the structure described in the tenth embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0170] Referring to Figures 27 to 29, the SiC semiconductor device 1J includes a SiC chip 2, an n-type base region 6, an n-type buffer region 7, an n-type drift region 8, a p-type column region 19, and a functional device 9. The drift region 8 includes a first region 8a and a second region 8b. The functional device 9 is a superjunction type SiC-SBD in this embodiment. The base region 6 is formed as the cathode region of the SiC-SBD in this embodiment.

[0171] The SiC semiconductor device 1J includes a p-type guard region 21, an insulating film 22, a first main surface electrode 23, and a second main surface electrode 24, similar to the functional device 9 according to the first embodiment (see Figures 24 to 26). The differences from the functional device 9 according to the first embodiment (see Figures 24 to 26) will be explained below.

[0172] In this embodiment, the guard region 21 is formed shallower than the multiple column regions 19 and is formed at a depth position on the first main surface 3 side relative to the bottom of the multiple columns. Preferably, the guard region 21 is formed in the region on the first main surface 3 side of the intermediate portion of the multiple column regions 19. The guard region 21 may be connected to both longitudinal ends of the multiple column regions 19. In this embodiment, the insulating film 22 has an opening 25 in the inner part of the first main surface 3 that exposes the inner edges of the multiple column regions 19 and the guard region 21. The first main surface electrode 23 is electrically connected to the drift region 8, the multiple column regions 19 and the guard region 21 within the opening 25.

[0173] As described above, this structure provides a SiC semiconductor device 1J having a superjunction-type SiC-SBD whose electrical characteristics are improved by the drift region 8 and the column region 19. Of course, the structure of the functional device 9 (superjunction-type SiC-SBD) according to the second embodiment can also be applied to any one of the 9th to 12th embodiments, excluding the 10th embodiment.

[0174] Figure 30 is a plan view showing a structure in which a functional device 9 according to a third embodiment is applied to a SiC semiconductor device 1A according to the first embodiment. Figure 31 is a cross-sectional view along the line XXXI-XXXI shown in Figure 30. Figure 32 is an enlarged view of region XXXII shown in Figure 30. Figure 33 is a cross-sectional view along the line XXXIII-XXXIII shown in Figure 32. Figure 34 is an enlarged view of region XXXIV shown in Figure 31. Hereinafter, structures corresponding to the structure described in the first embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0175] Referring to Figures 30 to 34, the SiC semiconductor device 1A includes a SiC chip 2, an n-type base region 6, an n-type buffer region 7, an n-type drift region 8, and a functional device 9. In this embodiment, the functional device 9 is a trench-gate type SiC-MISFET. In this embodiment, the base region 6 is formed as the drain region of the SiC-MISFET.

[0176] The SiC semiconductor device 1A has an active surface 31, an outside surface 32, and first to fourth connecting surfaces 33A to 33D formed on the first main surface 3. The active surface 31, the outside surface 32, and the first to fourth connecting surfaces 33A to 33D demarcate an active mesa 34 on the first main surface 3. The active surface 31 may be referred to as the "first surface," the outside surface 32 as the "second surface" or "peripheral surface," and the active mesa 34 may be referred to as the "mesa."

[0177] The active surface 31 is formed with a gap inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 31 has a flat surface extending in the first direction X and the second direction Y. The active surface 31 has the aforementioned off-angle θ and off-direction D. In this embodiment, the active surface 31 is formed in a quadrilateral shape with four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0178] The outer surface 32 is located outside the active surface 31 and is recessed from the active surface 31 in the thickness direction of the SiC chip 2 (towards the second main surface 4). Specifically, the outer surface 32 is recessed to a depth less than the thickness of the drift region 8 so as to expose the drift region 8. In a plan view, the outer surface 32 is formed in a band shape extending along the active surface 31. In this embodiment, the outer surface 32 is formed in an annular shape (specifically a square annular shape) surrounding the active surface 31 in a plan view. The outer surface 32 has a flat surface extending in the first direction X and the second direction Y and is formed substantially parallel to the active surface 31. The outer surface 32 has an off-angle θ and off-direction D, similar to the active surface 31. The outer surface 32 is in communication with the first to fourth sides 5A to 5D.

[0179] The first to fourth connecting surfaces 33A to 33D extend in the normal direction Z and connect the active surface 31 and the outer surface 32. The first connecting surface 33A is located on the side of the first surface 5A, the second connecting surface 33B is located on the side of the second surface 5B, the third connecting surface 33C is located on the side of the third surface 5C, and the fourth connecting surface 33D is located on the side of the fourth surface 5D. The first connecting surface 33A and the second connecting surface 33B extend in the first direction X and face the second direction Y. The third connecting surface 33C and the fourth connecting surface 33D extend in the second direction Y and face the first direction X. The first to fourth connecting surfaces 33A to 33D expose the drift region 8.

[0180] The first to fourth connecting surfaces 33A to 33D may extend almost vertically between the active surface 31 and the outer surface 32 so as to define the rectangular prism-shaped active platform 34. The first to fourth connecting surfaces 33A to 33D may also be inclined diagonally downward from the active surface 31 toward the outer surface 32 so as to define the pyramidal-shaped active platform 34. In this way, the SiC semiconductor device 1A includes an active platform 34 formed in the drift region 8 on the first main surface 3. The active platform 34 is formed only in the drift region 8 and not in the base region 6 or the buffer region 7.

[0181] The SiC semiconductor device 1A includes a SiC-MISFET formed on the active surface 31. The structure of the SiC-MISFET will be described in detail below. The SiC semiconductor device 1A includes a p-type body region 35 formed on the surface layer of the active surface 31. The body region 35 forms part of the body diode of the SiC-MISFET. The body region 35 may be formed over the entire surface layer of the active surface 31.

[0182] The SiC semiconductor device 1A includes an n-type source region 36 formed on the surface of the body region 35. The source region 36 forms the source of the SiC-MISFET. The source region 36 may be formed over the entire surface of the body region 35. The source region 36 has an n-type impurity concentration that exceeds the n-type impurity concentration of the drift region 8. The source region 36 forms the channel CH of the SiC-MISFET with the drift region 8 within the body region 35.

[0183] The SiC semiconductor device 1A includes a plurality of trench gate structures 37 formed on the active surface 31. The plurality of trench gate structures 37 form the gate of the SiC-MISFET and control the inversion (on) and non-inversion (off) of the channel CH. The plurality of trench gate structures 37 are formed to traverse the body region 35 and the source region 36 and reach the drift region 8.

[0184] Multiple trench gate structures 37 are formed at intervals in the first direction X in a plan view, and each is formed in a strip shape extending in the second direction Y. Each trench gate structure 37 is formed at an interval from the bottom of the drift region 8 toward the active surface 31, and faces the buffer region 7 with a portion of the drift region 8 in between.

[0185] Each trench gate structure 37 includes a gate trench 38, a gate insulating film 39, and a gate electrode 40. The gate trench 38 is formed on the active surface 31. The gate insulating film 39 is formed as a film on the inner wall of the gate trench 38. The gate electrode 40 is embedded in the gate trench 38, sandwiching the gate insulating film 39. The gate electrode 40 faces the drift region 8, the body region 35, and the source region 36, sandwiching the gate insulating film 39. A gate potential is applied to the gate electrode 40.

[0186] The SiC semiconductor device 1A includes a plurality of trench source structures 41 formed on the active surface 31. Each of the plurality of trench source structures 41 is formed in the region between two adjacent trench gate structures 37 on the active surface 31. Each of the plurality of trench source structures 41 is formed in a strip shape extending in the second direction Y in a plan view. Each of the plurality of trench source structures 41 is formed so as to cross the body region 35 and the source region 36 and reach the drift region 8. The plurality of trench source structures 41 are formed with a gap from the bottom of the drift region 8 toward the active surface 31 and face the buffer region 7 with a portion of the drift region 8 in between.

[0187] Each trench source structure 41 has a depth exceeding the depth of the trench gate structure 37. The bottom wall of each trench source structure 41 is located on the bottom side of the drift region 8 relative to the bottom wall of each trench gate structure 37. In this embodiment, the bottom wall of each trench source structure 41 is located substantially coplanar with the outer surface 32. Of course, each trench source structure 41 may have a depth substantially equal to the depth of the trench gate structure 37.

[0188] Each trench source structure 41 includes a source trench 42, a source insulating film 43, and a source electrode 44. The source trench 42 is formed on the active surface 31. The source insulating film 43 is formed as a film on the inner wall of the source trench 42. The source electrode 44 is embedded in the source trench 42, sandwiching the source insulating film 43. A source potential is applied to the source electrode 44.

[0189] The SiC semiconductor device 1A includes a plurality of p-type contact regions 45 formed in the drift region 8 along the plurality of trench source structures 41. The p-type impurity concentration in the plurality of contact regions 45 exceeds the p-type impurity concentration in the body region 35. The plurality of contact regions 45 each cover the corresponding trench source structures 41 in a one-to-many correspondence, spaced apart in the second direction Y. The plurality of contact regions 45 may each cover the corresponding trench source structures 41 in a one-to-one correspondence. Each contact region 45 covers the side and bottom walls of each trench source structure 41 and is electrically connected to the body region 35.

[0190] The SiC semiconductor device 1A includes a plurality of p-type well regions 46 formed in the surface layer of the active surface 31, along the regions of the plurality of trench source structures 41. Preferably, the p-type impurity concentration in the plurality of well regions 46 is greater than the p-type impurity concentration in the body region 35 and less than the p-type impurity concentration in the contact region 45. The plurality of well regions 46 each cover the corresponding trench source structures 41, flanking the plurality of contact regions 45. Each well region 46 may be formed in a strip shape extending along the corresponding trench source structure 41. Each well region 46 covers the sidewalls and bottom walls of each trench source structure 41 and is electrically connected to the body region 35.

[0191] Referring to Figure 34, the SiC semiconductor device 1A includes a p-type outer contact region 48 formed on the surface layer of the drift region 8 on the outer surface 32. Preferably, the outer contact region 48 has a p-type impurity concentration that exceeds the p-type impurity concentration of the body region 35. In a plan view, the outer contact region 48 is formed at a distance from the periphery of the active surface 31 and the periphery of the outer surface 32. In a plan view, the outer contact region 48 is formed in a band shape extending along the active surface 31. In this embodiment, the outer contact region 48 is formed in an annular shape (specifically, a square annular shape) surrounding the active surface 31 in a plan view.

[0192] The outer contact region 48 is formed with a gap between the bottom of the drift region 8 and the outer surface 32. The entire outer contact region 48 is located on the bottom side of the drift region 8 relative to the bottom walls of the multiple trench gate structures 37. The outer contact region 48 forms a pn junction with the drift region 8. This forms a pn junction diode in which the outer contact region 48 is the anode and the drift region 8 is the cathode.

[0193] The SiC semiconductor device 1A includes a p-type outer well region 49 formed on the surface layer of the outer surface 32. The outer well region 49 has a p-type impurity concentration lower than that of the outer contact region 48. Preferably, the p-type impurity concentration of the outer well region 49 is approximately equal to that of the well region 46. In a plan view, the outer well region 49 is formed in the region between the periphery of the active surface 31 and the outer contact region 48.

[0194] The outer well region 49 is formed in a band shape extending along the active surface 31 in a plan view. In this configuration, the outer well region 49 is formed in an annular shape (specifically, a square annular shape) surrounding the active surface 31 in a plan view. The outer well region 49 is electrically connected to the outer contact region 48. In this configuration, the outer well region 49 extends from the outer surface 32 toward the first to fourth connection surfaces 33A to 33D and covers the first to fourth connection surfaces 33A to 33D within the SiC chip 2. The outer well region 49 is electrically connected to the body region 35 at the surface of the active surface 31.

[0195] The outer well region 49 is formed deeper than the outer contact region 48. The outer well region 49 is formed with a gap between the bottom of the drift region 8 and the outer surface 32. The outer well region 49 is located on the bottom side of the drift region 8 relative to the bottom walls of the multiple trench gate structures 37. The outer well region 49 forms a pn joint with the drift region 8.

[0196] The SiC semiconductor device 1A includes at least one (preferably two to twenty) p-type field regions 50 formed in the region between the outer contact region 48 and the periphery of the outer surface 32 on the surface layer of the outer surface 32. The multiple field regions 50 relax the electric field within the SiC chip 2 on the outer surface 32. The number, width, depth, and p-type impurity concentration of the field regions 50 are arbitrary and can take various values ​​depending on the electric field to be relaxed. In this embodiment, the SiC semiconductor device 1A includes five field regions 50.

[0197] Multiple field regions 50 are formed at intervals from the outer contact region 48 toward the periphery of the outer surface 32. In a plan view, the multiple field regions 50 are formed in a band shape extending along the active surface 31. In this configuration, in a plan view, the multiple field regions 50 are formed in an annular shape (specifically, a square annular shape) surrounding the active surface 31. Thus, each of the multiple field regions 50 is formed as an FLR (Field Limiting Ring) region.

[0198] Multiple field regions 50 are formed at intervals from the bottom of the drift region 8 to the outer surface 32. The multiple field regions 50 are located on the bottom side of the drift region 8 relative to the bottom walls of the multiple trench gate structures 37. The multiple field regions 50 are formed deeper than the outer contact region 48. The innermost field region 50 may be connected to the outer contact region 48. The field regions 50 other than the innermost field region 50 may be formed in an electrically floating state.

[0199] The SiC semiconductor device 1A includes a main surface insulating film 51 that covers the first main surface 3 (active surface 31, outer surface 32, and first to fourth connecting surfaces 33A to 33D). The main surface insulating film 51 is continuous with the gate insulating film 39 and the source insulating film 43, exposing the gate electrode 40 and the source electrode 44.

[0200] The SiC semiconductor device 1A includes a sidewall structure 52 formed above the outer surface 32 so as to cover at least one of the first to fourth connection surfaces 33A to 33D. Specifically, the sidewall structure 52 is formed on the main surface insulating film 51. The sidewall structure 52 may contain an inorganic insulator or polysilicon.

[0201] The SiC semiconductor device 1A includes an interlayer insulating film 53 formed on a main surface insulating film 51. The interlayer insulating film 53 covers the active surface 31, the outer surface 32, and the first to fourth connecting surfaces 33A to 33D. The interlayer insulating film 53 covers the main surface insulating film 51 with a sidewall structure 52 in between.

[0202] The SiC semiconductor device 1A includes a gate main surface electrode 54 (first main surface electrode) formed on the first main surface 3 (on the interlayer insulating film 53). The gate main surface electrode 54 transmits the gate potential input from the outside to a plurality of trench gate structures 37 (gate electrodes 40). In this embodiment, the gate main surface electrode 54 is located on the active surface 31 and not on the outer surface 32. The gate main surface electrode 54 includes a gate pad electrode 55 and a gate wiring electrode 56. In this embodiment, the gate pad electrode 55 is located in a region on the periphery of the active surface 31, close to the center of the first connection surface 33A.

[0203] The gate wiring electrode 56 is drawn out from the gate main surface electrode 54 onto the interlayer insulating film 53. The gate wiring electrode 56 is formed in a strip shape that extends along the periphery of the active surface 31 so as to intersect (specifically orthogonally) with the ends of the multiple trench gate structures 37 in a plan view. The gate wiring electrode 56 penetrates the interlayer insulating film 53 and is electrically connected to the multiple trench gate structures 37 (gate electrodes 40). The gate wiring electrode 56 transmits the gate potential applied to the gate main surface electrode 54 to the multiple trench gate structures 37.

[0204] The SiC semiconductor device 1A includes a source main electrode 57 (second main electrode) formed on the first main surface 3 (on the interlayer insulating film 53). The source main electrode 57 transmits the source potential input from the outside to a plurality of trench source structures 41 (source electrodes 44). In this embodiment, the source main electrode 57 is located on the active surface 31 and the outer surface 32. The source main electrode 57 includes a source pad electrode 58 and a source wiring electrode 59. The source pad electrode 58 is located on the active surface 31 at a distance from the gate main electrode 54.

[0205] In this embodiment, the source pad electrode 58 is formed in a polygonal shape with a recess that is inwardly recessed on the active surface 31 so as to align with the gate main surface electrode 54 on the edge along the gate main surface electrode 54 in a plan view. The source pad electrode 58 penetrates the interlayer insulating film 53 and is electrically connected to a plurality of trench source structures 41, source regions 36 and a plurality of well regions 46. The source pad electrode 58 transmits the source potential input from the outside to the plurality of trench source structures 41, source regions 36 and a plurality of well regions 46.

[0206] The source wiring electrode 59 is drawn out from the source pad electrode 58 onto the interlayer insulating film 53 and is formed in a strip shape that extends along the periphery of the active surface 31 (first to fourth connection surfaces 33A to 33D). In this configuration, the source wiring electrode 59 is formed in an annular shape (specifically a square annular shape) that surrounds the gate main surface electrode 54, the source pad electrode 58, and the gate wiring electrode 56 in a plan view.

[0207] The source wiring electrode 59 covers the sidewall structure 52 with the interlayer insulating film 53 in between, and is drawn out from the active surface 31 side to the outer surface 32 side. The source wiring electrode 59 penetrates the interlayer insulating film 53 on the outer surface 32 side and is electrically connected to the outer contact region 48. Preferably, the source wiring electrode 59 covers the entire area of ​​the sidewall structure 52 and the entire area of ​​the outer contact region 48 around its entire circumference. The source wiring electrode 59 transmits the source potential applied to the source pad electrode 58 to the multiple outer contact regions 48.

[0208] The SiC semiconductor device 1A includes a drain electrode 60 (third main surface electrode) formed on the second main surface 4. The drain electrode 60 covers the entire area of ​​the second main surface 4 and is connected to the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D). The drain electrode 60 forms ohmic contact with the base region 6 (second main surface 4). The drain electrode 60 transmits the drain potential to the base region 6.

[0209] As described above, this structure makes it possible to provide a SiC semiconductor device 1A having a trench gate type SiC-MISFET whose electrical characteristics are improved by the drift region 8. Of course, the structure of the functional device 9 (SiC-MISFET) according to the third embodiment can also be applied to any one of the first to twelfth embodiments, excluding the first embodiment.

[0210] For example, when the structure of the functional device 9 according to the third embodiment is applied to a drift region 8 having a first region 8a and a second region 8b, the active plateau 34 is formed only in the second region 8b of the drift region 8, and the functional device 9 is formed in the second region 8b. Also, when the structure of the functional device 9 according to the third embodiment is formed in a p-type drift region 18, the structure is obtained by replacing the "n-type region" with the "p-type region" and the "p-type region" with the "n-type region".

[0211] Figure 35 is a plan view showing a structure in which a functional device 9 according to the fourth embodiment is applied to a SiC semiconductor device 1J according to the tenth embodiment. Figure 36 is an enlarged view of region XXXVI shown in Figure 35. Figure 37 is a cross-sectional view along the line XXXVII-XXXVII shown in Figure 36. Hereinafter, structures corresponding to the structure described in the tenth embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0212] Referring to Figures 35 to 37, the SiC semiconductor device 1J includes a SiC chip 2, an n-type base region 6, an n-type buffer region 7, an n-type drift region 8, a p-type column region 19, and a functional device 9. The drift region 8 includes a first region 8a and a second region 8b, as in the tenth embodiment. The column region 19 is formed in the second region 8b, as in the tenth embodiment. Figures 35 to 37 show an example in which the column region 19 is arranged with spacing in the first direction X (a-axis direction) in a plan view and is formed in a strip shape extending in the second direction Y (m-axis direction). In this embodiment, the functional device 9 is a trench-gate superjunction type SiC-MISFET. The structure of the SiC-MISFET will be described in detail below.

[0213] The SiC semiconductor device 1J includes a p-type body region 61 formed on the surface layer of the first main surface 3. The body region 61 forms part of the body diode of the SiC-MISFET. Specifically, the body region 61 is formed with a gap between the lower ends of the multiple column regions 19 and the first main surface 3 so as to be connected to the multiple column regions 19. Preferably, the body region 61 is formed with a gap between the intermediate parts of the multiple column regions 19 and the first main surface 3.

[0214] The SiC semiconductor device 1J includes an n-type source region 62 formed on the surface of the body region 61. The source region 62 forms the source of the SiC-MISFET. The source region 62 has an n-type impurity concentration that exceeds the n-type impurity concentration of the drift region 8. The source region 62 forms the channel CH of the SiC-MISFET with the drift region 8 within the body region 61.

[0215] The SiC semiconductor device 1J includes a plurality of trench gate structures 63 formed on the first main surface 3. The plurality of trench gate structures 63 form the gates of the SiC-MISFET and control the inversion (on) and non-inversion (off) of the channel CH. The plurality of trench gate structures 63 are formed to traverse the body region 61 and the source region 62 and reach the drift region 8.

[0216] Specifically, the multiple trench gate structures 63 are formed in the region between two adjacent column regions 19 in a plan view. The multiple trench gate structures 63 are each formed in a strip shape extending in the direction in which the multiple column regions 19 extend in a plan view. In other words, the multiple trench gate structures 63 are arranged in a stripe shape extending parallel to the multiple column regions 19. Of course, the multiple trench gate structures 63 are each formed in a strip shape extending in a direction intersecting (orthogonal to) the multiple column regions 19 in a plan view.

[0217] Each trench gate structure 63 is formed with a gap from the bottom of the drift region 8 toward the first main surface 3, and faces the buffer region 7 across a portion of the drift region 8. Specifically, each trench gate structure 63 is formed within the second region 8b with a gap from the first region 8a toward the first main surface 3, and faces the buffer region 7 across a portion of the second region 8b and the first region 8a.

[0218] Each trench gate structure 63 includes a gate trench 64, a gate insulating film 65, and a gate electrode 66. The gate trench 64 is formed on the first main surface 3. The gate insulating film 65 is formed as a film on the inner wall of the gate trench 64. The gate electrode 66 is embedded in the gate trench 64, sandwiching the gate insulating film 65. The gate electrode 66 faces the drift region 8 (second region 8b), the body region 61, and the source region 62, sandwiching the gate insulating film 65. A gate potential is applied to the gate electrode 66.

[0219] The SiC semiconductor device 1J includes a plurality of p-type contact regions 67 formed on the surface of the body region 61. The p-type impurity concentration in the plurality of contact regions 67 exceeds the p-type impurity concentration in the body region 61. The plurality of contact regions 67 are each formed in the region between two adjacent gate trenches 64 in a plan view. The plurality of contact regions 67 are each opposite to a plurality of column regions 19 in a one-to-one correspondence in a plan view. The plurality of contact regions 67 are each formed in a band shape extending in the second direction Y in a plan view. The plurality of contact regions 67 are each formed with a gap in the first direction X from two adjacent gate trenches 64.

[0220] The SiC semiconductor device 1J includes a main surface insulating film 68 that covers the first main surface 3. The main surface insulating film 68 is connected to the gate insulating film 65 and exposes the gate electrode 66. The SiC semiconductor device 1J also includes an interlayer insulating film 69 formed on the main surface insulating film 68. The interlayer insulating film 69 covers the first main surface 3 with the main surface insulating film 68 in between.

[0221] The SiC semiconductor device 1J includes a gate main surface electrode 70 (first main surface 3 electrode) formed on the first main surface 3 (on the interlayer insulating film 69). The gate main surface electrode 70 transmits the gate potential input from the outside to a plurality of trench gate structures 63 (gate electrodes 66). The gate main surface electrode 70 includes a gate pad electrode 71 and a gate wiring electrode 72. In this embodiment, the gate pad electrode 71 is located in a region adjacent to the center of the first side surface 5A at the periphery of the first main surface 3.

[0222] The gate wiring electrode 72 is drawn out from the gate main surface electrode 70 onto the interlayer insulating film 69. The gate wiring electrode 72 is formed in a strip shape that extends along the periphery of the first main surface 3 so as to intersect (specifically orthogonally) with the ends of the multiple trench gate structures 63 in a plan view. The gate wiring electrode 72 penetrates the interlayer insulating film 69 and is electrically connected to the multiple trench gate structures 63 (gate electrodes 66). The gate wiring electrode 72 transmits the gate potential applied to the gate main surface electrode 70 to the multiple trench gate structures 63.

[0223] The SiC semiconductor device 1J includes a source main surface electrode 73 (second main surface electrode) formed on the first main surface 3 (on the interlayer insulating film 69). The source main surface electrode 73 transmits the source potential input from the outside to the source region 62 and a plurality of contact regions 67. The source main surface electrode 73 includes a source pad electrode 74. The source pad electrode 74 is positioned on the first main surface 3 at a distance from the gate main surface electrode 70.

[0224] In this embodiment, the source pad electrode 74 is formed in a polygonal shape with a recess that is inwardly recessed of the first main surface 3 so as to align with the gate main surface electrode 70 on the edge along the gate main surface electrode 70 in a plan view. The source pad electrode 74 penetrates the interlayer insulating film 69 and is electrically connected to the source region 62 and the plurality of contact regions 45. The source pad electrode 74 transmits the source potential input from the outside to the source region 62 and the plurality of contact regions 45.

[0225] The SiC semiconductor device 1J includes a drain electrode 75 (third main surface electrode) formed on the second main surface 4. The drain electrode 75 covers the entire area of ​​the second main surface 4 and is connected to the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D). The drain electrode 75 forms ohmic contact with the base region 6 (second main surface 4).

[0226] As described above, this structure provides a SiC semiconductor device 1J having a trench-gate superjunction type SiC-MISFET in which the electrical characteristics are improved by the drift region 8 and the multiple column regions 19. Of course, the structure of the functional device 9 (SiC-MISFET) according to the fourth embodiment can also be applied to any one of the ninth to twelfth embodiments, excluding the tenth embodiment. For example, if the structure of the functional device 9 according to the fourth embodiment is formed in a p-type drift region 18, the structure will be obtained by replacing the "n-type region" with the "p-type region" and the "p-type region" with the "n-type region".

[0227] Figure 38 is a cross-sectional view showing a structure in which a functional device 9 according to the fifth embodiment is applied to a SiC semiconductor device 1J according to the tenth embodiment. Hereinafter, structures corresponding to the structures described in the tenth embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0228] Referring to Figure 38, the SiC semiconductor device 1J includes a SiC chip 2, an n-type base region 6, an n-type buffer region 7, an n-type drift region 8, a p-type column region 19, and a functional device 9. The drift region 8 includes a first region 8a and a second region 8b, as in the tenth embodiment. The column region 19 is formed in the second region 8b, as in the tenth embodiment. Figure 38 shows an example in which the column region 19 is arranged at intervals in the first direction X (a-axis direction) in a plan view and formed in a strip shape extending in the second direction Y (m-axis direction). In this embodiment, the functional device 9 is a planar gate superjunction type SiC-MISFET. The structure of the SiC-MISFET will be described in detail below.

[0229] The SiC semiconductor device 1J includes a plurality of p-type body regions 81 formed on the surface layer of the first main surface 3. The plurality of body regions 81 form part of the body diode of the SiC-MISFET. Specifically, the plurality of body regions 81 are formed with a gap between them and the first main surface 3, extending from the lower ends of the plurality of column regions 19 so as to be connected to the plurality of column regions 19 in a one-to-one correspondence. Preferably, the body regions 81 are formed with a gap between them and the first main surface 3, extending from the middle of the plurality of column regions 19 in the thickness direction. The plurality of body regions 81 may each be formed in a strip shape extending along the plurality of column regions 19 in a plan view.

[0230] The SiC semiconductor device 1J includes a plurality of n-type source regions 82 formed on the surface of a plurality of body regions 81, respectively. These form the sources of the SiC-MISFETs. The source regions 82 have an n-type impurity concentration that exceeds the n-type impurity concentration of the drift region 8. In a plan view, the plurality of source regions 82 are formed in the inner part of the corresponding body region 81, spaced apart from the periphery of the corresponding body region 81. In a plan view, the plurality of source regions 82 may each be formed in a strip shape extending along a plurality of column regions 19. Within the body region 81, the source regions 82 form the channels CH of the SiC-MISFETs with the drift region 8.

[0231] The SiC semiconductor device 1J includes a plurality of p-type contact regions 83 formed on the surface of a plurality of body regions 81. The p-type impurity concentration in the plurality of contact regions 83 exceeds the p-type impurity concentration in the body region 81. The plurality of contact regions 83 are formed on the surface of the corresponding body region 81 so as to penetrate the corresponding source region 82. The plurality of contact regions 83 may each be formed in a strip shape extending along a plurality of column regions 19 in a plan view. The SiC semiconductor device 1J includes a plurality of planar gate structures 84 formed on the first main surface 3. The plurality of planar gate structures 84 form the gate of the SiC-MISFET and control the inversion (on) and non-inversion (off) of the channel CH. The plurality of planar gate structures 84 cover the drift region 8, the body region 81, and the source region 82, respectively.

[0232] Specifically, the multiple planar gate structures 84 are formed in the regions between two adjacent body regions 81 in a plan view. The multiple planar gate structures 84 are each formed in a strip-like shape extending in the direction in which the multiple column regions 19 extend in a plan view. In other words, the multiple planar gate structures 84 are arranged in a strip-like shape extending parallel to the multiple column regions 19. Of course, the multiple planar gate structures 84 are each formed in a strip-like shape extending in a direction intersecting (orthogonal to) the multiple column regions 19 in a plan view.

[0233] Each planar gate structure 84 includes a gate insulating film 85 and a gate electrode 86. The gate insulating film 85 covers the channel CH on the first main surface 3. Specifically, the gate insulating film 85 covers the drift region 8 (second region 8b), the body region 81 and the source region 82. The gate electrode 86 faces the channel CH across the gate insulating film 85. Specifically, the gate electrode 86 faces the drift region 8 (second region 8b), the body region 81 and the source region 82 across the gate insulating film 85. A gate potential is applied to the gate electrode 86.

[0234] The SiC semiconductor device 1J includes an interlayer insulating film 87 formed on a first main surface 3. The interlayer insulating film 87 covers a plurality of planar gate structures 84. Similar to the functional device 9 according to the third embodiment, the SiC semiconductor device 1J includes a gate main surface electrode 70 (first main surface electrode), a source main surface electrode 73 (second main surface electrode), and a drain electrode 75. The gate main surface electrode 70 includes a gate pad electrode 71 and a gate wiring electrode 72. The gate wiring electrode 72 penetrates the interlayer insulating film 87 and is electrically connected to a plurality of planar gate structures 84 (gate electrodes 86). The source main surface electrode 73 includes a source pad electrode 74. The source pad electrode 74 penetrates the interlayer insulating film 87 and is electrically connected to a plurality of source regions 82 and a plurality of contact regions 45.

[0235] As described above, this structure makes it possible to provide a SiC semiconductor device 1J having a planar gate superjunction type SiC-MISFET in which the electrical characteristics are improved by the drift region 8 and the multiple column regions 19. Of course, the structure of the functional device 9 (SiC-MISFET) according to the fifth embodiment can also be applied to any one of the ninth to twelfth embodiments, excluding the tenth embodiment. For example, if the structure of the functional device 9 according to the fifth embodiment is formed in a p-type drift region 18, the structure will be obtained by replacing the "n-type region" with the "p-type region" and the "p-type region" with the "n-type region".

[0236] Each of the embodiments described above can be implemented in other forms. In each of the embodiments described above, a structure was described in which the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal and the second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal. However, in each of the embodiments described above, a structure may be adopted in which the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. The specific structure in this case can be obtained by swapping the "a-axis direction" and the "m-axis direction" in each of the embodiments described above.

[0237] In the embodiments described above, examples in which a SiC chip 2 is used were explained. However, instead of SiC chip 2, a WBG (Wide Band Gap) semiconductor chip made of a WBG semiconductor other than SiC may be used. A WBG semiconductor is a semiconductor that has a band gap that exceeds the band gap of Si (silicon). The specific structure in this case can be obtained by replacing "SiC" with "WBG semiconductor" in the descriptions of the embodiments described above. The WBG semiconductor chip may consist of a diamond chip made of, for example, a carbon single crystal (diamond). In other words, the WBG semiconductor chip may consist of a carbon-containing WBG semiconductor single crystal.

[0238] In the aforementioned 9th and 10th embodiments, examples were described in which the drift region 8 has an impurity concentration adjusted by at least two pentavalent elements, and the multiple column regions 19 have an impurity concentration adjusted by trivalent elements other than boron. However, in the aforementioned 9th and 10th embodiments, the drift region 8 may have an impurity concentration adjusted by at least two pentavalent elements, and the multiple column regions 19 may have an impurity concentration adjusted by any trivalent element. Furthermore, in the aforementioned 9th and 10th embodiments, the drift region 8 may have an impurity concentration adjusted by any pentavalent element, and the multiple column regions 19 may have an impurity concentration adjusted by trivalent elements other than boron.

[0239] In the aforementioned 11th and 12th embodiments, examples were described in which the drift region 18 has an impurity concentration adjusted by a trivalent element other than boron, and the multiple column regions 20 have an impurity concentration adjusted by a pentavalent element other than phosphorus and nitrogen. However, in the aforementioned 11th and 12th embodiments, the drift region 18 may have an impurity concentration adjusted by a trivalent element other than boron, and the multiple column regions 20 may have an impurity concentration adjusted by any pentavalent element. Furthermore, in the aforementioned 11th and 12th embodiments, the drift region 18 may have an impurity concentration adjusted by any pentavalent element, and the multiple column regions 20 may have an impurity concentration adjusted by a pentavalent element other than phosphorus and nitrogen.

[0240] The following are examples of features extracted from this specification and drawings. [A1] to [A29], [B1] to [B22], [C1] to [C33], and [D1] to [D24] below provide semiconductor devices capable of improving electrical characteristics. [E1] to [E22] below provide a method for manufacturing a semiconductor device capable of improving electrical characteristics. The alphanumeric characters in parentheses below represent corresponding components in the embodiments described above, but this is not intended to limit the scope of each item to the embodiments.

[0241] [A1] A semiconductor device (1A~1L) comprising a WBG (Wide Band Gap) semiconductor chip (2) having a main surface (3), and n-type drift regions (8, 18) formed on the surface layer of the main surface (3) having impurity concentrations adjusted by at least two pentavalent elements.

[0242] [A2] The semiconductor device (1A~1L) according to A1, wherein the drift region (8, 18) has an impurity concentration adjusted to increase toward the main surface (3).

[0243] [A3] The semiconductor device (1A to 1L) according to A1 or A2, wherein the drift region (8, 18) has an impurity concentration adjusted by a pentavalent element other than phosphorus.

[0244] [A4] The drift region (8, 18) contains nitrogen as a pentavalent element and a pentavalent element other than nitrogen, as described in any one of A1 to A3 (1A to 1L).

[0245] [A5] The drift region (8, 18) has a base concentration (CA) due to a first impurity which is a pentavalent element, and an additional concentration (CB) due to a second impurity which is a pentavalent element other than the first impurity, as described in any one of A1 to A4 (1A to 1L).

[0246] [A6] The semiconductor device described in A5 (1A~1L), wherein the first impurity is a pentavalent element other than phosphorus, and the second impurity is a pentavalent element other than phosphorus.

[0247] [A7] The semiconductor device (1A~1L) according to A6, wherein the first impurity is nitrogen and the second impurity is at least one of arsenic and antimony.

[0248] [A8] The semiconductor device (1A to 1L) according to any one of A5 to A7, wherein the added concentration (CB) has a concentration distribution that increases toward the main surface (3).

[0249] [A9] The semiconductor device (1A to 1L) according to any one of A5 to A8, wherein the base concentration (CA) has a substantially constant concentration distribution in the thickness direction.

[0250] [A10] A semiconductor device (1A~1L) comprising a WBG (Wide Band Gap) semiconductor chip (2) having a main surface (3), and p-type drift regions (8, 18) formed on the surface layer of the main surface (3) and having an impurity concentration adjusted by trivalent elements other than boron.

[0251] [A11] The semiconductor device (1A~1L) according to A10, wherein the drift regions (8, 18) have an impurity concentration adjusted to increase toward the main surface (3).

[0252] [A12] The drift region (8, 18) is the semiconductor device (1A to 1L) according to A10 or A11, containing at least one trivalent element of aluminum, gallium, and indium.

[0253] [A13] The drift region (8, 18) has a base concentration (CA) caused by a first impurity that is a trivalent element, and an additional concentration (CB) caused by a second impurity that is the same as or different from the first impurity and is a trivalent element. The semiconductor device (1A to 1L) according to any one of A10 to A12.

[0254] [A14] The first impurity is aluminum, and the second impurity is at least one of aluminum, gallium, and indium. The semiconductor device (1A to 1L) according to A13.

[0255] [A15] The additional concentration (CB) has a concentration distribution that increases toward the main surface (3). The semiconductor device (1A to 1L) according to A13 or A14.

[0256] [A16] The base concentration (CA) has a substantially constant concentration distribution in the thickness direction. The semiconductor device (1A to 1L) according to any one of A13 to A15.

[0257] [A17] The drift region (8, 18) has a thickness belonging to any one of the ranges of 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, and 20 μm or more and 25 μm or less. The semiconductor device (1A to 1L) according to any one of A1 to A16.

[0258] [A18] The WBG semiconductor chip (2) contains C (carbon). The semiconductor device (lA to 1L) according to any one of A1 to A17.

[0259] [A19] The WBG semiconductor chip (2) consists of a SiC chip (2). The semiconductor device (1A to 1L) according to any one of A1 to A18.

[0260] [A20] The semiconductor device (1A~1L) according to A19, wherein the SiC chip (2) is made of a hexagonal SiC single crystal, and the main surface (3) faces the c-plane of the SiC single crystal and has an off-angle (θ) of 10° or less between it and the c-plane.

[0261] [A21] The semiconductor device (1A~1L) according to A20, wherein the off-angle (θ) has an off-direction (D) along the a-axis direction of the SiC single crystal.

[0262] [A22] The drift region (8, 18) is formed in the WBG semiconductor epitaxial layer, as described in any one of A1 to A21 (1A to 1L).

[0263] [A23] A semiconductor device (1A to 1L) according to any one of A1 to A22, further comprising a functional device (9) formed on the main surface (3).

[0264] [A24] The functional device (9) is a semiconductor device (1A to 1L) as described in A23, including a diode.

[0265] [A25] The semiconductor device (1A~1L) according to A24, further comprising: an insulating film (22) that covers the main surface (3) such that the main surface (3) is partially exposed; a first main surface electrode (23) electrically connected to the main surface (3); and a second main surface electrode (24) formed on the surface (4) opposite to the main surface (3).

[0266] [A26] The semiconductor device (1A~1L) according to A25, wherein the insulating film (22) exposes the drift region (8, 18), and the first main surface electrode (23) forms a Schottky junction with the drift region (8, 18).

[0267] [A27] The functional device (9) is the semiconductor device (1A~1L) described in A23, further comprising a transistor.

[0268] [A28] The semiconductor device (1A~1L) according to A27, further comprising a channel (CH) formed on the surface of the drift region (8, 18), and a gate structure (37, 63, 84) formed on the main surface (3) for controlling the on / off state of the channel (CH).

[0269] [A29] The semiconductor device (1A~1L) according to A28, further comprising: first main surface electrodes (54, 70) disposed on the main surface (3) and electrically connected to the gate structure (37, 63, 84); second main surface electrodes (57, 73) disposed on the main surface (3) and electrically connected to the channel (CH); and third main surface electrodes (60, 75) formed on the surface (4) opposite to the main surface (3).

[0270] [B1] A WBG (Wide Band Gap) semiconductor chip (2) having one first main surface (3) and the other second main surface (4), a base region (6, 16) of a first conductivity type formed in the region on the second main surface (4) side within the WBG semiconductor chip (2), containing a first impurity of a first conductivity type and having a first concentration (C1), and a concentration that decreases from the first concentration (C1) to the second concentration (C2) starting from the base region (6, 16) within the WBG semiconductor chip (2), containing the first impurity, and starting from the base region (6, 16). A semiconductor device (1A to 1L) comprising: buffer regions (7, 17) of a first conductivity type having a density distribution; and drift regions (8, 18) of a first conductivity type formed in the region between the first main surface (3) and the buffer regions (7, 17) within the WBG semiconductor chip (2), containing the first impurity and a second impurity of a first conductivity type different from the first impurity, and having a density distribution that increases from the second concentration (C2) to the third concentration (C3) starting from the buffer regions (7, 17).

[0271] [B2] The semiconductor device (1A to 1L) according to B1, wherein the drift regions (8, 18) contain the first impurity and the second impurity in the surface region and the bottom region relative to the intermediate portion (MID) between the first main surface (3) and the buffer regions (7, 17).

[0272] [B3] The semiconductor device (1A to 1L) according to B1 or B2, wherein the third concentration (C3) is less than the first concentration (C1).

[0273] [B4] The semiconductor device (1A to 1L) according to any one of B1 to B3, wherein the third concentration (C3) is 10 times or more the second concentration (C2).

[0274] [B5] The semiconductor device (1A to 1L) according to any one of B1 to B4, wherein the drift region (8, 18) includes a base concentration (CA) caused by the first impurity and an additional concentration (CB) caused by the second impurity.

[0275] [B6] The semiconductor device (1A to 1L) according to B5, wherein the additional concentration (CB) has a concentration distribution that increases toward the first main surface (3).

[0276] [B7] The semiconductor device (1A to 1L) according to B5 or B6, wherein the base concentration (CA) has a substantially constant concentration distribution in the thickness direction.

[0277] [B8] The semiconductor device (1A to 1L) according to any one of B1 to B7, wherein the first conductivity type is n-type.

[0278] [B9] The semiconductor device (1A to 1L) according to B8, wherein the first impurity is a pentavalent element other than phosphorus.

[0279] [B10] The semiconductor device (1A to 1L) according to B8 or B9, wherein the first impurity is nitrogen.

[0280] [B11] The semiconductor device (1A to 1L) according to any one of B8 to B10, wherein the second impurity is a pentavalent element other than phosphorus.

[0281] [B12] The semiconductor device (1A to 1L) according to any one of B8 to B11, wherein the second impurity is at least one of arsenic and antimony.

[0282] [B13] A semiconductor device (1A to 1L) according to any one of B1 to B12, wherein the base region (6, 16) has a first thickness, the buffer region (7, 17) has a second thickness less than the first thickness, and the drift region (8, 18) has a third thickness greater than or equal to the second thickness.

[0283] [B14] The semiconductor device (1A to 1L) described in B13, wherein the third thickness is less than the first thickness.

[0284] [B15] The semiconductor device (1A to 1L) described in B13 or B14, wherein the third thickness is in any one of the following ranges: 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, and 20 μm or more and 25 μm or less.

[0285] [B16] The WBG semiconductor chip (2) is a semiconductor device (1A to 1L) according to any one of B1 to B15, containing C (carbon).

[0286] [B17] The WBG semiconductor chip (2) is a semiconductor device (1A to 1L) described in any one of B1 to B16, comprising a SiC chip (2).

[0287] [B18] The semiconductor device (1A~1L) according to B17, wherein the SiC chip (2) is made of a hexagonal SiC single crystal, and the first principal surface (3) faces the c-plane of the SiC single crystal and has an off-angle (θ) of 10° or less between it and the c-plane.

[0288] [B19] The semiconductor device (1A to 1L) according to B18, wherein the off-angle (θ) has an off-direction (D) along the a-axis direction of the SiC single crystal.

[0289] [B20] A semiconductor device (1A to 1L) according to any one of B1 to B19, wherein the base region (6, 16) is formed on a semiconductor substrate, the buffer region (7, 17) is formed on an epitaxial layer, and the drift region (8, 18) is formed on an epitaxial layer.

[0290] [B21] A semiconductor device (1A to 1L) according to any one of B1 to B20, further comprising a functional device (9) formed on the first main surface (3).

[0291] [B22] The functional device (9) is a semiconductor device (1A to 1L) according to B21, which includes at least one of a diode and a transistor.

[0292] [C1] A semiconductor device (1A~1L) comprising a WBG (Wide Band Gap) semiconductor chip (2) having a main surface (3), n-type drift regions (8, 18) formed on the surface layer of the main surface (3) and having impurity concentrations adjusted by at least two pentavalent elements, and p-type impurity regions (19, 20) formed within the drift regions (8, 18) to form a pn junction with the drift regions (8, 18).

[0293] [C2] A semiconductor device (1A~1L) comprising a WBG semiconductor chip (2) having a main surface (3), n-type drift regions (8, 18) formed on the surface layer of the main surface (3), and p-type impurity regions (19, 20) formed within the drift regions (8, 18) so as to form a pn junction with the drift regions (8, 18), and having an impurity concentration adjusted by trivalent elements other than boron.

[0294] [C3] The semiconductor device (1A to 1L) according to C2, wherein the drift region (8, 18) has an impurity concentration adjusted by at least two pentavalent elements.

[0295] [C4] The semiconductor device (1A to 1L) according to any one of C1 to C3, wherein the drift region (8, 18) has a concentration distribution that increases toward the main surface (3), and the impurity region (19, 20) has a concentration distribution that increases toward the main surface (3).

[0296] [C5] The drift region (8, 18) contains a pentavalent element other than phosphorus, as described in any one of C1 to C4 (1A to 1L).

[0297] [C6] The impurity region (19, 20) contains at least one trivalent element from among aluminum, gallium, and indium, as described in any one of C1 to C5 (1A to 1L).

[0298] [C7] The impurity region (19, 20) extends in the thickness direction within the drift region (8, 18) such that it forms a superjunction structure with the drift region (8, 18) and the pn junction, according to any one of C1 to C6 (1A to 1L).

[0299] [C8] The impurity region (19, 20) crosses the intermediate portion (MID) of the drift region (8, 18) with respect to the thickness direction of the drift region (8, 18), as described in any one of C1 to C7, semiconductor device (1A to 1L).

[0300] [C9] The impurity regions (19, 20) are formed with a gap between the bottom of the drift regions (8, 18) and the main surface (3), as described in any one of C1 to C8 (1A to 1L).

[0301] [C10] The drift region (8, 18) includes a base concentration (CA) due to a first impurity which is a pentavalent element, and an additional concentration (CB) due to a second impurity which is a pentavalent element other than the first impurity, according to any one of C1 to C9 (1A to 1L).

[0302] [C11] The drift region (8, 18) is formed on the surface of the main surface (3) spaced apart from the main surface (3) and includes a first region (8a, 18a) consisting of the base concentration (CA), and a second region (8b, 18b) formed in the region between the main surface (3) and the first region (8a, 18a) and consisting of the base concentration (CA) and the added concentration (CB), and the impurity region (19, 20) is formed within the second region (8b, 18b) so as to form the pn junction with the second region (8b, 18b), the semiconductor device (1A~1L) according to C10.

[0303] [C12] The impurity regions (19, 20) are formed within the second region (8b, 18b) with a gap between them and the main surface (3) side from the first region (8a, 18a), as described in C11 (1A~1L).

[0304] [C13] The semiconductor device (1A to 1L) according to any one of C10 to C12, wherein the added concentration (CB) has a concentration distribution that increases toward the main surface (3).

[0305] [C14] The semiconductor device (1A to 1L) according to any one of C10 to C13, wherein the base concentration (CA) has a substantially constant concentration distribution in the thickness direction.

[0306] [C15] The first impurity is a pentavalent element other than phosphorus, as described in any one of C10 to C14 (1A to 1L).

[0307] [C16] The semiconductor device (1A to 1L) according to any one of C10 to C15, wherein the first impurity is nitrogen and the second impurity is at least one of arsenic and antimony.

[0308] [C17] A semiconductor device (1A~1L) comprising a WBG semiconductor chip (2) having a main surface (3), a p-type drift region (8, 18) formed on the surface layer of the main surface (3) and having an impurity concentration adjusted by trivalent elements other than boron, and an n-type impurity region (19, 20) formed within the drift region (8, 18) to form a pn junction with the drift region (8, 18) and having an impurity concentration adjusted by pentavalent elements other than phosphorus and nitrogen.

[0309] [C18] The semiconductor device (1A to 1L) according to C17, wherein the drift region (8, 18) has a concentration distribution that increases toward the main surface (3), and the impurity region (19, 20) has a concentration distribution that increases toward the main surface (3).

[0310] [C19] The semiconductor device (1A to 1L) according to C17 or C18, wherein the impurity regions (19, 20) extend in the thickness direction within the drift regions (8, 18) so as to form a superjunction structure with the drift regions (8, 18) and the pn junction.

[0311] [C20] The drift region (8, 18) contains at least one trivalent element from among aluminum, gallium, and indium, and the impurity region (19, 20) contains at least one from among arsenic and antimony, wherein the semiconductor device (1A to 1L) is according to any one of C17 to C19.

[0312] [C21] The drift region (8, 18) has a thickness that falls within one of the following ranges: 1 μm to 5 μm, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, and 20 μm to 25 μm, according to any one of C1 to C20 (1A to 1L).

[0313] [C22] The WBG semiconductor chip (2) is a semiconductor device (1A to 1L) described in any one of C1 to C21, which contains C (carbon).

[0314] [C23] The WBG semiconductor chip (2) is a SiC chip (2), and is a semiconductor device (1A to 1L) as described in any one of C1 to C22.

[0315] [C24] The semiconductor device (1A~1L) according to C23, wherein the SiC chip (2) is made of a hexagonal SiC single crystal, and the main surface (3) faces the c-plane of the SiC single crystal and has an off-angle (θ) of 10° or less between it and the c-plane.

[0316] [C25] The semiconductor device (1A to 1L) according to C24, wherein the off-angle (θ) has an off-direction (D) along the a-axis direction of the SiC single crystal, and the impurity region (19, 20) is formed in a band shape extending along the a-axis direction in a plan view.

[0317] [C26] The drift region (8, 18) is formed in the epitaxial layer, and is a semiconductor device (1A to 1L) according to any one of C1 to C25.

[0318] [C27] A semiconductor device (1A to 1L) according to any one of C1 to C26, further comprising a functional device (9) formed on the main surface (3).

[0319] [C28] The functional device (9) is a semiconductor device (1A to 1L) as described in C27, including a diode.

[0320] [C29] The semiconductor device (1A~1L) according to C28, further comprising: an insulating film (22) that covers the main surface (3) such that the main surface (3) is partially exposed; a first main surface electrode (23) electrically connected to the main surface (3); and a second main surface electrode (24) formed on the surface (4) opposite to the main surface (3).

[0321] [C30] The insulating film (22) exposes the drift region (8, 18), and the first main surface electrode (23) forms a Schottky junction with the drift region (8, 18), as described in C29 (1A~1L).

[0322] [C31] The functional device (9) is a semiconductor device (1A to 1L) as described in C27, further comprising a transistor.

[0323] [C32] The semiconductor device (1A to 1L) according to C31, further comprising a channel (CH) formed on the surface of the drift region (8, 18), and a gate structure (37, 63, 84) formed on the main surface (3) for controlling the on / off state of the channel (CH).

[0324] [C33] A semiconductor device (1A~1L) according to C32, further comprising: first main surface electrodes (54, 70) disposed on the main surface (3) and electrically connected to the gate structure (37, 63, 84); second main surface electrodes (57, 73) disposed on the main surface (3) and electrically connected to the channel (CH); and third main surface electrodes (60, 75) formed on the surface (4) opposite to the main surface (3).

[0325] [D1] A WBG (Wide Band Gap) semiconductor chip (2) having one first main surface (3) and the other second main surface (4), a base region (6, 16) of a first conductivity type formed in the region on the second main surface (4) side within the WBG semiconductor chip (2), containing a first impurity of a first conductivity type and having a first concentration (C1), a buffer region (7, 17) of a first conductivity type formed in the region on the first main surface (3) side relative to the base region (6, 16) within the WBG semiconductor chip (2), containing the first impurity and having a concentration distribution that decreases from the first concentration (C1) to the second concentration (C2) starting from the base region (6, 16), and the WBG semiconductor chip (2 A semiconductor device (1A to 1L) comprising: a drift region (8, 18) of a first conductivity type formed in the region between the first main surface (3) and the buffer region (7, 17) within the ) and containing the first impurity and a second impurity of a first conductivity type different from the first impurity, and having a concentration distribution that increases from the second concentration (C2) to the third concentration (C3) starting from the buffer region (7, 17); and a plurality of column regions (19, 20) of a second conductivity type formed within the drift region (8, 18) so as to form a superjunction structure with the drift region (8, 18).

[0326] [D2] The semiconductor device (1A~1L) according to D1, wherein the column regions (19, 20) extend in the thickness direction so as to cross the intermediate portion (MID) of the drift regions (8, 18).

[0327] [D3] The semiconductor device (1A to 1L) according to D1 or D2, wherein the column regions (19, 20) are formed with a gap between the bottom of the drift regions (8, 18) and the first main surface (3).

[0328] [D4] The column regions (19, 20) have a concentration distribution that increases toward the first main surface (3), the semiconductor device (1A to 1L) according to any one of D1 to D3.

[0329] [D5] The drift region (8, 18) includes the base concentration (CA) due to the first impurity and the added concentration (CB) due to the second impurity, as described in any one of D1 to D4 (1A to 1L).

[0330] [D6] The semiconductor device (1A~1L) according to D5, wherein the drift regions (8, 18) are formed on the surface of the first main surface (3) spaced apart from the first main surface (3) and include a first region (8a, 18a) consisting of the base concentration (CA), and a second region (8b, 18b) formed in the region between the first main surface (3) and the first region (8a, 18a) and consisting of the base concentration (CA) and the additional concentration (CB), and the column regions (19, 20) are formed within the second region (8b, 18b) so as to form the superjunction structure with the second region (8b, 18b).

[0331] [D7] The semiconductor device (1A to 1L) according to D6, wherein the column regions (19, 20) are formed within the second region (8b, 18b) with a gap between them and the first main surface (3) from the first region (8a, 18a).

[0332] [D8] The semiconductor device (1A to 1L) according to any one of D5 to D7, wherein the added concentration (CB) has a concentration distribution that increases toward the first main surface (3).

[0333] [D9] The semiconductor device (1A to 1L) described in any one of D5 to D8, wherein the base concentration (CA) has a substantially constant concentration distribution in the thickness direction.

[0334] [D10] A semiconductor device (1A to 1L) according to any one of D1 to D9, wherein the first conductivity type is n type and the second conductivity type is p type.

[0335] [D11] The column regions (19, 20) contain trivalent elements other than boron, as described in D10 (1A~1L).

[0336] [D12] The semiconductor device (1A to 1L) according to D10 or D11, wherein the column regions (19, 20) contain at least one trivalent element selected from aluminum, gallium, and indium.

[0337] [D13] The semiconductor device (1A to 1L) described in any one of D10 to D12, wherein the first impurity is a pentavalent element other than phosphorus, and the second impurity is a pentavalent element other than phosphorus.

[0338] [D14] The semiconductor device (1A to 1L) according to any one of D10 to D13, wherein the first impurity is nitrogen and the second impurity is at least one of arsenic and antimony.

[0339] [D15] A semiconductor device (1A to 1L) according to any one of D1 to D14, wherein the base region (6, 16) has a first thickness, the buffer region (7, 17) has a second thickness less than the first thickness, and the drift region (8, 18) has a third thickness greater than or equal to the second thickness.

[0340] [D16] The semiconductor device (1A to 1L) described in D15, wherein the third thickness is less than the first thickness.

[0341] [D17] The semiconductor device (1A to 1L) described in D15 or D16, wherein the third thickness is in any one of the following ranges: 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, and 20 μm or more and 25 μm or less.

[0342] [D18] The WBG semiconductor chip (2) is a semiconductor device (1A to 1L) described in any one of D1 to D17, which contains C (carbon).

[0343] [D19] The WBG semiconductor chip (2) is a semiconductor device (1A to 1L) described in any one of D1 to D18, comprising a SiC chip (2).

[0344] [D20] The semiconductor device (1A~1L) according to D19, wherein the SiC chip (2) is made of a hexagonal SiC single crystal, and the first principal surface (3) faces the c-plane of the SiC single crystal and has an off-angle (θ) of 10° or less between it and the c-plane.

[0345] [D21] The semiconductor device (1A~1L) according to D20, wherein the off-angle (θ) has an off-direction (D) along the a-axis direction of the SiC single crystal, and the column regions (19, 20) are formed in a strip shape extending along the a-axis direction in a plan view.

[0346] [D22] A semiconductor device (1A to 1L) according to any one of D1 to D21, wherein the base region (6, 16) is formed on a semiconductor substrate, the buffer region (7, 17) is formed on an epitaxial layer, and the drift region (8, 18) is formed on an epitaxial layer.

[0347] [D23] A semiconductor device (1A to 1L) according to any one of D1 to D22, further comprising a functional device (9) formed on the first main surface (3).

[0348] [D24] The functional device (9) is a semiconductor device (1A to 1L) according to D23, which includes at least one of a diode and a transistor.

[0349] A method for manufacturing a semiconductor device (1A to 1L), comprising the steps of: preparing an epitaxial layer (14) made of a WBG (Wide Band Gap) semiconductor single crystal and adjusted to a low concentration of a first conductivity type; and forming a first conductivity type drift region (8, 18) having a target concentration by implanting a first conductivity type impurity into the epitaxial layer (14) by ion implantation.

[0350] [E2] A method for manufacturing a semiconductor device (1A to 1L) according to E1, wherein an epitaxial layer (14) adjusted to a low concentration with a first impurity is prepared, and the drift regions (8, 18) are formed by injecting a second impurity of a first conductivity type different from the first impurity into the epitaxial layer (14).

[0351] [E3] The method for manufacturing a semiconductor device (1A to 1L) according to E2, wherein the ion implantation method is a channeling implantation method for implanting the second impurity along the crystal axis (c axis) of the WBG semiconductor single crystal.

[0352] [E4] The method for manufacturing a semiconductor device (1A to 1L) according to E3, wherein the second impurity is injected into the epitaxial layer (14) at an angle of ±5° or less with respect to the crystal axis (c axis) of the WBG semiconductor single crystal.

[0353] [E5] A method for manufacturing a semiconductor device (1A to 1L) according to any one of E1 to E4, further comprising the step of implanting a second-conductivity impurity into the epitaxial layer (14) by ion implantation after the step of forming the drift regions (8, 18) to form a second-conductivity impurity region (19, 20) that forms a pn junction with the drift regions (8, 18).

[0354] [E6] The method for manufacturing a semiconductor device (1A to 1L) according to E5, wherein the ion implantation method is a channeling implantation method for implanting the second conductivity type impurity along the crystal axis (c axis) of the WBG semiconductor single crystal.

[0355] [E7] The method for manufacturing a semiconductor device (1A to 1L) according to E6, wherein the impurity of the second conductivity type is injected into the epitaxial layer (14) at an angle of ±5° or less with respect to the crystal axis (c axis) of the WBG semiconductor single crystal.

[0356] [E8] A method for manufacturing a semiconductor device (1A to 1L), comprising the steps of: preparing an n-type epitaxial layer (14) made of a WBG (Wide Band Gap) semiconductor single crystal and adjusted to a low concentration with nitrogen, a pentavalent element; and forming n-type drift regions (8, 18) having a target concentration by implanting pentavalent elements other than nitrogen into the epitaxial layer (14) by ion implantation.

[0357] [E9] The method for manufacturing a semiconductor device (1A to 1L) according to E8, wherein the ion implantation method is a channeling implantation method in which the pentavalent element is implanted along the crystal axis (c axis) of the WBG semiconductor single crystal.

[0358] [E10] A method for manufacturing a semiconductor device (1A to 1L) according to E8 or E9, wherein the drift regions (8, 18) are formed by implanting the pentavalent elements other than phosphorus.

[0359] [E11] A method for manufacturing a semiconductor device (1A to 1L) according to any one of E8 to E10, wherein the drift region (8, 18) is formed by implanting at least one of the pentavalent elements, which is arsenic and antimony.

[0360] [E12] A method for manufacturing a semiconductor device (1A to 1L) according to any one of E8 to E11, further comprising the step of implanting a trivalent element into the epitaxial layer (14) by ion implantation after the step of forming the drift regions (8, 18) to form p-type column regions (19, 20) that form a pn junction with the drift regions (8, 18).

[0361] [E13] The method for manufacturing a semiconductor device (1A to 1L) according to E12, wherein the ion implantation method is a channeling implantation method in which the trivalent element is implanted along the crystal axis (c axis) of the WBG semiconductor single crystal.

[0362] [E14] A method for manufacturing a semiconductor device (1A to 1L), comprising the steps of: preparing an epitaxial layer (14) made of a WBG (Wide Band Gap) semiconductor single crystal and including n-type drift regions (8, 18); and forming p-type impurity regions (19, 20) that form a pn junction with the drift regions (8, 18) by implanting trivalent elements other than boron into the epitaxial layer (14) by ion implantation.

[0363] [E15] A method for manufacturing a semiconductor device (1A to 1L) according to E14, wherein the drift regions (8, 18) and the impurity regions (19, 20) that form a superjunction structure are formed.

[0364] [E16] A method for manufacturing a semiconductor device (1A to 1L) according to E14 or E15, wherein a plurality of the aforementioned impurity regions (19, 20) are formed.

[0365] [E17] The method for manufacturing a semiconductor device (1A to 1L) according to any one of E14 to E16, wherein the ion implantation method is a channeling implantation method for implanting the trivalent element along the crystal axis (c axis) of the WBG semiconductor single crystal.

[0366] [E18] A method for manufacturing a semiconductor device (1A to 1L) according to any one of E14 to E17, wherein the impurity region (19, 20) is formed by implanting at least one of the trivalent elements selected from aluminum, gallium, and indium.

[0367] [E19] The WBG semiconductor single crystal contains C (carbon), a method for manufacturing a semiconductor device (1A to 1L) as described in any one of E1 to E18.

[0368] [E20] The WBG semiconductor single crystal is made of a SiC single crystal, a method for manufacturing a semiconductor device (1A to 1L) according to any one of E1 to E19.

[0369] [E21] A method for manufacturing a semiconductor device (1A to 1L) according to E20, wherein the epitaxial layer (14) having an off-angle (θ) of 10° or less between itself and the c-plane of the SiC single crystal is provided.

[0370] [E22] The method for manufacturing a semiconductor device (1A to 1L) according to E21, wherein the off-angle (θ) has an off-direction (D) along the a-axis direction of the SiC single crystal.

[0371] Although embodiments have been described in detail, these are merely specific examples used to clarify the technical content, and the present invention should not be interpreted as being limited to these specific examples. The scope of the present invention is limited by the appended claims. [Explanation of Symbols]

[0372] 1A SiC semiconductor device 1B SiC semiconductor device 1C SiC semiconductor device 1D SiC semiconductor device 1E SiC semiconductor device 1F SiC Semiconductor Device 1G SiC semiconductor device 1H SiC Semiconductor Device 1I SiC semiconductor device 1J SiC Semiconductor Device 1K SiC semiconductor device 1L SiC semiconductor device 2 SiC chips 3. First Main Surface 4. Second main surface 6 n-type base region 7 n-type buffer area 8 n-type drift region 8a 1st area 8b 2nd area 9 Functional Devices 14. Second SiC Epitaxial Layer 16 p-type base region 17 p-type buffer area 18 p-type drift region 18a 1st area 18b Second area 19. Column region (impurity region) 20 Column region (impurity region) 22 Insulating film 23. First main surface electrode 24 Second main surface electrode 37 Trench gate structure (gate structure) 54 Gate main surface electrode (first main surface electrode) 57 Source main surface electrode (second main surface electrode) 60 Drain electrode (third main surface electrode) 63 Trench gate structure (gate structure) 70 Gate main surface electrode (first main surface electrode) 73. Source main surface electrode (second main surface electrode) 75 Drain electrode (third main surface electrode) 84 Planar gate structure (gate structure) C1 1st concentration C2 second concentration C3 3rd concentration CA basal concentration CB added concentration D Off direction θ Off-angle Mid-drift region

Claims

1. A SiC chip having a main surface, An n-type drift region formed on the surface of the main surface, having an impurity concentration adjusted by at least two pentavalent elements, The drift region includes a p-type impurity region formed within the drift region so as to form a pn junction with the drift region, The drift region has a concentration distribution that increases toward the main surface. The SiC semiconductor device wherein the impurity region has a concentration distribution that increases toward the main surface.

2. A SiC chip having a main surface, An n-type drift region formed on the surface of the main surface, It includes a p-type impurity region formed within the drift region so as to form a pn junction with the drift region, and having an impurity concentration adjusted by trivalent elements other than boron, The drift region has a concentration distribution that increases toward the main surface. The SiC semiconductor device wherein the impurity region has a concentration distribution that increases toward the main surface.

3. The SiC semiconductor device according to claim 2, wherein the drift region has an impurity concentration adjusted by at least two pentavalent elements.

4. The SiC semiconductor device according to any one of claims 1 to 3, wherein the drift region includes a pentavalent element other than phosphorus.

5. The SiC semiconductor device according to any one of claims 1 to 4, wherein the impurity region contains at least one trivalent element selected from aluminum, gallium, and indium.

6. The SiC semiconductor device according to any one of claims 1 to 5, wherein the impurity region extends in the thickness direction within the drift region such that it forms a superjunction structure with the drift region and the pn junction.

7. The SiC semiconductor device according to any one of claims 1 to 6, wherein the impurity region crosses the intermediate portion of the drift region with respect to the thickness direction of the drift region.

8. The SiC semiconductor device according to any one of claims 1 to 7, wherein the impurity region is formed with a gap from the bottom of the drift region toward the main surface.

9. The SiC semiconductor device according to any one of claims 1 to 8, wherein the drift region includes a base concentration due to a first impurity which is a pentavalent element, and an additional concentration due to a second impurity which is a pentavalent element other than the first impurity.

10. The drift region is formed at a distance from the main surface and on the surface layer of the main surface, and includes a first region consisting of the base concentration, and a second region formed in the region between the main surface and the first region, consisting of the base concentration and the added concentration. The SiC semiconductor device according to claim 9, wherein the impurity region is formed within the second region so as to form the pn junction with the second region.

11. The SiC semiconductor device according to claim 10, wherein the impurity region is formed within the second region with a gap between it and the first region toward the main surface.

12. The SiC semiconductor device according to any one of claims 9 to 11, wherein the added concentration has a concentration distribution that increases toward the main surface.

13. The SiC semiconductor device according to any one of claims 9 to 12, wherein the base concentration has a substantially constant concentration distribution in the thickness direction.

14. The SiC semiconductor device according to any one of claims 9 to 13, wherein the first impurity is a pentavalent element other than phosphorus.

15. The first impurity is nitrogen, The SiC semiconductor device according to any one of claims 9 to 14, wherein the second impurity is at least one of arsenic and antimony.

16. A SiC chip having a main surface, A p-type drift region is formed on the surface of the main surface and has an impurity concentration adjusted by trivalent elements other than boron, It includes an n-type impurity region formed within the drift region so as to form a pn junction with the drift region, and having an impurity concentration adjusted by pentavalent elements other than phosphorus and nitrogen, The drift region has a concentration distribution that increases toward the main surface. The SiC semiconductor device wherein the impurity region has a concentration distribution that increases toward the main surface.

17. The SiC semiconductor device according to claim 16, wherein the impurity region extends in the thickness direction within the drift region such that it forms a superjunction structure with the drift region and the pn junction.

18. The drift region comprises at least one trivalent element selected from aluminum, gallium, and indium. The SiC semiconductor device according to claim 16 or claim 17, wherein the impurity region includes at least one of arsenic and antimony.

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